WO2017197684A1 - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents

基于ltps半导体薄膜晶体管的goa电路 Download PDF

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Publication number
WO2017197684A1
WO2017197684A1 PCT/CN2016/085598 CN2016085598W WO2017197684A1 WO 2017197684 A1 WO2017197684 A1 WO 2017197684A1 CN 2016085598 W CN2016085598 W CN 2016085598W WO 2017197684 A1 WO2017197684 A1 WO 2017197684A1
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Prior art keywords
electrically connected
thin film
film transistor
node
clock signal
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English (en)
French (fr)
Inventor
李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/312,040 priority Critical patent/US10403219B2/en
Priority to EA201891566A priority patent/EA035508B1/ru
Priority to KR1020187025654A priority patent/KR102033165B1/ko
Priority to GB1814452.7A priority patent/GB2563768B/en
Priority to JP2018541120A priority patent/JP6799069B2/ja
Publication of WO2017197684A1 publication Critical patent/WO2017197684A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a GOA circuit based on an LTPS semiconductor thin film transistor which can improve the output capability of an output point of a GOA circuit.
  • GOA Gate Driver on Array, line scan integrated on array substrate technology, utilizes existing TFT-LCD (Thin Film Transistor-Liquid Crystal) Display, thin film transistor liquid crystal display) Array process
  • TFT-LCD Thin Film Transistor-Liquid Crystal
  • Array process A technique in which the Gate line scan driving circuit is fabricated on an array substrate to realize the drive mode of Gate progressive scanning.
  • GOA technology can reduce external IC (Integrated Circuit, integrated circuit board (bonding) process, has the opportunity to increase production capacity and jump product cost, and can make LCD panel more suitable for making narrow border or borderless display products.
  • LTPS-TFT liquid crystal displays With low temperature polysilicon (Low Temperature Poly-silicon, LTPS)
  • LTPS-TFT liquid crystal displays have the advantages of high resolution, fast response, high brightness and high aperture ratio.
  • the gate driver can be fabricated on the thin film transistor array substrate by using GOA technology to achieve the goal of system integration, space saving and cost of driving the IC.
  • the GOA circuit includes a plurality of cascaded GOA units, wherein n is a positive integer, and the nth-level GOA unit includes: a first thin film transistor T1 whose gate is electrically connected to the first clock signal CK1, and the source is electrically Connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, the drain is electrically connected to the third node H(n); the second thin film transistor T2 has its gate electrically connected to the a node Q(n), the source is electrically connected to the second clock signal CK2, the drain is electrically connected to the output terminal G(n), and the third thin film transistor T3 is electrically connected to the third clock signal CK3.
  • the drain is electrically connected to the third node H(n), the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage; the fourth thin film transistor T4 is gated Electrically connected to the second node P(n), the drain is electrically connected to the output terminal G(n), the source is electrically connected to the constant voltage low level VGL, and the fifth thin film transistor T5 is electrically connected to the gate.
  • the constant voltage is high level VGH
  • the source is electrically connected to the third node H(n)
  • the drain is electrically connected to the first node Q(n)
  • the sixth thin film transistor T6 is electrically connected to the gate.
  • Three-node H(n), drain electrical connection a second node P(n), the source is electrically connected to the constant voltage low level VGL;
  • the seventh thin film transistor T7 has a gate electrically connected to the second node P(n), and the drain is electrically connected to the first a node Q(n), the source is electrically connected to the constant voltage low level VGL;
  • the eighth thin film transistor T8 has a gate electrically connected to the second clock signal CK2, and the source is electrically connected to the output terminal G(n)
  • the drain is electrically connected to the constant voltage low level VGL;
  • the first capacitor C1 has one end electrically connected to the first node Q(n), and the other end electrically connected to the output terminal G(n);
  • the second capacitor C2 One end is electrically connected to the second node P(n), and the other end is electrically connected to the second clock signal CK2.
  • FIG. 2 is a forward scan timing diagram of a conventional LTPS semiconductor thin film transistor-based GOA circuit shown in FIG. 1.
  • the working process is: Phase 1, pre-charge: G(n-1) and CK1 provide high level at the same time, T1 is turned on, T5 gate is connected to constant voltage high level VGH, so T5 is always in guide In the on state, the third node H(n) is precharged to a high level, T6 is turned on; the third node H(n) is always the same level as the first node Q(n), and the first node Q(n) Precharged to a high level, the second node P(n) is pulled low, and T4, T7 are turned off.
  • the output terminal G(n) outputs a high level: G(n-1) and CK1 jump to a low level, and CK2 provides a high level; the first node Q(n) is stored due to the storage of the first capacitor C1. Keeping high level, T2 is turned on, the high level of CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and the first node Q(n) is raised to a higher level. Level.
  • the output G(n) outputs a low level: CK3 and G(n+1) Simultaneously providing a high level, the first node Q(n) It is held at a high level; CK2 jumps to a low level, and a low level of CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a low level.
  • the first node Q(n) is pulled low to a constant voltage low level VGL: CK1 provides a high level again, G(n-1) remains low, and T1 turns on the first node Q(n) To constant voltage low level VGL, T6 is cut off.
  • stage 5 the first node Q(n) and the output terminal G(n) are in a low-level sustain phase: CK2 jumps to a high level, and the second node P(n) is charged due to the bootstrap action of the second capacitor C2. To the high level, T4 and T7 are turned on, and the low level of the first node Q(n) and the output terminal G(n) can be maintained.
  • the high and low levels of the output terminal G(n) are mainly realized by the thin film transistor T2. That is, when the first node Q(n) is precharged, when the clock signal CK2 is high, the output terminal G(n) is pulled high through the thin film transistor T2; when the clock signal CK2 is low, the output terminal G is passed through the thin film transistor T2. (n) Pull down.
  • the thin film transistor T2 has a limited charging capability, especially when the number of pixels expressed per inch in the image (Pixel) The higher the Per Inch, PPI), the faster the charging time is shortened, and the output G(n) may not reach the pre-required potential, or the corresponding RC. Delay (RC delay) time is too long, both of which will affect the charging result of the in-plane pixel (Pixel), which will affect the display effect of the LCD panel.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each stage GOA unit including a scan control module, an output module, a pull-down module, and an output adjustment module
  • n be a positive integer
  • the scan control module includes: a first thin film transistor, a third thin film transistor, and a fifth thin film transistor
  • the gate of the first thin film transistor is electrically connected to the first clock signal, and the source is electrically connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, and the drain is electrically connected to the first a third node
  • the gate of the third thin film transistor is electrically connected to the third clock signal, and the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage, and the drain is electrically Connected to the third node
  • the scan control module includes: a first thin film transistor, a third thin film transistor, and a
  • An advantage of the present invention is that the present invention provides LTPS based
  • the GOA circuit of the semiconductor thin film transistor introduces an output adjustment module composed of the ninth, tenth, eleventh, and twelfth thin film transistors T9, T10, T11, and T12, whether in forward scanning or reverse scanning.
  • the level of the fourth node M(n) occurs the same high and low level transitions as the second clock signal CK2 transitions between high and low levels.
  • the high and low levels of the output terminal G(n) are mainly realized by the second thin film transistor T2, and the LTPS based on the present invention is provided.
  • the GOA circuit of the thin film transistor can improve the output capability of the output terminal G(n) to a certain extent in the same time, and improve the charging rate of the in-plane Pixel, thereby improving the display effect of the liquid crystal panel.
  • the GOA circuit provided by the invention can be applied to the field of gate driving of mobile phones, displays and televisions.
  • FIG. 1 is a schematic diagram of a conventional GOA circuit based on an LTPS semiconductor thin film transistor
  • FIG. 2 is a forward scan timing diagram of a conventional LTPS semiconductor thin film transistor-based GOA circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a GOA circuit based on an LTPS semiconductor thin film transistor according to the present invention.
  • FIG. 4 is a timing chart of forward scanning of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 3;
  • FIG. 5 is a reverse scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG.
  • the GOA circuit includes: a plurality of cascaded GOA units, each of which includes a scan control module 32, an output module 34, a pull-down module 36, and an output adjustment module 38.
  • the scan control module 32 includes: a first thin film transistor T1, a third thin film transistor T3, and a fifth thin film transistor
  • the output module 34 includes: a second thin film transistor T2 and a first bootstrap capacitor C1;
  • the pull-down module 36 includes: a fourth thin film transistor T4, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film.
  • the output adjustment module 38 includes a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, and a twelfth thin film transistor T12.
  • the gate of the first thin film transistor T1 is electrically connected to the first clock signal CK1, and the source is electrically connected to the output terminal G of the upper n-1th GOA unit (n- 1), the drain is electrically connected to the third node H(n); the gate of the third thin film transistor T3 is electrically connected to the third clock signal CK3, and the source is electrically connected to the next n+1th GOA
  • the output terminal G(n+1) of the cell is electrically connected to the third node H(n); the gate of the fifth thin film transistor T5 is electrically connected to the constant voltage high level VGH, and the source is electrically connected to
  • the third node H(n) has a drain electrically connected to the first node Q(n).
  • the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), the source is electrically connected to the second clock signal CK2, and the drain is electrically connected to the output terminal G ( n); one end of the first bootstrap capacitor C1 is electrically connected to the first node Q(n), and the other end is electrically connected to the output terminal G(n).
  • the gate of the fourth thin film transistor T4 is electrically connected to the second node P(n)
  • the source is electrically connected to the constant voltage low level VGL, and the drain is electrically connected to the output terminal G(n);
  • the gate of the sixth thin film transistor T6 is electrically connected to the third node H(n), and the source is electrically Connected to the constant voltage low level VGL, the drain is electrically connected to the second node P(n);
  • the gate of the seventh thin film transistor T7 is electrically connected to the second node P(n), and the source is electrically connected a constant voltage low level VGL, the drain is electrically connected to the first node Q(n);
  • the gate of the eighth thin film transistor T8 is electrically connected to the fourth clock signal CK4, and the source is electrically connected to the constant voltage low level VGL, the drain is electrically connected to the output terminal G(n);
  • one end of the second bootstrap capacitor C2 is electrically connected to the second node P(n), and the other end is electrical
  • the gate of the ninth thin film transistor T9 is electrically connected to the second clock signal CK2, the source is electrically connected to the constant voltage high level VGH, and the drain is electrically connected to the fourth node M. (n); the gate of the tenth thin film transistor T10 is electrically connected to the first node Q(n), the source is electrically connected to the fourth node M(n), and the drain is electrically connected to the output terminal G(n)
  • the eleventh thin film transistor T11 has a gate electrically connected to the output terminal G(n-1), the source is electrically connected to the constant voltage low level VGL, and the drain is electrically connected to the fourth node M(n);
  • the gate of the twelfth thin film transistor T12 is electrically connected to the output terminal G(n+1), the source is electrically connected to the constant voltage low level VGL, and the drain is electrically connected to the fourth node M(n).
  • each of the thin film transistors described in the present invention is a low temperature polysilicon semiconductor thin film transistor.
  • the four clock signals of the GOA circuit are: the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are sequentially rotated. Output, and do not overlap each other.
  • the source of the first thin film transistor T1 is electrically connected to the circuit start signal STV; at the final stage GOA In the cell, the source of the third thin film transistor T3 is electrically connected to the circuit start signal STV.
  • LTPS based on the present invention
  • the GOA circuit of the semiconductor thin film transistor can perform forward scanning step by step from the first stage to the last stage, or can perform reverse scanning from the last stage to the first stage step by step.
  • first to the first level GOA First thin film transistor T1 in the cell Providing a first clock signal (ie, CK1 is a high level) and a circuit start signal STV; that is, a first clock signal CK1 and a previous level electrically connected to the first thin film transistor T1 during forward scanning Output G(n-1) of n-1 level GOA unit Also provide a high level.
  • a first clock signal ie, CK1 is a high level
  • STV a circuit start signal
  • the level of the fourth node M(n) occurs when the second clock signal CK2 jumps between high and low levels, whether during forward scanning or reverse scanning. High and low transitions.
  • the output capability of the output terminal G(n) can be improved to some extent in the same time, and the charging rate of the in-plane Pixel can be improved, thereby improving the display effect of the liquid crystal panel.
  • FIG. 4 it is a forward scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. In the forward scan, the working process is:
  • Phase 1, pre-charge the clock signal CK1 and the output terminal G(n-1) both provide a high level, the clock signals CK2, CK3, and CK4 both provide a low level, and the output terminal G(n+1) also provides a low level.
  • first thin film transistor T1 Controlled by the clock signal CK1, the third node H(n) is precharged to a high level, and the sixth thin film transistor T6 controlled by the third node H(n) is turned on; the fifth thin film transistor T5 is subjected to a constant voltage Level VGH The control is always on, so the level of the third node H(n) and the first node Q(n) are always the same, the first node Q(n) is precharged to a high level; the second node P(n) is Pulling down to a constant voltage low level VGL, the fourth and seventh thin film transistors T4, T7 controlled by the second node P(n) At the same time, at the same time, since the output terminal G(n-1) supplies a high level, the eleventh thin film transistor T11 is turned on, and the fourth node M(n) is pulled low.
  • phase 2 output G(n) outputs a high level: the clock signal CK1 and the output terminal G(n-1) both jump to a low level, the clock signal CK2 provides a high level, the clock signals CK3, CK4 and the output end G(n+1) still provides a low level; the first node Q(n) remains high due to the storage action of the first bootstrap capacitor C1; the second thin film transistor T2 Turned on, the high level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and causes the first node Q(n) to be raised to a higher level, Six thin film transistor T6 Still conducting; the second node P(n) maintains a constant voltage low level VGL, and the fourth and seventh thin film transistors T4 and T7 controlled by the second node P(n) are still turned off; meanwhile, the clock signal CK2 is provided high.
  • the ninth thin film transistor T9 is turned on, the constant voltage high level VGH precharges the fourth node M(n) to the constant voltage high level VGH; the tenth thin film transistor T10 is turned on, the fourth node M(n) The high level will charge the output G(n).
  • Phase 3 the output terminal G(n) outputs a low level: the clock signal CK2 jumps to a low level, and the clock signal CK3 and the output terminal G(n+1) both provide a high level, the clock signals CK1, CK4 and the output end.
  • G(n-1) still provides a low level; the third thin film transistor T3 controlled by the clock signal CK3 Turning on; the first node Q(n) is kept at a high level, and the second and sixth thin film transistors T2 and T6 are still turned on; the second node P(n) is still maintained at a constant voltage low level VGL, and is subjected to the second node P.
  • VGL precharges the fourth node M(n) to a constant voltage low level VGL; the tenth thin film transistor T10 is still in an on state, and the low level of the fourth node M(n) also pulls the output low The role of G(n).
  • phase 4 the first node Q(n) is pulled low to a constant voltage low level VGL: the clock signal CK1 is again supplied with a high level, and the clock signals CK2, CK3, CK4 and the output terminal G(n-1) are supplied with a low level; First thin film transistor T1 controlled by clock signal CK1 Turning on, pulling down the first node Q(n) to the constant voltage low level VGL, so that the second and sixth thin film transistors T2, T6 are turned off.
  • Phase 5 the first node Q (n) and the output terminal G (n) low-level maintenance phase: the clock signal CK2 provides a high level again, the clock signal CK1 jumps to a low level, the clock signals CK3, CK4 and the output terminal G(n-1), G(n+1) provide a low level; due to the bootstrap of the second bootstrap capacitor C2, the second node P(n) is charged to a high level, the fourth and seventh thin film transistors T4 , T7 Turned on, causing the first node Q(n) and the output terminal G(n) to remain low.
  • the second thin film transistor T2 is mainly realized, and the charging capacity of the second thin film transistor T2 is limited in a certain period of time, and the present invention provides LTPS
  • the GOA circuit of the thin film transistor in the pre-charging phase of the first node Q(n), passes through the output adjustment module composed of the ninth, tenth, eleventh, twelfth thin film transistors T9, T10, T11, T12, in the same
  • the output capability of the output terminal G(n) can be improved to a certain extent, and the charging rate of the in-plane Pixel can be improved, thereby improving the display effect of the liquid crystal panel.
  • FIG. 5 is a reverse scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 3, since the working processes of the forward and reverse scans are similar, the following describes the operation of the reverse scan.
  • the working process is:
  • Phase 1 pre-charge: both the clock signal CK3 and the output terminal G(n+1) provide a high level, the third thin film transistor T3 is turned on by the control of the clock signal CK3, and the third node H(n) is precharged to a high level.
  • the sixth thin film transistor T6 controlled by the third node H(n) is turned on; the fifth thin film transistor T5 Subject to constant voltage high level VGH The control is always on, so the level of the third node H(n) and the first node Q(n) are always the same, the first node Q(n) is precharged to a high level; the second node P(n) is Pull down to constant voltage low level VGL, fourth and seventh thin film transistors T4, T7 At the same time, at the same time, since the output terminal G(n+1) supplies a high level, the twelfth thin film transistor T12 is turned on, and the fourth node M(n) is pulled low.
  • phase 2 output G(n) outputs a high level: the clock signal CK2 provides a high level, and the first node Q(n) is due to the first bootstrap capacitor C1 The storage function remains high, the second thin film transistor T2 Turned on, the high level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and the first node Q(n) is raised to a higher level; Because the clock signal CK2 provides a high level, the ninth thin film transistor T9 is turned on, the constant voltage high level VGH precharges the fourth node M(n) to the constant voltage high level VGH; the tenth thin film transistor T10 is turned on, The high level of the fourth node M(n) charges the output terminal G(n).
  • Phase 3 the output terminal G(n) outputs a low level: the clock signal CK2 jumps to a low level, and the clock signal CK1 and the output terminal G(n-1) both provide a high level, and the first node Q(n) remains When the level is high, the second thin film transistor T2 is still turned on, and the low level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a low level; meanwhile, since the clock signal CK2 is provided low.
  • the ninth thin film transistor T9 is turned off; since the output terminal G(n-1) supplies a high level, the eleventh thin film transistor T11 is turned on, and the constant voltage low level VGL precharges the fourth node M(n) to The constant voltage low level VGL; the tenth thin film transistor T10 is still in an on state, and the low level of the fourth node M(n) also acts to pull down the output terminal G(n).
  • phase 4 the first node Q(n) is pulled low to a constant voltage low level VGL: the clock signal CK3 provides a high level again, the output terminal G(n+1) provides a low level; the third thin film transistor T3 is turned on, Pull down the first node Q(n) to the constant voltage low level VGL.
  • Phase 5 the first node Q(n) and the output terminal G(n) are maintained at a low level: the clock signal CK2 is again supplied with a high level, and the clock signal CK3 is jumped to a low level; due to the second bootstrap capacitor C2 Bootstrap, the second node P(n) is charged to a high level, and the fourth and seventh thin film transistors T4, T7 Turned on, causing the first node Q(n) and the output terminal G(n) to remain low.
  • the second thin film transistor T2 is mainly realized, and the charging capacity of the second thin film transistor T2 is limited in a certain period of time, and the present invention provides LTPS
  • the GOA circuit of the thin film transistor in the pre-charging phase of the first node Q(n), passes through the output adjustment module composed of the ninth, tenth, eleventh, twelfth thin film transistors T9, T10, T11, T12, in the same
  • the output capability of the output terminal G(n) can be improved to a certain extent, and the charging rate of the in-plane Pixel can be improved, thereby improving the display effect of the liquid crystal panel.
  • the present invention provides LTPS based
  • the GOA circuit of the semiconductor thin film transistor introduces an output adjustment module composed of the ninth, tenth, eleventh, and twelfth thin film transistors T9, T10, T11, and T12, whether in forward scanning or reverse scanning.
  • the level of the fourth node M(n) occurs the same high and low level transitions as the second clock signal CK2 transitions between high and low levels.
  • the high and low levels of the output terminal G(n) are mainly realized by the second thin film transistor T2, and the LTPS based on the present invention is provided.
  • the GOA circuit of the thin film transistor can improve the output capability of the output terminal G(n) to a certain extent in the same time, and improve the charging rate of the in-plane Pixel, thereby improving the display effect of the liquid crystal panel.
  • the GOA circuit provided by the invention can be applied to the field of gate driving of mobile phones, displays and televisions.

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Abstract

基于LTPS半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，每一级GOA单元均包括扫描控制模块（32）、输出模块（34）、下拉模块（36）以及输出调节模块（38）。引入了第九、第十、第十一、第十二薄膜晶体管（T9、T10、T11、T12）组成的输出调节模块（38），无论是在正向扫描时还是反向扫描时，第四节点（M(n)）的电平随着第二时钟信号（CK2）在高、低电平（VGH 、VGL）之间跳变而发生同样的高、低电平跳变。相比于现有技术中输出端（G(n)）的高低电平主要是靠第二薄膜晶体管（T2）来实现，基于LTPS薄膜晶体管的GOA电路，在相同的时间内，一定程度上可以提高输出端（G(n)）的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。

Description

基于LTPS半导体薄膜晶体管的GOA电路 技术领域
本发明涉及液晶显示领域，尤其是涉及一种可以提升GOA电路输出点的输出能力的基于LTPS半导体薄膜晶体管的GOA电路。
 背景技术
GOA（Gate Driver on Array，集成在阵列基板上的行扫描）技术，是利用现有TFT-LCD（Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器）阵列制程将Gate行扫描驱动电路制作在阵列基板上，实现对Gate逐行扫描的驱动方式的一项技术。GOA技术能减少外接IC（Integrated Circuit，集成电路板）的焊接（bonding）工序，有机会提升产能并跳变产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅（Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。而且由于LTPS半导体本身具有超高载流子迁移率的特性，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。
参考图1，现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括级联的多个GOA单元，设n为正整数，第n级GOA单元包括：第一薄膜晶体管T1，其栅极电性连接于第一时钟信号CK1，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点H(n)；第二薄膜晶体管T2，其栅极电性连接于第一节点Q(n)，源极电性连接于第二时钟信号CK2，漏极电性连接于输出端G(n)；第三薄膜晶体管T3，其栅极电性连接于第三时钟信号CK3，漏极电性连接于第三节点H(n)，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)；第四薄膜晶体管T4，其栅极电性连接于第二节点P(n)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电平VGL；第五薄膜晶体管T5，其栅极电性连接于恒压高电平VGH，源极电性连接于第三节点H(n)，漏极电性连接于第一节点Q(n)；第六薄膜晶体管T6，其栅极电性连接于第三节点H(n)，漏极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL；第七薄膜晶体管T7，其栅极电性连接于第二节点P(n)，漏极电性连接于第一节点Q(n)，源极电性连接于恒压低电平VGL；第八薄膜晶体管T8，其栅极电性连接于第二时钟信号CK2，源极电性连接于输出端G(n)，漏极电性连接于恒压低电平VGL；第一电容C1，其一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；第二电容C2，其一端电性连接于第二节点P(n)，另一端电性连接于第二时钟信号CK2。
图1所示的GOA电路既可以正向扫描也可以反向扫描，正、反向扫描的工作过程类似。结合图1与图2，以正向扫描为例进行说明，其中，图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时，其工作过程为：阶段1，预充电：G(n-1)与CK1同时提供高电平，T1导通，T5栅极接恒压高电平VGH因此T5一直处于导通的状态，第三节点H(n)被预充电至高电平，T6导通；第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平，第二节点P(n)被拉低，T4、T7截止。阶段2，输出端G(n)输出高电平：G(n-1)与CK1跳变为低电平，CK2提供高电平；第一节点Q(n)因第一电容C1的存储作用保持高电平，T2导通，CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平。阶段3，输出端G(n)输出低电平：CK3与G(n+1) 同时提供高电平，第一节点Q(n) 被保持在高电平；CK2跳变为低电平，CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平。阶段4，第一节点Q(n)拉低到恒压低电平VGL：CK1再次提供高电平，G(n-1)保持低电平，T1导通拉低第一节点Q(n)至恒压低电平VGL，T6截止。阶段5，第一节点Q(n)及输出端G(n)低电平维持阶段：CK2跳变为高电平，由于第二电容C2的自举作用，第二节点P(n)被充电至高电平，T4、T7导通，可以保持第一节点Q(n)及输出端G(n)的低电平。
在上述现有的GOA电路中， 输出端G(n)的高低电平主要是靠薄膜晶体管T2来实现。即当第一节点Q(n)被预充电以后，时钟信号CK2为高时，通过薄膜晶体管T2将输出端G(n)拉高；时钟信号CK2为低时，通过薄膜晶体管T2将输出端G(n)拉低。而在一定的时间内，薄膜晶体管T2对应的充电能力有限，尤其当在图像中每英寸所表达的像素数目（Pixel Per Inch，PPI）越高时，充电时间急剧缩短，输出端G(n)可能无法达到预先要求的电位，或者对应的RC Delay（RC延迟）时间过长，这两种情况都会影响到面内像素（Pixel）的充电结果，进而影响液晶面板的显示效果。
因此，亟需提供一种新的GOA电路，以提升GOA电路输出点的输出能力。
 技术问题
本发明的目的在于，提供一种基于LTPS半导体薄膜晶体管的GOA电路，与现有的基于LTPS半导体薄膜晶体管的GOA电路相比，在相同的时间内可以提高输出点G(n)的输出能力，提高面内像素的充电率，提高负载能力，进而改善液晶面板的显示效果。
 技术解决方案
为实现上述目的，本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及输出调节模块；设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述第二时钟信号；以及所述输出调节模块包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管；所述第九薄膜晶体管的栅极电性连接于所述第二时钟信号，源极电性连接于所述恒压高电平，漏极电性连接于第四节点；所述第十薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于所述第四节点，漏极电性连接于所述输出端G(n)；所述第十一薄膜晶体管的栅极电性连接于所述输出端G(n-1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述第十二薄膜晶体管的栅极电性连接于所述输出端G(n+1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点。
 有益效果
本发明的优点在于，本发明提供的基于LTPS 半导体薄膜晶体管的GOA电路，引入了第九、第十、第十一、第十二薄膜晶体管T9、T10、T11、T12组成的输出调节模块，无论是在正向扫描时还是反向扫描时，第四节点M(n)的电平随着第二时钟信号CK2在高、低电平之间跳变而发生同样的高、低电平跳变。相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管T2来实现，本发明提供的基于LTPS 薄膜晶体管的GOA电路，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。本发明所提供的GOA电路可应用于手机，显示器，电视的栅极驱动领域。
 附图说明
图1为现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图；
图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图3，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路的示意图；
图4为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图5为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图。
 本发明的最佳实施方式
下面结合附图对本发明提供的基于LTPS半导体薄膜晶体管的GOA电路做详细说明。
参考图3，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块32、输出模块34、下拉模块36以及输出调节模块38。
设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块32包括：第一薄膜晶体管T1、第三薄膜晶体管T3以及第五薄膜晶体管T5；所述输出模块34包括：第二薄膜晶体管T2以及第一自举电容C1；所述下拉模块36包括：第四薄膜晶体管T4、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8以及第二自举电容C2；所述输出调节模块38包括：第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11以及第十二薄膜晶体管T12。
在所述扫描控制模块32中：第一薄膜晶体管T1的栅极电性连接于第一时钟信号CK1，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点H(n)；第三薄膜晶体管T3的栅极电性连接于第三时钟信号CK3，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于第三节点H(n)；第五薄膜晶体管T5的栅极电性连接于恒压高电平VGH，源极电性连接于第三节点H(n)，漏极电性连接于第一节点Q(n)。
在所述输出模块34中：第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第二时钟信号CK2，漏极电性连接于输出端G(n)；第一自举电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)。
在所述下拉模块36中：第四薄膜晶体管T4的栅极电性连接于第二节点P(n) ，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第六薄膜晶体管T6的栅极电性连接于第三节点H(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第二节点P(n)；第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第一节点Q(n)；第八薄膜晶体管T8的栅极电性连接于第四时钟信号CK4，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第二自举电容C2的一端电性连接于第二节点P(n)，另一端电性连接于第二时钟信号CK2。
在所述输出调节模块38中：第九薄膜晶体管T9的栅极电性连接于第二时钟信号CK2，源极电性连接于恒压高电平VGH，漏极电性连接于第四节点M(n)；第十薄膜晶体管T10的栅极电性连接于第一节点Q(n)，源极电性连接于第四节点M(n)，漏极电性连接于输出端G(n)；第十一薄膜晶体管T11的栅极电性连接于输出端G(n-1)，源极电性连接于恒压低电平VGL，漏极电性连接于第四节点M(n)；第十二薄膜晶体管T12的栅极电性连接于输出端G(n+1)，源极电性连接于恒压低电平VGL，漏极电性连接于第四节点M(n)。
具体的，本发明所述的各个薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
具体的，所述的GOA电路的四条时钟信号：所述第一时钟信号CK1、所述第二时钟信号CK2、所述第三时钟信号CK3和所述第四时钟信号CK4的脉冲是依序轮流输出，且互不重叠。
特别地，在第一级GOA 单元中，第一薄膜晶体管T1 的源极电性连接于电路起始信号STV；在最后一级GOA 单元中，第三薄膜晶体管T3 的源极电性连接于电路起始信号STV。本发明所述的基于LTPS 半导体薄膜晶体管的GOA电路既可以从第一级向最后一级逐级进行正向扫描，也可以从最后一级向第一级逐级进行反向扫描。其中，在正向扫描时，首先向第一级GOA 单元中的第一薄膜晶体管T1 提供第一条时钟信号（即CK1为高电平）和电路起始信号STV；也即正向扫描时，与所述第一薄膜晶体管T1电性连接的第一时钟信号CK1和上一级第n-1级GOA单元的输出端G(n-1) 同时提供高电平。反向扫描时，首先向最后一级GOA 单元中的第三薄膜晶体管T3 提供第一条时钟信号（即CK3为高电平）和电路起始信号STV；也即反向扫描时，与所述第三薄膜晶体管电性连接的第三时钟信号CK3和下一级第n+1级GOA单元的输出端G(n+1)同时提供高电平。
本发明所述的基于LTPS 半导体薄膜晶体管的GOA电路，无论是在正向扫描时还是反向扫描时，第四节点M(n)的电平随着第二时钟信号CK2在高、低电平之间跳变而发生同样的高、低电平跳变。与现有技术相比，能够在相同的时间内，一定程度上提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。
参考图4，其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时，其工作过程为：
阶段1、预充电：时钟信号CK1与输出端G(n-1)均提供高电平，时钟信号CK2、CK3、CK4均提供低电平，输出端G(n+1)也提供低电平；第一薄膜晶体管T1 受时钟信号CK1的控制导通，第三节点H(n)被预充电至高电平，受第三节点H(n)控制的第六薄膜晶体管T6导通；第五薄膜晶体管T5 受恒压高电平VGH 的控制始终导通，故第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平；第二节点P(n)被拉低至恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7 截止；同时，由于输出端G(n-1)提供高电平，第十一薄膜晶体管T11导通，第四节点M(n)被拉低。
阶段2、输出端G(n)输出高电平：时钟信号CK1与输出端G(n-1)均跳变为低电平，时钟信号CK2提供高电平，时钟信号CK3、CK4和输出端G(n+1)仍提供低电平；第一节点Q(n)因第一自举电容C1的存储作用保持高电平；第二薄膜晶体管T2 导通，时钟信号CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平，第六薄膜晶体管T6 仍导通；第二节点P(n)保持恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7仍截止；同时，由于时钟信号CK2提供高电平，第九薄膜晶体管T9导通，恒压高电平VGH将第四节点M(n)预充电至恒压高电平VGH；第十薄膜晶体管T10导通，第四节点M(n)的高电平会对输出端G(n)进行充电。
阶段3、输出端G(n)输出低电平：时钟信号CK2跳变为低电平，时钟信号CK3与输出端G(n+1)均提供高电平，时钟信号CK1、CK4及输出端G(n-1)仍提供低电平；受时钟信号CK3控制的第三薄膜晶体管T3 导通；第一节点Q(n)保持高电平，第二、第六薄膜晶体管T2、T6仍导通；第二节点P(n)仍保持恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7仍截止；由于第二薄膜晶体管T2仍导通，时钟信号CK2的低电平输出到输出端G(n)，从而拉低输出端G(n)；同时，由于时钟信号CK2提供低电平，第九薄膜晶体管T9截止；由于输出端G（n+1）提供高电平，第十二薄膜晶体管T12导通，恒压低电平VGL将第四节点M(n)预充电至恒压低电平VGL；第十薄膜晶体管T10仍处于导通的状态，第四节点M(n)的低电平也会起到拉低输出端G(n)的作用。
阶段4，第一节点Q(n)拉低到恒压低电平VGL：时钟信号CK1再次提供高电平，时钟信号CK2、CK3、CK4和输出端G(n-1)提供低电平；受时钟信号CK1控制的第一薄膜晶体管T1 导通，拉低第一节点Q(n)至恒压低电平VGL，使得第二、第六薄膜晶体管T2、T6截止。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段：时钟信号CK2再次提供高电平，时钟信号CK1跳变为低电平，时钟信号CK3、CK4和输出端G(n-1)、G(n+1)提供低电平；由于第二自举电容C2的自举，第二节点P(n)被充电至高电平，第四、第七薄膜晶体管T4、T7 导通，使得第一节点Q(n)及输出端G(n)保持低电平。
相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管T2来实现，而在一定的时间内第二薄膜晶体管T2对应的充电能力有限，本发明提供的基于LTPS 薄膜晶体管的GOA电路，在第一节点Q(n)预充电阶段，通过第九、第十、第十一、第十二薄膜晶体管T9、T10、T11、T12组成的输出调节模块，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。
参考图5，其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图，由于正、反向扫描的工作过程类似，以下简述反向扫描的工作过程。在反向扫描时，其工作过程为：
阶段1、预充电：时钟信号CK3与输出端G(n+1)均提供高电平，第三薄膜晶体管T3受时钟信号CK3的控制导通，第三节点H(n)被预充电至高电平，受第三节点H(n)控制的第六薄膜晶体管T6导通；第五薄膜晶体管T5 受恒压高电平VGH 的控制始终导通，故第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平；第二节点P(n)被拉低至恒压低电平VGL，第四、第七薄膜晶体管T4、T7 截止；同时，由于输出端G(n+1)提供高电平，第十二薄膜晶体管T12导通，第四节点M(n)被拉低。
阶段2、输出端G(n)输出高电平：时钟信号CK2提供高电平，第一节点Q(n)因第一自举电容C1 的存储作用保持高电平，第二薄膜晶体管T2 导通，时钟信号CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平；同时，由于时钟信号CK2提供高电平，第九薄膜晶体管T9导通，恒压高电平VGH将第四节点M(n)预充电至恒压高电平VGH；第十薄膜晶体管T10导通，第四节点M(n)的高电平会对输出端G(n)进行充电。
阶段3、输出端G(n)输出低电平：时钟信号CK2跳变为低电平，时钟信号CK1与输出端G(n-1)均提供高电平，第一节点Q(n)仍为高电平，第二薄膜晶体管T2仍导通，时钟信号CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平；同时，由于时钟信号CK2提供低电平，第九薄膜晶体管T9截止；由于输出端G（n-1）提供高电平，第十一薄膜晶体管T11导通，恒压低电平VGL将第四节点M(n)预充电至恒压低电平VGL；第十薄膜晶体管T10仍处于导通的状态，第四节点M(n)的低电平也会起到拉低输出端G(n)的作用。
阶段4，第一节点Q(n)拉低到恒压低电平VGL：时钟信号CK3再次提供高电平，输出端G(n+1)提供低电平；第三薄膜晶体管T3导通，拉低第一节点Q(n)至恒压低电平VGL。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段：时钟信号CK2再次提供高电平，时钟信号CK3跳变为低电平；由于第二自举电容C2的自举，第二节点P(n)被充电至高电平，第四、第七薄膜晶体管T4、T7 导通，使得第一节点Q(n)及输出端G(n)保持低电平。
相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管T2来实现，而在一定的时间内第二薄膜晶体管T2对应的充电能力有限，本发明提供的基于LTPS 薄膜晶体管的GOA电路，在第一节点Q(n)预充电阶段，通过第九、第十、第十一、第十二薄膜晶体管T9、T10、T11、T12组成的输出调节模块，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。
综上所述，本发明提供的基于LTPS 半导体薄膜晶体管的GOA电路，引入了第九、第十、第十一、第十二薄膜晶体管T9、T10、T11、T12组成的输出调节模块，无论是在正向扫描时还是反向扫描时，第四节点M(n)的电平随着第二时钟信号CK2在高、低电平之间跳变而发生同样的高、低电平跳变。相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管T2来实现，本发明提供的基于LTPS 薄膜晶体管的GOA电路，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。本发明所提供的GOA电路可应用于手机，显示器，电视的栅极驱动领域。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (7)

  1. 一种基于LTPS半导体薄膜晶体管的GOA电路，其中，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及输出调节模块；
    设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
    所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；
    所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；
    所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述第二时钟信号；
    所述输出调节模块包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管；所述第九薄膜晶体管的栅极电性连接于所述第二时钟信号，源极电性连接于所述恒压高电平，漏极电性连接于第四节点；所述第十薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于所述第四节点，漏极电性连接于所述输出端G(n)；所述第十一薄膜晶体管的栅极电性连接于所述输出端G(n-1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述第十二薄膜晶体管的栅极电性连接于所述输出端G(n+1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；以及
    所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠，所述第四节点的电平随着所述第二时钟信号在高、低电平之间跳变而发生同样的高、低电平跳变。
  2. 如权利要求1所述的GOA电路，其中，正向扫描时，与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1) 同时提供高电平；反向扫描时，与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
  3. 一种基于LTPS半导体薄膜晶体管的GOA电路，其中，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及输出调节模块；
    设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
    所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；
    所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；
    所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述第二时钟信号；以及
    所述输出调节模块包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管；所述第九薄膜晶体管的栅极电性连接于所述第二时钟信号，源极电性连接于所述恒压高电平，漏极电性连接于第四节点；所述第十薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于所述第四节点，漏极电性连接于所述输出端G(n)；所述第十一薄膜晶体管的栅极电性连接于所述输出端G(n-1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述第十二薄膜晶体管的栅极电性连接于所述输出端G(n+1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点。
  4. 如权利要求3所述的GOA电路，其中，所述第四节点的电平随着所述第二时钟信号在高、低电平之间跳变而发生同样的高、低电平跳变。
  5. 如权利要求3所述的GOA电路，其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠。
  6. 如权利要求3所述的GOA电路，其中，正向扫描时，与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1) 同时提供高电平；反向扫描时，与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
  7. 如权利要求3所述的GOA电路，其中，所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
PCT/CN2016/085598 2016-05-18 2016-06-13 基于ltps半导体薄膜晶体管的goa电路 Ceased WO2017197684A1 (zh)

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