WO2017193647A1 - 显示装置和驱动装置 - Google Patents

显示装置和驱动装置 Download PDF

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Publication number
WO2017193647A1
WO2017193647A1 PCT/CN2017/072807 CN2017072807W WO2017193647A1 WO 2017193647 A1 WO2017193647 A1 WO 2017193647A1 CN 2017072807 W CN2017072807 W CN 2017072807W WO 2017193647 A1 WO2017193647 A1 WO 2017193647A1
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WO
WIPO (PCT)
Prior art keywords
gate
gate control
output pin
line
lines
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PCT/CN2017/072807
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English (en)
French (fr)
Inventor
李鹏涛
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/534,244 priority Critical patent/US20180203274A1/en
Publication of WO2017193647A1 publication Critical patent/WO2017193647A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133308—Support structures for LCD panels, e.g. frames or bezels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display device and a driving device.
  • the gate control line and the data line are connected to different sides of the driving circuit, and the gate control line is mainly connected to both sides of the driving circuit, resulting in the sector area on both sides of the display panel. Larger, so that the frame of the display device is wider.
  • One of the objects of the present invention is to provide a display device and a driving device for enabling the display device to implement a narrow bezel.
  • the present invention provides a display device including: a driving device and a display panel, the display panel including a gate control line, a plurality of gate lines, and a plurality of data lines, the plurality of gate lines and The plurality of data lines intersect to define a pixel unit, and the driving device comprises a driving circuit and a gate output pin and a source output pin disposed on the driving circuit;
  • connection end of the data line is connected to the corresponding source output pin
  • the gate line is connected to the corresponding gate control line, the connection end of the gate control line is connected to the corresponding gate output pin, and the connection end of the gate control line and the data
  • the connection ends of the wires are connected to the same side of the drive circuit.
  • connection end of the gate control line is connected to a side of the driving circuit close to the display panel, and a connection end of the data line is connected to a side of the driving circuit close to the display panel side.
  • the gate output pin and the source output pin are both disposed on a side of the driving circuit adjacent to the display panel.
  • the gate line and the gate control line are disposed in the same layer.
  • the gate control line is disposed in parallel with the data line.
  • the gate lines are sequentially arranged, and the gate control lines connected to the gate lines are sequentially arranged.
  • the gate lines are sequentially arranged, and the gate control lines connected to the gate lines are arranged according to a shape of the display panel instead of sequentially.
  • the gate control line is disposed in parallel with the data line, and the gate control line and the data line are alternately disposed.
  • the gate control line is disposed in parallel with the data line, and one of the gate control lines is disposed every plurality of the data lines.
  • the display panel is a special-shaped display panel.
  • the present invention further provides a driving device for a display device, the display device comprising a display panel, the display panel comprising a gate control line, a plurality of gate lines and a plurality of data lines, the plurality of The gate line and the plurality of data lines intersect to define a pixel unit, and the driving device comprises: a driving circuit and a gate output pin and a source output pin disposed on the driving circuit;
  • the gate data pin is used to connect a connection end of a corresponding gate control line, and the gate control line is used to connect a corresponding gate line;
  • the source output pin is used to connect a connection end of a corresponding data line, and a connection end of the gate control line and a connection end of the data line are connected to a same side of the driving circuit.
  • the gate output pin and the source output pin are connected to a side of the driving circuit close to the display panel.
  • the gate output pin and the source output pin are alternately arranged.
  • a gate output pin is provided every several source output pins.
  • connection end of the data line is connected with the corresponding source output pin
  • the gate line is connected with the corresponding gate control line
  • the gate control The connection end of the line is connected to the corresponding gate output pin
  • the connection end of the gate control line and the connection end of the data line are connected to the same side of the drive circuit, that is, the side of the drive circuit close to the display panel, avoiding the gate
  • the connection end of the pole control line and the connection end of the data line are connected to different sides of the driving circuit, thereby reducing the sector area on both sides of the display panel, thereby making the display
  • the device implements a narrow bezel.
  • FIG. 1 is a schematic structural view of a liquid crystal display device
  • FIG. 2 is a schematic structural diagram of a display device according to a first embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a gate output pin and a source output pin in the first embodiment
  • FIG. 5 is a schematic structural diagram of a display device according to a second embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a display device according to a third embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a display device according to a fourth embodiment of the present invention.
  • the liquid crystal display device includes a driving circuit 1 and a display panel 2.
  • the display panel 2 includes a plurality of gate control lines, a plurality of gate lines, and a plurality of pieces of data.
  • a line, a plurality of gate lines and a plurality of data lines define a pixel unit 3
  • the pixel unit 3 includes a thin film transistor 31 and a pixel electrode 32
  • the plurality of gate lines include gate lines G1, G2, G3, ..., Gn, and a plurality of data lines
  • the line includes s1, S2, S3, S4, ..., Sn
  • the plurality of gate control lines include G1', G2', G3', ..., Gn', wherein only the gate line G1 is shown in FIG. G2, G3, data lines S1, S2, S3, S4 and gate control lines G1', G2', G3'.
  • the gate control line is drawn by a broken line, the gate line is connected to the driving circuit 1 through the corresponding gate control line, and the gate control line is connected to the driving.
  • the gate control line forms a sector (fanout area) on the left side of the display panel 2.
  • the data line is connected to the side of the drive circuit 1 close to the pixel unit 3.
  • the drive circuit 1 of the prior art adopts a one-chip structure. Therefore, the drive circuit 1 can drive the gate of the thin film transistor 31 through the gate line and drive the source of the thin film transistor through the data line.
  • the gate control line can also be located on the right side of the drive circuit 1, which is not specifically shown.
  • the gate control line and the data line are connected to different sides of the driving circuit 1, and the gate control line is mainly connected to the left and right sides of the driving circuit 1, resulting in the display panel 2
  • the area of the left and right sides of the sector is large, so that the frame of the display device is wider.
  • the display device includes: a driving device and a display panel 2.
  • the display panel 2 includes a gate control line and a plurality of gates.
  • the line and the plurality of data lines, the plurality of gate lines and the plurality of data lines intersect to define the pixel unit 3, and the driving device comprises the driving circuit 1 and the gate output pin and the source output pin disposed on the driving circuit 1, the data
  • the connection end of the line is connected to the corresponding source output pin
  • the gate line is connected to the corresponding gate control line
  • the connection end of the gate control line is connected to the corresponding gate output pin
  • the connection end of the gate control line is connected to the corresponding gate output pin
  • the connection end with the data line is connected to the same side of the drive circuit 1, that is, the side of the drive circuit 1 close to the display panel 2, wherein the connection end of the data line is the source output of the data line and the drive circuit 1.
  • One end of the pin connection, and the connection end of the gate control line is one end of the gate
  • the plurality of gate lines may include gate lines G1, G2, G3, ..., Gn, and the plurality of data lines include S1, S2, S3, S4, ..., Sn, wherein only the gate is in FIG.
  • Lines G1, G2, G3 and data lines S1, S2, S3, and S4 are described as an example.
  • the gate control line and the gate line are correspondingly disposed.
  • each gate line corresponds to one gate control line, so the number of gate control lines is multiple, and the plurality of gate control lines may include G1', G2', G3', ..., Gn', wherein, in Fig. 2, only G1', G2', G3' are taken as an example for description.
  • FIG. 2 As can be seen from FIG.
  • the gate line G1 corresponds to the gate control line G1'
  • the gate line G1 is connected to the corresponding gate control line G1'
  • the gate control line G1' is connected to the gate output pin, thereby realizing the gate.
  • the line G1 is connected to the driving circuit 1 through the corresponding gate control line G1' and the gate output pin
  • the gate line G2 corresponds to the gate control line G2'
  • the gate line G2 is connected to the corresponding gate control line G2'.
  • the pole control line G2' is connected to the gate output pin of the driving circuit 1, so that the gate line G2 is connected to the driving circuit 1 through the corresponding gate control line G2' and the gate output pin; the gate line G3 and the gate control Corresponding to the line G3', the gate line G3 is connected to the corresponding gate control line G3', and the gate control line G3' is connected to the gate output pin of the driving circuit 1, thereby implementing the gate line G3 through the corresponding gate control line G3. 'and the gate output pin is connected to the drive circuit 1.
  • the gate control line is drawn by a broken line.
  • the driving circuit 1 is provided with four sides, the connecting end of the data line is connected to the side close to the display panel 2, and the connecting end of the gate control line is also connected to the side close to the display panel 2, That is, the connection end of the gate control line and the connection end of the data line are connected to the drive circuit 1 The same side.
  • the gate lines and the gate control lines are disposed in the same layer.
  • the gate control lines can be formed synchronously during the process of fabricating the gate lines so that the gate lines and the gate control lines are disposed in the same layer, thereby reducing manufacturing costs.
  • the gate control line is disposed in parallel with the data line.
  • a plurality of data lines are arranged in parallel, and a plurality of gate control lines are arranged in parallel, and the gate control lines and the data lines are also arranged in parallel. This arrangement facilitates the arrangement of the gate control lines, thereby reducing the complexity of the wiring in the display panel.
  • the gate lines are sequentially arranged, and the gate control lines connected to the gate lines are sequentially arranged.
  • the gate lines G1, G2, G3 are arranged in order from top to bottom, and the gate lines are arranged in parallel, and the gate control lines G1', G2', G3' are arranged in order from left to right.
  • the gate control line and the data line are alternately arranged. As shown in Fig. 2, the gate control line and the data line are arranged in the order of the gate control line G1', the data line S1, the gate control line G2', the data line S2, the gate control line G3', and the data line S3.
  • FIG. 3 is a schematic diagram of a gate output pin and a source output pin in the first embodiment.
  • the drive circuit 1 is provided with a gate output pin and a source output pin, and the gate output is provided.
  • the pin and source output pins are located on the same side of the drive circuit 1, that is, on the side close to the display panel 2.
  • the number of gate output pins is the same as the number of gate control lines
  • the number of source output pins is the same as the number of data lines.
  • the gate output pin may include gate output pins L1, L2, L3, ..., Ln
  • the source output pin may include source output pins M1, M2, M3, ..., Mn, only in FIG.
  • each gate control line corresponds to one gate output pin
  • each data line corresponds to one source output pin.
  • the gate output pin L1 corresponds to the gate.
  • Control line G1', gate output pin L2 corresponds to gate control line G2'
  • gate output pin L3 corresponds to gate control line G3'
  • source output pin M1 corresponds to data line S1
  • source output The pin M2 corresponds to the data line S2
  • the source output pin M3 corresponds to the data line S3.
  • the gate control line G1' is connected to the gate output pin L1, so that the gate control line G1' is connected to the driving circuit 1 through the corresponding gate output pin L1; the gate control line G2' and the gate output pin L2 is connected, so that the gate control line G2' is connected to the driving circuit 1 through the corresponding gate output pin L2; the gate control line G3' is connected to the gate output pin L3, thereby realizing the gate
  • the control line G3' is connected to the drive circuit 1 through the corresponding gate output pin L3.
  • the data line S1 is connected to the source output pin M1, so that the data line S1 is connected to the driving circuit 1 through the corresponding source output pin M1; the data line S2 is connected to the source output pin M2, thereby implementing the data line S2.
  • the corresponding source output pin M2 is connected to the driving circuit 1; the data line S3 is connected to the source output pin M3, so that the data line S3 is connected to the driving circuit 1 through the corresponding source output pin M3.
  • the gate output pin is located on a side of the driving circuit 1 close to the display panel 2, so that the gate control line is connected to one of the driving circuit 1 close to the display panel 2.
  • the source output pin is located on the side of the drive circuit 1 adjacent to the display panel 2 so that the data line is connected to the side of the drive circuit 1 close to the display panel 2.
  • the gate output pin and the source output pin are alternately arranged. As shown in FIG. 3, the gate output pin and the source output pin are left to right according to the gate output pin L1, the source output pin M1, the gate output pin L2, and the source output pin M2. The order of the gate output pin L3 and the source output pin M3 is set. This arrangement makes the connection between the gate line and the gate control line more convenient, thereby simplifying the structure of the display panel and reducing the process complexity.
  • the pixel unit 3 includes a thin film transistor 31 and a pixel electrode 32.
  • the thin film transistor 31 may include a gate electrode, an active layer, a source and a drain, a gate line connected to a gate of the corresponding thin film transistor 31, and a data line connected to a source of the corresponding thin film transistor 31.
  • the pixel electrode 32 is connected to the drain of the thin film transistor 31.
  • the driving circuit 1 adopts a one-chip structure, and the driving circuit 1 integrates the functions of the gate driving circuit and the source driving circuit, so that the driving circuit 1 can drive the thin film transistor 31 through the gate line.
  • the gate and the source of the thin film transistor are driven through the data line.
  • the display device further includes a timing controller 4 for outputting a timing control signal to the driving circuit 1.
  • FIG. 4 is another schematic structural view of the display device in the first embodiment. As shown in FIG. 4, the gate lines G1, G2, and G3 are sequentially arranged from top to bottom, and the gate control lines G1', G2', and G3' are arranged. Arranged from right to left.
  • the display device is a liquid crystal display device.
  • the display device can be applied to the vehicle-mounted field, that is, the display device can be an in-vehicle display device.
  • connection end of the data line and the corresponding The source output pin is connected, the gate line is connected to the corresponding gate control line, the connection end of the gate control line is connected to the corresponding gate output pin, and the connection end of the gate control line is connected to the connection end of the data line to
  • the same side of the driving circuit that is, the side of the driving circuit close to the display panel, prevents the connection end of the gate control line and the connection end of the data line from being connected to different sides of the driving circuit, and lowering the sectors on both sides of the display panel
  • the area is such that the display device achieves a narrow bezel.
  • the embodiment further enables the display device to achieve no borders.
  • the wiring of the gate control line is simple, the process complexity is reduced, and the display device has high yield and high reliability.
  • FIG. 5 is a schematic structural diagram of a display device according to a second embodiment of the present invention. As shown in FIG. 5, the difference between this embodiment and the first embodiment is that the gate control line connected to the gate line is displayed according to the display. The shapes of the panels 2 are arranged instead of sequentially.
  • the display panel 2 may be a special-shaped display panel.
  • the display panel 2 when the shape of the display panel 2 is a non- (long) square, the display panel 2 may be referred to as a shaped display panel.
  • the shape of the display panel 2 shown in FIG. 5 is an inverted trapezoid.
  • the gate control lines G1', G2', and G3' are taken as an example.
  • the gate control line G1' is connected to the gate line G1
  • the gate control line G2' is connected to the gate line G2.
  • the gate control line G3' is connected to the gate line G3, and the gate control line is disposed from left to right in the order of the gate control line G1', the gate control line G3', and the gate control line G2'.
  • connection end of the data line is connected to the corresponding source output pin
  • the gate line is connected to the corresponding gate control line
  • the connection end of the gate control line and the corresponding gate are connected.
  • the output pin is connected, and the connection end of the gate control line and the connection end of the data line are connected to the same side of the driving circuit, that is, the side of the driving circuit close to the display panel, avoiding the connection end and the data line of the gate control line
  • the connection ends are connected to different sides of the drive circuit, reducing the sector area on both sides of the display panel, thereby enabling the display device to achieve a narrow bezel.
  • the display device can also realize the display of the shaped frame.
  • the wiring of the gate control line is simple, the process complexity is reduced, and the display device has high yield and high reliability.
  • FIG. 6 is a schematic structural diagram of a display device according to a third embodiment of the present invention. As shown in FIG. 6, the difference between the present embodiment and the second embodiment is that the shape of the display panel 2 is semicircular.
  • connection end of the data line is connected to the corresponding source output pin
  • the gate line is connected to the corresponding gate control line
  • the connection end of the gate control line is connected.
  • the connection end of the gate control line and the connection end of the data line are connected to the same side of the driving circuit, that is, the side of the driving circuit close to the display panel, avoiding the gate control line
  • the connection end of the connection end and the data line are connected to different sides of the drive circuit, which reduces the sector area on both sides of the display panel, thereby enabling the display device to implement a narrow bezel.
  • the embodiment further enables the display device to achieve no borders.
  • the wiring of the gate control line is simple, the process complexity is reduced, and the display device has high yield and high reliability.
  • FIG. 7 is a schematic structural diagram of a display device according to a fourth embodiment of the present invention. As shown in FIG. 7, the difference between this embodiment and the first embodiment is that a gate control is set every plurality of data lines. Line, one gate output pin is set every several source output pins.
  • a gate output pin is placed every two source output pins.
  • the source output pin and the gate output pin in Figure 7 follow the source output pin from left to right.
  • M1, source output pin M2, gate output pin L1, source output pin M3, source output pin M4, and gate output pin L2 are sequentially set.
  • gate lines G1 and G2 and the gate control lines G1' and G2' are shown in the display panel 2 in Fig. 7, and the rest of the structures are not specifically shown.
  • the set position and number of the gate output pin and the source output pin can be determined according to the resolution of the display device. Therefore, the position and number of setting of the gate output pin and the source output pin in different resolution display devices can be different.
  • connection end of the data line is connected to the corresponding source output pin
  • the gate line is connected to the corresponding gate control line
  • the connection end of the gate control line and the corresponding gate are connected.
  • the output pin is connected, and the connection end of the gate control line and the connection end of the data line are connected to the same side of the driving circuit, that is, the side of the driving circuit close to the display panel, avoiding the connection end and the data line of the gate control line
  • the connection ends are connected to different sides of the drive circuit, reducing the sector area on both sides of the display panel, thereby enabling the display device to achieve a narrow bezel.
  • the embodiment further enables the display device to achieve no borders.
  • the wiring of the gate control line is simple, the process complexity is reduced, and the display device has high yield and high reliability.
  • a fifth embodiment of the present invention provides a driving device.
  • the driving device includes: a driving circuit 1 and a gate output pin and a source output pin disposed on the driving circuit 1.
  • a gate data pin is used to connect a connection end of a corresponding gate control line
  • the gate control line is used to connect a corresponding gate line
  • the source output pin is used to connect a corresponding data line connection
  • the connection end of the gate control line and the connection end of the data line are connected to the same side of the driving circuit 1.
  • the gate output pin is used to connect with the corresponding gate control line; the source output pin is used to connect with the corresponding data line.
  • the number of gate output pins is the same as the number of gate control lines, and the number of source output pins is the same as the number of data lines.
  • the gate output pin may include gate output pins L1, L2, L3, ..., Ln, and the source output pin may include source output pins M1, M2, M3, ..., Mn, only in FIG.
  • the gate output pins L1, L2, and L3 and the source output pins M1, M2, and M3 are taken as an example for description.
  • the gate output pin and the source output pin are alternately arranged. As shown in FIG. 3, the gate output pin and the source output pin are left to right according to the gate output pin L1, the source output pin M1, the gate output pin L2, and the source output pin M2. The order of the gate output pin L3 and the source output pin M3 is set. This arrangement makes the connection between the gate line and the gate control line more convenient, thereby simplifying the structure of the display panel and reducing the process complexity.
  • a gate output pin is provided every several source output pins, which is not specifically drawn.
  • connection end of the data line is connected to the corresponding source output pin
  • the gate line is connected to the corresponding gate control line
  • the connection end of the gate control line and the corresponding gate are connected.
  • the output pin is connected, and the connection end of the gate control line and the connection end of the data line are connected to the same side of the driving circuit, that is, the side of the driving circuit close to the display panel, avoiding the connection end and the data line of the gate control line
  • connection ends are connected to different sides of the drive circuit, reducing the sector area on both sides of the display panel connected to the drive device, thereby enabling the display device using the drive device to achieve a narrow bezel.

Abstract

一种显示装置和一种驱动装置，该显示装置包括：驱动装置和显示面板（2），所述显示面板（2）包括栅极控制线、多条栅线和多条数据线，所述多条栅线和所述多条数据线交叉限定出像素单元（3），所述驱动装置包括驱动电路（1）和设置于所述驱动电路（1）上的栅极输出引脚和源极输出引脚；所述数据线的连接端与对应的所述源极输出引脚连接，所述栅线与对应的所述栅极控制线连接，所述栅极控制线的连接端与对应的所述栅极输出引脚连接，且所述栅极控制线的连接端与所述数据线的连接端连接至所述驱动电路（1）的同一侧；避免了栅极控制线的连接端和数据线的连接端连接至所述驱动电路（1）的不同侧，降低了显示面板（2）两侧的扇区面积，从而使得显示装置实现窄边框。

Description

显示装置和驱动装置 技术领域
本发明涉及显示技术领域，特别涉及显示装置和驱动装置。
背景技术
随着显示技术的发展，液晶显示装置的应用越来越广泛。但是，现有技术的方案存在如下技术问题：栅极控制线与数据线连接于驱动电路的不同侧，栅极控制线主要连接于驱动电路的两侧，导致显示面板的两侧的扇区面积较大，从而使得显示装置的边框较宽。
发明内容
本发明的目的之一是提供一种显示装置和一种驱动装置，用于使得所述显示装置实现窄边框。
为实现上述目的，本发明提供了一种显示装置，包括：驱动装置和显示面板，所述显示面板包括栅极控制线、多条栅线和多条数据线，所述多条栅线和所述多条数据线交叉限定出像素单元，所述驱动装置包括驱动电路和设置于驱动电路上的栅极输出引脚和源极输出引脚；
所述数据线的连接端与对应的所述源极输出引脚连接，
所述栅线与对应的所述栅极控制线连接，所述栅极控制线的连接端与对应的所述栅极输出引脚连接，且所述栅极控制线的连接端与所述数据线的连接端连接至所述驱动电路的同一侧。
可选地，所述栅极控制线的连接端连接至所述驱动电路的靠近所述显示面板的一侧，所述数据线的连接端连接至所述驱动电路的靠近所述显示面板的一侧。
可选地，所述栅极输出引脚和源极输出引脚均设置于所述驱动电路的靠近所述显示面板的一侧。
可选地，所述栅线和所述栅极控制线同层设置。
可选地，所述栅极控制线与所述数据线平行设置。
可选地，所述栅线顺序排列，与所述栅线连接的所述栅极控制线顺序排列。
可选地，所述栅线顺序排列，与所述栅线连接的所述栅极控制线根据所述显示面板的形状而非顺序地排列。
可选地，所述栅极控制线与所述数据线平行设置，且所述栅极控制线和所述数据线交替设置。
可选地，所述栅极控制线与所述数据线平行设置，且每隔多条所述数据线设置一条所述栅极控制线。
可选地，所述显示面板为异形显示面板。
为实现上述目的，本发明还提供了一种显示装置的驱动装置，所述显示装置包括显示面板，所述显示面板包括栅极控制线、多条栅线和多条数据线，所述多条栅线和所述多条数据线交叉限定出像素单元，所述驱动装置包括：驱动电路以及设置于驱动电路上的栅极输出引脚和源极输出引脚；
所述栅极数据引脚用于连接对应的栅极控制线的连接端，所述栅极控制线用于连接对应的栅线；
所述源极输出引脚用于连接对应的数据线的连接端，所述栅极控制线的连接端与所述数据线的连接端连接至所述驱动电路的同一侧。
可选地，所述栅极输出引脚和源极输出引脚连接至所述驱动电路的靠近所述显示面板的一侧。
可选地，所述栅极输出引脚和所述源极输出引脚交替设置。
可选地，每隔多个源极输出引脚设置一个栅极输出引脚。
本发明具有以下有益效果：本发明提供的显示装置和驱动装置的技术方案中，数据线的连接端与对应的源极输出引脚连接，栅线与对应的栅极控制线连接，栅极控制线的连接端与对应的栅极输出引脚连接，栅极控制线的连接端与数据线的连接端连接至驱动电路的同一侧，即，驱动电路的靠近显示面板的一侧，避免了栅极控制线的连接端和数据线的连接端连接至驱动电路的不同侧，降低了显示面板两侧的扇区面积，从而使得显示 装置实现窄边框。
附图说明
图1为一种液晶显示装置的结构示意图；
图2为本发明的第一实施例提供的一种显示装置的结构示意图；
图3为第一实施例中的栅极输出引脚和源极输出引脚的示意图；
图4为第一实施例中的显示装置的另一种结构示意图；
图5为本发明的第二实施例提供的一种显示装置的结构示意图；
图6为本发明的第三实施例提供的一种显示装置的结构示意图；
图7为本发明的第四实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的显示装置和驱动装置进行详细描述。
图1为一种液晶显示装置的结构示意图，如图1所示，该液晶显示装置包括驱动电路1和显示面板2，显示面板2包括多条栅极控制线、多条栅线和多条数据线，多条栅线和多条数据线限定出像素单元3，像素单元3包括薄膜晶体管31和像素电极32，多条栅线包括栅线G1、G2、G3、……、Gn，多条数据线包括s1、S2、S3、S4、……、Sn，多条栅极控制线包括G1’、G2’、G3’、……、Gn’，其中，图1中仅示出了栅线G1、G2、G3、数据线S1、S2、S3、S4以及栅极控制线G1’、G2’、G3’。图1中为了清楚地表示出栅极控制线和栅线的区别，将栅极控制线用虚线画出，栅线通过对应的栅极控制线与驱动电路1连接，栅极控制线连接至驱动电路1的左侧，则栅极控制线在显示面板2的左侧形成扇区(fanout区)。数据线连接至驱动电路1的靠近像素单元3的一侧。现有技术中的驱动电路1采用一个芯片(one-chip)的结构，因此，驱动电路1可通过栅线驱动薄膜晶体管31的栅极以及通过数据线驱动薄膜晶体管的源极。类似地，栅极控制线还可以位于驱动电路1的右侧，此种情况不再具体画出。
但是，上述技术方案中，栅极控制线与数据线连接于驱动电路1的不同侧，栅极控制线主要连接于驱动电路1的左右两侧，导致显示面板2 的左右两侧的扇区面积较大，从而使得显示装置的边框较宽。
图2为本发明的第一实施例提供的一种显示装置的结构示意图，如图2所示，该显示装置包括：驱动装置和显示面板2，显示面板2包括栅极控制线、多条栅线和多条数据线，多条栅线和多条数据线交叉限定出像素单元3，驱动装置包括驱动电路1和设置于驱动电路1上的栅极输出引脚和源极输出引脚，数据线的连接端与对应的源极输出引脚连接，栅线与对应的栅极控制线连接，栅极控制线的连接端与对应的栅极输出引脚连接，且栅极控制线的连接端与数据线的连接端连接至驱动电路1的同一侧，即，驱动电路1的靠近显示面板2的一侧，其中，数据线的连接端为数据线的用于与驱动电路1的源极输出引脚连接的一端，栅极控制线的连接端为栅极控制线的用于与驱动电路1的栅极输出引脚连接的一端。
本实施例中，多条栅线可包括栅线G1、G2、G3、……、Gn，多条数据线包括S1、S2、S3、S4、……、Sn，其中，图2中仅以栅线G1、G2、G3以及数据线S1、S2、S3、S4为例进行描述。栅极控制线和栅线对应设置，优选地，每一条栅线对应于一条栅极控制线，因此栅极控制线的数量为多条，多条栅极控制线可包括G1’、G2’、G3’、……、Gn’，其中，图2中仅以G1’、G2’、G3’为例进行描述。从图2可以看出，栅线G1和栅极控制线G1’对应，栅线G1和对应的栅极控制线G1’连接，栅极控制线G1’和栅极输出引脚连接，从而实现栅线G1通过对应的栅极控制线G1’和栅极输出引脚与驱动电路1连接；栅线G2和栅极控制线G2’对应，栅线G2和对应的栅极控制线G2’连接，栅极控制线G2’和驱动电路1的栅极输出引脚连接，从而实现栅线G2通过对应的栅极控制线G2’和栅极输出引脚与驱动电路1连接；栅线G3和栅极控制线G3’对应，栅线G3和对应的栅极控制线G3’连接，栅极控制线G3’和驱动电路1的栅极输出引脚连接，从而实现栅线G3通过对应的栅极控制线G3’和栅极输出引脚与驱动电路1连接。图2中为了清楚地表示出栅极控制线和栅线的区别，将栅极控制线用虚线画出。
如图2所示，驱动电路1具备四个侧边，数据线的连接端连接至其靠近显示面板2的一侧，栅极控制线的连接端也连接至其靠近显示面板2的一侧，即，栅极控制线的连接端与数据线的连接端连接至驱动电路1的 同一侧。
优选地，栅线和栅极控制线同层设置。在制造栅线的过程中可同步形成栅极控制线，以使得栅线和栅极控制线同层设置，从而降低了制造成本。
优选地，栅极控制线与数据线平行设置。本实施例中，多条数据线之间平行设置，多条栅极控制线之间平行设置，而栅极控制线和数据线之间也平行设置。此种设置方式便于栅极控制线的排布，从而降低了显示面板中的布线的复杂度。
本实施例中，栅线顺序排列，与栅线连接的栅极控制线顺序排列。如图2所示，栅线G1、G2、G3从上至下顺序排列，且栅线之间平行设置，栅极控制线G1’、G2’、G3’从左至右顺序排列。
本实施例中，栅极控制线和数据线交替设置。如图2所示，栅极控制线和数据线按照栅极控制线G1’、数据线S1、栅极控制线G2’、数据线S2、栅极控制线G3’、数据线S3的顺序设置。
图3为第一实施例中的栅极输出引脚和源极输出引脚的示意图，如图3所示，驱动电路1上设置有栅极输出引脚和源极输出引脚，栅极输出引脚和源极输出引脚位于驱动电路1的同一侧，即其靠近显示面板2的一侧。优选地，栅极输出引脚的数量和栅极控制线的数量相同，源极输出引脚的数量和数据线的数量相同。栅极输出引脚可包括栅极输出引脚L1、L2、L3、……、Ln，源极输出引脚可包括源极输出引脚M1、M2、M3、……、Mn，图3中仅以栅极输出引脚L1、L2、L3以及源极输出引脚M1、M2、M3为例进行描述。优选地，每一条栅极控制线对应于一个栅极输出引脚，每一条数据线对应于一个源极输出引脚，如图2和图3所示，栅极输出引脚L1对应于栅极控制线G1’，栅极输出引脚L2对应于栅极控制线G2’，栅极输出引脚L3对应于栅极控制线G3’，源极输出引脚M1对应于数据线S1，源极输出引脚M2对应于数据线S2，源极输出引脚M3对应于数据线S3。栅极控制线G1’和栅极输出引脚L1连接，从而实现栅极控制线G1’通过对应的栅极输出引脚L1和驱动电路1连接；栅极控制线G2’和栅极输出引脚L2连接，从而实现栅极控制线G2’通过对应的栅极输出引脚L2和驱动电路1连接；栅极控制线G3’和栅极输出引脚L3连接，从而实现栅极 控制线G3’通过对应的栅极输出引脚L3和驱动电路1连接。数据线S1和源极输出引脚M1连接，从而实现数据线S1通过对应的源极输出引脚M1和驱动电路1连接；数据线S2和源极输出引脚M2连接，从而实现数据线S2通过对应的源极输出引脚M2和驱动电路1连接；数据线S3和源极输出引脚M3连接，从而实现数据线S3通过对应的源极输出引脚M3和驱动电路1连接。如图2和图3所示，本实施例中，栅极输出引脚位于驱动电路1的靠近显示面板2的一侧，以便于栅极控制线连接至驱动电路1的靠近显示面板2的一侧；源极输出引脚位于驱动电路1的靠近显示面板2的一侧，以便于数据线连接至驱动电路1的靠近显示面板2的一侧。
本实施例中，栅极输出引脚和源极输出引脚交替设置。如图3所示，栅极输出引脚和源极输出引脚从左至右按照栅极输出引脚L1、源极输出引脚M1、栅极输出引脚L2、源极输出引脚M2、栅极输出引脚L3、源极输出引脚M3的顺序设置。此种设置方式使得栅线和栅极控制线之间的连线更加方便，从而简化了显示面板的结构，降低了工艺复杂度。
本实施例中，像素单元3包括薄膜晶体管31和像素电极32。薄膜晶体管31可包括栅极、有源层、源极和漏极，栅线和对应的薄膜晶体管31的栅极连接，数据线和对应的薄膜晶体管31的源极连接。像素电极32与薄膜晶体管31的漏极连接。
本实施例中，驱动电路1采用一个芯片(one-chip)的结构，该驱动电路1集成了栅极驱动电路和源极驱动电路的功能，因此该驱动电路1可通过栅线驱动薄膜晶体管31的栅极以及通过数据线驱动薄膜晶体管的源极。
进一步地，该显示装置还包括时序控制器4，该时序控制器4用于向驱动电路1输出时序控制信号。
图4为第一实施例中的显示装置的另一种结构示意图，如图4所示，栅线G1、G2、G3从上至下顺序排列，栅极控制线G1’、G2’、G3’从右至左顺序排列。
优选地，本实施例中，显示装置为液晶显示装置。在实际应用中，显示装置可应用于车载领域，即，显示装置可以为车载显示装置。
本实施例提供的显示装置的技术方案中，数据线的连接端与对应的 源极输出引脚连接，栅线与对应的栅极控制线连接，栅极控制线的连接端与对应的栅极输出引脚连接，栅极控制线的连接端与数据线的连接端连接至驱动电路的同一侧，即，驱动电路的靠近显示面板的一侧，避免了栅极控制线的连接端和数据线的连接端连接至驱动电路的不同侧，降低了显示面板两侧的扇区面积，从而使得显示装置实现窄边框。本实施例进一步还可以使得显示装置实现无边框。本实施例的显示装置中，栅极控制线的布线简单，降低了工艺复杂度，从而使得显示装置的良率高且可靠性高。
图5为本发明的第二实施例提供的一种显示装置的结构示意图，如图5所示，本实施例与上述第一实施例的区别在于，与栅线连接的栅极控制线根据显示面板2的形状而非顺序地排列。
本实施例中，显示面板2可以为异形显示面板，例如，显示面板2的形状为非(长)方形时，该显示面板2可称为异形显示面板。图5中所示的显示面板2的形状为倒梯形。图5中以栅极控制线G1’、G2’、G3’为例进行描述，如图5所示，栅极控制线G1’与栅线G1连接，栅极控制线G2’与栅线G2连接，栅极控制线G3’与栅线G3连接，栅极控制线从左至右按照栅极控制线G1’、栅极控制线G3’、栅极控制线G2’的顺序设置。
本实施例提供的显示装置的技术方案中，数据线的连接端与对应的源极输出引脚连接，栅线与对应的栅极控制线连接，栅极控制线的连接端与对应的栅极输出引脚连接，栅极控制线的连接端与数据线的连接端连接至驱动电路的同一侧，即，驱动电路的靠近显示面板的一侧，避免了栅极控制线的连接端和数据线的连接端连接至驱动电路的不同侧，降低了显示面板两侧的扇区面积，从而使得显示装置实现窄边框。本实施例中还可以使得显示装置实现异形边框显示。本实施例的显示装置中，栅极控制线的布线简单，降低了工艺复杂度，从而使得显示装置的良率高且可靠性高。
图6为本发明的第三实施例提供的一种显示装置的结构示意图，如图6所示，本实施例与上述第二实施例的区别在于，显示面板2的形状为半圆形。
本实施例提供的显示装置的技术方案中，数据线的连接端与对应的源极输出引脚连接，栅线与对应的栅极控制线连接，栅极控制线的连接端 与对应的栅极输出引脚连接，栅极控制线的连接端与数据线的连接端连接至驱动电路的同一侧，即，驱动电路的靠近显示面板的一侧，避免了栅极控制线的连接端和数据线的连接端连接至驱动电路的不同侧，降低了显示面板两侧的扇区面积，从而使得显示装置实现窄边框。本实施例进一步还可以使得显示装置实现无边框。本实施例的显示装置中，栅极控制线的布线简单，降低了工艺复杂度，从而使得显示装置的良率高且可靠性高。
图7为本发明的第四实施例提供的一种显示装置的结构示意图，如图7所示，本实施例与上述第一实施例的区别在于，每隔多条数据线设置一条栅极控制线，每隔多个源极输出引脚设置一个栅极输出引脚。
如图7所示，每隔两个源极输出引脚设置一个栅极输出引脚，例如，图7中的源极输出引脚和栅极输出引脚从左至右按照源极输出引脚M1、源极输出引脚M2、栅极输出引脚L1、源极输出引脚M3、源极输出引脚M4、栅极输出引脚L2的顺序设置。
需要说明的是，图7中的显示面板2中仅画出了栅线G1、G2和栅极控制线G1’、G2’，其余结构均未具体画出。
本发明中，栅极输出引脚和源极输出引脚的设置位置和数量可根据显示装置的分辨率确定。因此，不同分辨率的显示装置中栅极输出引脚和源极输出引脚的设置位置和数量可以是不同的。
本实施例提供的显示装置的技术方案中，数据线的连接端与对应的源极输出引脚连接，栅线与对应的栅极控制线连接，栅极控制线的连接端与对应的栅极输出引脚连接，栅极控制线的连接端与数据线的连接端连接至驱动电路的同一侧，即，驱动电路的靠近显示面板的一侧，避免了栅极控制线的连接端和数据线的连接端连接至驱动电路的不同侧，降低了显示面板两侧的扇区面积，从而使得显示装置实现窄边框。本实施例进一步还可以使得显示装置实现无边框。本实施例的显示装置中，栅极控制线的布线简单，降低了工艺复杂度，从而使得显示装置的良率高且可信性高。
本发明的第五实施例提供了一种驱动装置，如图3所示，该驱动装置包括：驱动电路1和设置于驱动电路1上的栅极输出引脚和源极输出引脚，所述栅极数据引脚用于连接对应的栅极控制线的连接端，所述栅极控制线用于连接对应的栅线；所述源极输出引脚用于连接对应的数据线的连 接端，所述栅极控制线的连接端与所述数据线的连接端连接至驱动电路1的同一侧。
本实施例中，栅极输出引脚用于与对应的栅极控制线连接；源极输出引脚用于与对应的数据线连接。优选地，栅极输出引脚的数量和栅极控制线的数量相同，源极输出引脚的数量和数据线的数量相同。栅极输出引脚可包括栅极输出引脚L1、L2、L3、……、Ln，源极输出引脚可包括源极输出引脚M1、M2、M3、……、Mn，图3中仅以栅极输出引脚L1、L2、L3以及源极输出引脚M1、M2、M3为例进行描述。
本实施例中，栅极输出引脚和源极输出引脚交替设置。如图3所示，栅极输出引脚和源极输出引脚从左至右按照栅极输出引脚L1、源极输出引脚M1、栅极输出引脚L2、源极输出引脚M2、栅极输出引脚L3、源极输出引脚M3的顺序设置。此种设置方式使得栅线和栅极控制线之间的连线更加方便，从而简化了显示面板的结构，降低了工艺复杂度。
在实际应用中，可选地，每隔多个源极输出引脚设置一个栅极输出引脚，此种情况不再具体画出。
本实施例提供的驱动装置的技术方案中，数据线的连接端与对应的源极输出引脚连接，栅线与对应的栅极控制线连接，栅极控制线的连接端与对应的栅极输出引脚连接，栅极控制线的连接端与数据线的连接端连接至驱动电路的同一侧，即，驱动电路的靠近显示面板的一侧，避免了栅极控制线的连接端和数据线的连接端连接至驱动电路的不同侧，降低了与该驱动装置连接的显示面板两侧的扇区面积，从而使得使用该驱动装置的显示装置实现窄边框。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种显示装置，包括：驱动装置和显示面板，所述显示面板包括栅极控制线、多条栅线和多条数据线，所述多条栅线和所述多条数据线交叉限定出像素单元，所述驱动装置包括驱动电路和设置于所述驱动电路上的栅极输出引脚和源极输出引脚；
    所述数据线的连接端与对应的所述源极输出引脚连接，所述栅线与对应的所述栅极控制线连接，所述栅极控制线的连接端与对应的所述栅极输出引脚连接，且所述栅极控制线的连接端与所述数据线的连接端连接至所述驱动电路的同一侧。
  2. 根据权利要求1所述的显示装置，其中，所述栅极控制线的连接端连接至所述驱动电路的靠近所述显示面板的一侧，所述数据线的连接端连接至所述驱动电路的靠近所述显示面板的一侧。
  3. 根据权利要求2所述的显示装置，其中，所述栅极输出引脚和所述源极输出引脚均设置于所述驱动电路的靠近所述显示面板的一侧。
  4. 根据权利要求1所述的显示装置，其中，所述栅线和所述栅极控制线同层设置。
  5. 根据权利要求1所述的显示装置，其中，所述栅极控制线与所述数据线平行设置。
  6. 根据权利要求1所述的显示装置，其中，所述栅线顺序排列，与所述栅线连接的所述栅极控制线顺序排列。
  7. 根据权利要求1所述的显示装置，其中，所述栅线顺序排列，与所述栅线连接的所述栅极控制线根据所述显示面板的形状而非顺序地排 列。
  8. 根据权利要求1所述的显示装置，其中，所述栅极控制线与所述数据线平行设置，且所述栅极控制线和所述数据线交替设置。
  9. 根据权利要求1所述的显示装置，其中，所述栅极控制线与所述数据线平行设置，且每隔多条所述数据线设置一条所述栅极控制线。
  10. 根据权利要求1至9中任一项所述的显示装置，其中，所述显示面板为异形显示面板。
  11. 一种显示装置的驱动装置，所述显示装置包括显示面板，所述显示面板包括栅极控制线、多条栅线和多条数据线，所述多条栅线和所述多条数据线交叉限定出像素单元，所述驱动装置包括：驱动电路以及设置于驱动电路上的栅极输出引脚和源极输出引脚；
    所述栅极数据引脚用于连接对应的栅极控制线的连接端，所述栅极控制线用于连接对应的栅线；
    所述源极输出引脚用于连接对应的数据线的连接端，所述栅极控制线的连接端与所述数据线的连接端连接至所述驱动电路的同一侧。
  12. 根据权利要求11所述的驱动装置，其中，所述栅极输出引脚和源极输出引脚连接至所述驱动电路的靠近所述显示面板的一侧。
  13. 根据权利要求11所述的驱动装置，其中，所述栅极输出引脚和所述源极输出引脚交替设置。
  14. 根据权利要求11所述的驱动装置，其中，每隔多个源极输出引脚设置一个栅极输出引脚。
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