WO2017185822A1 - 移位寄存器、栅极驱动电路、阵列基板 - Google Patents

移位寄存器、栅极驱动电路、阵列基板 Download PDF

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Publication number
WO2017185822A1
WO2017185822A1 PCT/CN2017/070233 CN2017070233W WO2017185822A1 WO 2017185822 A1 WO2017185822 A1 WO 2017185822A1 CN 2017070233 W CN2017070233 W CN 2017070233W WO 2017185822 A1 WO2017185822 A1 WO 2017185822A1
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Prior art keywords
transistor
pull
pole
shift register
clock signal
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PCT/CN2017/070233
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English (en)
French (fr)
Inventor
陈华斌
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/543,437 priority Critical patent/US10102806B2/en
Publication of WO2017185822A1 publication Critical patent/WO2017185822A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the invention belongs to the technical field of gate driving, and particularly relates to a shift register, a gate driving circuit and an array substrate.
  • a gate driving circuit for driving each gate line to generate a scan signal ie, a turn output turn-on signal
  • a scan signal ie, a turn output turn-on signal
  • the driving circuit is composed of a plurality of cascaded shift registers, and the output end of each shift register is connected to a gate line.
  • the scanning direction of the gate lines in the array substrate is determined to be either a forward (from top to bottom) scan or a reverse (from bottom to top) scan.
  • a forward (from top to bottom) scan or a reverse (from bottom to top) scan.
  • Dual Scan which requires an array substrate to be scanned both in the forward direction and in the reverse direction.
  • the invention aims at the problem that the structure of the existing gate driving circuit capable of realizing the bidirectional scanning function is complicated and the number of required control signals is large, and provides a shift register with a simple structure and a small number of control signals required.
  • a gate driving circuit including the shift register, and an array substrate including the gate driving circuit.
  • a technical solution adopted by the present invention is a shift register, which includes a discharge unit, a holding unit, an output unit, a pull-down unit, a charging unit, an input terminal, a reset terminal, a first clock signal terminal, a second clock signal terminal, a constant voltage terminal, and an output terminal, wherein:
  • the buffer discharge unit controls whether the signal of the constant voltage end is transmitted to the output end according to the signal of the input end, the signal of the reset end, and the level of the pull-down node, and whether the signal of the constant voltage end and the second clock signal end is transmitted to the pull-up node;
  • the holding unit controls the level of the pull-down node according to the signal of the second clock signal end and the level of the pull-up node;
  • the output unit controls whether the signal of the first clock signal end is transmitted to the output end according to the level of the pull-up node
  • the pull-down unit controls whether to transmit the signal of the constant voltage end to the output end according to the signal of the second clock signal end;
  • the charging unit maintains the level of the output.
  • the buffer discharge unit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein:
  • the first pole of the first transistor is connected to the second clock signal end, the second pole is connected to the pull-up node, and the gate is connected to the input end;
  • the first pole of the second transistor is connected to the pull-up node, the second pole is connected to the first clock signal end, and the gate is connected to the reset end;
  • the first pole of the third transistor is connected to the pull-up node, the second pole is connected to the constant voltage end, and the gate is connected to the pull-down node;
  • the first pole of the fourth transistor is connected to the output end, the second pole is connected to the constant voltage end, and the gate is connected to the pull-down node.
  • the holding unit comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein:
  • the first pole of the fifth transistor is connected to the second clock signal end, the second pole is connected to the pull-down node, and the gate is connected to the first pole of the seventh transistor and the second pole of the eighth transistor;
  • the first pole of the sixth transistor is connected to the pull-down node, the second pole is connected to the constant voltage end, and the gate is connected to the pull-up node;
  • the first pole of the seventh transistor is connected to the gate of the fifth transistor, the second pole is connected to the constant voltage end, and the gate is connected to the pull-up node;
  • the first pole of the eighth transistor is connected to the second clock signal end, the second pole is connected to the gate of the fifth transistor, and the gate is connected to the second clock signal end.
  • the output unit includes a ninth transistor, wherein
  • the first pole of the ninth transistor is connected to the first clock signal end, the second pole is connected to the output end, and the gate is connected to the pull-up node.
  • the pull-down unit includes a tenth transistor, wherein
  • the first pole of the tenth transistor is connected to the output end, the second pole is connected to the constant voltage end, and the gate is connected to the second clock signal end.
  • the charging unit includes a storage capacitor, wherein
  • the first end of the storage capacitor is connected to the pull-up node, and the second end is connected to the output end.
  • all of the transistors are N-type transistors
  • transistors are P-type transistors.
  • a gate driving circuit which includes:
  • a plurality of cascaded shift registers the shift registers being the shift registers described above.
  • the gate driving circuit further includes a first control line, a second control line, and a constant pressure line, wherein:
  • the first control line is connected to a first clock signal end of all odd-numbered shift registers and a second clock signal end of all even-stage shift registers;
  • the second control line is connected to a first clock signal end of all even-stage shift registers and a second clock signal end of all odd-numbered shift registers;
  • the constant voltage line is connected to the constant voltage end of all the bit registers
  • the pull-up node of each of the shift registers is connected to the reset terminal of the previous stage shift register and the input terminal of the next stage shift register.
  • the input of the first stage shift register inputs a separate signal
  • the reset stage of the last stage shift register inputs a separate signal
  • an array substrate which includes:
  • each shift register of the gate driving circuit is connected to a gate line.
  • the gate driving circuit of the present invention can realize bidirectional scanning, and the number of devices therein is small, which is equivalent to the number of devices in the existing unidirectional scanning gate driving circuit; and the gate driving circuit of the present invention only needs two
  • the control signal ie, two clock signals
  • the gate driving circuit of the present invention has a simple structure and low cost.
  • FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • FIG. 2 is a schematic block diagram showing the composition of a gate driving circuit according to an embodiment of the present invention
  • FIG. 3 is a signal timing diagram of a shift register of a gate driving circuit in a forward scanning manner according to an embodiment of the present invention
  • FIG. 4 is a signal timing diagram of a shift register therein in a reverse scan of a gate driving circuit according to an embodiment of the present invention.
  • the embodiment provides a shift register including a buffer discharge unit, a holding unit, an output unit, a pull-down unit, a charging unit, an input end, a reset end, and a first clock signal end. a second clock signal terminal, a constant voltage terminal, and an output terminal, wherein:
  • the buffer discharge unit is based on the signal of the input terminal INPUT, the reset terminal RESET The signal and the level of the pull-down node PD, control whether the signal of the constant voltage terminal VSS is transmitted to the output terminal OUTPUT, and whether the signal of the constant voltage terminal VSS and the second clock signal terminal CLKB is transmitted to the pull-up node PU;
  • the holding unit controls the level of the pull-down node PD according to the signal of the second clock signal terminal CLKB and the level of the pull-up node PU;
  • the output unit controls whether to transmit the signal of the first clock signal terminal CLK to the output terminal OUTPUT according to the level of the pull-up node PU;
  • the pull-down unit controls whether to transmit the signal of the constant voltage terminal VSS to the output terminal OUTPUT according to the signal of the second clock signal terminal CLKB;
  • the charging unit maintains the level of the output terminal OUTPUT.
  • the buffer discharge unit includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4, wherein
  • the first pole of the first transistor M1 is connected to the second clock signal terminal CLKB, the second pole is connected to the pull-up node PU, and the gate is connected to the input terminal INPUT;
  • the first pole of the second transistor M2 is connected to the pull-up node PU, the second pole is connected to the first clock signal terminal CLK, and the gate is connected to the reset terminal RESET;
  • the first pole of the third transistor M3 is connected to the pull-up node PU, the second pole is connected to the constant voltage terminal VSS, and the gate is connected to the pull-down node PD;
  • the first transistor of the fourth transistor M4 is connected to the output terminal OUTPUT, the second electrode is connected to the constant voltage terminal VSS, and the gate is connected to the pull-down node PD.
  • the holding unit includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8, wherein
  • the first pole of the fifth transistor M5 is connected to the second clock signal terminal CLKB, the second pole is connected to the pull-down node PD, and the gate is connected to the first pole of the seventh transistor M7 and the second pole of the eighth transistor M8;
  • the first pole of the sixth transistor M6 is connected to the pull-down node PD, the second pole is connected to the constant voltage terminal VSS, and the gate is connected to the pull-up node PU;
  • the first pole of the seventh transistor M7 is connected to the gate of the fifth transistor M5, the second pole is connected to the constant voltage terminal VSS, and the gate is connected to the pull-up node PU;
  • the first pole of the eighth transistor M8 is connected to the second clock signal terminal CLKB, and the second The pole is connected to the gate of the fifth transistor M5, and the gate is connected to the second clock signal terminal CLKB.
  • the output unit comprises a ninth transistor M9, wherein
  • the first pole of the ninth transistor M9 is connected to the first clock signal terminal CLK, the second pole is connected to the output terminal OUTPUT, and the gate is connected to the pull-up node PU.
  • the pull-down unit comprises a tenth transistor M10; wherein
  • the first pole of the tenth transistor M10 is connected to the output terminal OUTPUT, the second pole is connected to the constant voltage terminal VSS, and the gate is connected to the second clock signal terminal CLKB.
  • the charging unit comprises a storage capacitor C; wherein
  • the first end of the storage capacitor C is connected to the pull-up node PU, and the second end is connected to the output terminal OUTPUT.
  • all of the above transistors are N-type transistors, more specifically N-type thin film transistors; or all of the above transistors are P-type transistors, more specifically P-type thin film transistors.
  • the embodiment further provides a gate driving circuit, including:
  • the gate driving circuit further includes: a first control line, a second control line, and a constant pressure line; wherein
  • the first control line is connected to the first clock signal terminal CLK of all odd-numbered shift registers and the second clock signal terminal CLKB of all even-stage shift registers;
  • the second control line is connected to the first clock signal terminal CLK of all even-stage shift registers and the second clock signal terminal CLKB of all odd-numbered shift registers;
  • the constant voltage line is connected to the constant voltage terminal VSS of all shift registers;
  • the pull-up node PU of the shift register is connected to the reset terminal RESET of the previous stage shift register and the input terminal of the next stage shift register.
  • the shift registers of each stage are not connected to other shift registers through the output terminal, but are connected to other shift registers through the pull-up node; of course, according to the above connection
  • the input terminal INPUT of the first stage shift register and the reset terminal RESET of the last stage shift register have no input, so it is necessary to set a special signal line for them, and the gate drive is introduced.
  • the initial signal of the road starting to work is not described in detail here.
  • the two control lines of the gate driving circuit ie, the first control line and the second control line
  • the adjacent shift registers are connected to the two control lines in opposite directions.
  • the actual clock signals received by the adjacent shift registers are guaranteed to be the same; and the constant voltage lines provide a constant level signal for the constant voltage terminals VSS of all the shift registers.
  • the gate driving circuit of the embodiment can realize bidirectional scanning, and the number of devices therein is small, which is equivalent to the number of devices in the existing unidirectional scanning gate driving circuit; and the gate driving circuit of the embodiment only needs
  • the two control signals ie, two clock signals, constant voltage signals, etc. are regarded as non-control signals
  • the gate driving circuit of the embodiment has a simple structure. low cost.
  • the operation mode of the gate driving circuit of the present embodiment will be specifically described below by taking an example in which all transistors are N-type transistors.
  • Case S1 When the gate driving circuit of the present embodiment scans forward (from top to bottom), as shown in FIG. 3, the operation of the shift register in the gate driving circuit specifically includes the following stages S11 to S15.
  • S11 stage providing a high level signal for the first clock signal terminal CLK, a low level signal for the second clock signal terminal CLKB, a high level signal for the input terminal INPUT, and a low level signal for the reset terminal RESET, A low level signal is provided for the constant voltage terminal VSS.
  • the upper stage (n-1th stage) shift register starts operating before the shift register of the stage (nth stage), so the pull-up node PU of the previous stage shift register becomes high. Normally, it will provide a high level signal to the input terminal INPUT of the shift register of this stage. number. Therefore, in the shift register of the current stage, the first transistor M1 is turned on, and the low level signal of the second clock signal terminal CLKB is introduced into the pull-up node PU via the first transistor M1, and the pull-up node PU is at a low level, due to storage. The function of the capacitor C, the output terminal OUTPUT is also low, and the shift register of this stage outputs a low level.
  • S12 phase providing a low level signal for the first clock signal terminal CLK, a high level signal for the second clock signal terminal CLKB, a high level signal for the input terminal INPUT, and a low level signal for the reset terminal RESET, A low level signal is provided for the constant voltage terminal VSS.
  • the input terminal INPUT of the shift register of this stage is still high level
  • the first transistor M1 continues to conduct
  • the high level signal of the second clock signal terminal CLKB is introduced into the pull-up node PU
  • the pull-up node PU becomes Is high, that is, the reset terminal RESET of the upper stage (n-1th stage) shift register and the input terminal INPUT of the next stage (n+1th stage) shift register become high level;
  • the upper shift register enters the following S13 phase, and the next shift register enters the above S11 phase.
  • the ninth transistor M9 Since the pull-up node PU is at a high level, the ninth transistor M9 is turned on, and the low level of the first clock signal terminal CLK is introduced to the output terminal OUTPUT, and the shift register of the current stage still outputs a low level. Meanwhile, in the shift register of the stage, the high level of the pull-up node PU further turns on the sixth transistor M6 and the seventh transistor M7, and introduces the low level of the constant voltage terminal VSS into the control node CN and the pull-down node PD; Therefore, although the second clock signal terminal CLKB is at a high level at this time, the eighth transistor M8 is equivalent to an open circuit, so that the fifth transistor M5 is also turned off.
  • S13 stage providing a high level signal for the first clock signal terminal CLK, a low level signal for the second clock signal terminal CLKB, a low level signal for the input terminal INPUT, and a high level signal for the reset terminal RESET, A low level signal is provided for the constant voltage terminal VSS.
  • the input terminal INPUT and the second clock signal terminal CLKB of the shift register of the current stage both become low level, so that the first transistor M1 and the tenth transistor M10 are turned off, the second clock signal terminal CLKB and the constant voltage terminal
  • the VSS signal cannot enter the pull-up node PU and the output OUTPUT.
  • the signal of the reset terminal RESET is the signal of the pull-up node PU of the next stage (n+1th stage) shift register, and becomes a high level at this time; thus, the second transistor M2 is turned on, the first clock The signal level CLK is high level through the second The transistor M2 enters the pull-up node PU, and the pull-up node PU maintains a high level, so the ninth transistor M9 is turned on, and the high level of the first clock signal terminal CLK is introduced to the output terminal OUTPUT via the ninth transistor M9, and the shift register of the current stage The output is high.
  • S14 stage providing a low level signal for the first clock signal terminal CLK, a high level signal for the second clock signal terminal CLKB, a low level signal for the input terminal INPUT, and a high level signal for the reset terminal RESET, A low level signal is provided for the constant voltage terminal VSS.
  • the reset terminal RESET of the shift register of the current stage is still at a high level, so that the low level of the first clock signal terminal CLK is transmitted to the pull-up node PU via the second transistor M2, and the pull-up node PU becomes low-powered.
  • Flat that is, the reset terminal RESET of the upper stage (n-1th stage) shift register and the input terminal INPUT of the next stage (n+1th stage) shift register are both turned low, so the upper level
  • the shift register enters the following S15 stage, and the next stage shift register enters the above S13 stage.
  • the sixth transistor M6 and the seventh transistor M7 are turned off, and the low level of the constant voltage terminal VSS cannot enter the control node CN and the pull-down node PD, so the high level signal of the second clock signal terminal CLKB passes through the eighth transistor M8.
  • the fifth transistor M5 enters the control node CN and the pull-down node PD, respectively, so that they are all at a high level.
  • the third transistor M3 and the fourth transistor M4 connected to the pull-down node PD are both turned on, and the low-level signal of the constant voltage terminal VSS is introduced through the fourth transistor M4 (of course, also introduced through the tenth transistor M10).
  • OUTPUT the shift register of this stage outputs low level.
  • S15 stage Provide a low level signal for the input terminal INPUT, a low level signal for the reset terminal RESET, and a low level signal for the constant voltage terminal VSS.
  • the input terminal INPUT and the reset terminal RESET of the shift register of the current stage are both low level signals, so the second transistor M2 and the first transistor M1 are both turned off.
  • the eighth transistor M8, the fifth transistor M5, and the tenth transistor M10 are both turned on, and the pull-down node PD is at a high level, thereby
  • the third transistor M3 and the fourth transistor M4 are turned on, and the low-level signal of the constant voltage terminal VSS causes the pull-up node PU and the output terminal OUTPUT to be low level, and the shift register of the current stage outputs a low level; and when the second Time When the clock signal terminal CLKB provides a low level signal, the eighth transistor M8, the fifth transistor M5, and the tenth transistor M10 are all turned off, and the signal of the constant voltage terminal VSS cannot be input to the output terminal OUTPUT and the pull-up node PU, and the storage capacitor C The discharge starts, but since the period of the clock signal is very short, the discharge time is very short.
  • the output terminal OUTPUT can still maintain a low level before the next high level of the second clock
  • the shift register can maintain the low level output regardless of the state of the two clock signals.
  • the shift registers of the respective stages are in accordance with "(n-1)th - nth - (n+1)th order"
  • the sequence ie, from top to bottom sequentially outputs a turn-on signal (high level signal), and the operating states of adjacent shift registers differ by half a clock cycle.
  • the required signal of the input terminal INPUT is one-half clock cycle ahead of the level of the pull-up node PU, so it is just right to the upper level (n-1) Level)
  • the pull-up node PU of the shift register is connected to the input terminal INPUT of the shift register of the stage; at the same time, for any stage (n-th stage) shift register, the signal ratio of the reset terminal RESET required
  • the level of the pull-up node PU is half a clock cycle behind, so that the pull-up node PU of the next stage (n+1th stage) shift register can be connected to the reset terminal RESET of the shift register of the current stage; thus,
  • Each stage shift register can be sequentially subjected to the same driving process, and a forward scan of the gate driving circuit (i.e., the gate driving circuit of the present embodiment) including these shift registers is realized.
  • Case S2 When the gate driving circuit of the present embodiment scans in reverse (from bottom to top), as shown in FIG. 4, the operation of the shift register in the gate driving circuit specifically includes the following stages S21 to S25.
  • S21 stage providing a low level signal for the first clock signal terminal CLK, a high level signal for the second clock signal terminal CLKB, a low level signal for the input terminal INPUT, and a high level signal for the reset terminal RESET, A low level signal is provided for the constant voltage terminal VSS.
  • this stage has no practical effect on the stage (n-th stage) shift register, but it is actually present, so it is explained here.
  • a separate signal can also be used as the input of its reset terminal RESET, so it may not exist at this stage, but directly from the following S22 stage.
  • the next stage (n+1th stage) shift register starts operating before the shift stage of the stage (nth stage), so the pull-up node PU of the next stage shift register becomes high.
  • a high level signal is supplied to the reset terminal RESET of the shift register of this stage. Therefore, in the shift register of the current stage, the second transistor M2 is turned on, and the low-level signal of the first clock signal terminal CLK is introduced into the pull-up node PU, and the second clock signal terminal CLKB is at the high level, and the tenth transistor M10 is turned on, and the low level of the constant voltage terminal VSS is introduced to the output terminal OUTPUT via the tenth transistor M10, and the shift register of the current stage outputs a low level.
  • S22 stage providing a high level signal for the first clock signal terminal CLK, a low level signal for the second clock signal terminal CLKB, a low level signal for the input terminal INPUT, and a high level signal for the reset terminal RESET, A low level signal is provided for the constant voltage terminal VSS.
  • the reset terminal RESET of the shift register of this stage remains at a high level, and the first clock signal terminal CLK becomes a high level, whereby the pull-up node PU also becomes a high level, that is, the upper level (
  • the n-1th stage shift register reset terminal RESET and the next stage shift register (n+1th level) input terminal ITPUT become high level, so that the upper stage shift register enters the above S21 stage , and the next stage shift register enters the following S23 stage.
  • the ninth transistor M9 Since the pull-up node PU is at a high level, the ninth transistor M9 is turned on, and the high level of the first clock signal terminal CLK is introduced to the output terminal OUTPUT; meanwhile, in the shift register of the current stage, the second clock signal terminal CLKB is Low level, so the tenth transistor M10 is turned off, and the low level of the constant voltage terminal VSS does not enter the output terminal OUTPUT; the shift register of this stage outputs a high level.
  • S23 stage providing a low level signal for the first clock signal terminal CLK, a high level signal for the second clock signal terminal CLKB, a high level signal for the input terminal INPUT, and a low level signal for the reset terminal RESET, Low for the constant voltage terminal VSS Level signal.
  • the next stage (n+1)th shift register enters the following S24 stage, so its pull-up node PU becomes low level, that is, the reset end of the current stage (nth stage) shift register RESET It becomes low level; at the same time, the upper stage (n-1)th shift register enters the above S22 stage, so the input terminal INPUT of the stage (nth level) shift register becomes high level.
  • the first transistor M1 since the input terminal INPUT is at a high level, the first transistor M1 is turned on, and the high level signal of the second clock signal terminal CLKB is introduced into the pull-up node PU, and is pulled up.
  • the node PU is kept at a high level.
  • the ninth transistor M9 is turned on, and the low level of the first clock signal terminal CLK is introduced to the output terminal OUTPUT, and the shift register of the current stage outputs a low level.
  • S24 stage providing a high level signal for the first clock signal terminal CLK, a low level signal for the second clock signal terminal CLKB, a high level signal for the input terminal INPUT, and a low level signal for the reset terminal RESET, A low level signal is provided for the constant voltage terminal VSS.
  • the INPUT of the shift register of the current stage is kept at a high level, so the low level of the second clock signal terminal CLKB passes the first transistor M1 to turn the pull-up node PU to a low level, and thus the ninth transistor M9 Shutdown, the signal of the first clock signal terminal CLK cannot be introduced to the output terminal OUTPUT, the output terminal OUTPUT is kept low according to the action of the storage capacitor C, and the shift register of the current stage outputs a low level.
  • S25 stage Provide a low level signal for the input terminal INPUT, a low level signal for the reset terminal RESET, and a low level signal for the constant voltage terminal VSS.
  • the input terminal INPUT and the reset terminal RESET of the shift register of this stage are both low level, so the signal of the two clock signals is used by the function of the storage capacitor C. How, the output OUTPUT is kept low and will not be described in detail here.
  • the shift registers of the respective stages are in accordance with the "(n+1)th - nth - (n-1)th order"
  • the sequence ie, from bottom to top sequentially outputs a turn-on signal (high level signal), and the operating states of adjacent shift registers differ by half a clock cycle.
  • the required signal at the input INPUT is later than the level of the pull-up node PU.
  • the pull-up node PU of the previous stage (n-1th stage) shift register can be connected to the input terminal INPUT of the shift register of the current stage; at the same time, for any level (nth level)
  • the signal of the reset terminal RESET required is one half clock cycle ahead of the level of the pull-up node PU, so that the pull-up of the next stage (n+1th stage) shift register can be just right.
  • the node PU is connected to the reset terminal RESET of the shift register of the current stage; thus, each shift register can be sequentially subjected to the same driving process, and the gate driving circuit including the shift registers is realized (ie, the implementation) The reverse scan of the gate drive circuit of the example.
  • This embodiment provides an array substrate, including:
  • each shift register of the gate driving circuit is connected to a gate line.
  • the array substrate should also include other known structures such as data lines, pixel circuits, and the like, and will not be described in detail herein.
  • the embodiment further provides a display device including the above array substrate.
  • the display device can be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种移位寄存器、包含该移位寄存器的栅极驱动电路、包含该栅极驱动电路的阵列基板。所述移位寄存器包括缓冲放电单元、保持单元、输出单元、下拉单元、充电单元、输入端(INTUT)、重置端(RESET)、第一时钟信号端(CLK)、第二时钟信号端(CLKB)、定压端(VSS)和输出端(OUTPUT)，其中：缓冲放电单元根据输入端(INPUT)的信号、重置端(RESET)的信号以及下拉节点(PD)的电平，控制是否将定压端(VSS)的信号传至输出端(OUTPUT)，以及是否将定压端(VSS)和第二时钟信号端(CLKB)的信号传至上拉节点(PU)；保持单元根据第二时钟信号端(CLKB)的信号和上拉节点(PU)的电平控制下拉节点(PD)的电平；输出单元根据上拉节点(PU)的电平控制是否将第一时钟信号端(CLK)的信号传至输出端(OUTPUT)；下拉单元根据第二时钟信号端(CLKB)的信号控制是否将定压端(VSS)的信号传至输出端(OUTPUT)；充电单元保持输出端(OUTPUT)的电平。

Description

移位寄存器、栅极驱动电路、阵列基板 技术领域
本发明属于栅极驱动技术领域，具体涉及移位寄存器、栅极驱动电路、阵列基板。
背景技术
在GOA(Gate On Array)模式的阵列基板中，用于驱动各栅线产生扫描信号(即轮流输出导通信号)的栅极驱动电路是直接制造在阵列基板的基底上的，其中，栅极驱动电路由多个级联的移位寄存器组成，每个移位寄存器的输出端连接一条栅线，通过向栅极驱动电路提供几个简单的控制信号，即可使各移位寄存器依次向各栅线输出导通信号。
通常，阵列基板中栅线的扫描方向是确定的，为正向(从上向下)扫描或为反向(从下向上)扫描。但在有些情况下(如多屏显示时)，可能需要实现双向扫描(Dual Scan)，即要求一个阵列基板既能正向扫描也能反向扫描。
为实现双向扫描功能，必须对栅极驱动电路进行改变，增加其中器件的数量，并同时增加所需的控制信号(也就是增加控制信号线)，这导致现有的能实现双向扫描功能的栅极驱动电路的结构都很复杂，所需的控制信号的数量也较多。
发明内容
本发明针对现有的能实现双向扫描功能的栅极驱动电路的结构复杂、所需的控制信号的数量多的问题，提供一种结构简单且所需的控制信号的数量较少的移位寄存器、包含该移位寄存器的栅极驱动电路、以及包含该栅极驱动电路的阵列基板。
本发明所采用的一种技术方案是一种移位寄存器，其包括缓 冲放电单元、保持单元、输出单元、下拉单元、充电单元、输入端、重置端、第一时钟信号端、第二时钟信号端、定压端和输出端，其中：
缓冲放电单元根据输入端的信号、重置端的信号以及下拉节点的电平，控制是否将定压端的信号传至输出端，以及是否将定压端和第二时钟信号端的信号传至上拉节点；
保持单元根据第二时钟信号端的信号和上拉节点的电平控制下拉节点的电平；
输出单元根据上拉节点的电平控制是否将第一时钟信号端的信号传至输出端；
下拉单元根据第二时钟信号端的信号控制是否将定压端的信号传至输出端；
充电单元保持输出端的电平。
优选的是，所述缓冲放电单元包括第一晶体管、第二晶体管、第三晶体管、第四晶体管，其中：
所述第一晶体管的第一极连接第二时钟信号端，第二极连接上拉节点，栅极连接输入端；
所述第二晶体管的第一极连接上拉节点，第二极连接第一时钟信号端，栅极连接重置端；
所述第三晶体管的第一极连接上拉节点，第二极连接定压端，栅极连接下拉节点；
所述第四晶体管的第一极连接输出端，第二极连接定压端，栅极连接下拉节点。
进一步优选的是，所述保持单元包括第五晶体管、第六晶体管、第七晶体管、第八晶体管，其中：
所述第五晶体管的第一极连接第二时钟信号端，第二极连接下拉节点，栅极连接第七晶体管的第一极以及第八晶体管的第二极；
所述第六晶体管的第一极连接下拉节点，第二极连接定压端，栅极连接上拉节点；
所述第七晶体管的第一极连接第五晶体管的栅极，第二极连接定压端，栅极连接上拉节点；
所述第八晶体管的第一极连接第二时钟信号端，第二极连接第五晶体管的栅极，栅极连接第二时钟信号端。
进一步优选的是，所述输出单元包括第九晶体管，其中，
所述第九晶体管的第一极连接第一时钟信号端，第二极连接输出端，栅极连接上拉节点。
进一步优选的是，所述下拉单元包括第十晶体管，其中，
所述第十晶体管的第一极连接输出端，第二极连接定压端，栅极连接第二时钟信号端。
进一步优选的是，所述充电单元包括存储电容，其中，
所述存储电容的第一端连接上拉节点，第二端连接输出端。
进一步优选的是，所有晶体管均为N型晶体管；
或所有晶体管均为P型晶体管。
本发明所采用的另一种技术方案是一种栅极驱动电路，其包括：
多个级联的移位寄存器，所述移位寄存器为上述的移位寄存器。
优选的是，所述栅极驱动电路还包括第一控制线、第二控制线、定压线，其中：
所述第一控制线与所有奇数级的移位寄存器的第一时钟信号端和所有偶数级的移位寄存器的第二时钟信号端相连；
所述第二控制线与所有偶数级的移位寄存器的第一时钟信号端和所有奇数级的移位寄存器的第二时钟信号端相连；
所述定压线与所有位寄存器的定压端相连；
每个所述移位寄存器的上拉节点连接上一级移位寄存器的重置端和下一级移位寄存器的输入端。
优选的是，第一级移位寄存器的输入端输入单独的信号，最后一级移位寄存器的重置端输入单独的信号。
本发明所采用的再一种技术方案是一种阵列基板，其包括：
多条栅线；
上述的栅极驱动电路，栅极驱动电路的每个移位寄存器的输出端连接一条栅线。
本发明的栅极驱动电路可实现双向扫描，且其中的器件数量较少，与现有的单向扫描的栅极驱动电路中的器件数量相当；并且本发明的栅极驱动电路只需要两个控制信号(即两个时钟信号)，也与现有的单向扫描的栅极驱动电路相同；故本发明的栅极驱动电路结构简单、成本低。
附图说明
图1为本发明的实施例的一种移位寄存器的结构示意图；
图2为本发明的实施例的一种栅极驱动电路的组成示意框图；
图3为本发明的实施例的栅极驱动电路正向扫描时其中的移位寄存器的信号时序图；
图4为本发明的实施例的栅极驱动电路反向扫描时其中的移位寄存器的信号时序图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
第一实施例
如图1至图4所示，本实施例提供一种移位寄存器，其包括缓冲放电单元、保持单元、输出单元、下拉单元、充电单元、输入端、重置端、第一时钟信号端、第二时钟信号端、定压端和输出端，其中：
缓冲放电单元根据输入端INPUT的信号、重置端RESET的 信号以及下拉节点PD的电平，控制是否将定压端VSS的信号传至输出端OUTPUT，以及是否将定压端VSS和第二时钟信号端CLKB的信号传至上拉节点PU；
保持单元根据第二时钟信号端CLKB的信号和上拉节点PU的电平控制下拉节点PD的电平；
输出单元根据上拉节点PU的电平控制是否将第一时钟信号端CLK的信号传至输出端OUTPUT；
下拉单元根据第二时钟信号端CLKB的信号控制是否将定压端VSS的信号传至输出端OUTPUT；
充电单元保持输出端OUTPUT的电平。
如图1所示，优选的，缓冲放电单元包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4，其中，
第一晶体管M1的第一极连接第二时钟信号端CLKB，第二极连接上拉节点PU，栅极连接输入端INPUT；
第二晶体管M2的第一极连接上拉节点PU，第二极连接第一时钟信号端CLK，栅极连接重置端RESET；
第三晶体管M3的第一极连接上拉节点PU，第二极连接定压端VSS，栅极连接下拉节点PD；
第四晶体管M4的第一极连接输出端OUTPUT，第二极连接定压端VSS，栅极连接下拉节点PD。
进一步优选的，保持单元包括第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8，其中，
第五晶体管M5的第一极连接第二时钟信号端CLKB，第二极连接下拉节点PD，栅极连接第七晶体管M7的第一极以及第八晶体管M8的第二极；
第六晶体管M6的第一极连接下拉节点PD，第二极连接定压端VSS，栅极连接上拉节点PU；
第七晶体管M7的第一极连接第五晶体管M5的栅极，第二极连接定压端VSS，栅极连接上拉节点PU；
第八晶体管M8的第一极连接第二时钟信号端CLKB，第二 极连接第五晶体管M5的栅极，栅极连接第二时钟信号端CLKB。
进一步优选的，输出单元包括第九晶体管M9，其中，
第九晶体管M9的第一极连接第一时钟信号端CLK，第二极连接输出端OUTPUT，栅极连接上拉节点PU。
进一步优选的，下拉单元包括第十晶体管M10；其中，
第十晶体管M10的第一极连接输出端OUTPUT，第二极连接定压端VSS，栅极连接第二时钟信号端CLKB。
进一步优选的，充电单元包括存储电容C；其中，
存储电容C的第一端连接上拉节点PU，第二端连接输出端OUTPUT。
优选的，以上晶体管全部为N型晶体管，更具体为N型薄膜晶体管；或，以上晶体管全部为P型晶体管，更具体为P型薄膜晶体管。
本实施例还提供一种栅极驱动电路，其包括：
多个级联的上述的移位寄存器。
优选的，如图2所示，栅极驱动电路还包括：第一控制线、第二控制线、定压线；其中，
第一控制线与所有奇数级的移位寄存器的第一时钟信号端CLK和所有偶数级的移位寄存器的第二时钟信号端CLKB相连；
第二控制线与所有偶数级的移位寄存器的第一时钟信号端CLK和所有奇数级的移位寄存器的第二时钟信号端CLKB相连；
定压线与所有移位寄存器的定压端VSS相连；
移位寄存器的上拉节点PU连接上一级移位寄存器的重置端RESET和下一级移位寄存器的输入端。
也就是说，本实施例的栅极驱动电路中，各级移位寄存器并不是通过输出端与其他的移位寄存器相连，而是通过上拉节点与其他移位寄存器连接；当然，按照以上连接方式，第一级移位寄存器的输入端INPUT以及最后一级移位寄存器的重置端RESET没有输入，故需要为它们设置专门的信号线，引入使栅极驱动电 路开始工作的初始信号，在此不再详细描述。
同时，该栅极驱动电路的两条控制线(即，第一控制线和第二控制线)中分别提供反向的时钟信号，而相邻移位寄存器与两条控制线的连接方式相反，从而保证相邻移位寄存器收到的实际时钟信号相同；而定压线则为所有移位寄存器的定压端VSS提供恒定的电平信号。
本实施例的栅极驱动电路可实现双向扫描，且其中的器件数量较少，与现有的单向扫描的栅极驱动电路中的器件数量相当；并且本实施例的栅极驱动电路只需要两个控制信号(即，两个时钟信号，定压信号等看作非控制信号)，也与现有的单向扫描的栅极驱动电路相同；故本实施例的栅极驱动电路结构简单、成本低。
具体的，下面以全部晶体管都是N型晶体管为例，具体说明本实施例的栅极驱动电路的运行方式。
情况S1：当本实施例的栅极驱动电路正向(从上向下)扫描时，如图3所示，该栅极驱动电路中的移位寄存器的工作过程具体包括以下阶段S11至S15。
S11阶段：为第一时钟信号端CLK提供高电平信号，为第二时钟信号端CLKB提供低电平信号，为输入端INPUT提供高电平信号，为重置端RESET提供低电平信号，为定压端VSS提供低电平信号。
本阶段中，本级(第n级)移位寄存器的实际工作状态并未产生变化，但由于其输入端INPUT连接的是上一级(第n-1级)移位寄存器的上拉节点PU，故本阶段的状态是实际存在的，因此在此进行说明。当然，对第一级移位寄存器而言，则可用单独的信号作为其输入端INPUT的输入，故其可不存在本阶段，而直接从以下S12阶段开始工作。
在正向扫描时，上一级(第n-1级)移位寄存器先于本级(第n级)移位寄存器开始工作，故上一级移位寄存器的上拉节点PU变为高电平时即会向本级移位寄存器的输入端INPUT提供高电平信 号。由此，本级移位寄存器中，第一晶体管M1导通，第二时钟信号端CLKB的低电平信号经第一晶体管M1引入上拉节点PU，上拉节点PU为低电平，由于存储电容C的作用，输出端OUTPUT也为低电平，本级移位寄存器输出低电平。
S12阶段：为第一时钟信号端CLK提供低电平信号，为第二时钟信号端CLKB提供高电平信号，为输入端INPUT提供高电平信号，为重置端RESET提供低电平信号，为定压端VSS提供低电平信号。
本阶段中，本级移位寄存器的输入端INPUT仍为高电平，第一晶体管M1继续导通，将第二时钟信号端CLKB的高电平信号导入上拉节点PU，上拉节点PU变为高电平，即上一级(第n-1级)移位寄存器的重置端RESET和下一级(第n+1级)移位寄存器的输入端INPUT均变为高电平；从而上一级移位寄存器进入以下S13阶段，而下一级移位寄存器进入以上S11阶段。由于上拉节点PU为高电平，故第九晶体管M9导通，将第一时钟信号端CLK的低电平引入输出端OUTPUT，本级移位寄存器仍输出低电平。同时，本级移位寄存器中，上拉节点PU的高电平还使第六晶体管M6和第七晶体管M7导通，将定压端VSS的低电平引入控制节点CN和下拉节点PD；由此，虽然此时第二时钟信号端CLKB为高电平，但第八晶体管M8等效于断路，故第五晶体管M5也关断。
S13阶段：为第一时钟信号端CLK提供高电平信号，为第二时钟信号端CLKB提供低电平信号，为输入端INPUT提供低电平信号，为重置端RESET提供高电平信号，为定压端VSS提供低电平信号。
本阶段中，本级移位寄存器的输入端INPUT和第二时钟信号端CLKB均变为低电平，从而第一晶体管M1和第十晶体管M10关断，第二时钟信号端CLKB和定压端VSS的信号不能进入上拉节点PU和输出端OUTPUT。而重置端RESET的信号为下一级(第n+1级)移位寄存器的上拉节点PU的信号，此时变为高电平；由此，第二晶体管M2导通，第一时钟信号端CLK的高电平经第二 晶体管M2进入上拉节点PU，上拉节点PU保持高电平，故第九晶体管M9导通，第一时钟信号端CLK的高电平经第九晶体管M9引入输出端OUTPUT，本级移位寄存器输出高电平。
S14阶段：为第一时钟信号端CLK提供低电平信号，为第二时钟信号端CLKB提供高电平信号，为输入端INPUT提供低电平信号，为重置端RESET提供高电平信号，为定压端VSS提供低电平信号。
本阶段中，本级移位寄存器的重置端RESET仍为高电平，从而第一时钟信号端CLK的低电平经第二晶体管M2传至上拉节点PU，上拉节点PU变为低电平，即上一级(第n-1级)移位寄存器的重置端RESET和下一级(第n+1级)移位寄存器的输入端INPUT均变为低电平，故上一级移位寄存器进入以下S15阶段，而下一级移位寄存器进入以上S13阶段。进一步的，第六晶体管M6和第七晶体管M7关断，定压端VSS的低电平无法进入控制节点CN和下拉节点PD，故第二时钟信号端CLKB的高电平信号经第八晶体管M8、第五晶体管M5分别进入控制节点CN和下拉节点PD，使它们均为高电平。由此，与下拉节点PD相连的第三晶体管M3和第四晶体管M4均导通，定压端VSS的低电平信号经第四晶体管M4引入(当然同时也通过第十晶体管M10引入)输出端OUTPUT，本级移位寄存器输出低电平。
S15阶段：为输入端INPUT提供低电平信号，为重置端RESET提供低电平信号，为定压端VSS提供低电平信号。
在本阶段中，本级移位寄存器的输入端INPUT和重置端RESET均为低电平信号，故第二晶体管M2、第一晶体管M1均关断。
这样，本级移位寄存器中，当第二时钟信号端CLKB提供高电平信号时，第八晶体管M8、第五晶体管M5、第十晶体管M10均导通，下拉节点PD为高电平，从而第三晶体管M3和第四晶体管M4导通，定压端VSS的低电平信号使上拉节点PU和输出端OUTPUT均为低电平，本级移位寄存器输出低电平；而当第二时 钟信号端CLKB提供低电平信号时，第八晶体管M8、第五晶体管M5、第十晶体管M10均关断，定压端VSS的信号不能导入到输出端OUTPUT和上拉节点PU，存储电容C开始放电，但由于时钟信号的周期很短，故该放电时间很短，在下一次第二时钟信号端CLKB的高电平来临前，输出端OUTPUT仍可维持低电平，本级移位寄存器输出低电平。
由此可见，只要保证输入端INPUT和重置端RESET均为低电平，则不论两个时钟信号的状态如何，移位寄存器均能保持低电平输出。
如上所述，在本实施例的栅极驱动电路正向扫描(S1情况)时，各级移位寄存器按照“第(n-1)级-第n级-第(n+1)级”的顺序(即从上至下的顺序)依次输出导通信号(高电平信号)，相邻移位寄存器的工作状态相差半个时钟周期。对任意一级(第n级)移位寄存器而言，其所需的输入端INPUT的信号比上拉节点PU的电平领先半个时钟周期，故正好可将上一级(第n-1级)移位寄存器的上拉节点PU连接至本级移位寄存器的输入端INPUT；同时，对任意一级(第n级)移位寄存器而言，其所需的重置端RESET的信号比上拉节点PU的电平落后半个时钟周期，故正好可将下一级(第n+1级)移位寄存器的上拉节点PU连接至本级移位寄存器的重置端RESET；这样，即可使每级移位寄存器都依次经历相同的驱动过程，实现了包含这些移位寄存器的栅极驱动电路(即，本实施例的栅极驱动电路)的正向扫描。
情况S2：当本实施例的栅极驱动电路反向(从下向上)扫描时，如图4所示，该栅极驱动电路中的移位寄存器的工作过程具体包括以下阶段S21至S25。
S21阶段：为第一时钟信号端CLK提供低电平信号，为第二时钟信号端CLKB提供高电平信号，为输入端INPUT提供低电平信号，为重置端RESET提供高电平信号，为定压端VSS提供低电平信号。
与正向扫描时类似，本阶段对本级(第n级)移位寄存器而言并无实际作用，但却是实际存在的，故在此进行说明。相应地，对最后一级移位寄存器而言，也可用单独的信号作为其重置端RESET的输入，故其可不存在本阶段，而直接从以下S22阶段开始工作。
在反向扫描时，下一级(第n+1级)移位寄存器先于本级(第n级)移位寄存器开始工作，故下一级移位寄存器的上拉节点PU变为高电平时即会向本级移位寄存器的重置端RESET提供高电平信号。由此，本级移位寄存器中，第二晶体管M2导通，将第一时钟信号端CLK的低电平信号引入上拉节点PU，同时第二时钟信号端CLKB为高电平，第十晶体管M10导通，定压端VSS的低电平经第十晶体管M10引入输出端OUTPUT，本级移位寄存器输出低电平。
S22阶段：为第一时钟信号端CLK提供高电平信号，为第二时钟信号端CLKB提供低电平信号，为输入端INPUT提供低电平信号，为重置端RESET提供高电平信号，为定压端VSS提供低电平信号。
本阶段中，本级移位寄存器的重置端RESET保持高电平，而第一时钟信号端CLK变为高电平，由此上拉节点PU也变为高电平，即上一级(第n-1级)移位寄存器的重置端RESET和下一级移位寄存器(第n+1级)的输入端ITPUT均变为高电平，从而上一级移位寄存器进入以上S21阶段，而下一级移位寄存器进入以下S23阶段。由于上拉节点PU为高电平，故第九晶体管M9导通，将第一时钟信号端CLK的高电平引入输出端OUTPUT；同时，本级移位寄存器中，第二时钟信号端CLKB为低电平，故第十晶体管M10关断，定压端VSS的低电平不会进入输出端OUTPUT；本级移位寄存器输出高电平。
S23阶段：为第一时钟信号端CLK提供低电平信号，为第二时钟信号端CLKB提供高电平信号，为输入端INPUT提供高电平信号，为重置端RESET提供低电平信号，为定压端VSS提供低 电平信号。
本阶段中，下一级(第n+1)级移位寄存器进入以下S24阶段，故其上拉节点PU变为低电平，即本级(第n级)移位寄存器的重置端RESET变为低电平；同时上一级(第n-1)级移位寄存器进入以上S22阶段，故本级(第n级)级移位寄存器的输入端INPUT变为高电平。本级(第n级)级移位寄存器中，由于输入端INPUT为高电平，故第一晶体管M1导通，将第二时钟信号端CLKB的高电平信号引入上拉节点PU，上拉节点PU保持高电平，进而，第九晶体管M9导通，将第一时钟信号端CLK的低电平引入输出端OUTPUT，本级移位寄存器输出低电平。
S24阶段：为第一时钟信号端CLK提供高电平信号，为第二时钟信号端CLKB提供低电平信号，为输入端INPUT提供高电平信号，为重置端RESET提供低电平信号，为定压端VSS提供低电平信号。
本阶段中，本级移位寄存器的输入端INPUT保持高电平，故第二时钟信号端CLKB的低电平经过第一晶体管M1将上拉节点PU变为低电平，进而第九晶体管M9关断，第一时钟信号端CLK的信号不能引入输出端OUTPUT，输出端OUTPUT根据存储电容C的作用保持低电平，本级移位寄存器输出低电平。
S25阶段：为输入端INPUT提供低电平信号，为重置端RESET提供低电平信号，为定压端VSS提供低电平信号。
与以上正向扫描时的S15阶段相同，本阶段中，本级移位寄存器的输入端INPUT和重置端RESET均为低电平，故通过存储电容C的作用，不论两个时钟信号端的信号如何，输出端OUTPUT都保持低电平，在此不再详细描述。
如上所述，在本实施例的栅极驱动电路反向扫描(S2情况)时，各级移位寄存器按照“第(n+1)级-第n级-第(n-1)级”的顺序(即从下至上的顺序)依次输出导通信号(高电平信号)，相邻移位寄存器的工作状态相差半个时钟周期。对任意一级(第n级)移位寄存器而言，其所需的输入端INPUT的信号比上拉节点PU的电平落后 半个时钟周期，故正好可将上一级(第n-1级)移位寄存器的上拉节点PU连接至本级移位寄存器的输入端INPUT；同时，对任意一级(第n级)移位寄存器而言，其所需的重置端RESET的信号比上拉节点PU的电平领先半个时钟周期，故正好可将下一级(第n+1级)移位寄存器的上拉节点PU连接至本级移位寄存器的重置端RESET；这样，即可使每级移位寄存器都依次经历相同的驱动过程，实现了包含这些移位寄存器的栅极驱动电路(即，本实施例的栅极驱动电路)的反向扫描。
由此可见，本实施例的栅极驱动电路中，只要改变其初始信号的情况，即可分别实现正向扫描和反向扫描两种不同的扫描方式，即实现双向扫描。
应当理解，虽然以上是以所有晶体管均为N型晶体管为例进行说明，但应当理解，若所有晶体管均为P型晶体管，则只要使所有信号的电平都相反，即可使栅极驱动电路按照相同的过程进行工作和输出(区别仅在于输出信号中以低电平为导通信号)，在此不再详细描述。
第二实施例
本实施例提供一种阵列基板，其包括：
多条栅线；
上述的栅极驱动电路，栅极驱动电路的每个移位寄存器的输出端连接一条栅线。
当然，阵列基板中还应包括数据线、像素电路等其他已知结构，在此不再详细描述。
本实施例还提供一种显示装置，其包括上述的阵列基板。
具体的，该显示装置可为液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等具有显示功能的任何产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (11)

  1. 一种移位寄存器，包括缓冲放电单元、保持单元、输出单元、下拉单元、充电单元、输入端、重置端、第一时钟信号端、第二时钟信号端、定压端和输出端，其中：
    缓冲放电单元根据输入端的信号、重置端的信号以及下拉节点的电平，控制是否将定压端的信号传至输出端，以及是否将定压端的信号和第二时钟信号端的信号传至上拉节点；
    保持单元根据第二时钟信号端的信号和上拉节点的电平控制下拉节点的电平；
    输出单元根据上拉节点的电平控制是否将第一时钟信号端的信号传至输出端；
    下拉单元根据第二时钟信号端的信号控制是否将定压端的信号传至输出端；
    充电单元保持输出端的电平。
  2. 根据权利要求1所述的移位寄存器，其中，所述缓冲放电单元包括第一晶体管、第二晶体管、第三晶体管、第四晶体管，以及其中：
    所述第一晶体管的第一极连接第二时钟信号端，第二极连接上拉节点，栅极连接输入端；
    所述第二晶体管的第一极连接上拉节点，第二极连接第一时钟信号端，栅极连接重置端；
    所述第三晶体管的第一极连接上拉节点，第二极连接定压端，栅极连接下拉节点；
    所述第四晶体管的第一极连接输出端，第二极连接定压端，栅极连接下拉节点。
  3. 根据权利要求2所述的移位寄存器，其种，所述保持单元包括第五晶体管、第六晶体管、第七晶体管、第八晶体管，以及 其中：
    所述第五晶体管的第一极连接第二时钟信号端，第二极连接下拉节点，栅极连接第七晶体管的第一极以及第八晶体管的第二极；
    所述第六晶体管的第一极连接下拉节点，第二极连接定压端，栅极连接上拉节点；
    所述第七晶体管的第一极连接第五晶体管的栅极，第二极连接定压端，栅极连接上拉节点；
    所述第八晶体管的第一极连接第二时钟信号端，第二极连接第五晶体管的栅极，栅极连接第二时钟信号端。
  4. 根据权利要求3所述的移位寄存器，其中，所述输出单元包括第九晶体管，以及其中，
    所述第九晶体管的第一极连接第一时钟信号端，第二极连接输出端，栅极连接上拉节点。
  5. 根据权利要求4所述的移位寄存器，其中，所述下拉单元包括第十晶体管，以及其中，
    所述第十晶体管的第一极连接输出端，第二极连接定压端，栅极连接第二时钟信号端。
  6. 根据权利要求5所述的移位寄存器，其中，所述充电单元包括存储电容，以及其中，
    所述存储电容的第一端连接上拉节点，第二端连接输出端。
  7. 根据权利要求6所述的移位寄存器，其中，
    所有晶体管均为N型晶体管；
    或所有晶体管均为P型晶体管。
  8. 一种栅极驱动电路，其包括：
    多个级联的移位寄存器，所述移位寄存器为权利要求1至7中任意一项所述的移位寄存器。
  9. 根据权利要求8所述的栅极驱动电路，还包括第一控制线、第二控制线、定压线，其中：
    所述第一控制线与所有奇数级的移位寄存器的第一时钟信号端和所有偶数级的移位寄存器的第二时钟信号端相连；
    所述第二控制线与所有偶数级的移位寄存器的第一时钟信号端和所有奇数级的移位寄存器的第二时钟信号端相连；
    所述定压线与所有位寄存器的定压端相连；
    每个所述移位寄存器的上拉节点连接上一级移位寄存器的重置端和下一级移位寄存器的输入端。
  10. 根据权利要求9所述的栅极驱动电路，其中，第一级移位寄存器的输入端输入单独的信号，最后一级移位寄存器的重置端输入单独的信号。
  11. 一种阵列基板，其包括：
    多条栅线；
    权利要求8至10中任一项所述的栅极驱动电路，栅极驱动电路的每个移位寄存器的输出端连接一条栅线。
PCT/CN2017/070233 2016-04-26 2017-01-05 移位寄存器、栅极驱动电路、阵列基板 Ceased WO2017185822A1 (zh)

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