WO2017183511A1 - 不揮発性半導体記憶装置 - Google Patents
不揮発性半導体記憶装置 Download PDFInfo
- Publication number
- WO2017183511A1 WO2017183511A1 PCT/JP2017/014766 JP2017014766W WO2017183511A1 WO 2017183511 A1 WO2017183511 A1 WO 2017183511A1 JP 2017014766 W JP2017014766 W JP 2017014766W WO 2017183511 A1 WO2017183511 A1 WO 2017183511A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- side wall
- capacitor
- insulating film
- capacitive
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 138
- 238000003860 storage Methods 0.000 title claims abstract description 64
- 239000003990 capacitor Substances 0.000 claims abstract description 328
- 125000006850 spacer group Chemical group 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims description 52
- 239000011810 insulating material Substances 0.000 claims description 38
- 239000007769 metal material Substances 0.000 claims description 15
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 238000005549 size reduction Methods 0.000 abstract 1
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 139
- 238000004519 manufacturing process Methods 0.000 description 36
- 239000000463 material Substances 0.000 description 31
- 238000000034 method Methods 0.000 description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 229910004298 SiO 2 Inorganic materials 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 13
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 13
- 238000010586 diagram Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- RGCLLPNLLBQHPF-HJWRWDBZSA-N phosphamidon Chemical compound CCN(CC)C(=O)C(\Cl)=C(/C)OP(=O)(OC)OC RGCLLPNLLBQHPF-HJWRWDBZSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 230000001590 oxidative effect Effects 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 4
- 229910003468 tantalcarbide Inorganic materials 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 244000126211 Hericium coralloides Species 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Definitions
- the present invention relates to a nonvolatile semiconductor memory device.
- nonvolatile semiconductor memory device a nonvolatile semiconductor memory device in which memory cells each having a charge storage layer in a memory gate structure are arranged in a matrix is known.
- data is written by injecting charge into the charge storage layer of the memory cell, while data can be erased by drawing out the charge in the charge storage layer.
- a low bit voltage is applied to the channel layer of the memory gate structure and a high charge storage gate voltage is applied to the memory gate electrode.
- Charges can be injected into the charge storage layer by the quantum tunnel effect caused by the voltage difference between the bit voltage and the memory gate voltage.
- Such a nonvolatile semiconductor memory device is known to have a charge pump circuit that generates a high-voltage charge storage gate voltage to be applied to a memory cell.
- a Dickson type charge pump circuit is known as a basic charge pump circuit.
- FIG. 10 is a circuit diagram of a four-stage Dickson charge pump circuit 100, for example.
- V1 indicates a constant input voltage input from the input electrode
- V2 indicates an output voltage output from the output electrode
- Patent Document 1 discloses a manufacturing method in which a capacitor element is formed simultaneously with a memory cell using a process for manufacturing the memory cell. Specifically, Patent Document 1 discloses a technique for forming a capacitor element used in a drive circuit of a memory cell using a process for manufacturing a charge storage type memory cell having a control gate electrode and a memory gate electrode. ing.
- Patent Document 1 after forming a control gate electrode, an ONO film in which a silicon oxide film, a silicon nitride film serving as a charge storage layer, and a silicon oxide film are stacked is formed in a memory cell formation region and a capacitor element formation region.
- the memory gate electrode is formed at a predetermined position on the ONO film in the memory cell formation region.
- a part of an ONO film that causes charge accumulation in a memory cell is left in a capacitor element formation region, and the ONO film is used as a capacitor insulating film in the capacitor element.
- the ONO film used as a capacitor insulating film is optimized for film quality and film thickness by focusing on the write operation, read operation and erase operation of the memory cell.
- the withstand voltage characteristic when applied is insufficient.
- a high-voltage charge storage gate voltage is generated in the last-stage capacitor element, so that the capacitor insulation film of the capacitor element arranged in the last stage is continuously applied.
- a high voltage charge storage gate voltage is applied to the gate. Therefore, when the ONO film is used as the capacitor insulating film in the conventional charge pump circuit 100, there is a problem that the withstand voltage of the capacitor insulating film is not sufficient.
- a plurality of capacitive elements provided in the charge pump circuit are divided into a front stage side and a rear stage side, a plurality of capacitive elements on the front stage side, and a plurality of capacitive elements on the rear stage side It is also conceivable to provide separate power sources.
- a plurality of power supplies for applying different voltages to the plurality of capacitive elements on the front stage side and the plurality of capacitive elements on the rear stage side are provided. There is a problem that the configuration becomes complicated by that amount, and the size cannot be reduced.
- the present invention has been made in consideration of the above points, and proposes a nonvolatile semiconductor memory device that can stabilize the capacitance characteristic while improving the breakdown voltage characteristic of the capacitor and can be downsized.
- the purpose is to do.
- One side wall spacer made of an insulating material provided along the side surface, another side wall spacer made of the insulating material provided along the other side surface of the memory gate structure, and the first selection gate insulating film A first selection gate electrode provided on the first sidewall spacer, and a second selection gate electrode formed on the second selection gate insulating film.
- a second selection gate structure formed along the other sidewall spacer, and provided on the surface of the semiconductor substrate adjacent to the first selection gate structure so as to be insulated from the first selection gate electrode.
- the charge pump circuit is provided with a plurality of capacitive elements, and each of the capacitive elements has the one sidewall spacer and the other between the capacitive electrode and the capacitive sidewall electrode.
- a capacitor side wall insulating film made of the same layer as the side wall spacer is provided.
- the same film as the sidewall spacer of the memory cell is used for the capacitive sidewall insulating film of the capacitive element of the charge pump circuit provided on the same semiconductor substrate as the memory cell. Since the side wall spacer of the memory cell can adjust the film quality and film thickness by paying attention to the withstand voltage, when used as the capacitor side wall insulating film of the capacitive element of the charge pump circuit, the capacitance of the capacitive element is improved while improving the withstand voltage characteristic of the capacitive element. The characteristics can be stabilized. In addition, since a power supply for suppressing the voltage applied to the capacitor element to a low voltage is not required, the configuration can be simplified and the size can be reduced accordingly.
- FIG. 4 is a schematic diagram showing a cross-sectional configuration at a BB ′ portion in FIG. 3. It is the schematic which shows the planar layout of the charge pump circuit provided with four capacitive elements. It is sectional drawing which shows the structure of the non-volatile semiconductor memory device by other embodiment. It is the schematic which shows the planar layout of the non-volatile semiconductor memory device provided with the fin part.
- FIG. 8A is a schematic diagram showing a cross-sectional configuration at a DD ′ portion in FIG. 7, and FIG. 8B is a schematic diagram showing a cross-sectional configuration at a EE ′ portion in FIG.
- FIG. 8 is a schematic diagram illustrating a cross-sectional configuration in the FF ′ portion of FIG. 7. It is a circuit diagram which shows the circuit structure of the conventional charge pump circuit. 4 is a timing chart showing the relationship between an input voltage V1 applied to a charge pump circuit, each voltage of a first clock ⁇ 1 and a second clock ⁇ 2, and an output voltage V2.
- Nonvolatile Semiconductor Memory Device of Present Invention 1-1.
- Memory cell 1-1-1 Operation of write selection memory cell 1-1-2.
- Operation of write unselected memory cell 1-1-3 Operation of read memory cell 1-1-4.
- About charge pump circuit ⁇ 2.
- Action and Effect> ⁇ Regarding Charge Pump Circuit with Four Capacitance Elements> ⁇ 4.
- Nonvolatile Semiconductor Memory Device According to Other Embodiment> ⁇ 5.
- a memory cell 2 and a charge pump circuit 4 are formed on the same semiconductor substrate S1.
- a voltage obtained by boosting the input voltage by the charge pump circuit 4 can be applied to the memory gate electrode MG of the memory cell 2.
- one memory cell 2 is shown, but actually, a plurality of memory cells 2 are arranged in the row direction and the column direction, and the memory cell array 2 is arranged in a matrix. Configure.
- a drain region 8a and a source region 8b are formed at a predetermined distance on the surface of the semiconductor substrate S1, and a first selection gate structure 6 and a memory gate structure 5 are formed between the drain region 8a and the source region 8b.
- a second selection gate structure 7 is disposed.
- a bit line BL is connected to the drain region 8a formed on the surface of the semiconductor substrate S1 adjacent to the first select gate structure 6, and a bit voltage applied to the bit line BL can be applied.
- the source line SL is connected to the source region 8b formed on the surface of the semiconductor substrate S1 adjacent to the second select gate structure 7, and the source voltage applied to the source line SL can be applied.
- the memory gate structure 5 is formed on the semiconductor substrate S1 between the drain region 8a and the source region 8b via a lower memory gate insulating film 10 made of an insulating material such as silicon oxide (SiO, SiO 2 ), for example, silicon nitride ( Si 3 N 4 ), silicon oxynitride (SiON), alumina (Al 2 O 3 ), hafnium oxide (HfO 2 ), etc., and has a charge storage layer EC.
- the memory gate electrode MG is provided via the upper memory gate insulating film 11 made of the same insulating material as the lower memory gate insulating film 10. As described above, the memory gate structure 5 has a configuration in which the charge storage layer EC is insulated from the semiconductor substrate S1 and the memory gate electrode MG by the lower memory gate insulating film 10 and the upper memory gate insulating film 11.
- the memory gate electrode MG is formed of a conductive material such as polysilicon, for example, and a charge storage gate voltage boosted by, for example, a charge pump circuit 4 described later can be applied via the memory gate line ML.
- a wall-like side wall spacer 13a made of an insulating material such as silicon oxide (SiO, SiO 2 ), for example, is formed along one side wall, and the first side wall spacer 13a passes through the first side wall spacer 13a.
- a select gate structure 6 is adjacent.
- the sidewall spacer 13a formed between the memory gate structure 5 and the first selection gate structure 6 is formed with a predetermined film thickness, and the memory gate electrode MG of the memory gate structure 5 and the first selection The gate structure 6 can be insulated from the first selection gate electrode DG.
- the distance between the memory gate electrode MG and the first selection gate electrode DG is less than 5 [nm]
- the sidewall spacer 13a There is a risk of breakdown voltage failure.
- the semiconductor substrate S1 for example, 50 [nm from the surface) between the memory gate electrode MG and the first selection gate electrode DG. ] (Region (surface region)) until the data is read, it becomes difficult for a read current to flow between the memory gate structure 5 and the first select gate structure 6.
- the distance between the memory gate electrode MG and the first selection gate electrode DG is preferably formed to be 5 [nm] or more and 40 [nm] or less, and the film thickness of the sidewall spacer 13a Also, it is desirable that the thickness be 5 [nm] or more and 40 [nm] or less.
- a first selection gate electrode DG made of a conductive material such as polysilicon is formed on the first selection gate insulating film 12a, and the first selection gate line A predetermined voltage may be applied from DL to the first selection gate electrode DG.
- the distance be 5 [nm] or more and 40 [nm] or less. Therefore, in the case of this embodiment, it is desirable that the film thickness of the sidewall spacer 13b provided between the memory gate electrode MG and the second selection gate electrode SG is also 5 [nm] or more and 40 [nm] or less.
- the second select gate structure 7 is made of an insulating material such as silicon oxide (SiO, SiO 2 ) on the semiconductor substrate S1 between the side wall spacer 13b and the source region 8b, and has a film thickness of 9 nm or less.
- the second selection gate insulating film 12b having a thickness of 3 [nm] or less is provided.
- the second select gate insulating film 12b is formed in a manufacturing process different from the side wall spacers 13a and 13b, and the film thickness thereof is smaller than the film thickness of the side wall spacers 13a and 13b. .
- a second selection gate electrode SG made of a conductive material such as polysilicon is formed on the second selection gate insulating film 12b, and the second selection gate line A predetermined voltage may be applied from the SGL to the second selection gate electrode SG.
- the side wall spacers 13a and 13b provided in the memory cell 2 are formed by a CVD (chemical vapor deposition) method, and the film quality is better than an oxide film formed by thermally oxidizing polysilicon. Therefore, it is possible to design a film having a high withstand voltage and a high degree of freedom without considering consumption due to thermal oxidation of polysilicon.
- CVD chemical vapor deposition
- the film thickness and film quality of the lower memory gate insulating film 10, the charge storage layer EC, the upper memory gate insulating film 11, the first selection gate insulating film 12a, and the second selection gate insulating film 12b depend on the write operation of the memory cell 2. In order to optimize the read and erase operations.
- the side wall spacers 13a and 13b are formed as different layers independent of the above-described lower memory gate insulating film 10 and the like.
- the film quality and film thickness can be set by paying attention to the breakdown voltage between the gate structures 6 and between the memory gate structure 5 and the second selection gate structure 7.
- a charge storage gate voltage Vprog (for example, a voltage of 12 [V]) is applied to the memory gate electrode MG from the memory gate line ML, and a reference voltage Vss (for example, 0 [V]) is applied as a substrate voltage to the semiconductor substrate S1. Is applied).
- a reference voltage Vss (for example, a voltage of 0 [V]) is applied to the second selection gate electrode SG as a gate-off voltage from the second selection gate line SGL, and a source-off voltage is applied to the source region 8b from the source line SL.
- a reference voltage Vss (for example, a voltage of 0 [V]) is applied.
- the second selection transistor T2 is turned off, and a source-side non-conducting region is formed in the semiconductor substrate S1 immediately below the second selection gate structure 7.
- the source region 8b and the channel layer forming carrier region (the region in which carriers are induced when forming the channel layer) of the semiconductor substrate S1 immediately below the memory gate structure 5 are electrically connected by the source-side non-conducting region.
- the channel layer forming carrier region is blocked and voltage application from the source line SL is blocked.
- the power supply voltage Vdd (for example, a voltage higher than 0 [V] and lower than 1.5 [V]) is applied as the first selection gate line selection voltage from the first selection gate line DL to the first selection gate electrode DG.
- a reference voltage Vss (for example, a voltage of 0 [V]) is applied to the drain region 8a as a write voltage from the bit line BL.
- the first selection transistor T1 is turned on, a drain-side conduction region is formed in the semiconductor substrate S1 immediately below the first selection gate structure 6, and a drain region 8a and a channel layer formation immediately below the memory gate structure 5 are formed.
- the carrier region is electrically connected.
- a depletion layer is formed in the channel layer forming carrier region directly below the memory gate structure 5, and based on the charge storage gate voltage, the semiconductor substrate S1 directly below the memory gate structure 5
- the potential increases and the voltage difference between the memory gate electrode MG and the surface of the semiconductor substrate S1 becomes smaller. Therefore, in the write unselected memory cell 2, the depletion layer does not cause a voltage difference that causes a quantum tunnel effect between the memory gate electrode MG and the semiconductor substrate S1, and prevents charge injection into the charge storage layer EC. it can.
- the potential on the surface of the semiconductor substrate S1 immediately below the memory gate structure 5 is reduced by the depletion layer formed on the semiconductor substrate S1 immediately below the memory gate structure 5. It is possible to prevent the first selection gate insulating film 12a of 6 and the second selection gate insulating film 12b of the second selection gate structure 7 from reaching.
- the low voltage write voltage applied from the bit line BL to the drain region 8a and the first select gate line select voltage applied to the first select gate electrode DG are matched. Even if the first select gate insulating film 12a is thin, the potential of the semiconductor substrate S1 immediately below the memory gate structure 5 is blocked by the depletion layer. 12a dielectric breakdown can be prevented.
- the semiconductor substrate S1 immediately below the memory gate structure 5 becomes conductive, and the drain region 8a The source region 8b is electrically connected, and as a result, the source line SL of the reference voltage Vss and the bit line BL of the power supply voltage Vdd are electrically connected via the memory cell 2. Thereby, in the nonvolatile semiconductor memory device 1, the read voltage of the power supply voltage Vdd of the bit line BL connected to the read memory cell 2 is lowered.
- the data read operation of whether or not charges are accumulated in the charge accumulation layer EC of the memory cell 2 by detecting whether or not the read voltage of the bit line BL has changed. Can be executed. Note that a read unselect voltage of the same reference voltage Vss as the source voltage can be applied to the bit line BL to which only the memory cell (read unselected memory cell) 2 from which data is not read is connected.
- the nonvolatile semiconductor memory device 1 includes a plurality of capacitive elements C1, C2,... And PN junction diodes D1, D2, D3,.
- a Dixon type charge pump circuit 4 is provided.
- FIG. 1 shows a cross-sectional configuration of a region in which, for example, two capacitive elements C1 and C2 are arranged.
- One capacitive element C1 is formed between the PN junction diodes D1 and D2, and the PN junction diode D2, Another capacitive element C2 is formed between D3.
- the description will be made by paying attention to the capacitive element C1, and the description of the capacitive element C2 having the same basic configuration as that of the capacitive element C1 will be omitted to avoid duplication of description.
- the capacitive element C1 includes capacitive side wall electrodes 19a and capacitive electrode structures 16a that are arranged alternately in turn, and further between the capacitive side wall electrodes 19a and the capacitive electrode structure 16a.
- Each has a configuration in which a wall-shaped capacitor side wall insulating film 21 is provided.
- the insulating layer IS has a configuration in which a plurality of capacitive electrode structures 16a having the same configuration are arranged at a predetermined interval.
- the capacitor electrode structure 16a has a configuration in which the charge storage layer ECa and the insulating film 11a are sequentially stacked on the insulating layer IS, and the capacitor electrode 17a is further provided on the insulating film 11a.
- the capacitor electrode 17a is formed in the manufacturing process of forming the memory gate electrode MG of the memory cell 2, and is the same layer as the memory gate electrode MG.
- the charge storage layer ECa provided in the capacitor electrode structure 16a is formed in the manufacturing process of forming the charge storage layer EC of the memory cell 2, and is the same layer as the charge storage layer EC.
- the insulating film 11a provided on the capacitor electrode structure 16a is formed in the manufacturing process of forming the upper memory gate insulating film 11 of the memory cell 2, and is the same layer as the upper memory gate insulating film 11.
- the capacitor side wall insulating film 21 is formed in the manufacturing process of forming the side wall spacers 13a and 13b of the memory cell 2, and is the same layer as the side wall spacers 13a and 13b. For this reason, the capacitor side wall insulating film 21 does not include the charge storage layer ECa, and is formed only from an insulating material such as silicon oxide (SiO, SiO 2 ) having the same film quality as the side wall spacers 13a and 13b.
- the film thickness of the capacitor side wall insulating film 21 is formed to be 5 [nm] or more and 40 [nm] or less in accordance with the film thickness of the side wall spacers 13a and 13b.
- the capacitor side wall insulating film 21 is formed along each side wall of the capacitor electrode structure 16a when the side wall spacers 13a and 13b of the memory cell 2 are formed by the CVD method. Because it is the same layer as the sidewall spacers 13a and 13b, the film quality is better and the withstand voltage is higher than the oxide film formed by thermally oxidizing polysilicon, and the consumption due to the thermal oxidation of polysilicon is not considered. Therefore, it is possible to design the film thickness with a high degree of freedom.
- the capacitor side wall insulating film 21 includes a lower memory gate insulating film 10, a charge storage layer EC, and an upper memory whose film thickness and film quality are restricted in order to optimize the write operation, read operation, and erase operation of the memory cell 2. Since the gate insulating film 11, the first selection gate insulating film 12a, and the second selection gate insulating film 12b are formed as independent and different layers, the capacitor electrode structure 16a (16b) is not subject to the restriction. The film quality and film thickness can be set by paying attention to the breakdown voltage between the capacitor side wall electrodes 19a (19b).
- the capacitor side wall electrode 19a formed along the capacitor side wall insulating film 21 is formed in the manufacturing process of forming the first selection gate electrode DG and the second selection gate electrode SG of the memory cell 2, and the first selection It is the same layer as the gate electrode DG and the second selection gate electrode SG.
- the capacitive side wall electrode 19a between the adjacent capacitive electrode structures 16a is formed so as to fill a gap between the capacitive side wall insulating films 21 arranged to face each other between the adjacent capacitive electrode structures 16a.
- the terminal capacitive electrode structure 16a that is not adjacent to the other capacitive element C2 is formed with the reverse conductivity type junction 15a of the PN junction diode D1 along the capacitive sidewall insulating film 21.
- the reverse of the PN junction diode D2 is filled so as to fill a gap between the capacitive sidewall insulating film 21 in one capacitive element C1 and the capacitive sidewall insulating film 21 in the other capacitive element C2.
- a conductive junction 15b is formed.
- a reverse conductivity type junction 15c of the PN junction diode D3 is formed between the adjacent capacitive element C2 and another capacitive element (not shown).
- the reverse conductivity type junctions 15a, 15b, 15c are formed of a reverse conductivity type semiconductor material having a different conductivity type from the capacitance electrodes 17a, 17b and the capacitance side wall electrodes 19a, 19b, and the capacitance elements C1, C2,. PN junction diodes D1, D2, and D3, which will be described later, can be formed in adjacent regions.
- the capacitor electrodes 17a, 17b and the capacitor side wall electrodes 19a, 19b are formed of an N-type semiconductor material
- the reverse conductivity type junctions 15a, 15b, 15c are formed of a P-type semiconductor material. It is formed by.
- the reverse conductivity type junctions 15a, 15b, and 15c are the same layer as the capacitor side wall electrodes 19a and 19b, and form the capacitor side wall electrodes 19a and 19b, and an input electrode 24a and an output electrode 24b described later in the manufacturing process.
- the semiconductor material remaining at this time is formed by doping a P-type impurity by ion implantation.
- the capacitive element C2 is different from the capacitive element C1 described above in that it is formed between the reverse conductivity type junctions 15b and 15c.
- the capacitive electrode structure 16b and the capacitive sidewall electrode 19b are described above.
- the capacitor C1 has the same configuration as the capacitor electrode structure 16a and the capacitor side wall electrode 19a.
- a Dickson type charge pump circuit 4 provided with two capacitive elements C1, C2 and three PN junction diodes D1, D2, D3 will be described. To do.
- the Dickson type charge pump circuit 4 provided with two capacitive elements C1, C2 and three PN junction diodes D1, D2, D3 is provided between the input electrode and the output electrode.
- PN junction diodes D1, D2, and D3 are connected in series, and the capacitance side wall electrode 19a of the capacitive element C1 and the anode of the PN junction diode D2 are connected to the cathode of the PN junction diode D1, and the cathode of the PN junction diode D2 In addition, the capacitor side wall electrode 19b of the capacitor C2 and the anode of the PN junction diode D3 are connected.
- the input voltage V1 is applied to the anode of the PN junction diode D1, and the voltage of the first clock ⁇ 1 is applied to the capacitor electrode 17a of one capacitor element C1 that is an odd-numbered stage.
- the voltage of the second clock ⁇ 2 having the opposite phase to the first clock ⁇ 1 is applied to the capacitor electrode 17b of C2.
- the charge pump circuit 4 repeatedly charges and discharges the charge at the timing of the high-level and low-level voltage changes of the first clock ⁇ 1 and the second clock ⁇ 2 in the capacitive elements C1 and C2, and the first clock ⁇ 1 and the second clock ⁇ 2 A voltage obtained by multiplying the amplitude voltage by the number corresponding to the number of stages of the capacitive elements C1 and C2 is output from the output electrode as the output voltage V2.
- the charge pump circuit 4 can also be used as a negative booster circuit.
- the charge pump circuit 4 is used as a negative booster circuit, an input voltage is applied to the output electrode, the voltage of the first clock ⁇ 1 is applied to the capacitor C1, and the capacitor C2 has a phase opposite to that of the first clock ⁇ 1. The voltage of the second clock ⁇ 2 is applied.
- the charge pump circuit 4 repeatedly charges and discharges the charge at the timing of the high-level and low-level voltage changes of the first clock ⁇ 1 and the second clock ⁇ 2 in the capacitive elements C1 and C2, and the first clock ⁇ 1 and the second clock
- a negative voltage (for example, ⁇ 12 [V]) obtained by multiplying the voltage having the amplitude of the clock ⁇ 2 by the number corresponding to the number of stages of the capacitive elements C1 and C2 can be output from the input electrode.
- the negative voltage generated by the charge pump circuit 4 can be used at the time of data erasing operation for extracting charges from the charge storage layer EC of the memory cell 2.
- FIG. 3 is a schematic diagram showing a planar layout of the charge pump circuit 4 shown in FIG. 2, mainly including the capacitor electrodes 17a and 17b, the capacitor side wall electrodes 19a and 19b, and the reverse conductivity type junction 15a in FIG. 15b, 15c, capacitor side wall insulating film 21, input electrode 24a, and output electrode 24b.
- the cross-sectional configuration of the charge pump circuit 4 in FIG. 1 shows the cross-sectional configuration of the AA ′ portion in FIG.
- a PN junction diode D1 is disposed between the input electrode 24a and one capacitive element C1, and between the one capacitive element C1 and another capacitive element C2.
- a PN junction diode D2 is arranged, and a PN junction diode D3 is arranged between the other capacitive element C2 and the output electrode 24b.
- These capacitive elements C1, C2 and PN junction diodes D1, D2, D3 are alternately arranged. Has been placed.
- the capacitive element C1 includes a comb-shaped capacitive electrode structure 16a, a wall-shaped capacitive sidewall insulating film 21 formed along the sidewall of the capacitive electrode structure 16a, and the capacitive sidewall insulating film 21. And a capacitor side wall electrode 19a formed along the side wall.
- the capacitor electrode structure 16a is provided with one contact 25a at a predetermined position, and the voltage of the first clock ⁇ 1 is applied to the capacitor electrode 17a via the contact 25a.
- the capacitive sidewall insulating film 21 is formed in a meandering manner between the capacitive electrode structure 16a and the capacitive sidewall electrode 19a, so that it is disposed between the capacitive electrode structure 16a and the capacitive sidewall electrode 19a.
- the area of the capacitor side wall insulating film 21 can be increased, and a large capacity can be obtained in a limited region.
- the capacitor side wall insulating film 21 is formed in a meandering manner in accordance with the comb-teeth shape of the capacitor electrode structure 16a has been described.
- the present invention is not limited thereto, and for example, the capacitor electrode structure 16a is formed in a serpentine shape, and the capacitor side wall insulating film 21 is also formed in a serpentine shape along the capacitor electrode structure 16a.
- the capacitor electrode structure 16a is formed in a spiral shape to form the capacitor electrode structure 16a.
- the capacitor side wall insulating film 21 may be formed in a spiral shape to increase the area of the capacitor side wall insulating film 21 disposed between the capacitor electrode structure 16a and the capacitor side wall electrode 19a.
- a PN junction diode D2 provided between one capacitive element C1 and another capacitive element C2 includes a reverse-conductivity-type junction 15b and a conduction unit 28 described later.
- the reverse conductivity type junction 15b is provided between the capacitor side wall insulating films 21 facing each other in a region where one capacitor element C1 and another capacitor element C2 are adjacent to each other, and the capacitor side wall electrode 19a in the one capacitor element C1 The other capacitor element C2 is joined to the capacitor side wall electrode 19b.
- the capacitor side wall electrode 19a and the capacitor side wall electrode 19b are each made of an N-type semiconductor material (for example, N-type polysilicon), and the reverse conductivity type junction portion 15b is made of a P-type semiconductor material (for example, a P-type semiconductor material). Therefore, the capacitor side wall electrode 19a, the reverse conductivity type junction 15b, and the capacitor side wall electrode 19b constitute an NPN junction structure.
- the capacitive side wall electrode 19a and the reverse conductivity type junction 15b in the capacitive element C1 in the previous stage are, for example, a conducting portion formed of a metal material or the like Electrical connection by 28.
- the conductive portion 28 includes a first contact 29a provided on the capacitor side wall electrode 19a of the capacitive element C1, a second contact 29b provided on the reverse conductivity type junction 15b, the first contact 29a and the second contact 29a.
- connection portion 28a for connecting the contact 29b, with the first contact 29a, the connection portion 28a, and the second contact 29b interposed, and the capacitance side wall electrode 19a in the capacitive element C1 in the previous stage, and the reverse conductivity type junction portion 15b can be electrically connected.
- the configuration in which the capacitive side wall electrode 19a and the reverse conductivity type junction 15b are electrically connected that is, the NP junction structure of the NPN junction structure is electrically connected
- a PN junction diode D2 is configured by the PN junction portion 28b joined to 19b.
- the NPN junction is not provided in the region where the conducting portion 28 is not provided. Due to the formation of the structure, the capacitive side wall electrode 19a in the capacitive element C1 in the previous stage and the capacitive side wall electrode 19b in the capacitive element C2 in the subsequent stage are electrically separated.
- the capacitive element C2 in the subsequent stage also has a capacitive electrode structure 16b formed in a comb shape like the capacitive element C1 in the previous stage, and the wall along the side wall of the capacitive electrode structure 16b.
- a capacitor side wall insulating film 21 is formed.
- the capacitive element C2 in the subsequent stage is formed between the reverse conductivity type junctions 15b and 15c of the PN junction diodes D2 and D3, and between the reverse conductivity type junctions 15b and 15c, the capacitive electrode structure Capacitor side wall electrodes 19b formed in accordance with the comb-teeth shape of the body 16b are provided.
- the subsequent capacitive element C2 is provided with another contact 25b at a predetermined position of the capacitive electrode structure 16b, and the first clock ⁇ 1 is connected to the capacitive electrode 17b via the contact 25b.
- the voltage of the second clock ⁇ 2 having the opposite phase is applied.
- an output electrode 24b is provided in the subsequent capacitive element C2 via a PN junction diode D3.
- the input electrode 24a and the output electrode 24b are made of, for example, an N-type semiconductor material (for example, N-type polysilicon), and the input voltage V1 is applied to the input electrode 24a via the input contact 26a, and the output electrode 24b
- the output contact 26b connected to the memory gate line is provided at a predetermined position.
- the semiconductor material is left around the dummy insulating film 21a by the etch back performed in the manufacturing process.
- the material is used as the input electrode 24a and the output electrode 24b.
- the output voltage V2 boosted by the capacitive elements C1 and C2 is sequentially applied to the memory gate electrode MG of the memory cell 2 via the output contact 26b provided on the output electrode 24b and the memory gate line. Can be applied.
- the nonvolatile semiconductor memory device 1 having such a configuration can be formed by using a general semiconductor manufacturing process using a photolithography technique, a film forming technique such as an oxidation or CVD method, an etching technique, and an ion implantation method. The description is omitted here.
- a silicide layer formed from the surface of the capacitor side wall electrode 19a in one capacitor element C1 to the surface of the reverse conductivity type junction 15b may be provided as a conductive portion.
- the reverse conductivity type junctions 15a, 15b, 15c extending in a strip shape along the side wall of the capacitor side wall insulating film 21 is described, but the present invention is not limited to this.
- a reverse conductivity type junction is provided only in a region where the input electrode 24a and the capacitor side wall electrode 19a in one capacitor element C1 face each other, or the capacitor side wall electrode 19a in one capacitor element C1 and another capacitor element
- a reverse conductivity type junction is provided only in a region of C2 facing the capacitor side wall electrode 19b, or a reverse conductivity type junction is provided only in a region of the other capacitor element C2 where the capacitor side wall electrode 19b and the output electrode 24b are opposed. It may be provided.
- a reverse conductivity type junction is provided in a region where the conductive portion 28 is not provided.
- a junction part made of a semiconductor material may not be formed, and a physical cutting part for dividing the capacitor side wall electrodes 19a and 19b may be provided.
- the charge pump circuit 4 is provided in the insulating layer IS of the semiconductor substrate S1 provided with the memory cell 2, and the capacitive elements C1, C1 in the charge pump circuit 4 are provided.
- the capacitor sidewall insulating film 21 between the capacitor sidewall electrode 19a (19b) and the capacitor electrode 17a (17b) of C2 is formed in the same layer as the sidewall spacers 13a and 13b of the memory cell 2.
- the charge pump circuit 4 In the nonvolatile semiconductor memory device 1, the charge pump circuit 4 generates a high-voltage charge storage gate voltage Vprog that can inject charges into the charge storage layer EC by the quantum tunnel effect in the memory cell 2, and the charge storage gate voltage Vprog is applied to the memory gate electrode MG of the memory cell 2 by the memory gate line ML.
- the capacitive sidewall insulating film 21 of the capacitive elements C1 and C2 is the same layer as the sidewall spacers 13a and 13b of the memory cell 2 whose film quality and film thickness are adjusted by paying attention to the withstand voltage.
- the nonvolatile semiconductor memory device 1 does not require a power supply for suppressing the voltage applied to the capacitive element to a low voltage as in the prior art, so that the configuration can be simplified and the size can be reduced accordingly. obtain.
- the power supply voltage Vdd (for example, a voltage higher than 0 [V] and lower than 1.5 [V]) is boosted by the charge pump circuit 4 to generate a high-voltage charge storage gate voltage Vprog. Therefore, the power source in the nonvolatile semiconductor memory device 1 can be a single power source with the power source voltage Vdd.
- the Dixon type charge pump circuit 4 including two capacitance elements C1 and C2 has been described.
- the present invention is not limited to this, and a Dixon type charge pump circuit including a plurality of other capacitive elements such as three or four may be used.
- a planar layout of a Dickson charge pump circuit according to the present invention having four capacitive elements will be described below.
- FIG. 5 schematically shows a planar layout of a Dickson charge pump circuit 31 provided with four capacitive elements C1a, C2a, C3a, C4a and five PN junction diodes D1a, D2a, D3a, D4a, D5a.
- FIG. 5 shows in the charge pump circuit 31, odd-stage capacitive elements C1a and C3a to which the voltage of the first clock ⁇ 1 is applied are arranged in one direction.
- the charge pump circuit 31 includes even-stage capacitive elements C2a and C4a to which the voltage of the second clock ⁇ 2 having the opposite phase to the first clock ⁇ 1 is applied in parallel with the capacitive elements C1a and C3a. They are arranged side by side in one direction.
- the charge pump circuit 31 is provided with an input electrode 38a so as to be adjacent to the reverse conductivity type junction 40a of the first stage PN junction diode D1a disposed at one end, and the input contact 27a, to which the input voltage V1 is applied.
- 27b is provided on the input electrode 38a.
- the first stage PN junction diode D1a has a pair of dummy electrode structures 34a and 34b arranged at a predetermined distance, and a wall-shaped dummy insulating film provided along the side walls of the dummy electrode structures 34a and 34b. 32a and 32b are provided.
- the PN junction diode D1a has a plurality of dummy electrode structures 34a arranged in one direction at a predetermined distance and a plurality of dummy electrodes paired with the dummy electrode structure 34a.
- the electrode structures 34b are also arranged in one direction with a predetermined distance.
- dummy electrode structures 34a, 34b and dummy insulating films 32a, 32b are also provided in the other PN junction diodes D2a, D3a, D4a, D5a, but here the dummy provided in the first stage PN junction diode D1a
- the electrode structures 34a and 34 and the dummy insulating films 32a and 32b are formed in a manufacturing process for forming common capacitance electrode bodies 33a and 33b, which will be described later, and are in the same layer as the common capacitance electrode bodies 33a and 33b. Therefore, the dummy electrode structures 34a and 34b have a configuration in which a charge storage layer, an insulating film, and an electrode are sequentially stacked on an insulating layer, like the common capacitor electrode bodies 33a and 33b.
- the dummy insulating films 32a and 32b are formed along the side walls of the dummy electrode structures 34a and 34b in the manufacturing process for forming the capacitor side wall insulating film 32 described later. It consists of the same layer. Therefore, the dummy insulating films 32a and 32b, like the capacitor side wall insulating film 32, do not include a charge storage layer, and only an insulating material such as silicon oxide (SiO, SiO 2 ) having the same film quality as the capacitor side wall insulating film 32 is used. Can be formed from
- the dummy electrode structures 34a, 34 are arranged so that the semiconductor material can remain so as to fill the gap between the dummy insulating films 32a, 32b around the electrode structures 34a, 34b.
- the remaining semiconductor material becomes the input electrode 38a, the capacitor side wall electrodes 36a, 36b, etc.
- the joints 40a and 40b can be formed. Therefore, the reverse conductivity type junctions 40a, 40b, etc. are in the same layer as the input electrode 38a, the capacitor side wall electrodes 36a, 36b, etc.
- the PN junction diode D1a has a reverse conductivity type junction in a region where the dummy insulating film 32a of the dummy electrode structure 34a aligned in one direction and the dummy insulating film 32b of the dummy electrode structure 34b aligned in the same direction face each other.
- 40a is provided, the input electrode 38a disposed on the one dummy electrode structure 34a side and the capacitor side wall electrode 36a of the capacitor element C1a disposed on the other dummy electrode structure 34b side are connected to each other in reverse conductivity. It is divided by the mold joint 40a.
- the input electrode 38a is formed along the side wall of the dummy insulating film 32a around the one dummy electrode structure 34a, and has a sidewall shape whose top is gently inclined toward the substrate surface. Is formed.
- the input contacts 27a and 27b are formed so as to straddle the dummy insulating film 32a and the dummy electrode structure 34a from the input electrode 38a, and the width is narrow while increasing the installation area by the dummy insulating film 32a and the dummy electrode structure 34a.
- the input voltage V1 can be reliably applied to the input electrode 38a.
- the PN junction diode D1a provided between the input electrode 38a and the capacitive element C1a includes a reverse conductivity type junction 40a and a conduction unit 28.
- the conduction unit 28 allows the input electrode 38a and the reverse conductivity type junction to be connected. 40a is electrically connected.
- the input electrode 38a and the capacitor side wall electrode 36a are each made of an N-type semiconductor material (for example, N-type polysilicon), and the reverse conductivity type junction 40a is a P-type semiconductor material (for example, P-type polysilicon). Therefore, the input electrode 38a, the reverse conductivity type junction 40a, and the capacitor side wall electrode 36a constitute an NPN junction structure.
- the PN junction diode D1a has a PN junction where the reverse conductivity type junction 40a and the capacitor side wall electrode 36a are joined.
- the odd-numbered capacitive elements C1a and C3a are provided with a common capacitive electrode body 33a common to the capacitive elements C1a and C3a, and are shared by one contact 25a provided at a predetermined position of the common capacitive electrode body 33a.
- the voltage of the first clock ⁇ 1 can be applied to the capacitive electrode body 33a.
- the common capacitor electrode body 33a has a configuration in which a charge storage layer, an insulating film, and a capacitor electrode 37a are sequentially stacked on an insulating layer, and comb teeth arranged in the formation region of the first-stage capacitor element C1a. And a comb-like capacitive electrode structure 35c disposed in the formation region of the third-stage capacitive element C3a.
- the capacitive element C1a (C3a) includes such a comb-shaped capacitive electrode structure 35a (35c) and a wall-shaped capacitive sidewall formed along the sidewall of the capacitive electrode structure 35a (35c).
- the insulating film 32 includes a capacitor side wall electrode 36a (36c) formed along the side wall of the capacitor side wall insulating film 32. Since the capacitor side wall insulating film 32 is formed over the entire side wall of the common capacitor electrode body 33a, the capacitor side wall insulating film 32 is adjacent to the third stage from the side wall of the capacitor electrode structure 35a disposed in the first stage capacitor element C1a.
- the capacitor electrode structure 35a disposed in the capacitor element C3a of the eye is continuously provided over the side wall of the capacitor electrode structure 35a.
- the capacitive side wall insulating film 32 is formed in a meandering manner according to the comb-teeth shape of the capacitive electrode structures 35a and 35c, and the capacitive side wall electrodes 36a, A part of 36c is formed in a comb-like shape, and the electrical connection between the capacitor side wall electrodes 36a, 36c is cut by the cutting part 39.
- the cutting portion 39 is provided between the capacitive elements C1a and C3a, and is formed of a semiconductor material of a reverse conductivity type (in this case, P type) having a conductivity type different from that of the capacitor side wall electrodes 36a and 36c. Has been.
- the cutting part 39 can form an NPN junction structure in the junction region of the capacitive elements C1a and C3a, and can disconnect the electrical connection between the capacitive sidewall electrodes 36a and 36c.
- Each cutting portion 39 is the same layer as the reverse conductivity type junctions 40a, 40b, etc., and can be formed at the same time when the reverse conductivity type junctions 40a, 40b, etc. are formed by ion implantation performed in the manufacturing process, for example. .
- a second-stage PN junction diode D2a is provided between the first-stage capacitive element C1a and the second-stage capacitive element C2a disposed opposite to the capacitive element C1a, and the PN junction diode D2a
- the reverse conductivity type junction 40b is formed between the capacitor side wall electrode 36a in the first-stage capacitor element C1a and the capacitor side wall electrode 36b in the second-stage capacitor element C2a.
- the second-stage PN junction diode D2a is also provided with wall-like dummy insulating films 32a and 32b along the side walls of the dummy electrode structures 34a and 34b, similarly to the first-stage PN junction diode D1a described above. However, the description is omitted here.
- the second-stage PN junction diode D2a provided between the first-stage capacitor element C1a and the second-stage capacitor element C2a includes a reverse-conductivity-type junction 40b and a conduction part 28, and the conduction part 28, the capacitor side wall electrode 36a in the first-stage capacitor element C1a and the reverse conductivity type junction 40a are electrically connected. Similar to the first stage PN junction diode D1a described above, the second stage PN junction diode D2a forms an NPN junction structure with the capacitor side wall electrode 36a, the reverse conductivity type junction 40a, and the capacitor side wall electrode 36b. It has a PN junction where the conductivity type junction 40a and the capacitor side wall electrode 36a are joined.
- the even-numbered capacitive elements C2a and C4a are provided with a common capacitive electrode body 33b common to the capacitive elements C2a and C4a, and are shared by other contacts 25b provided at predetermined positions of the common capacitive electrode body 33b.
- a voltage of the second clock ⁇ 2 having a phase opposite to that of the first clock ⁇ 1 can be applied to the capacitive electrode body 33b.
- the common capacitor electrode body 33b also has a configuration in which a charge storage layer, an insulating film, and a capacitor electrode 37b are sequentially stacked on the insulating layer, and comb teeth arranged in the formation region of the second-stage capacitor element C2a. And a comb-like capacitive electrode structure 35d disposed in the formation region of the fourth-stage capacitive element C4a.
- the linearly extending portion 30a in the common capacitive electrode body 33a provided over the odd-numbered capacitive elements C1a and C3a and the even-stage capacitive elements C2a and C4a are provided.
- the linearly extending portion 30c of the common capacitor electrode body 33b is parallel to one direction, and the extended portion 30a of one common capacitor electrode body 33a and the other common capacitor electrode body 33b
- the comb-tooth shaped portions 30b and 30d of the common capacitance electrode bodies 33a and 33b are arranged in a region sandwiched between the extended portions 30c.
- the capacitive element C2a (C4a) also has a capacitive electrode structure 35b (35d) formed in a comb shape and a wall-shaped capacitive sidewall insulation formed along the sidewall of the capacitive electrode structure 35b (35d). And a capacitor side wall electrode 36b (36d) formed along the side wall of the capacitor side wall insulating film 32.
- the capacitor side wall insulating film 32 extends over the entire side wall of the common capacitor electrode body 33b. It is connected continuously.
- the capacitive sidewall insulating film 32 is formed in a meandering manner in accordance with the comb-teeth shape of the capacitive electrode structures 35b and 35d.
- a part of the capacitor side wall electrodes 36b, 36d is formed in a comb shape in accordance with the meandering shape of the capacitor side wall insulating film 32, and the electrical connection between the capacitor side wall electrodes 36b, 36d is made by the cut portion 39. Disconnected.
- the capacitor side wall insulating films 32 formed on these capacitor elements C1a, C2a, C3a, C4a form the side wall spacers 13a, 13b of the memory cell 2 shown in FIG. 1 as in the above-described embodiment. It is formed in the manufacturing process and is the same layer as the side wall spacers 13a and 13b. For this reason, the capacitor side wall insulating film 32 does not include the charge storage layer, and is formed only of an insulating material such as silicon oxide (SiO, SiO 2 ) having the same film quality as the side wall spacers 13a and 13b.
- the thickness of the capacitor side wall insulating film 32 is 5 nm or more and 40 nm or less in accordance with the thickness of the side wall spacers 13a and 13b.
- the capacitor sidewall insulating film 32 is also formed along the entire sidewalls of the common capacitor electrode bodies 33a and 33b when the sidewall spacers 13a and 13b of the memory cell 2 are formed by the CVD method. Because it is the same layer as 13a and 13b, it has better film quality and higher withstand voltage than the oxide film formed by thermally oxidizing polysilicon, and it is free without considering the consumption of polysilicon due to thermal oxidation. High degree of film thickness design is possible.
- the capacitor side wall insulating film 32 includes a lower memory gate insulating film 10, a charge storage layer EC, and an upper memory whose film thickness and film quality are restricted in order to optimize the write operation, read operation, and erase operation of the memory cell 2. Since the gate insulating film 11, the first selection gate insulating film 12a, and the second selection gate insulating film 12b (FIG. 1) are formed as independent and different layers, the capacitor electrodes 37a, The film quality and film thickness can be set by paying attention to the breakdown voltage between 37b and the capacitor side wall electrodes 36a, 36b, 36c, 36d.
- a third-stage PN junction diode D3a is provided between the second-stage capacitive element C2a and the third-stage capacitive element C3a disposed opposite to the capacitive element C2a.
- a fourth-stage PN junction diode D4a is provided between the capacitive element C3a and the fourth-stage capacitive element C4a arranged opposite to the capacitive element C3a.
- the conductive region 28 is provided in the junction region between the capacitive side wall electrode 36b (36c) on the front stage side and the reverse conductivity type junction 40c (40d), The conductive region 28 is not provided in the junction region between the reverse conductivity type junction 40c (40d) and the capacitor side wall electrode 36c (36d) on the rear stage side, and a PN junction is provided.
- the final stage PN junction diode D5a also includes a conduction portion 28 in the junction region between the capacitive sidewall electrode 36d of the capacitive element C4a and the reverse conductivity type junction 40e, while the reverse conductivity type junction 40e and the output In the junction region with the electrode 38b, the conduction portion 28 is not provided, but a PN junction portion is provided.
- the capacitor side wall insulating film 32 in the charge pump circuit 31 is formed in the same manner as the nonvolatile semiconductor memory device 1 shown in FIG.
- the withstand voltage characteristics of the capacitive elements C1a, C2a, C3a, and C4a are improved as compared with the conventional capacitive element in which the silicon nitride film is provided in the capacitive insulating film. Capacitance characteristics can be stabilized while improving.
- the charge pump circuit 31 does not require a power source for suppressing the voltage to a low level as in the prior art, and accordingly, the configuration can be simplified and the size can be reduced.
- dummy electrode structures 34a and 34b are provided for the PN junction diodes D1a, D2a, D3a, D4a, and D5a.
- the capacitor side wall electrodes 36a, 36b, 36c, 36d are formed from the semiconductor material by etch back in the manufacturing process, the semiconductor material remains around the dummy electrode structures 34a, 34b. Therefore, the reverse conductive type junctions 40a, 40b, 40c, 40d, and 40e of the respective PN junction diodes D1a, D2a, D3a, D4a, and D5a can be easily formed using the remaining semiconductor material.
- the common capacitance electrode is disposed in a region sandwiched between the extension portion 30a of the common capacitance electrode body 33a and the extension portion 30c of the common capacitance electrode body 33b.
- the present invention is not limited to this, and the extension portions 30a of the common capacitance electrode body 33a and the extension of the common capacitance electrode body 33b are described.
- the comb-shaped portions 30b and 30d of the common capacitor electrode bodies 33a and 33b are not provided in the region sandwiched between the mounting portions 30c, and the comb teeth of the common capacitor electrode bodies 33a and 33b are provided at various other locations.
- the shape portions 30b and 30d may be provided.
- the present invention is not limited to this, the memory gate electrode, the first selection gate electrode, the second selection gate electrode
- the capacitor electrode and the capacitor side wall electrode may be formed of a metal material such as aluminum (Al), titanium aluminum (TiAl), tantalum carbide (TaC), or silicon tantalum nitride (TaSiN).
- the memory cell 42 shown in FIG. 6 also includes the above-mentioned “(1-1-1) Operation of write selected memory cell”, “(1-1-2) Operation of write unselected memory cell”, “(1- Although operations according to “1-3) Operation of Read Memory Cell” and “(1-1-4) Operation of Erase Memory Cell” can be executed, the description thereof is omitted here to avoid duplication of description.
- the upper surfaces of the memory cell 42 and the charge pump circuit 44 are flattened by the flattening process such as CMP performed in the manufacturing process. 44 is covered with an interlayer insulating layer 57 and an upper interlayer insulating layer (not shown).
- the memory cell 42 includes, for example, a memory gate structure 45 that forms a memory transistor MT, a first selection gate structure 46 that forms a first selection transistor T1, and a second selection transistor T2 that are formed on a semiconductor substrate S1.
- Two selection gate structures 47 are formed, and silicide layers 43a and 43b are formed on the surfaces of the drain region 8a and the source region 8b, respectively.
- a wall-like sidewall portion 55a made of SiN or the like formed along the side wall of the first selection gate structure 46 is provided on the surface of the drain region 8a, and the second selection gate is provided on the surface of the source region 8b.
- a wall-shaped side wall portion 55b made of SiN or the like formed along the side wall of the structure 47 is provided.
- the upper memory gate insulating film 48 of the memory gate structure 45, the first selection gate insulating film 54a of the first selection gate structure 46, and the second selection gate insulating film 54b of the second selection gate structure 47 Is formed of an insulating material different from the lower memory gate insulating film 10 (for example, a high-k material such as hafnium oxide (HfO 2 ) or hafnium nitride silicate (HfSiON)).
- a high-k material such as hafnium oxide (HfO 2 ) or hafnium nitride silicate (HfSiON)
- a wall-like side wall spacer 51a made of an insulating material is formed along one side wall, and a wall-like gate side wall insulating film 52a is formed along the side wall spacer 51a.
- the first select gate structure 46 is adjacent to each other through the side wall spacer 51a and the gate side wall insulating film 52a.
- the memory gate structure 45 is formed with a wall-like side wall spacer 51b made of an insulating material along the other side wall opposite to the one side wall, and has a wall shape along the side wall spacer 51b.
- the gate side wall insulating film 52b is formed, and the second select gate structure 47 is adjacent to each other through the side wall spacer 51b and the gate side wall insulating film 52b.
- the gate sidewall insulating films 52a and 52b do not have the charge storage layer EC formed therein, and are formed of an insulating material (for example, a high-k material) different from the sidewall spacers 51a and 51b.
- the combined thickness of the side wall spacer 51a (51b) and the gate side wall insulating film 52a (52b) is a problem of breakdown voltage failure in the side wall spacer 51a (51b) and the gate side wall insulating film 52a (52b), and the memory gate structure 45 and Since there is a possibility that a read current decrease between the first selection gate structures 46 (second selection gate structures 47) may occur, the distance may be 5 nm or more and 40 nm or less. desirable.
- the memory gate electrode MG1, the first selection gate electrode DG1, and the second selection gate electrode SG1 made of a metal material are formed by a damascene method using a sacrificial electrode.
- Side wall spacers 51a and 51b are formed along the side walls of the sacrificial electrode and the like provided at the position where the memory gate electrode MG1 is to be formed, and then gate side wall insulating films 52a and 52b are formed.
- an interlayer insulating layer 57 is formed and the upper surface is planarized.
- the sacrificial electrode is removed, and a memory gate electrode MG1, a first select gate electrode DG1, and a second select gate electrode SG1 made of a metal material are formed in the space from which the sacrificial electrode is removed.
- the semiconductor substrate S1 on which such a memory cell 2 is formed is provided with a Dixon type charge pump circuit 44 including a plurality of capacitive elements C1b and a plurality of PN junction diodes (not shown). Although the charge pump circuit 44 includes a plurality of capacitive elements C1b and a plurality of PN junction diodes, only one capacitive element C1b is illustrated in FIG.
- a plurality of capacitive elements C1b are formed on the insulating layer IS, and a plurality of PN junction diodes (not shown) are formed at predetermined positions of the semiconductor substrate S1, for example.
- PN junction diode for example, a general PN junction diode using an N-type diffusion layer and a P-type diffusion layer formed on the surface of the semiconductor substrate S1 can be applied.
- the capacitive element C1b includes a capacitive sidewall electrode 63 and a capacitive electrode structure 61 that are alternately arranged with a capacitive sidewall insulating film 65 and a capacitive interelectrode insulating film 66 interposed therebetween. It has the structure arranged in.
- a plurality of capacitor electrode structures 61 having the same configuration are arranged on the insulating layer IS with a predetermined interval, and the capacitor side wall electrode 63 is arranged so as to sandwich the capacitor electrode structure 61. ing.
- the capacitor electrode 62 made of a metal material and the capacitor side wall electrode 63 also made of a metal material provided in the capacitor electrode structure 61 are the memory gate electrode MG1, the first selection gate electrode DG1, and It is the same layer as the second selection gate electrode SG1, and is formed by a damascene method using a sacrificial electrode. Specifically, a sacrificial electrode is formed at a position where the capacitor electrode 62 is to be formed or a position where the capacitor side wall electrode 63 is to be formed, and after the interlayer insulating layer 57 is formed, the upper surface is flattened. Thereafter, the sacrificial electrode is removed, and the capacitor electrode 62 and the capacitor side wall electrode 63 made of a metal material are formed in the space from which the sacrificial electrode is removed.
- the capacitor electrode structure 61 has a configuration in which a charge storage layer ECa and an insulating film 48a are stacked on an insulating layer IS, and a capacitor electrode 62 is formed on the insulating film 48a.
- the charge storage layer ECa provided in the capacitor electrode structure 61 is formed in the manufacturing process of forming the charge storage layer EC of the memory cell 42, and is the same layer as the charge storage layer EC.
- the insulating film 48a provided on the body 61 is formed in the manufacturing process of forming the upper memory gate insulating film 48 of the memory cell 42, and is the same layer as the upper memory gate insulating film 48.
- a wall-like capacitor side wall insulating film 65 is formed on each opposing side wall, and a wall-like capacitor interelectrode insulating film 66 made of an insulating material different from the capacitor side wall insulating film 65 is provided. It is formed along the capacitor side wall insulating film 65.
- the capacitor side wall insulating film 65 is formed in the manufacturing process for forming the side wall spacers 51a and 51b of the memory cell 42, and is formed in the same layer as the side wall spacers 51a and 51b. Is formed in the manufacturing process of forming the gate sidewall insulating films 52a and 52b of the memory cell 42, and is the same layer as the gate sidewall insulating films 52a and 52b.
- the capacitor side wall insulating film 65 is made of an insulating material such as silicon oxide (SiO, SiO 2 ), while the capacitor interelectrode insulating film 66 is made of a material other than silicon oxide, like the gate side wall insulating films 52a and 52b. It can be formed of an insulating material such as a -k material.
- the capacitor side wall insulating film 65 and the capacitor inter-electrode insulating film 66 are not formed with the charge storage layer ECa therein, and are not insulating materials. Can only be formed from. Note that the capacitor side wall insulating film 65 and the capacitor interelectrode insulating film 66 have a total thickness of 5 [nm] in accordance with the film thickness of the side wall spacer 51a (51b) and the gate side wall insulating film 52a (52b). It is desirable that the thickness be 40 nm or less.
- the capacitor side wall insulating film 65 is formed on each side wall of the sacrificial electrode provided at the position where the capacitor electrode structure 61 is to be formed when the side wall spacers 51a and 51b of the memory cell 42 are formed by the CVD method. Since it is formed along the same layer as the side wall spacers 51a and 51b, the film quality is better and the withstand voltage is higher than that of an oxide film formed by thermally oxidizing polysilicon. Therefore, it is possible to design a film with a high degree of freedom without considering consumption due to thermal oxidation.
- the capacitor side wall insulating film 65 includes the lower memory gate insulating film 10, the charge storage layer EC, and the upper memory whose film thickness and film quality are restricted to optimize the write operation, read operation, and erase operation of the memory cell 42. Since the gate insulating film 48, the first selection gate insulating film 54a, and the second selection gate insulating film 54b are formed as independent and different layers, the capacitor electrode structure 61 and the capacitor side wall are not affected by the restriction. Focusing on the breakdown voltage between the electrodes 63, the film quality and film thickness can be set.
- the capacitor inter-electrode insulating film 66 is provided with a capacitor side wall electrode 63 formed on the insulating layer IS through the insulating film 68 on the side wall side where the capacitor side wall insulating film 65 is not formed.
- the capacitor side wall electrode 63 and the insulating film 68 are also arranged at the ends of the capacitor element C1b.
- a portion 69 is formed along the respective side walls of the capacitor side wall electrode 63 and the insulating film 68 at the end, for example, side walls made of SiN or the like.
- the nonvolatile semiconductor memory device 41 having such a configuration can be formed by using a general semiconductor manufacturing process using a photolithography technique, a film forming technique such as an oxidation or CVD method, an etching technique, and an ion implantation method. The description is omitted here.
- the capacitor sidewall insulating film 65 in the charge pump circuit 44 is replaced with the sidewall spacer of the memory cell 42 in the same manner as the nonvolatile semiconductor memory device 1 shown in FIG.
- the charge pump circuit 44 does not require a power source for suppressing the voltage to a low level as in the prior art, and accordingly, the configuration can be simplified and the size can be reduced.
- the capacitive element C1b since the inter-capacitor insulating film 66 is provided in addition to the capacitive side wall insulating film 65, the withstand voltage characteristic of the capacitive element C1b can be improved accordingly.
- the memory gate electrode MG1, the first selection gate electrode DG1 as the memory gate electrode, the first selection gate electrode, the second selection gate electrode, the capacitance electrode, and the capacitance side wall electrode containing the metal material is not limited to this, for example, a plurality of types of different types of metal materials These metal layers may be sequentially stacked to form a memory gate electrode, a first selection gate electrode, a second selection gate electrode, a capacitor electrode, and a capacitor side wall electrode having a stacked structure.
- FIG. 7 is a schematic diagram showing a planar layout of a non-volatile semiconductor memory device 81 according to another embodiment in which fin portions S2 and S3 are provided on a semiconductor substrate. Even in the nonvolatile semiconductor memory device 81 having such fin portions S2 and S3, the same effects as those of the above-described embodiment can be obtained. 7 mainly focuses on the fin portions S2 and S3, the memory gate structure 85, the first selection gate structure 86, the second selection gate structure 87, the capacitor electrode structure 91, and the capacitor side wall electrode 92.
- the configuration shown in FIG. Here, the description of the same configuration as the nonvolatile semiconductor memory device 1 shown in FIG. 1 and the nonvolatile semiconductor memory device 41 shown in FIG. 6 is omitted, and the difference from the nonvolatile semiconductor memory devices 1 and 41 is noted. Will be described below.
- the memory cell 82 shown in FIG. 7 also includes the above-mentioned “(1-1-1) Operation of write selected memory cell”, “(1-1-2) Operation of write unselected memory cell”, “(1- Although operations according to “1-3) Operation of Read Memory Cell” and “(1-1-4) Operation of Erase Memory Cell” can be executed, the description thereof is omitted here to avoid duplication of description.
- the nonvolatile semiconductor memory device 81 is arranged in the memory forming portion 83 so that the plurality of fin portions S2 run in parallel in the x direction, and the memory cell 82 is formed in each fin portion S2.
- the nonvolatile semiconductor memory device 81 includes a memory gate structure 85, a first selection gate structure 86, and a second selection gate structure in the y direction that intersects the x direction in which each fin portion S2 extends.
- the memory gate structure 85, the first selection gate structure 86, and the second selection gate structure 87 are disposed so as to straddle the fin portions S2.
- the fin portion S3 extending in the x direction is also provided in the region where the charge pump circuit 84 is formed, and the capacitor electrode structure 91 and the capacitor side wall electrode 92 are formed in the y direction intersecting the x direction.
- the capacitor electrode structure 91 and the capacitor side wall electrode 92 are arranged so as to straddle the fin portion S3.
- the capacitance between the fin portion S3 and the capacitive electrode structure 91 and the capacitance between the fin portion S3 and the capacitive sidewall electrode 92 are formed on the surface of the fin portion S3.
- the distance between the fins S3 that run in parallel and the number of fins S3 formed are selected so as not to affect the capacitance of the capacitive element C1c (capacitance between the capacitive electrode structure 91 and the capacitive sidewall electrode 92). Yes.
- the capacitor electrode 93 and the capacitor side wall electrode 92 of the capacitor electrode structure 91 are formed of a metal material such as aluminum (Al), titanium aluminum (TiAl), tantalum carbide (TaC), or silicon tantalum nitride (TaSiN). Yes.
- a memory gate structure 85 is disposed between the first selection gate structure 86 and the second selection gate structure 87, and the memory gate structure 85, the first selection gate structure 86, A memory cell 82 having a memory transistor MT, a first selection transistor T1, and a second selection transistor T2 is formed in a region where the second selection gate structure 87 straddles each fin portion S2.
- the first selection is made between the drain region 89a and the source region 89b formed on the surface of the fin portion S2.
- a gate structure 86, a memory gate structure 85, and a second selection gate structure 87 are provided.
- the drain region 89a and the source region 89b formed on the surface of the fin portion S2 with a predetermined distance are made of a semiconductor material such as SiGe, and are selectively formed on the surface of the fin portion S2 by an epitaxial growth method.
- the film thickness is as follows.
- the memory gate structure 85 has a high insulating material such as hafnium oxide (HfO 2 ) on the fin portion S2 via the lower memory gate insulating film 10 and the charge storage layer EC.
- An upper memory gate insulating film 48 made of -k material or hafnium nitride silicate (HfSiON) is formed, and a memory gate electrode MG2 is provided on the upper memory gate insulating film 48.
- a wall-shaped side wall spacer 97a made of an insulating material is formed along one side wall, and a wall-shaped first gate is formed between the side wall spacer 97a and the memory gate electrode MG2.
- a sidewall insulating film 96a is provided.
- a wall-like side wall spacer 97b made of an insulating material is also formed on the other side wall, and a wall-like second spacer is also formed between the side wall spacer 97b and the memory gate electrode MG2.
- One gate sidewall insulating film 96b is provided.
- the first gate sidewall insulating films 96a and 96b are formed in the same manufacturing process as the upper memory gate insulating film 48, and the upper memory is made of the same insulating material as the upper memory gate insulating film 48 (for example, a high-k material).
- the gate insulating film 48 is integrally formed.
- a lower first selection gate insulating film 101a made of an insulating material such as silicon oxide (SiO, SiO 2 ) is provided on the fin portion S2 between the sidewall spacer 97a and the sidewall portion 103a.
- the upper first selection gate insulating film 102a made of an insulating member (for example, a high-k material) different from the first selection gate insulating film 101a is provided on the lower first selection gate insulating film 101a.
- the first select gate structure 86 is provided with a wall-shaped second gate sidewall insulating film 98a along the sidewall spacer 97a, and a wall-shaped sidewall sidewall insulating film along the sidewall of the sidewall portion 103a. 100a is formed.
- the second gate sidewall insulating film 98a and the sidewall sidewall insulating film 100a are formed in the manufacturing process of forming the upper first selection gate insulating film 102a, and the lower first selection gate insulating film 101a and the sidewall are formed.
- the spacer 97a is made of an insulating material (for example, a high-k material) different from the insulating material.
- the total thickness of the lower first selection gate insulating film 101a and the upper first selection gate insulating film 102a is desirably 9 [nm] or less, preferably 3 [nm] or less.
- the first selection gate electrode DG2 formed of the same metal material as the memory gate electrode MG2 is formed on the upper first selection gate insulating film 102a, and the first selection gate electrode A second gate sidewall insulating film 98a and a sidewall sidewall insulating film 100a are formed along the sidewall of DG2.
- the second selection gate structure 87 has a lower second selection gate insulating film 101b made of an insulating material such as silicon oxide (SiO, SiO 2 ) on the fin portion S2 between the sidewall spacer 97b and the sidewall portion 103b.
- An upper second selection gate insulating film 102b made of an insulating member (for example, a high-k material) different from the second selection gate insulating film 101b is provided on the lower second selection gate insulating film 101b. It has a configuration.
- the second select gate structure 87 is also provided with a wall-shaped second gate sidewall insulating film 98b along the sidewall spacer 97b, and a wall-shaped sidewall sidewall insulating film along the sidewall of the sidewall portion 103b. 100b is formed.
- the second gate sidewall insulating film 98b and the sidewall sidewall insulating film 100b are formed in the manufacturing process of forming the upper second selection gate insulating film 102b, and the lower second selection gate insulating film 101b and the sidewall are formed.
- the spacer 97b is formed of an insulating material (for example, a high-k material) different from the insulating material.
- the total thickness of the lower second selection gate insulating film 101b and the upper second selection gate insulating film 102b is desirably 9 [nm] or less, preferably 3 [nm] or less.
- a second selection gate electrode SG2 formed of the same metal material as the memory gate electrode MG2 is formed on the upper second selection gate insulating film 102b, and the second selection gate electrode A second gate sidewall insulating film 98b and a sidewall sidewall insulating film 100b are formed along the sidewall of SG2.
- the first gate sidewall insulating film 96a (96b), the sidewall spacer 97a (97b), and the second gate sidewall insulating film 98a (98b) are provided. It is desirable that the combined film thickness is 5 [nm] or more and 40 [nm] or less.
- FIG. 8B showing a cross-sectional configuration in the EE ′ portion of FIG. 7 will be described.
- the sidewall portions 103a and 103b are formed on the insulating layer IS covering the semiconductor substrate S1.
- the first selection gate structure 86 and the memory gate structure 85 are accordingly provided.
- the second selection gate structure 87, the side wall spacers 97a and 97b, and the side wall portions 103a and 103b are formed to be vertically longer than the position where the fin portion S2 is located, whereby the first selection gate structure 86 and the memory gate structure 85, the second selection gate structure 87, the sidewall spacers 97a and 97b, and the sidewall portions 103a and 103b are at the same height as the position where the fin portion S2 is located.
- an insulating layer IS is provided on the semiconductor substrate S1 on which the memory cells 82 are formed, and a capacitance as shown in FIG. 7 is formed on the insulating layer IS.
- a charge pump circuit 84 with element C1c may be provided.
- the charge pump circuit 84 is also a Dixon type charge pump circuit, as in the above-described embodiment, and includes a plurality of capacitive elements C1c having the same configuration as the capacitive element C1c, and a plurality of PN junction diodes.
- the high output voltage V2 boosted in accordance with the operation principle of the Dixon type charge pump circuit can be generated.
- the following explanation will be given focusing on the configuration of one capacitive element C1c as shown in FIG.
- FIG. 9 is a schematic diagram showing a cross-sectional configuration of the FF ′ portion of FIG.
- a capacitive sidewall insulating film 106 is provided between the capacitive sidewall electrode 92 and the capacitive electrode structure 91 in the capacitive element C1c.
- the region where the capacitive element C1c is formed is at the same height as the position where the fin portions S2 and S3 are formed. Therefore, in the formation region of the capacitive element C1c where the upper surface of the insulating layer IS is lower than the upper surfaces of the fin portions S2, S3, the capacitive electrode structure 91, the capacitive sidewall electrode 92, the capacitive sidewall insulating film 106, etc.
- the fin portions S2 and S3 are formed to be vertically longer than the region where the fin portions S2 and S3 are present, the area where the capacitor side wall electrode 92 and the capacitor electrode structure 91 face each other is increased, and the capacitance of the capacitor C1c can be increased. .
- the capacitor side wall insulating film 106 is formed in the manufacturing process of forming the side wall spacers 97a and 97b of the memory cell 82, and is the same layer as the side wall spacers 97a and 97b.
- the capacitor side wall insulating film 106 is formed on each side wall of the sacrificial electrode provided at the position where the capacitor electrode structure 91 is to be formed when the side wall spacers 97a and 97b of the memory cell 82 are formed by the CVD method. Since these are formed in the same layer as the side wall spacers 97a and 97b, the film quality is better and the withstand voltage is higher than that of an oxide film formed by thermally oxidizing polysilicon. Therefore, it is possible to design a film with a high degree of freedom without considering consumption due to thermal oxidation.
- the capacitor side wall insulating film 106 includes the lower memory gate insulating film 10, the charge storage layer EC, and the upper memory whose film thickness and film quality are restricted to optimize the write operation, read operation, and erase operation of the memory cell 82. Since the gate insulating film 48, the first select gate insulating film 101a, and the second select gate insulating film 101b are formed as independent and different layers, the capacitor electrode structure 91 and the capacitor side wall are not affected by the restriction. Focusing on the breakdown voltage between the electrodes 92, the film quality and film thickness can be set.
- the capacitor electrode structure 91 has a configuration in which the charge storage layer ECa and the insulating film 48a are stacked on the insulating layer IS, and the capacitor electrode 93 is formed on the insulating film 48a.
- the charge storage layer ECa of the capacitor electrode structure 91 is formed in the manufacturing process for forming the charge storage layer EC of the memory cell 82, and is the same layer as the charge storage layer EC, and is an insulating film of the capacitor electrode structure 91 48 a is formed in the manufacturing process of forming the upper memory gate insulating film 48 of the memory cell 82 and is the same layer as the upper memory gate insulating film 48.
- a wall-shaped first inter-capacitor insulating film 105 is formed between the capacitor side wall insulating film 106 and the capacitor electrode 93.
- the first capacitor-electrode insulating film 105 includes the insulating film 48a of the capacitor electrode structure 91, the first gate sidewall insulating films 96a, 96b, the second gate sidewall insulating films 98a, 98b of the memory cell 82, etc. It is formed in the manufacturing process to be formed, and becomes the same layer as these insulating film 48a, first gate sidewall insulating films 96a, 96b, and the like.
- the capacitor side wall insulating film 106 has a wall-like second capacitor electrode insulating film 107 made of an insulating material different from that of the capacitor side wall insulating film 106 on the side wall where the first capacitor interelectrode insulating film 105 is not formed. Is formed.
- the second inter-capacitor insulating film 107 is similar to the first inter-capacitor insulating film 105 formed on the side wall of the capacitive electrode 93, and the first gate side wall insulating films 96a and 96b of the memory cell 82, Formed in the manufacturing process of forming the second gate sidewall insulating films 98a, 98b, and the same as the first gate sidewall insulating films 96a, 96b and the second gate sidewall insulating films 98a, 98b of the memory cell 82. It becomes one layer.
- the second capacitor interelectrode insulating film 107 is provided with a capacitor side wall electrode 92 formed on the insulating film 109 on the side wall side where the capacitor side wall insulating film 106 is not formed.
- a wall-shaped side wall insulating film 111 made of the same insulating material (for example, SiN) as the capacitor electrode insulating film 107 is formed at the end of the capacitor element C1c along the side walls of the insulating film 109 and the capacitor side wall electrode 92.
- side wall portions 112 and 113 made of the same insulating material (SiO, SiO 2, etc.) as the capacitor side wall insulating film 106 are provided along the side wall of the side wall insulating film 111.
- the nonvolatile semiconductor memory device 81 having such a configuration can be formed by using a general semiconductor manufacturing process using a photolithography technique, a film forming technique such as an oxidation or CVD method, an etching technique, and an ion implantation method. The description is omitted here.
- the capacitor sidewall insulating film 106 in the charge pump circuit 84 is replaced with the sidewall spacers 97a and 97b of the memory cell 82 in the same manner as the nonvolatile semiconductor memory device 1 shown in FIG.
- the charge pump circuit 84 does not require a power source for suppressing the voltage to a low level as in the prior art, and accordingly, the configuration can be simplified and the size can be reduced.
- the first gate sidewall insulating films 96a and 96b and the second gate sidewall insulating films 98a and 98b formed along the sidewall spacers 97a and 97b of the memory cell 82 are formed in the same layer.
- the capacitor-electrode insulating film 105 and the second capacitor-electrode insulating film 107 between the capacitor electrode 93 and the capacitor side wall electrode 92, the first capacitor-electrode insulating film 105 and the second capacitor electrode
- the withstand voltage characteristic of the capacitive element C1c can be further improved by the amount of the inter-layer insulating film 107 provided.
- another gate sidewall insulating film made of an insulating material different from that of the sidewall spacers 13a and 13b is provided along the sidewall spacers 13a and 13b of the memory cell 2, while the charge pump Capacitance elements C1 and C2 in the circuit 4 are provided with a wall-like capacitive interelectrode insulating film made of the same layer as the gate sidewall insulating film, together with the capacitive sidewall insulating film 21, between the capacitive electrodes 17a and 17b and the capacitive sidewall electrodes 19a and 19b. It may be provided.
- a first inter-capacitor insulating film 105 as shown in FIG. 9 may be provided along the side walls of the capacitive electrodes 17a and 17b.
- the capacitive interelectrode insulating film 66 is provided in addition to the capacitive sidewall insulating film 65 has been described, but the present invention is not limited to this, and only the capacitive sidewall insulating film 65 is provided. May be provided. Further, as the other capacitor element C1b, a first capacitor-electrode insulating film 105 as shown in FIG. 9 may be provided along each side wall of the capacitor electrode 62.
- the present invention is not limited to this, and only the capacitor side wall insulating film 106 is provided, or only one of the first capacitor electrode insulating film 105 and the second capacitor electrode insulating film 107 is provided. You may do it.
- each capacitor element of the charge pump circuit has a configuration in which a capacitor side wall insulating film made of the same layer as the side wall spacer of the memory cell is provided between the capacitor side wall electrode and the capacitor electrode, FIG.
- the configurations of the embodiments of FIGS. 1, 3, and 5 to 9 may be variously combined.
- the present invention is not limited to this, and the first clock ⁇ 1 or the second clock ⁇ 2 A voltage of 2 clocks ⁇ 2 may be applied to the capacitor side wall electrode.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
<1.本発明の不揮発性半導体記憶装置の構成>
1-1.メモリセルについて
1-1-1.書き込み選択メモリセルの動作
1-1-2.書き込み非選択メモリセルの動作
1-1-3.読み出しメモリセルの動作
1-1-4.消去メモリセルの動作
1-2.チャージポンプ回路について
<2.作用および効果>
<3.4個の容量素子を備えたチャージポンプ回路について>
<4.他の実施の形態による不揮発性半導体記憶装置について>
<5.フィン部を備えた不揮発性半導体記憶装置について>
<6.その他>
図1に示すように、不揮発性半導体記憶装置1には、メモリセル2と、チャージポンプ回路4とが同じ半導体基板S1上に形成されており、例えばチャージポンプ回路4で入力電圧を昇圧して得られた電圧を、メモリセル2のメモリゲート電極MGに印加し得る。なお、図1では、1つのメモリセル2を図示しているが、実際には複数のメモリセル2が行方向および列方向に配置されており、行列状に配置されたメモリセル2でメモリセルアレイを構成する。
メモリセル2は、例えばP型の半導体基板S1上に、N型のメモリトランジスタMTを形成するメモリゲート構造体5と、N型MOS(Metal-Oxide-Semiconductor)の第1選択トランジスタT1を形成する第1選択ゲート構造体6と、同じくN型MOSの第2選択トランジスタT2を形成する第2選択ゲート構造体7とが形成されている。
電荷蓄積層ECに電荷が注入されるメモリセル(書き込み選択メモリセル)2の動作を説明する。メモリゲート電極MGには、メモリゲート線MLから電荷蓄積ゲート電圧Vprog(例えば、12[V]の電圧)が印加され、半導体基板S1には、基板電圧として基準電圧Vss(例えば、0[V]の電圧)が印加される。第2選択ゲート電極SGには、第2選択ゲート線SGLからゲートオフ電圧として基準電圧Vss(例えば、0[V]の電圧)が印加され、ソース領域8bには、ソース線SLからソースオフ電圧として基準電圧Vss(例えば、0[V]の電圧)が印加される。
書き込み選択メモリセルと第1選択ゲート線DLを共有するメモリセルであって、電荷蓄積層ECへの電荷の注入が阻止されるメモリセル(書き込み非選択メモリセル)2の動作について説明する。書き込み非選択メモリセル2には、書き込み選択メモリセルの場合と同様に、メモリゲート線MLからメモリゲート電極MGに電荷蓄積ゲート電圧Vprogが印加され、半導体基板S1に基板電圧として基準電圧Vssが印加される。
メモリセル2のデータの読み出し動作では、読み出し電圧を電源電圧Vdd(例えば0[V]より大きく、1.5[V]以下の電圧)とし、ビット線BLを電源電圧Vddにプリチャージし、ソース電圧を基準電圧Vss(例えば、0[V]の電圧)とし、ソース線SLを基準電圧Vssにする。データを読み出すメモリセル(読み出しメモリセル)2において電荷蓄積層ECに電荷が蓄積されている場合(データが書き込まれている場合)には、メモリゲート構造体5直下の半導体基板S1が非導通状態となり、ドレイン領域8aとソース領域8bとの電気的な接続が遮断され得る。これにより、データを読み出すメモリセル2では、ドレイン領域8aに接続されたビット線BLで読み出し電圧とした電源電圧Vddがそのまま維持され得る。
メモリセル2の電荷蓄積層EC内から電荷を引き抜くデータの消去動作時には、メモリゲート線MLからメモリゲート電極MGに消去ゲート電圧Verase(例えば、-12[V])が印加されることで、基板電圧として基準電圧Vss(例えば、0[V]の電圧)になっている半導体基板S1に向けて電荷蓄積層EC内の電荷が引き抜かれてデータが消去され得る。
かかる構成に加えて、この不揮発性半導体記憶装置1には、複数の容量素子C1,C2,…と、PN接合ダイオードD1,D2,D3,…とを備えたディクソン型のチャージポンプ回路4が設けられている。ここで、図1では、例えば2つの容量素子C1,C2が配置された領域の断面構成を示しており、PN接合ダイオードD1,D2間に一の容量素子C1が形成され、PN接合ダイオードD2,D3間に他の容量素子C2が形成されている。以下、容量素子C1に着目して説明し、当該容量素子C1と基本的構成が同じ容量素子C2については説明の重複を避けるためその説明は省略する。
以上の構成において、不揮発性半導体記憶装置1では、メモリセル2が設けられた半導体基板S1の絶縁層ISにチャージポンプ回路4を設け、チャージポンプ回路4における容量素子C1,C2の容量側壁電極19a(19b)および容量電極17a(17b)間の容量側壁絶縁膜21を、メモリセル2の側壁スペーサ13a,13bと同一層とした。
なお、上述した実施の形態においては、2つの容量素子C1,C2を備えたディクソン型のチャージポンプ回路4について説明したが、本発明はこれに限らず、3つや4つ等その他複数の容量素子を備えたディクソン型のチャージポンプ回路としてもよい。ここで、例えば4つの容量素子を備えた、本発明によるディクソン型のチャージポンプ回路の平面レイアウトについて、以下説明する。
なお、上述した実施の形態においては、図1に示すメモリゲート電極MG、第1選択ゲート電極DG、第2選択ゲート電極SG、容量電極17a…、および容量側壁電極19a…等をポリシリコン等の半導体材料により形成した場合について述べたが、本発明はこれに限らず、これらメモリゲート電極、第1選択ゲート電極、第2選択ゲート電極、容量電極、および容量側壁電極を、例えばアルミ(Al)や、チタンアルミ(TiAl)、炭化タンタル(TaC)、窒化ケイ素タンタル(TaSiN)等の金属材料により形成するようにしてもよい。
図7は、半導体基板にフィン部S2,S3を設けた他の実施の形態による不揮発性半導体記憶装置81の平面レイアウトを示した概略図であり、このようなフィン部S2,S3を備えた不揮発性半導体記憶装置81であっても上述した実施の形態と同様の効果を得ることができる。なお、図7では、主にフィン部S2,S3、メモリゲート構造体85、第1選択ゲート構造体86、第2選択ゲート構造体87、容量電極構造体91、および容量側壁電極92に着目して図示した構成となっている。ここでは、図1に示した不揮発性半導体記憶装置1や図6に示した不揮発性半導体記憶装置41と同じ構成について説明は省略し、当該不揮発性半導体記憶装置1,41との相違点に着目して以下説明する。
なお、本発明は、上述した各実施の形態に限定されるものではなく、本発明の要旨の範囲内で種々の変形実施が可能であり、例えば「(1-1-1)書き込み選択メモリセルの動作」、「(1-1-2)書き込み非選択メモリセルの動作」、「(1-1-3)読み出しメモリセルの動作」および「(1-1-4)消去メモリセルの動作」における電圧値以外の他の電圧値を適用して各動作を実行してもよい。
2,42,82 メモリセル
4,31,44,84 チャージポンプ回路
5,45,85 メモリゲート構造体
6,46,86 第1選択ゲート構造体
7,47,87 第2選択ゲート構造体
10 下部メモリゲート絶縁膜
11,48 上部メモリゲート絶縁膜
13a,13b,51a,51b,97a,97b 側壁スペーサ
17a,17b,62,93 容量電極
21,32,65,106 容量側壁絶縁膜
28 導通部
19a,19b,36a,36b,36c,36c,36d,63,92 容量側壁電極
52a,52b,96a,96b,98a,98b ゲート側壁絶縁膜
66,105,107 容量電極間絶縁膜
MG,MG1,MG2 メモリゲート電極
DG,DG1,DG2 第1選択ゲート電極
SG,SG1,SG2 第2選択ゲート電極
EC 電荷蓄積層
C1,C2,C1a,C2a,C3a,C4a,C1b,C1c 容量素子
D1,D2,D3,D1a,D2a,D3a,D4a,D5a PN接合ダイオード
Claims (9)
- 半導体基板上に設けられたメモリセルと、前記半導体基板に形成された絶縁層上に設けられたチャージポンプ回路とを備えた不揮発性半導体記憶装置であって、
前記メモリセルは、
下部メモリゲート絶縁膜、電荷蓄積層、上部メモリゲート絶縁膜、およびメモリゲート電極が積層されたメモリゲート構造体と、
前記メモリゲート構造体の一方の側面に沿って設けられ、絶縁材料でなる一の側壁スペーサと、
前記メモリゲート構造体の他方の側面に沿って設けられ、前記絶縁材料でなる他の側壁スペーサと、
第1選択ゲート絶縁膜上に第1選択ゲート電極が設けられ、前記一の側壁スペーサに沿って形成された第1選択ゲート構造体と、
第2選択ゲート絶縁膜上に第2選択ゲート電極が設けられ、前記他の側壁スペーサに沿って形成された第2選択ゲート構造体と、
前記第1選択ゲート構造体と隣接した前記半導体基板表面に前記第1選択ゲート電極と絶縁するように設けられ、ビット線が電気的に接続されたドレイン領域と、
前記第2選択ゲート構造体と隣接した前記半導体基板表面に前記第2選択ゲート電極と絶縁するように設けられ、ソース線が電気的に接続されたソース領域とを備え、
前記チャージポンプ回路は、複数の容量素子が設けられており、
各前記容量素子には、
容量電極と容量側壁電極との間に、前記一の側壁スペーサおよび前記他の側壁スペーサと同一層でなる容量側壁絶縁膜が設けられている
ことを特徴とする不揮発性半導体記憶装置。 - 前記容量電極は、前記メモリゲート電極と同一層でなり、
前記容量側壁電極は、前記第1選択ゲート電極および前記第2選択ゲート電極と同一層でなる
ことを特徴とする請求項1に記載の不揮発性半導体記憶装置。 - 前記容量素子は、
電荷蓄積層、絶縁膜および前記容量電極が積層された容量電極構造体を備え、
前記容量側壁絶縁膜は、
前記容量電極構造体の側壁に沿って形成され、かつ、該容量電極構造体に設けられた前記電荷蓄積層を備えずに、前記一の側壁スペーサおよび前記他の側壁スペーサを構成する絶縁材料と同じ絶縁材料からなる
ことを特徴とする請求項1または2に記載の不揮発性半導体記憶装置。 - 前記容量側壁絶縁膜は、前記一の側壁スペーサおよび前記他の側壁スペーサの膜厚と同じ膜厚に形成されている
ことを特徴とする請求項1~3のいずれか1項に記載の不揮発性半導体記憶装置。 - 前記メモリゲート電極と、前記第1選択ゲート電極と、前記第2選択ゲート電極と、前記容量電極と、前記容量側壁電極とには、金属材料が含まれている
ことを特徴とする請求項1~4のいずれか1項に記載の不揮発性半導体記憶装置。 - 前記半導体基板は、前記絶縁層から突き出たフィン部を備え、
前記メモリセルは、
前記メモリゲート構造体、前記第1選択ゲート構造体、前記第2選択ゲート構造体、前記一の側壁スペーサおよび前記他の側壁スペーサが、前記フィン部を跨ぐように前記絶縁層上に形成されている
ことを特徴とする請求項1~5のいずれか1項に記載の不揮発性半導体記憶装置。 - 前記チャージポンプ回路は、
第1クロックの電圧が印加される一の前記容量素子と、
前記第1クロックと逆位相の第2クロックの電圧が印加される他の前記容量素子と、
前記一の容量素子と前記他の容量素子との間に設けらえたPN接合ダイオードと、
を備えることを特徴とする請求項1~4のいずれか1項に記載の不揮発性半導体記憶装置。 - 前記PN接合ダイオードは、
前記容量側壁電極と同一層でなり、かつ前記容量側壁電極の導電型とは異なる導電型からなる逆導電型接合部と、
前段の前記容量素子に設けられた前記容量側壁電極と前記逆導電型接合部とを電気的に接続する導通部と、
を備えること特徴とする請求項7に記載の不揮発性半導体記憶装置。 - 前記メモリセルは、前記側壁スペーサに沿って壁状のゲート側壁絶縁膜を備え、
前記容量素子の前記容量電極および前記容量側壁電極間には、前記ゲート側壁絶縁膜と同一層でなる容量電極間絶縁膜が設けられている
ことを特徴とする請求項1~8のいずれか1項に記載の不揮発性半導体記憶装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG11201801387TA SG11201801387TA (en) | 2016-04-20 | 2017-04-11 | Nonvolatile semiconductor storage device |
KR1020177037522A KR102282200B1 (ko) | 2016-04-20 | 2017-04-11 | 불휘발성 반도체 기억 장치 |
EP17785850.3A EP3355354B1 (en) | 2016-04-20 | 2017-04-11 | Nonvolatile semiconductor storage device |
CN201780001846.9A CN109075171B (zh) | 2016-04-20 | 2017-04-11 | 非易失性半导体存储装置 |
IL257640A IL257640B (en) | 2016-04-20 | 2018-02-20 | A non-volatile semiconductor storage device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016-084337 | 2016-04-20 | ||
JP2016084337A JP6232464B2 (ja) | 2016-04-20 | 2016-04-20 | 不揮発性半導体記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017183511A1 true WO2017183511A1 (ja) | 2017-10-26 |
Family
ID=60115889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2017/014766 WO2017183511A1 (ja) | 2016-04-20 | 2017-04-11 | 不揮発性半導体記憶装置 |
Country Status (8)
Country | Link |
---|---|
EP (1) | EP3355354B1 (ja) |
JP (1) | JP6232464B2 (ja) |
KR (1) | KR102282200B1 (ja) |
CN (1) | CN109075171B (ja) |
IL (1) | IL257640B (ja) |
SG (1) | SG11201801387TA (ja) |
TW (1) | TWI636554B (ja) |
WO (1) | WO2017183511A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3493243A1 (en) * | 2017-11-30 | 2019-06-05 | Renesas Electronics Corporation | A semiconductor device and a manufacturing method thereof |
US20200083233A1 (en) * | 2017-08-30 | 2020-03-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit and method for manufacturing the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10622073B2 (en) * | 2018-05-11 | 2020-04-14 | Texas Instruments Incorporated | Integrated circuit including vertical capacitors |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010259155A (ja) * | 2009-04-21 | 2010-11-11 | Renesas Electronics Corp | 半導体装置 |
JP2010278314A (ja) * | 2009-05-29 | 2010-12-09 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2012248652A (ja) * | 2011-05-27 | 2012-12-13 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2014017343A (ja) * | 2012-07-09 | 2014-01-30 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
JP2014229844A (ja) | 2013-05-27 | 2014-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001358238A (ja) * | 1992-04-07 | 2001-12-26 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
JP4899241B2 (ja) * | 1999-12-06 | 2012-03-21 | ソニー株式会社 | 不揮発性半導体記憶装置およびその動作方法 |
JP2002208290A (ja) * | 2001-01-09 | 2002-07-26 | Mitsubishi Electric Corp | チャージポンプ回路およびこれを用いた不揮発性メモリの動作方法 |
JP4149170B2 (ja) * | 2002-01-22 | 2008-09-10 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JP2009141218A (ja) * | 2007-12-07 | 2009-06-25 | Toshiba Corp | 半導体装置 |
JP5538024B2 (ja) * | 2010-03-29 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置 |
JP5629120B2 (ja) * | 2010-04-26 | 2014-11-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2012038818A (ja) * | 2010-08-04 | 2012-02-23 | Toshiba Corp | 半導体装置 |
JP2014078661A (ja) * | 2012-10-12 | 2014-05-01 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP6161267B2 (ja) * | 2012-11-28 | 2017-07-12 | ルネサスエレクトロニクス株式会社 | コンデンサ、およびチャージポンプ回路 |
-
2016
- 2016-04-20 JP JP2016084337A patent/JP6232464B2/ja active Active
- 2016-11-11 TW TW105136791A patent/TWI636554B/zh active
-
2017
- 2017-04-11 CN CN201780001846.9A patent/CN109075171B/zh active Active
- 2017-04-11 EP EP17785850.3A patent/EP3355354B1/en active Active
- 2017-04-11 SG SG11201801387TA patent/SG11201801387TA/en unknown
- 2017-04-11 KR KR1020177037522A patent/KR102282200B1/ko active IP Right Grant
- 2017-04-11 WO PCT/JP2017/014766 patent/WO2017183511A1/ja active Application Filing
-
2018
- 2018-02-20 IL IL257640A patent/IL257640B/en unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010259155A (ja) * | 2009-04-21 | 2010-11-11 | Renesas Electronics Corp | 半導体装置 |
JP2010278314A (ja) * | 2009-05-29 | 2010-12-09 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2012248652A (ja) * | 2011-05-27 | 2012-12-13 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2014017343A (ja) * | 2012-07-09 | 2014-01-30 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
JP2014229844A (ja) | 2013-05-27 | 2014-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP3355354A4 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200083233A1 (en) * | 2017-08-30 | 2020-03-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit and method for manufacturing the same |
US10879258B2 (en) * | 2017-08-30 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cell comprising a metal control gate with a work function for an enlarged operation window |
EP3493243A1 (en) * | 2017-11-30 | 2019-06-05 | Renesas Electronics Corporation | A semiconductor device and a manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JP2017195270A (ja) | 2017-10-26 |
IL257640B (en) | 2022-02-01 |
JP6232464B2 (ja) | 2017-11-15 |
TW201739037A (zh) | 2017-11-01 |
EP3355354A4 (en) | 2019-06-26 |
EP3355354B1 (en) | 2022-02-23 |
CN109075171A (zh) | 2018-12-21 |
EP3355354A1 (en) | 2018-08-01 |
SG11201801387TA (en) | 2018-03-28 |
CN109075171B (zh) | 2023-06-20 |
KR102282200B1 (ko) | 2021-07-26 |
IL257640A (en) | 2018-04-30 |
TWI636554B (zh) | 2018-09-21 |
KR20180136362A (ko) | 2018-12-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4246400B2 (ja) | 半導体記憶装置 | |
JP5985293B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US9508837B2 (en) | Semiconductor device and method of manufacturing same | |
US9196363B2 (en) | Semiconductor device | |
JP6407644B2 (ja) | 半導体装置の製造方法 | |
JP7200054B2 (ja) | 半導体装置およびその製造方法 | |
WO2017183511A1 (ja) | 不揮発性半導体記憶装置 | |
JP6359432B2 (ja) | 半導体装置の製造方法 | |
TWI612523B (zh) | 記憶體單元及非揮發性半導體記憶裝置 | |
JP2008028257A (ja) | 半導体装置及びその製造方法 | |
CN110364198B (zh) | 编码型快闪存储器及其制造方法 | |
US20110058410A1 (en) | Semiconductor memory device | |
TWI681552B (zh) | 反或型快閃記憶體及其製造方法 | |
JP5961681B2 (ja) | メモリセル、不揮発性半導体記憶装置およびメモリセルの書き込み方法 | |
JP6266688B2 (ja) | 不揮発性半導体記憶装置 | |
JP6783447B2 (ja) | 不揮発性半導体記憶装置のデータ書き込み方法 | |
TWI612640B (zh) | 記憶元件及其製造方法 | |
JP4388921B2 (ja) | 半導体集積回路装置の動作方法 | |
JP2006066924A (ja) | 半導体集積回路装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ENP | Entry into the national phase |
Ref document number: 20177037522 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 257640 Country of ref document: IL |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11201801387T Country of ref document: SG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17785850 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |