WO2017173720A1 - 液晶面板的驱动电路及其驱动方法 - Google Patents

液晶面板的驱动电路及其驱动方法 Download PDF

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Publication number
WO2017173720A1
WO2017173720A1 PCT/CN2016/083500 CN2016083500W WO2017173720A1 WO 2017173720 A1 WO2017173720 A1 WO 2017173720A1 CN 2016083500 W CN2016083500 W CN 2016083500W WO 2017173720 A1 WO2017173720 A1 WO 2017173720A1
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Prior art keywords
gate
pixel clock
clock signal
voltage
signal
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PCT/CN2016/083500
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English (en)
French (fr)
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陈胤宏
吴宇
胡安乐
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深圳市华星光电技术有限公司
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Priority to US15/125,155 priority Critical patent/US10276110B2/en
Publication of WO2017173720A1 publication Critical patent/WO2017173720A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the invention belongs to the technical field of circuits, and in particular to a driving circuit of a liquid crystal panel and a driving method thereof.
  • LCDs liquid crystal displays
  • liquid crystal displays are moving toward large size and high resolution, so it is necessary to arrange a plurality of gate drivers on one side or both sides of the liquid crystal panel.
  • the trace of the array wiring (WOA) is long, resulting in a relatively large impedance, so the turn-on voltage (ie, VGH voltage) supplied to the gate driver is affected by the impedance. And attenuation. Since the gate drivers of different positions have large differences in the VGH voltages actually received, the actual charging time of the regions driven by the adjacent gate drivers is different, and thus the regions driven by the adjacent gate drivers have defects of horizontal blocks. , seriously affect the display quality of the liquid crystal display.
  • an object of the present invention is to provide a driving circuit for a liquid crystal panel, comprising: a signal controller for generating a pixel clock signal and performing duty ratio of the pixel clock signal Adjustment; a gate driver for receiving a pixel clock signal whose duty ratio is adjusted and a reference gate turn-on voltage, and a pixel clock signal adjusted according to the received duty ratio and a reference gate provided by an external signal source
  • the pole turn-on voltage calculates the actual gate turn-on voltage supplied to the gate line.
  • the number of the gate drivers is N; wherein, when the first gate driver to the Nth gate driver are sequentially arranged in a direction away from the signal controller, the signal controller is The duty ratio of the pixel clock signals supplied to the first gate driver to the Nth gate driver is linearly increased so that each gate driver calculates the actual value according to the corresponding pixel clock signal and the reference gate turn-on voltage The gate turn-on voltages are all the same.
  • each gate driver supplies the calculated actual gate-on voltage to the m gate lines;
  • the signal controller includes: a generating unit for generating a pixel clock signal; and a counting unit for counting When the number is a natural multiple of m, a counting signal is generated;
  • a duty ratio adjusting unit is configured to receive the counting signal, and adjust a duty ratio of the pixel clock signal according to the received counting signal;
  • the first output unit is configured to: The duty cycle adjusted pixel clock signal is output to the corresponding gate driver.
  • each of the gate drivers includes: a detecting unit, configured to detect a high level duration of the received pixel clock signal and a time difference of a high level duration of the adjacent two pixel clock signals; And calculating an actual gate-on voltage according to a high-level duration of the received pixel clock signal, the time difference, the reference gate-on voltage, and a high-level continuous lower limit time of the pixel clock signal; And an output unit, configured to output the calculated actual gate-on voltage to the corresponding m gate lines.
  • the calculating unit uses the following formula 1 according to the high level duration of the received pixel clock signal, the time difference, the reference gate on voltage, and the high level continuous lower limit time of the pixel clock signal. Calculate the actual gate turn-on voltage,
  • VGH K ⁇ (Tr-T0)/ ⁇ t+V0
  • VGH represents the actual gate-on voltage
  • Tr represents a high-level duration of the received pixel clock signal
  • T0 represents a high-level continuous lower-limit time of the pixel clock signal
  • ⁇ t represents the time difference
  • V0 represents The reference gate turn-on voltage
  • Another object of the present invention is to provide a driving method of a driving circuit of a liquid crystal panel, the driving circuit including a signal controller and a gate driver, wherein the driving method includes: the signal controller generates a pixel clock signal, and Adjusting the duty cycle of the pixel clock signal; the gate driver calculates the actual supplied to the gate line according to the pixel clock signal whose duty ratio is adjusted and the reference gate turn-on voltage supplied by the external signal source Gate turn-on voltage.
  • each gate driver supplies the calculated actual gate-on voltage to the m gate lines;
  • the signal controller includes: a generating unit, a counting unit, a duty ratio adjusting unit, and a first output unit;
  • the method for the signal controller to generate the pixel clock signal and the reference gate turn-on voltage, and to adjust the duty ratio of the pixel clock signal comprises: generating a pixel clock signal with adjustable duty ratio; and counting unit A counting signal is generated when the counting number is a natural multiple of m; the duty ratio adjusting unit adjusts the duty ratio of the pixel clock signal according to the counting signal; the first output unit adjusts the duty cycle of the pixel clock signal and the reference The gate turn-on voltage is output to the corresponding gate driver.
  • each of the gate drivers includes: a detecting unit, a calculating unit, and a second output unit; wherein each of the gate drivers is calculated according to the pixel clock signal whose duty ratio is adjusted and the reference gate turn-on voltage
  • the specific method for the actual gate turn-on voltage on the gate line includes: detecting unit detects the high level duration of the received pixel clock signal and the time difference of the high level duration of the adjacent two pixel clock signals
  • the calculation unit calculates the actual gate-on voltage according to the high-level duration, the time difference, the reference gate-on voltage, and the high-level continuous lower limit time of the pixel clock signal; the second output unit will calculate The actual gate-on voltage is output to the corresponding m gate lines.
  • the gate-on voltage VGH voltages outputted by the respective gate drivers are the same, so that the actual charging time of the regions driven by the respective gate drivers is the same, thereby improving The display quality of the liquid crystal display.
  • FIG. 1 shows a block diagram of a liquid crystal display according to an embodiment of the present invention
  • FIG. 2 shows a block diagram of a signal controller in accordance with an embodiment of the present invention
  • FIG. 3 is a waveform diagram showing a scan start signal and each pixel clock signal provided by a signal controller according to an embodiment of the present invention
  • FIG. 4 shows a block diagram of a gate controller in accordance with an embodiment of the present invention.
  • FIG. 1 shows a block diagram of a liquid crystal display according to an embodiment of the present invention.
  • a liquid crystal display includes: a liquid crystal panel assembly 300; a gate driver 400 and a data driver 500, both of which are connected to the liquid crystal panel assembly 300; and a signal controller 600 for controlling the liquid crystal panel assembly 300, a gate driver 400 and a data driver 500.
  • the liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in an array.
  • the liquid crystal panel assembly 300 may include a lower display panel (not shown) and an upper display panel (not shown) facing each other, and a liquid crystal layer (not shown) interposed between the lower display panel and the upper display panel.
  • a display signal line can be arranged on the lower display panel.
  • the display signal lines may include a plurality of gate lines transmitting gate signals G 3m to as G 1 in transmitting data signals and a plurality of data lines D 1 to D n.
  • the gate lines G 1 3m G extending to the row direction and substantially parallel to each other, and the data line D 1 to D n in the column direction and extending substantially parallel to one another.
  • Each of the pixels PX includes: a switching device connected to a corresponding gate line and a corresponding data line; and a liquid crystal capacitor connected to the switching device.
  • Each pixel PX may also include a storage capacitor, which is connected in parallel with the liquid crystal capacitor, if necessary.
  • the switching device of each pixel PX is a three-terminal device, thus having a control terminal connected to the corresponding gate line, an input terminal connected to the corresponding data line, and an output terminal connected to the corresponding liquid crystal capacitor.
  • the gate driver 400 is connected to the gate lines G 1 to G 3m, and 1 to 3m gate signal G is applied to the gate line G, the gate signal is supplied from an external source to the gate driver 400 of the high-level gate A combination of a signal (hereinafter referred to as a reference gate-on voltage V0) and a low-level gate signal (hereinafter referred to as a gate-off voltage Voff).
  • a reference gate-on voltage V0 a signal
  • Voff voltage Voff a low-level gate signal
  • three gate drivers 400 are disposed on one side of the liquid crystal panel assembly 300, wherein the three gate drivers 400 are sequentially arranged in a direction away from the signal controller 600, and are closest to the signal controller 600.
  • the gate driver 400 is defined as a first gate driver 400, and the gate driver 400 farthest from the signal controller 600 is defined as a third gate driver 400 located between the first gate driver 400 and the third gate driver 400.
  • Gate driver 400 is defined as a second gate driver. It should be understood that the number of the gate drivers 400 in the present invention is not limited to three, and may be specifically set according to actual conditions.
  • Gate lines G 1 to G 3m are connected to the gate driver 400. Specifically, the gate lines G 1 to G m are connected to the first gate driver 400, the gate lines G m+1 to G 2m are connected to the second gate driver 400, and the gate lines G 2m+1 to G 3m are connected Go to the third gate driver 400.
  • the gate lines G 1 to G m, G m + 1 gate line to G 2m, gate Lines G 2m+1 through G 3m are each connected to each of the corresponding two gate drivers.
  • the data driver 500 is connected to the data lines D 1 to D n of the liquid crystal panel assembly 300 and applies a data voltage to the pixels PX.
  • Signal controller 600 controls the operation of gate driver 400 and data driver 500.
  • the signal controller 600 receives input image signals (R, G, and B) and a plurality of input control signals for controlling display of the input image signals, such as a vertical sync signal Vsync, a horizontal sync signal, from an external graphics controller (not shown). Hsync, main clock signal MCLK, data enable signal DE.
  • the signal controller 600 appropriately processes the input image signals (R, G, and B) in accordance with the input control signals, thereby generating image data DAT that conforms to the operating conditions of the liquid crystal panel assembly 300. Then, the signal controller 600 generates the gate control signal CONT1 and the data control signal CONT2, transfers the gate control signal CONT1 to the respective gate drivers 400, and transfers the data control signal CONT2 and the image data DAT to the data driver 500.
  • the gate control signal CONT1 may include a scan start signal STV for initiating an operation of the gate driver 400, that is, a scan operation, and at least one pixel clock signal CKV for controlling when the actual gate-on voltage VGH is output.
  • the gate control signal CONT1 may also include an output enable signal OE for limiting the duration of the actual gate-on voltage VGH.
  • the duty ratio of the pixel clock signal CKV provided by the signal controller 600 can be adjusted. Specifically, the duty ratio of the pixel clock signal CKV supplied from the signal controller 600 to the first to third gate drivers 400 to 400 is linearly increased.
  • the gate driver 400 applies three response to the gate control signals CONT1 to the gate lines G 1 to G 3m actual gate-on voltage VGH is turned on is connected to the gate lines G 1 to G 3m switching device. Specifically, each gate driver 400 calculates an actual gate-on voltage VGH according to the received reference gate-on voltage V0 and the pixel clock signal CKV whose duty ratio is adjusted, since the signal controller 600 provides the first The duty ratio of the pixel clock signal CKV of the gate driver 400 to the third gate driver 400 linearly increases, and thus the first gate driver 400 to the third gate driver 400 apply the actual gates to the gate lines G 1 to G 3m The pole conduction voltage VGH is the same.
  • the data control signal CONT2 may include: a horizontal synchronization start signal STH, a transmission indicating that the image data DAT; a load signal LOAD, which request data voltage is applied to the image data DAT corresponding to the data lines D 1 through D n; and a data clock signal HCLK .
  • the data control signal CONT2 may also include an inversion signal RVS for inverting the polarity of the data voltage with respect to the common voltage Vcom, which is hereinafter referred to as "polarity of the data voltage.”
  • the data driver 500 receives the image data DAT from the signal controller 600 in response to the data control signal CONT2, and selects the gray voltage corresponding to the image data DAT to convert the image data into a data voltage. Then, the data driver 500 supplies the data voltages to the data lines D 1 to D n .
  • the difference between the data voltage supplied to each pixel PX and the common voltage Vcom can be interpreted as a voltage with which the liquid crystal capacitor of each pixel PX is charged, that is, a pixel voltage.
  • the arrangement of the liquid crystal molecules in the liquid crystal layer varies depending on the amplitude of the pixel voltage, and thus the polarity of the light transmitted through the liquid crystal layer can also be changed, resulting in a change in the transmittance of the liquid crystal layer.
  • the signal controller 600 and the respective gate drivers 400 according to embodiments of the present invention are described below.
  • FIG. 2 shows a block diagram of a signal controller in accordance with an embodiment of the present invention.
  • FIG. 3 shows a waveform diagram of a scan start signal and each pixel clock signal provided by a signal controller in accordance with an embodiment of the present invention.
  • a signal controller signal controller 600 includes: a generating unit 610 for generating a pixel clock signal CKV; and a counting unit 620 for counting a number of times a natural number of m And generating a count signal; the duty ratio adjusting unit 630 is configured to receive the count signal, and adjust the duty ratio of the pixel clock signal CKV according to the received count signal; the first output unit 640 is configured to adjust the duty ratio The adjusted pixel clock signal CKV is output to the corresponding gate driver.
  • the production unit 610 generates a pixel clock signal CKV. It should be noted that the pixel clock signal CKV generated by the production unit 610 can be directly supplied to the first gate driver 400 as the adjusted pixel clock signal CKV1.
  • the counting unit 620 is configured to count the number of corresponding gate lines driven by the respective gate drivers 400, wherein the counting unit 620 generates a counting signal when the counting number is a natural multiple of m.
  • the counting unit 620 when the count number is 0, m, 2 m, that is, when the count number is 0, 1, 2 times m, the counting unit 620 generates a count signal.
  • the duty ratio adjusting unit 630 receives the count signal and adjusts the duty ratio of the pixel clock signal CKV according to the received count signal. Wherein, when the count number received by the duty ratio adjusting unit 630 is 0, it increases the high level duration of the pixel clock signal CKV by 0 to form the first pixel clock signal CKV1; when the duty ratio adjusting unit 630 receives When the count number is m, it increases the ⁇ t of the high level duration of the pixel clock signal CKV to form the second pixel clock signal CKV2; when the count number received by the duty ratio adjusting unit 630 is 2m, the pair of pixel clock signals The high level duration of CKV is increased by 2 ⁇ t to form a third pixel clock signal CKV3.
  • the first output unit 640 outputs the first pixel clock signal CKV1, the second pixel clock signal CKV2, and the third pixel clock signal CKV3 to the first, second, and third gate drivers 400, respectively.
  • FIG. 4 shows a block diagram of a gate controller in accordance with an embodiment of the present invention.
  • each gate driver 400 includes: a detecting unit 410, configured to detect a high level duration of the received pixel clock signal and a high level duration of two adjacent pixel clock signals. a time difference; the calculating unit 420 is configured to: according to the high level duration of the received pixel clock signal, the time difference, the reference gate-on voltage V0, and the high level of the pixel clock signal The lower limit time is used to calculate the actual gate-on voltage VGH; the second output unit 430 is configured to output the calculated actual gate-on voltage VGH to the corresponding m gate lines.
  • the calculation unit 420 is based on the high-level duration of the received pixel clock signal, the time difference of the high-level duration of the adjacent two pixel clock signals, the reference gate-on voltage V0, and the high-power of the pixel clock signal.
  • the average lower limit time is calculated using the following Equation 1 to calculate the actual gate-on voltage VGH.
  • VGH K ⁇ (Tr-T0)/ ⁇ t+V0
  • VGH represents the actual gate-on voltage
  • Tr represents a high-level duration of the received pixel clock signal
  • T0 is a constant value indicating a high-level continuous minimum time of the pixel clock signal, ie, the production unit 610
  • a high level duration of the pixel clock signal CKV is generated
  • ⁇ t represents the time difference
  • V0 represents the reference gate turn-on voltage
  • the detecting unit 410 detects the high level duration of the first pixel clock signal CKV1 and the first pixel clock signal.
  • the time difference between the high level duration of the CKV1 and the adjacent pixel clock signal, the calculation unit 420 according to the high level duration of the first pixel clock signal CKV1, the first pixel clock signal CKV1 and the high voltage of the adjacent pixel clock signal The time difference of the flat duration, the reference gate-on voltage V0, and the high-level continuous lower limit time of the pixel clock signal calculate the actual gate-on voltage VGH using the above formula 1, and the second output unit 430 calculates the actual gate turnon voltage VGH output to the gate lines G 1 to G m.
  • the output unit 430 corresponds to the second gate-on reference voltage V0 is output to the gate lines G 1 to G m.
  • the detecting unit 410 detects the high level duration of the second pixel clock signal CKV2 and the second pixel clock signal CKV2 and the The time difference of the high level duration of the one pixel clock signal CKV1, the calculation unit 420 according to the high level duration of the second pixel clock signal CKV2, the time difference between the second pixel clock signal CKV2 and the first pixel clock signal CKV1, the reference gate
  • the turn-on voltage V0 and the high-level continuous lower limit time of the pixel clock signal calculate the actual gate-on voltage VGH using the above formula 1, and the second output unit 430 outputs the calculated actual gate-on voltage VGH to the gate.
  • the detecting unit 410 detects the high level duration of the third pixel clock signal CKV3 and the third pixel clock signal CKV3 and the first The time difference of the high level duration of the two-pixel clock signal CKV2, the calculation unit 420 according to the high level duration of the third pixel clock signal CKV3, the time difference of the third pixel clock signal CKV3 and the second pixel clock signal CKV2, the reference gate
  • the turn-on voltage V0 and the high-level continuous lower limit time of the pixel clock signal calculate the actual gate-on voltage VGH using the above formula 1, and the second output unit 430 outputs the calculated actual gate-on voltage VGH to the gate.
  • the gate-on voltage VGH voltages output by the respective gate drivers are the same, so that the actual charging time of the regions driven by the respective gate drivers is the same, thereby improving the display quality of the liquid crystal display.

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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶面板的驱动电路包括：信号控制器（600），用于产生像素时钟信号，并对像素时钟信号的占空比进行调整；栅极驱动器（400），用于接收占空比被调整后的像素时钟信号以及由外部信号源提供的基准栅极导通电压，并根据接收的占空比被调整后的像素时钟信号以及基准栅极导通电压计算出提供到栅极线上的实际栅极导通电压。还提供了一种液晶面板的驱动电路的驱动方法。该液晶面板的驱动电路及其驱动方法，使得各个栅极驱动器（400）输出的栅极导通电压VGH电压相同，从而使各个栅极驱动器（400）驱动的区域实际充电时间相同，进而提高液晶显示器的显示品质。

Description

液晶面板的驱动电路及其驱动方法 技术领域
本发明属于电路技术领域，具体地讲，涉及一种液晶面板的驱动电路及其驱动方法。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，LCD)因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已被应用于生产生活的各个方面。
目前液晶显示器都在向着大尺寸、高解析度的方向发展，因此需要在液晶面板的一侧或者两侧布置多个栅极驱动器。然而，由于液晶面板上的走线区域较窄，会使阵列布线(WOA)的走线较长，从而导致阻抗比较大，因此提供给栅极驱动器的导通电压(即VGH电压)会因阻抗而衰减。不同位置的栅极驱动器由于实际接收到的VGH电压存在较大差异，造成相邻的栅极驱动器驱动的区域实际充电时间不同，因此相邻的栅极驱动器驱动的区域会有水平区块的缺陷，严重影响液晶显示器的显示品质。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种液晶面板的驱动电路，其包括：信号控制器，用于产生像素时钟信号，并对所述像素时钟信号的占空比进行调整；栅极驱动器，用于接收占空比被调整后的像素时钟信号以及基准栅极导通电压，并根据接收的占空比被调整后的像素时钟信号以及由外部信号源提供的基准栅极导通电压计算出提供到栅极线上的实际栅极导通电压。
进一步地，所述栅极驱动器的数量为N个；其中，当第一栅极驱动器至第N栅极驱动器沿着远离所述信号控制器的方向依序排布时，所述信号控制器依 序提供给第一栅极驱动器至第N栅极驱动器的像素时钟信号的占空比线性增大，以使每个栅极驱动器根据对应的像素时钟信号以及基准栅极导通电压计算出的实际栅极导通电压均相同。
进一步地，每个栅极驱动器将计算出的实际栅极导通电压提供给m条栅极线；所述信号控制器包括：生成单元，用于产生像素时钟信号；计数单元，用于当计数数字为m的自然数倍时，产生一计数信号；占空比调整单元，用于接收计数信号，并根据接收的计数信号对像素时钟信号的占空比进行调整；第一输出单元，用于将占空比调整后的像素时钟信号输出到对应的栅极驱动器。
进一步地，每个栅极驱动器包括：侦测单元，用于侦测接收到的像素时钟信号的高电平持续时间以及相邻两个像素时钟信号的高电平持续时间的时间差；计算单元，用于根据接收到的像素时钟信号的高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间计算出实际栅极导通电压；第二输出单元，用于将计算出的实际栅极导通电压输出到对应的m条栅极线上。
进一步地，所述计算单元根据接收到的像素时钟信号的高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间利用下面的式子1计算出实际栅极导通电压，
[式子1]
VGH＝K×(Tr-T0)/Δt+V0
其中，VGH表示所述实际栅极导通电压，Tr表示接收到的像素时钟信号的高电平持续时间，T0表示像素时钟信号的高电平持续下限时间，Δt表示所述时间差，V0表示所述基准栅极导通电压。
本发明的另一目的还在于提供一种液晶面板的驱动电路的驱动方法，所述驱动电路包括信号控制器和栅极驱动器，其中，所述驱动方法包括：信号控制器产生像素时钟信号，并对所述像素时钟信号的占空比进行调整；栅极驱动器根据占空比被调整后的像素时钟信号以及由外部信号源提供的基准栅极导通电压计算出提供到栅极线上的实际栅极导通电压。
进一步地，每个栅极驱动器将计算出的实际栅极导通电压提供给m条栅极线；所述信号控制器包括：生成单元、计数单元、占空比调整单元、第一输出单元；其中，信号控制器产生像素时钟信号以及基准栅极导通电压，并对所述像素时钟信号的占空比进行调整的方法具体包括：生成单元产生占空比可调的像素时钟信号；计数单元在计数数字为m的自然数倍时产生一计数信号；占空比调整单元根据计数信号对像素时钟信号的占空比进行调整；第一输出单元将占空比调整后的像素时钟信号以及基准栅极导通电压输出到对应的栅极驱动器。
进一步地，每个栅极驱动器包括：侦测单元、计算单元、第二输出单元；其中，每个栅极驱动器根据占空比被调整后的像素时钟信号以及基准栅极导通电压计算出提供到栅极线上的实际栅极导通电压的具体方法包括：侦测单元侦测接收到的像素时钟信号的高电平持续时间以及相邻两个像素时钟信号的高电平持续时间的时间差；计算单元根据所述高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间计算出实际栅极导通电压；第二输出单元将计算出的实际栅极导通电压输出到对应的m条栅极线上。
本发明的有益效果：本发明的液晶面板的驱动电路及其驱动方法，各个栅极驱动器输出的栅极导通电压VGH电压相同，从而使各个栅极驱动器驱动的区域实际充电时间相同，进而提高液晶显示器的显示品质。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1示出了根据本发明的实施例的液晶显示器的框图；
图2示出了根据本发明的实施例的信号控制器的模块图；
图3示出了根据本发明的实施例的信号控制器提供的扫描开始信号和各像素时钟信号的波形图；
图4示出了根据本发明的实施例的栅极控制器的模块图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
图1示出了根据本发明的实施例的液晶显示器的框图。
参照图1，根据本发明的实施例的液晶显示器包括：液晶面板组件300；栅极驱动器400和数据驱动器500，二者都连接到液晶面板组件300；信号控制器600，用于控制液晶面板组件300、栅极驱动器400和数据驱动器500。
液晶面板组件300包括多条显示信号线和连接到显示信号线并按阵列排列的多个像素PX。液晶面板组件300可以包括：彼此面对的下显示面板(未示出)和上显示面板(未示出)，以及被插入在下显示面板和上显示面板之间的液晶层(未示出)。
可以在下显示面板上布置显示信号线。显示信号线可以包括传送栅极信号的多条栅极线G1至G3m和传送数据信号的多条数据线D1至Dn。栅极线G1至G3m按行方向延伸并且彼此大致平行，并且数据线D1至Dn按列方向延伸并且彼此大致平行。
每个像素PX包括：开关器件，连接到相应的栅极线和相应的数据线；以及液晶电容器，连接到该开关器件。如果必要，每个像素PX也可以包括存储电容器，其与液晶电容器并联连接。
每个像素PX的开关器件是三端器件，因此具有连接到相应栅极线的控制端、连接到相应数据线的输入端和连接到相应液晶电容器的输出端。
栅极驱动器400连接到栅极线G1至G3m，并向栅极线G1至G3m施加栅极信号，该栅极信号是由外部源提供给栅极驱动器400的高电平栅极信号(此后称之为基准栅极导通电压V0)和低电平栅极信号(此后称之为栅极截止电压Voff)的组合。参照图1，在液晶面板组件300的一侧布置三个栅极驱动器400， 其中，这三个栅极驱动器400沿着远离信号控制器600的方向依序布置，将距离信号控制器600最近的栅极驱动器400定义为第一栅极驱动器400，距离信号控制器600最远的栅极驱动器400定义为第三栅极驱动器400，位于第一栅极驱动器400和第三栅极驱动器400中间的栅极驱动器400定义为第二栅极驱动器。应当理解的是，本发明中的栅极驱动器400的数量并不限制于三个，可以根据实际情况具体设定。
栅极线G1至G3m都连接到这些栅极驱动器400。具体地，栅极线G1至Gm连接到第一栅极驱动器400，栅极线Gm+1至G2m连接到第二栅极驱动器400，栅极线G2m+1至G3m连接到第三栅极驱动器400。
作为本发明的另一实施方式，可以在液晶面板组件300的相对两侧分别布置三个栅极驱动器，并且栅极线G1至Gm、栅极线Gm+1至G2m、栅极线G2m+1至G3m都分别连接到对应的两个栅极驱动器的每一个。
数据驱动器500连接到液晶面板组件300的数据线D1至Dn，并向像素PX施加数据电压。信号控制器600控制栅极驱动器400和数据驱动器500的操作。
信号控制器600从外部图形控制器(未示出)接收输入图像信号(R、G和B)以及用于控制输入图像信号的显示的多个输入控制信号，例如垂直同步信号Vsync、水平同步信号Hsync、主时钟信号MCLK、数据使能信号DE。信号控制器600根据输入控制信号适当处理输入图像信号(R、G和B)，从而产生符合液晶面板组件300的操作条件的图像数据DAT。然后，信号控制器600产生栅极控制信号CONT1和数据控制信号CONT2，将栅极控制信号CONT1传送到各栅极驱动器400，并将数据控制信号CONT2和图像数据DAT传送到数据驱动器500。
栅极控制信号CONT1可以包括：扫描开始信号STV，用于启动栅极驱动器400的操作、即扫描操作；以及至少一个像素时钟信号CKV，用于控制何时输出实际栅极导通电压VGH。栅极控制信号CONT1也可以包括输出使能信号OE，用于限制实际栅极导通电压VGH的持续时间。进一步地，信号控制器600提供的像素时钟信号CKV的占空比可以被调整。具体地，信号控制器600提供给第一栅极驱动器400至第三栅极驱动器400的像素时钟信号CKV的占空比线性增大。
三个栅极驱动器400通过响应于栅极控制信号CONT1向栅极线G1至G3m施加实际栅极导通电压VGH而导通连接到栅极线G1至G3m的开关器件。具体地，每个栅极驱动器400根据接收的基准栅极导通电压V0和占空比被调整后的像素时钟信号CKV计算出实际栅极导通电压VGH，由于信号控制器600提供给第一栅极驱动器400至第三栅极驱动器400的像素时钟信号CKV的占空比线性增大，因此第一栅极驱动器400至第三栅极驱动器400向栅极线G1至G3m施加实际栅极导通电压VGH相同。
数据控制信号CONT2可以包括：水平同步开始信号STH，其指示图像数据DAT的传输；加载信号LOAD，其请求向数据线D1至Dn施加与图像数据DAT对应的数据电压；以及数据时钟信号HCLK。数据控制信号CONT2也可以包括反转信号RVS，用于反转数据电压相对于公共电压Vcom的极性，这此后被称为“数据电压的极性”。
数据驱动器500响应于数据控制信号CONT2从信号控制器600接收图像数据DAT，并选择与图像数据DAT对应的灰度电压而将图像数据转换为数据电压。然后，数据驱动器500将数据电压提供给数据线D1至Dn。
在三个栅极驱动器400通过响应于栅极控制信号CONT1向栅极线G1至G3m施加实际栅极导通电压VGH而导通连接到栅极线G1至Gn的开关器件之后，提供给数据线D1至Dn的数据电压通过导通的开关器件而被传送到每个像素PX。
提供给每个像素PX的数据电压和公共电压Vcom之间的差可以被解释为是利用其对每个像素PX的液晶电容器充电的电压、即像素电压。液晶层内的液晶分子的排列根据像素电压的幅度而变化，因而通过液晶层传送的光的极性也可以变化，从而导致液晶层的透射率的变化。
以下对根据本发明的实施例的信号控制器600和各栅极驱动器400进行描述说明。
图2示出了根据本发明的实施例的信号控制器的模块图。图3示出了根据本发明的实施例的信号控制器提供的扫描开始信号和各像素时钟信号的波形图。
参照图2和图3，根据本发明的实施例的信号控制器信号控制器600包括：生成单元610，用于产生像素时钟信号CKV；计数单元620，用于当计数数字为m的自然数倍时，产生一计数信号；占空比调整单元630，用于接收计数信号，并根据接收的计数信号对像素时钟信号CKV的占空比进行调整；第一输出单元640，用于将占空比调整后的像素时钟信号CKV输出到对应的栅极驱动器。
具体地，生产单元610产生像素时钟信号CKV。应当说明的是，生产单元610产生的像素时钟信号CKV可以直接作为被调整后的像素时钟信号CKV1提供给第一栅极驱动器400。
计数单元620用于对各栅极驱动器400驱动对应的栅极线的条数进行计数，其中，当计数数字为m的自然数倍时，计数单元620产生一计数信号。
例如，当计数数字为0、m、2m时，即计数数字为m的0、1、2倍时，计数单元620均产生一计数信号。
占空比调整单元630接收计数信号，并根据接收的计数信号对像素时钟信号CKV的占空比进行调整。其中，当占空比调整单元630接收的计数数字为0时，其对像素时钟信号CKV的高电平持续时间增加0，以形成第一像素时钟信号CKV1；当占空比调整单元630接收的计数数字为m时，其对像素时钟信号CKV的高电平持续时间增加Δt，以形成第二像素时钟信号CKV2；当占空比调整单元630接收的计数数字为2m时，其对像素时钟信号CKV的高电平持续时间增加2Δt，以形成第三像素时钟信号CKV3。
第一输出单元640将第一像素时钟信号CKV1、第二像素时钟信号CKV2和第三像素时钟信号CKV3分别输出到第一、第二和第三栅极驱动器400。
图4示出了根据本发明的实施例的栅极控制器的模块图。
参照图2至图4，每个栅极驱动器400包括：侦测单元410，用于侦测接收到的像素时钟信号的高电平持续时间以及相邻两个像素时钟信号的高电平持续时间的时间差；计算单元420，用于根据接收到的像素时钟信号的高电平持续时间、所述时间差、基准栅极导通电压V0以及像素时钟信号的高电平持 续下限时间计算出实际栅极导通电压VGH；第二输出单元430用于将计算出的实际栅极导通电压VGH输出到对应的m条栅极线上。
进一步地，计算单元420根据接收到的像素时钟信号的高电平持续时间、相邻两个像素时钟信号的高电平持续时间的时间差、基准栅极导通电压V0以及像素时钟信号的高电平持续下限时间利用下面的式子1计算出实际栅极导通电压VGH。
[式子1]VGH＝K×(Tr-T0)/Δt+V0
其中，VGH表示所述实际栅极导通电压；Tr表示接收到的像素时钟信号的高电平持续时间；T0为一定值，其表示像素时钟信号的高电平持续下限时间，即生产单元610产生像素时钟信号CKV的高电平持续时间；Δt表示所述时间差，V0表示所述基准栅极导通电压。
具体地，当第一输出单元640将第一像素时钟信号CKV1输出到第一栅极驱动器400时，侦测单元410侦测第一像素时钟信号CKV1的高电平持续时间以及第一像素时钟信号CKV1与相邻的像素时钟信号的高电平持续时间的时间差，计算单元420根据第一像素时钟信号CKV1的高电平持续时间、第一像素时钟信号CKV1与相邻的像素时钟信号的高电平持续时间的时间差、基准栅极导通电压V0以及像素时钟信号的高电平持续下限时间利用上述式子1计算出实际栅极导通电压VGH，第二输出单元430将计算出的实际栅极导通电压VGH输出到栅极线G1至Gm上。这里，由于在提供第一像素时钟信号CKV1之前，没有任何对比信号，因此所述相邻的像素时钟信号的高电平持续时间为0，而第一像素时钟信号CKV1与所述相邻的像素时钟信号的高电平持续时间的时间差为第一像素时钟信号CKV1的高电平持续时间。这样，相当于第二输出单元430将基准栅极导通电压V0输出到栅极线G1至Gm上。
当第一输出单元640将第二像素时钟信号CKV2输出到第二栅极驱动器400时，侦测单元410侦测第二像素时钟信号CKV2的高电平持续时间以及第二像素时钟信号CKV2与第一像素时钟信号CKV1的高电平持续时间的时间差，计算单元420根据第二像素时钟信号CKV2的高电平持续时间、第二像素时钟信号CKV2与第一像素时钟信号CKV1的时间差、基准栅极导通电压V0以及像素时钟信号的高电平持续下限时间利用上述式子1计算出实际栅极导通 电压VGH，第二输出单元430将计算出的实际栅极导通电压VGH输出到栅极线Gm+1至G2m上。
当第一输出单元640将第三像素时钟信号CKV3输出到第二栅极驱动器400时，侦测单元410侦测第三像素时钟信号CKV3的高电平持续时间以及第三像素时钟信号CKV3与第二像素时钟信号CKV2的高电平持续时间的时间差，计算单元420根据第三像素时钟信号CKV3的高电平持续时间、第三像素时钟信号CKV3与第二像素时钟信号CKV2的时间差、基准栅极导通电压V0以及像素时钟信号的高电平持续下限时间利用上述式子1计算出实际栅极导通电压VGH，第二输出单元430将计算出的实际栅极导通电压VGH输出到栅极线G2m+1至G3m上。
综上所述，根据本发明的实施例，各个栅极驱动器输出的栅极导通电压VGH电压相同，从而使各个栅极驱动器驱动的区域实际充电时间相同，进而提高液晶显示器的显示品质。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (14)

  1. 一种液晶面板的驱动电路，其中，包括：
    信号控制器，用于产生像素时钟信号，并对所述像素时钟信号的占空比进行调整；
    栅极驱动器，用于接收占空比被调整后的像素时钟信号以及由外部信号源提供的基准栅极导通电压，并根据接收的占空比被调整后的像素时钟信号以及基准栅极导通电压计算出提供到栅极线上的实际栅极导通电压。
  2. 根据权利要求1所述的液晶面板的驱动电路，其中，所述栅极驱动器的数量为N个；
    其中，当第一栅极驱动器至第N栅极驱动器沿着远离所述信号控制器的方向依序排布时，所述信号控制器依序提供给第一栅极驱动器至第N栅极驱动器的像素时钟信号的占空比线性增大，以使每个栅极驱动器根据对应的像素时钟信号以及基准栅极导通电压计算出的实际栅极导通电压均相同。
  3. 根据权利要求2所述的液晶面板的驱动电路，其中，每个栅极驱动器将计算出的实际栅极导通电压提供给m条栅极线；
    所述信号控制器包括：
    生成单元，用于产生像素时钟信号；
    计数单元，用于当计数数字为m的自然数倍时，产生一计数信号；
    占空比调整单元，用于接收计数信号，并根据接收的计数信号对像素时钟信号的占空比进行调整；
    第一输出单元，用于将占空比调整后的像素时钟信号输出到对应的栅极驱动器。
  4. 根据权利要求2所述的液晶面板的驱动电路，其中，每个栅极驱动器 包括：
    侦测单元，用于侦测接收到的像素时钟信号的高电平持续时间以及相邻两个像素时钟信号的高电平持续时间的时间差；
    计算单元，用于根据接收到的像素时钟信号的高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间计算出实际栅极导通电压；
    第二输出单元，用于将计算出的实际栅极导通电压输出到对应的m条栅极线上。
  5. 根据权利要求3所述的液晶面板的驱动电路，其中，每个栅极驱动器包括：
    侦测单元，用于侦测接收到的像素时钟信号的高电平持续时间以及相邻两个像素时钟信号的高电平持续时间的时间差；
    计算单元，用于根据接收到的像素时钟信号的高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间计算出实际栅极导通电压；
    第二输出单元，用于将计算出的实际栅极导通电压输出到对应的m条栅极线上。
  6. 根据权利要求4所述的液晶面板的驱动电路，其中，所述计算单元根据接收到的像素时钟信号的高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间利用下面的式子1计算出实际栅极导通电压，
    [式子1]
    VGH＝K×(Tr-T0)/Δt+V0
    其中，VGH表示所述实际栅极导通电压，Tr表示接收到的像素时钟信号的高电平持续时间，T0表示像素时钟信号的高电平持续下限时间，Δt表示所 述时间差，V0表示所述基准栅极导通电压。
  7. 根据权利要求5所述的液晶面板的驱动电路，其中，所述计算单元根据接收到的像素时钟信号的高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间利用下面的式子1计算出实际栅极导通电压，
    [式子1]
    VGH＝K×(Tr-T0)/Δt+V0
    其中，VGH表示所述实际栅极导通电压，Tr表示接收到的像素时钟信号的高电平持续时间，T0表示像素时钟信号的高电平持续下限时间，Δt表示所述时间差，V0表示所述基准栅极导通电压。
  8. 一种液晶面板的驱动电路的驱动方法，其中，所述驱动电路包括信号控制器和栅极驱动器，其中，所述驱动方法包括：
    信号控制器产生像素时钟信号，并对所述像素时钟信号的占空比进行调整；
    栅极驱动器根据占空比被调整后的像素时钟信号以及由外部信号源提供的基准栅极导通电压计算出提供到栅极线上的实际栅极导通电压。
  9. 根据权利要求8所述的液晶面板的驱动电路的驱动方法，其中，所述栅极驱动器的数量为N个；
    其中，当第一栅极驱动器至第N栅极驱动器沿着远离所述信号控制器的方向依序排布时，所述信号控制器依序提供给第一栅极驱动器至第N栅极驱动器的像素时钟信号的占空比线性增大，以使每个栅极驱动器根据对应的像素时钟信号以及基准栅极导通电压计算出的实际栅极导通电压均相同。
  10. 根据权利要求9所述的液晶面板的驱动电路的驱动方法，其中，每个栅极驱动器将计算出的实际栅极导通电压提供给m条栅极线；所述信号控制器包括：生成单元、计数单元、占空比调整单元、第一输出单元；
    其中，信号控制器产生像素时钟信号，并对所述像素时钟信号的占空比进行调整的方法具体包括：
    生成单元产生占空比可调的像素时钟信号以及基准栅极导通电压；
    计数单元在计数数字为m的自然数倍时产生一计数信号；
    占空比调整单元根据计数信号对像素时钟信号的占空比进行调整；
    第一输出单元将占空比调整后的像素时钟信号输出到对应的栅极驱动器。
  11. 根据权利要求9所述的液晶面板的驱动电路的驱动方法，其中，每个栅极驱动器包括：侦测单元、计算单元、第二输出单元；
    其中，每个栅极驱动器根据占空比被调整后的像素时钟信号以及由外部信号源提供的基准栅极导通电压计算出提供到栅极线上的实际栅极导通电压的具体方法包括：
    侦测单元侦测接收到的像素时钟信号的高电平持续时间以及相邻两个像素时钟信号的高电平持续时间的时间差；
    计算单元根据所述高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间计算出实际栅极导通电压；
    第二输出单元将计算出的实际栅极导通电压输出到对应的m条栅极线上。
  12. 根据权利要求10所述的液晶面板的驱动电路的驱动方法，其中，每个栅极驱动器包括：侦测单元、计算单元、第二输出单元；
    其中，每个栅极驱动器根据占空比被调整后的像素时钟信号以及由外部信号源提供的基准栅极导通电压计算出提供到栅极线上的实际栅极导通电压的具体方法包括：
    侦测单元侦测接收到的像素时钟信号的高电平持续时间以及相邻两个像素时钟信号的高电平持续时间的时间差；
    计算单元根据所述高电平持续时间、所述时间差、所述基准栅极导通电压 以及像素时钟信号的高电平持续下限时间计算出实际栅极导通电压；
    第二输出单元将计算出的实际栅极导通电压输出到对应的m条栅极线上。
  13. 根据权利要求11所述的液晶面板的驱动电路的驱动方法，其中，所述计算单元根据所述高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间利用下面的式子1计算出实际栅极导通电压，
    [式子1]
    VGH＝K×(Tr-T0)/Δt+V0
    其中，VGH表示所述实际栅极导通电压，Tr表示所述高电平持续时间，T0表示像素时钟信号的高电平持续下限时间，Δt表示所述时间差，V0表示所述基准栅极导通电压。
  14. 根据权利要求12所述的液晶面板的驱动电路的驱动方法，其中，所述计算单元根据所述高电平持续时间、所述时间差、所述基准栅极导通电压以及像素时钟信号的高电平持续下限时间利用下面的式子1计算出实际栅极导通电压，
    [式子1]
    VGH＝K×(Tr-T0)/Δt+V0
    其中，VGH表示所述实际栅极导通电压，Tr表示所述高电平持续时间，T0表示像素时钟信号的高电平持续下限时间，Δt表示所述时间差，V0表示所述基准栅极导通电压。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11847973B2 (en) * 2016-06-01 2023-12-19 Samsung Display Co., Ltd. Display device capable of displaying an image of uniform brightness
KR102513988B1 (ko) * 2016-06-01 2023-03-28 삼성디스플레이 주식회사 표시 장치
KR20180000771A (ko) * 2016-06-23 2018-01-04 삼성디스플레이 주식회사 표시 장치
CN106652957B (zh) * 2017-01-16 2020-04-24 昆山龙腾光电股份有限公司 液晶显示装置及驱动方法
CN107068086B (zh) * 2017-03-30 2019-01-25 京东方科技集团股份有限公司 像素充电方法和电路
CN107393460B (zh) * 2017-08-08 2020-03-27 惠科股份有限公司 一种显示装置的驱动方法和驱动装置
CN108269547B (zh) * 2018-02-08 2020-07-14 京东方科技集团股份有限公司 像素补偿方法及补偿模块、计算机存储介质、显示装置
US10692415B2 (en) * 2018-04-24 2020-06-23 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driving circuit of irregular screen panel and driving method
CN110459161B (zh) * 2019-08-23 2023-04-07 北京集创北方科技股份有限公司 接收装置、驱动芯片、显示装置及电子设备
CN111681583A (zh) * 2020-06-04 2020-09-18 Tcl华星光电技术有限公司 Goa驱动电路及显示装置
CN112331128B (zh) * 2020-12-02 2022-05-03 深圳市华星光电半导体显示技术有限公司 阵列基板及显示装置
CN112967670B (zh) * 2021-03-03 2022-11-18 北京集创北方科技股份有限公司 显示驱动方法、装置和芯片、显示设备以及存储介质
CN114170986B (zh) * 2021-12-09 2023-01-24 Tcl华星光电技术有限公司 液晶显示面板及显示装置
CN114038388B (zh) * 2021-12-14 2024-04-05 集创北方(珠海)科技有限公司 源极驱动芯片的输出控制电路以及显示面板
CN114765013B (zh) * 2022-05-23 2024-02-23 合肥京东方显示技术有限公司 一种显示驱动电路、显示驱动方法及相关设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101819744A (zh) * 2010-04-28 2010-09-01 友达光电股份有限公司 栅极驱动器及其所应用的液晶显示器
EP1923859B1 (en) * 2006-11-20 2012-03-28 Samsung Electronics Co., Ltd. Liquid crystal display and method of driving the same
CN103745707A (zh) * 2013-12-31 2014-04-23 深圳市华星光电技术有限公司 补偿栅极驱动电路信号线阻值的方法及应用该方法的液晶显示面板
CN105374330A (zh) * 2015-12-01 2016-03-02 深圳市华星光电技术有限公司 显示装置及其驱动方法
CN105469757A (zh) * 2015-12-10 2016-04-06 深圳市华星光电技术有限公司 显示面板扫描驱动方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100537886B1 (ko) * 1998-06-26 2006-03-14 삼성전자주식회사 게이트 온 전압 파형 조절이 가능한 박막 트랜지스터 액정표시장치
KR100666317B1 (ko) * 1999-12-15 2007-01-09 삼성전자주식회사 구동 신호 인가시점 결정모듈, 이를 포함한 액정표시패널어셈블리 및 액정표시패널 어셈블리의 구동 방법
KR100898784B1 (ko) * 2002-10-14 2009-05-20 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
JP2007072162A (ja) * 2005-09-07 2007-03-22 Mitsubishi Electric Corp 表示装置
KR20110077868A (ko) * 2009-12-30 2011-07-07 엘지디스플레이 주식회사 액정 표시장치의 구동장치
KR101097353B1 (ko) * 2010-05-07 2011-12-23 삼성모바일디스플레이주식회사 게이트 구동회로 및 이를 이용한 유기전계발광표시장치
KR101997775B1 (ko) * 2012-12-05 2019-10-01 엘지디스플레이 주식회사 쉬프트 레지스터 및 이를 포함하는 평판 표시 장치
KR102114155B1 (ko) * 2013-10-01 2020-05-25 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1923859B1 (en) * 2006-11-20 2012-03-28 Samsung Electronics Co., Ltd. Liquid crystal display and method of driving the same
CN101819744A (zh) * 2010-04-28 2010-09-01 友达光电股份有限公司 栅极驱动器及其所应用的液晶显示器
CN103745707A (zh) * 2013-12-31 2014-04-23 深圳市华星光电技术有限公司 补偿栅极驱动电路信号线阻值的方法及应用该方法的液晶显示面板
CN105374330A (zh) * 2015-12-01 2016-03-02 深圳市华星光电技术有限公司 显示装置及其驱动方法
CN105469757A (zh) * 2015-12-10 2016-04-06 深圳市华星光电技术有限公司 显示面板扫描驱动方法

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