WO2017166412A1 - 数据驱动器及具有该数据驱动器的液晶显示器 - Google Patents

数据驱动器及具有该数据驱动器的液晶显示器 Download PDF

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Publication number
WO2017166412A1
WO2017166412A1 PCT/CN2016/083506 CN2016083506W WO2017166412A1 WO 2017166412 A1 WO2017166412 A1 WO 2017166412A1 CN 2016083506 W CN2016083506 W CN 2016083506W WO 2017166412 A1 WO2017166412 A1 WO 2017166412A1
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data
pmos transistor
nmos transistor
data line
transistor
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PCT/CN2016/083506
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English (en)
French (fr)
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黄笑宇
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深圳市华星光电技术有限公司
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Priority to US15/115,597 priority Critical patent/US10269315B2/en
Publication of WO2017166412A1 publication Critical patent/WO2017166412A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a data driver and a liquid crystal display having the same.
  • LCDs liquid crystal displays
  • the driving voltage supplied to the liquid crystal pixels during the display process of the liquid crystal display needs to be reversed in polarity.
  • the polarity reversal method commonly used in liquid crystal displays is a single-point polarity inversion method, that is, the polarity of the voltage stored in each liquid crystal pixel in the liquid crystal display is the voltage pole stored by the liquid crystal pixels adjacent to the upper, lower, left, and right sides. The opposite is true.
  • the single-point polarity inversion method adopted by the liquid crystal display has the best display effect in the existing polarity inversion mode, some display defects related to the single-point polarity inversion method are generated under some special screens. For example, cross talk (Cross Talk) and other issues. Therefore, it is necessary to convert the single-point polarity inversion mode to the two-point polarity inversion mode under these special screens, that is, the liquid crystal pixel group in the liquid crystal display stores the polarity of the voltage adjacent to the upper, lower, left and right liquid crystals. The voltages stored in the pixel group are opposite in polarity, wherein each liquid crystal pixel group includes at least two liquid crystal pixels having the same voltage polarity.
  • a data driver of the display comprising: an output module, configured to output N sets of data voltage groups to N sets of data line groups; N selection modules, each selection module corresponding to a set of data voltage groups and a set of data line groups; wherein When the liquid crystal display drives the pixels in different polarity inversion manners, each selection module selects a data voltage in a corresponding group of data voltage groups according to different control signals and provides them to a corresponding group of data line groups.
  • Data line comprising: an output module, configured to output N sets of data voltage groups to N sets of data line groups; N selection modules, each selection module corresponding to a set of data voltage groups and a set of data line groups; wherein When the liquid crystal display drives the pixels in different polarity inversion manners, each selection module selects a data voltage in a corresponding group of data voltage groups according to different control signals and provides them to a corresponding group of data line groups.
  • each selection module selects a data voltage in a corresponding set of data voltage groups according to different control signals to provide a corresponding set of data.
  • a data line in the line group; wherein the single-point polarity inversion manner is: each of the pixels in the liquid crystal display stores a polarity opposite to a voltage stored in a pixel adjacent to the upper, lower, left, and right pixels .
  • each selection module selects a data voltage in a corresponding set of data voltage groups according to different control signals to provide a corresponding set of data.
  • a data line in the line group wherein the two-point polarity inversion mode is: a voltage polarity stored in each pixel group in the liquid crystal display is stored in a voltage group of a pixel group adjacent to the upper, lower, left, and right sides thereof The opposite is true, wherein each pixel group includes at least two pixels having the same voltage polarity.
  • each set of data voltage groups includes: a first data voltage, a second data voltage, a third data voltage, and a fourth data voltage
  • each set of data lines includes: a first data line, a second data line, and a third data a line, a fourth data line
  • the control signal includes a high level signal and a low level signal
  • each selection module is configured according to the The high level signal selects the first data voltage, the second data voltage, the third data voltage, and the fourth data voltage in the corresponding set of data voltage groups to be sequentially supplied to the first data line in the corresponding one of the data line groups, The second data line, the third data line, and the fourth data line.
  • each selection module selects a first data voltage in the corresponding set of data voltage groups according to the low level signal, and second The data voltage, the third data voltage, and the fourth data voltage are sequentially supplied to the first data line, the third data line, the second data line, and the fourth data line of the corresponding one of the group of data lines.
  • each set of data voltage groups includes: a first data voltage, a second data voltage, a third data voltage, and a fourth data voltage; each set of data lines includes: a first data line, a second data line, and a third data a line, a fourth data line; the control signal includes a high level signal and a low level signal; wherein, when When the liquid crystal display drives the pixels in a single-point polarity inversion manner, each selection module selects a first data voltage, a second data voltage, and a corresponding one of the corresponding one of the data voltage groups according to the low-level signal. The three data voltages and the fourth data voltage are sequentially supplied to the first data line, the second data line, the third data line, and the fourth data line of the corresponding one of the group of data lines.
  • each selection module selects a first data voltage in the corresponding set of data voltage groups according to the high level signal, and second The data voltage, the third data voltage, and the fourth data voltage are sequentially supplied to the first data line, the third data line, the second data line, and the fourth data line of the corresponding one of the group of data lines.
  • the selection module includes at least: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor; wherein the input ends of the first NMOS transistor and the first PMOS transistor are used to receive the second data
  • the input terminals of the voltage, the second NMOS transistor and the second PMOS transistor are configured to receive a third data voltage, and an output end of the first PMOS transistor and an output end of the second NMOS transistor are both connected to the third data line, and the second PMOS transistor
  • the output end and the output end of the first NMOS transistor are both connected to the second data line, and the control ends of the first NMOS transistor, the first PMOS transistor, the second NMOS transistor and the second PMOS transistor are both used to receive the control signal.
  • the selection module includes at least: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor; wherein the input ends of the first NMOS transistor and the first PMOS transistor are used to receive the second data
  • the input terminals of the voltage, the second NMOS transistor and the second PMOS transistor are configured to receive a third data voltage, and an output end of the first NMOS transistor and an output end of the second PMOS transistor are both connected to the third data line, the first PMOS transistor
  • the output terminals of the output terminal connected to the second NMOS transistor are both connected to the second data line, and the control terminals of the first NMOS transistor, the first PMOS transistor, the second NMOS transistor and the second PMOS transistor are both used to receive the control signal.
  • Another object of the present invention is to provide a liquid crystal display comprising the above described data controller.
  • the liquid crystal display and the data driver of the present invention can achieve the purpose of freely switching between a single-point polarity inversion method and a two-point polarity inversion method.
  • FIG. 1 shows a block diagram of a liquid crystal display according to an embodiment of the present invention
  • FIG. 2 shows a block diagram of a data driver in accordance with an embodiment of the present invention
  • FIG. 3 shows a circuit configuration diagram of a selection module in accordance with an embodiment of the present invention
  • FIG. 4 shows a circuit configuration diagram of a selection module in accordance with another embodiment of the present invention.
  • FIG. 1 shows a block diagram of a liquid crystal display according to an embodiment of the present invention.
  • a liquid crystal display includes: a liquid crystal panel assembly 300; a scan driver 400 and a data driver 500, both connected to the liquid crystal panel assembly 300; a gray voltage generator 800 connected to the data driver 500 And a signal controller 600 for controlling the liquid crystal panel assembly 300, the scan driver 400, the data driver 500, and the gray voltage generator 800.
  • the liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in an array.
  • the liquid crystal panel assembly 300 may include: a lower display panel facing each other (not shown) And an upper display panel (not shown), and a liquid crystal layer (not shown) interposed between the lower display panel and the upper display panel.
  • a display signal line can be arranged on the lower display panel.
  • the display signal line may include a plurality of gate lines G1 to Gn that transmit gate signals and a plurality of data lines D1 to Dm that transmit data signals.
  • the gate lines G1 to Gn extend in the row direction and are substantially parallel to each other, and the data lines D1 to Dm extend in the column direction and are substantially parallel to each other.
  • Each of the pixels PX includes: a switching device connected to a corresponding gate line and a corresponding data line; and a liquid crystal capacitor connected to the switching device.
  • Each pixel PX may also include a storage capacitor, which is connected in parallel with the liquid crystal capacitor, if necessary.
  • the switching device of each pixel PX is a three-terminal device, thus having a control terminal connected to the corresponding gate line, an input terminal connected to the corresponding data line, and an output terminal connected to the corresponding liquid crystal capacitor.
  • the scan driver 400 is connected to the gate lines G1 to Gn and applies a gate signal to the gate lines G1 to Gn, which is a high-level gate signal supplied from the external source to the scan driver 400 (hereinafter referred to as A combination of a gate-on voltage Von) and a low-level gate signal (hereinafter referred to as a gate-off voltage Voff).
  • a scan driver 400 is disposed on one side of a liquid crystal panel assembly 300, and gate lines G1 to Gn are both connected to these scan drivers 400.
  • the invention is not limited thereto. That is, one scan driver may be respectively disposed on opposite sides of the liquid crystal panel assembly 300, and the gate lines G1 to Gn are both connected to each of the two scan drivers.
  • the gray voltage generator 800 generates a gray voltage that is closely related to the transmittance of the pixel PX. This gray voltage is supplied to each pixel PX and has a positive value or a negative value according to the common voltage Vcom.
  • the data driver 500 is connected to the data lines D1 to Dm of the liquid crystal panel assembly 300, and applies the gray voltage generated by the gray voltage generator 800 to the pixel PX as a data voltage. If the gray voltage generator 800 does not supply all of the gray voltages but only the reference gray voltages, the data driver 500 can generate various gray voltages by dividing the reference gray voltages, and select various gray scales. One of the voltages acts as a data voltage.
  • Signal controller 600 controls the operation of scan driver 400 and data driver 500.
  • the signal controller 600 receives an input image signal (R, G) from an external graphics controller (not shown). And B) and a plurality of input control signals for controlling display of the input image signal, such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a master clock signal MCLK, and a data enable signal DE.
  • the signal controller 600 appropriately processes the input image signals (R, G, and B) in accordance with the input control signals, thereby generating image data DAT that conforms to the operating conditions of the liquid crystal panel assembly 300. Then, the signal controller 600 generates the gate control signal CONT1 and the data control signal CONT2, transfers the gate control signal CONT1 to the scan driver 400, and transfers the data control signal CONT2 and the image data DAT to the data driver 500.
  • the gate control signal CONT1 may include a scan start signal STV for starting an operation of the scan driver 400, that is, a scan operation, and at least one clock signal for controlling when the gate-on voltage Von is output.
  • the gate control signal CONT1 may also include an output enable signal OE for limiting the duration of the gate-on voltage Von.
  • the clock signal can be used as the selection signal SE.
  • the data control signal CONT2 may include a horizontal synchronization start signal STH indicating transmission of the image data DAT, a load signal LOAD requesting application of a data voltage corresponding to the image data DAT to the data lines D1 to Dm, and a data clock signal HCLK.
  • the data control signal CONT2 may also include an inversion signal RVS for inverting the polarity of the data voltage with respect to the common voltage Vcom, which is hereinafter referred to as "polarity of the data voltage.”
  • the data driver 500 receives the image data DAT from the signal controller 600 in response to the data control signal CONT2, and selects the image data by selecting the gray voltage corresponding to the image data DAT from among the plurality of gray voltages supplied from the gray voltage generator 800. Convert to data voltage. Then, the data driver 500 supplies the data voltages to the data lines D1 to Dm.
  • the scan driver 400 turns on the switching devices connected to the gate lines G1 to Gn by applying the gate-on voltage Von to the gate lines G1 to Gn in response to the gate control signal CONT1. Then, the data voltages supplied to the data lines D1 to Dm are transmitted to each of the pixels PX through the turned-on switching devices.
  • the difference between the data voltage supplied to each pixel PX and the common voltage Vcom can be interpreted as a voltage with which the liquid crystal capacitor of each pixel PX is charged, that is, a pixel voltage.
  • the arrangement of the liquid crystal molecules in the liquid crystal layer varies depending on the amplitude of the pixel voltage, and thus the polarity of the light transmitted through the liquid crystal layer can also be changed, resulting in a change in the transmittance of the liquid crystal layer.
  • FIG. 2 shows a block diagram of a data driver in accordance with an embodiment of the present invention.
  • a data driver 500 includes an output module 510 and N selection modules 520.
  • the output module 510 applies the gradation voltage generated by the gradation voltage generator 800 to the pixel PX as a data voltage. If the gray voltage generator 800 does not provide all of the gray voltages but only the reference gray voltages, the output module 510 can generate various gray voltages by dividing the reference gray voltages, and select various gray scales. One of the voltages acts as a data voltage.
  • the output module 510 receives the image data DAT from the signal controller 600 in response to the data control signal CONT2 by selecting the gray voltage corresponding to the image data DAT from the plurality of gray voltages supplied from the gray voltage generator 800. Convert image data to data voltage. Output module 510 then provides the data voltages to data lines D1 through Dm.
  • each group of data lines includes four data lines, which are a first data line, a second data line, a third data line, and a fourth data line, but the invention is not limited thereto.
  • each set of data voltage groups includes a first data voltage, a second data voltage, a third data voltage, and a fourth data voltage, but the invention is not limited thereto.
  • the output module 510 outputs N sets of data voltage groups to N sets of data line groups; each of the N selection modules 520 corresponds to a set of data voltage groups and a set of data line groups.
  • each selection module 520 selects data voltages in its corresponding set of data voltage groups according to different control signals B into its corresponding set of data line groups. Data line.
  • each selection module 520 selects data voltages in a corresponding group of data voltage groups according to different control signals B into a corresponding group of data lines.
  • the single-dot inversion method means that the polarity of the voltage stored in each pixel is opposite to the polarity of the voltage stored in the pixels adjacent to the top, bottom, left, and right.
  • each selection module 520 selects data voltages in a corresponding set of data voltage groups according to different control signals B to a corresponding one of the data lines.
  • the two-dot inversion method means that the polarity of the voltage stored in each pixel group is opposite to the polarity of the voltage stored in the pixel group adjacent to the upper, lower, left and right sides, wherein each pixel group includes at least two voltages having the same polarity Pixels.
  • FIG. 3 shows a circuit configuration diagram of a selection module in accordance with an embodiment of the present invention.
  • a selection module 520 corresponds to four data lines and four data voltages. It should be understood that the circuit configurations of the other selection modules 520 and the corresponding four data lines and four data voltages are as shown in FIG. The same is shown.
  • each of the selection modules 520 includes a first NMOS transistor 521, a first PMOS transistor 522, a second NMOS transistor 523, and a second PMOS transistor 524.
  • the input ends of the first NMOS transistor 521 and the first PMOS transistor 522 are for receiving the second data voltage, the output end of the first NMOS transistor 521 is connected to the second data line, and the output end of the first PMOS transistor 522 is connected to the third data.
  • the input ends of the second NMOS transistor 523 and the second PMOS transistor 524 are for receiving the third data voltage, the output of the second NOS transistor 523 is connected to the third data line, and the output of the second PMOS transistor 524 is connected to the The two data lines; the control terminals of the first NMOS transistor 521, the first PMOS transistor 522, the second NMOS transistor 523, and the second PMOS transistor 524 are both used to receive the control signal B.
  • control signal B includes a high level signal and a low level signal, but the present invention is not limited thereto.
  • the working principle of the selection module 520 is that when the pixels are driven in a single dot inversion manner, the control terminals of the first NMOS transistor 521 and the second NMOS transistor 523 receive a high level signal and are turned on, and the first PMOS transistor 522 is turned on. And the control terminal of the second PMOS transistor 524 is turned off due to receiving the high level signal, and the first data voltage, the second data voltage, the third data voltage, and the fourth data voltage are sequentially supplied to the first data line and the second The data line, the third data line, and the fourth data line.
  • the control terminals of the first NMOS transistor 521 and the second NMOS transistor 523 receive the low level signal and are turned off, and the control terminals of the first PMOS transistor 522 and the second PMOS transistor 524 are turned off.
  • the first data voltage, the second data voltage, the third data voltage, and the fourth data voltage are sequentially supplied to the first data line, the third data line, and the second data line, because the low level signal is received.
  • the fourth data line is sequentially supplied to the first data line, the third data line, and the second data line, because the low level signal is received.
  • FIG. 4 shows a circuit configuration diagram of a selection module in accordance with another embodiment of the present invention.
  • the input terminals of the first NMOS transistor 521 and the first PMOS transistor 522 are used to receive the second data voltage, and the output terminal of the first PMOS transistor 522.
  • the output of the first NMOS transistor 521 is connected to the third data line;
  • the input of the second NMOS transistor 523 and the second PMOS transistor 524 is for receiving the third data voltage, the second PMOS transistor 524
  • the output terminal is connected to the third data line, and the output end of the second NMOS transistor 523 is connected to the second data line;
  • the control terminals of the first NMOS transistor 521, the first PMOS transistor 522, the second NMOS transistor 523, and the second PMOS transistor 524 Both are used to receive the control signal B.
  • the selection module 520 operates on the principle that when the pixel is driven in a single dot inversion manner, the control terminals of the first NMOS transistor 521 and the second NMOS transistor 523 receive a low level signal and are turned off, and the first PMOS transistor 522 and The control terminal of the second PMOS transistor 524 is turned on by receiving the low level signal, and the first data voltage, the second data voltage, the third data voltage, and the fourth data voltage are sequentially supplied to the first data line and the second The data line, the third data line, and the fourth data line.
  • the control terminals of the first NMOS transistor 521 and the second NMOS transistor 523 receive a high level signal to be turned on, and the control of the first PMOS transistor 522 and the second PMOS transistor 524 The terminal is turned off due to receiving the high level signal, and the first data voltage, the second data voltage, the third data voltage, and the fourth data voltage are sequentially supplied to the first data line, the third data line, the second data line, The fourth data line.
  • liquid crystal display and the data driver of the present invention it is possible to achieve free switching between the single-point polarity inversion method and the two-point polarity inversion method.

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Abstract

提供了一种液晶显示器及其数据驱动器，其中，该数据驱动器包括：输出模块(510)，用于输出N组数据电压组到N组数据线组；N个选择模块(520)，每个选择模块(520)对应一组数据电压组及一组数据线组；其中，当所述液晶显示器以不同的极性反转方式对像素进行驱动时，每个选择模块(520)根据不同的控制信号选择对应的一组数据电压组中的数据电压提供给对应的一组数据线组中的数据线。该液晶显示器及其数据驱动器能够实现在单点极性反转方式和双点极性反转方式之间自由切换的目的。

Description

数据驱动器及具有该数据驱动器的液晶显示器 技术领域
本发明属于显示技术领域，具体地讲，涉及一种数据驱动器及具有该数据驱动器的液晶显示器。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，LCD)因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已被应用于生产生活的各个方面。
在应用过程中，为了避免液晶显示器中液晶像素的直流阻隔效应，以及避免液晶像素极化，在液晶显示器的显示过程中提供给液晶像素的驱动电压需要进行极性反转。目前液晶显示器中较为常用的极性反转方式是单点极性反转方式，即液晶显示器中的每个液晶像素所存储的电压极性都与其上下左右相邻的液晶像素所存储的电压极性相反。
虽然液晶显示器采用的单点极性反转方式在现有的极性反转方式中显示效果最佳，但是在某些特殊画面下会产生一些与单点极性反转方式相关的显示不良，例如串扰(Cross Talk)等问题。这就需要在这些特殊画面下将单点极性反转方式转换为双点极性反转方式，即液晶显示器中的每个液晶像素组所存储的电压极性都与其上下左右相邻的液晶像素组所存储的电压极性相反，其中，每个液晶像素组包括至少两个电压极性相同的液晶像素。
因此，有必要提出一种能够在单点极性反转方式和双点极性反转方式之间自由切换的液晶显示器。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种用于液晶 显示器的数据驱动器，其包括：输出模块，用于输出N组数据电压组到N组数据线组；N个选择模块，每个选择模块对应一组数据电压组及一组数据线组；其中，当所述液晶显示器以不同的极性反转方式对像素进行驱动时，每个选择模块根据不同的控制信号选择对应的一组数据电压组中的数据电压提供给对应的一组数据线组中的数据线。
进一步地，当所述液晶显示器以单点极性反转方式对像素进行驱动时，每个选择模块根据不同的控制信号选择对应的一组数据电压组中的数据电压提供给对应的一组数据线组中的数据线；其中，所述单点极性反转方式为：所述液晶显示器中的每个像素所存储的电压极性都与其上下左右相邻的像素所存储的电压极性相反。
进一步地，当所述液晶显示器以双点极性反转方式对像素进行驱动时，每个选择模块根据不同的控制信号选择对应的一组数据电压组中的数据电压提供给对应的一组数据线组中的数据线；其中，所述双点极性反转方式为：所述液晶显示器中的每个像素组所存储的电压极性都与其上下左右相邻的像素组所存储的电压极性相反，其中，每个像素组包括至少两个电压极性相同的像素。
进一步地，每组数据电压组包括：第一数据电压、第二数据电压、第三数据电压、第四数据电压；每组数据线组包括：第一数据线、第二数据线、第三数据线、第四数据线；所述控制信号包括高电平信号和低电平信号；其中，当所述液晶显示器以单点极性反转方式对像素进行驱动时，每个选择模块根据所述高电平信号选择对应的一组数据电压组中的第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给对应的一组数据线组中的第一数据线、第二数据线、第三数据线、第四数据线。
进一步地，当所述液晶显示器以双点极性反转方式对像素进行驱动时，每个选择模块根据所述低电平信号选择对应的一组数据电压组中的第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给对应的一组数据线组中的第一数据线、第三数据线、第二数据线、第四数据线。
进一步地，每组数据电压组包括：第一数据电压、第二数据电压、第三数据电压、第四数据电压；每组数据线组包括：第一数据线、第二数据线、第三数据线、第四数据线；所述控制信号包括高电平信号和低电平信号；其中，当 所述液晶显示器以单点极性反转方式对像素进行驱动时，每个选择模块根据所述低电平信号选择对应的一组数据电压组中的第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给对应的一组数据线组中的第一数据线、第二数据线、第三数据线、第四数据线。
进一步地，当所述液晶显示器以双点极性反转方式对像素进行驱动时，每个选择模块根据所述高电平信号选择对应的一组数据电压组中的第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给其对应的一组数据线组中的第一数据线、第三数据线、第二数据线、第四数据线。
进一步地，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一PMOS晶体管的输出端和第二NMOS晶体管的输出端均连接到第三数据线，第二PMOS晶体管的输出端和第一NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
进一步地，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一NMOS晶体管的输出端和第二PMOS晶体管的输出端均连接到第三数据线，第一PMOS晶体管的输出端连接到第二NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
本发明的另一目的还在于提供一种液晶显示器，其包括上述的数据控制器。
本发明的有益效果：本发明的液晶显示器及其数据驱动器，能够实现在单点极性反转方式和双点极性反转方式之间自由切换的目的。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1示出了根据本发明的实施例的液晶显示器的框图；
图2示出了根据本发明的实施例的数据驱动器的模块图；
图3示出了根据本发明的实施例的选择模块的电路结构图；
图4示出了根据本发明的另一实施例的选择模块的电路结构图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚元件，夸大了层和区域的厚度。相同的标号在附图中始终表示相同的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
图1示出了根据本发明的实施例的液晶显示器的框图。
参照图1，根据本发明的实施例的液晶显示器包括：液晶面板组件300；扫描驱动器400和数据驱动器500，二者都连接到液晶面板组件300；灰度电压产生器800，连接到数据驱动器500；以及信号控制器600，用于控制液晶面板组件300、扫描驱动器400、数据驱动器500和灰度电压产生器800。
液晶面板组件300包括多条显示信号线和连接到显示信号线并按阵列排列的多个像素PX。液晶面板组件300可以包括：彼此面对的下显示面板(未示 出)和上显示面板(未示出)，以及被插入在下显示面板和上显示面板之间的液晶层(未示出)。
可以在下显示面板上布置显示信号线。显示信号线可以包括传送栅极信号的多条栅极线G1至Gn和传送数据信号的多条数据线D1至Dm。栅极线G1至Gn按行方向延伸并且彼此大致平行，并且数据线D1至Dm按列方向延伸并且彼此大致平行。
每个像素PX包括：开关器件，连接到相应的栅极线和相应的数据线；以及液晶电容器，连接到该开关器件。如果必要，每个像素PX也可以包括存储电容器，其与液晶电容器并联连接。
每个像素PX的开关器件是三端器件，因此具有连接到相应栅极线的控制端、连接到相应数据线的输入端和连接到相应液晶电容器的输出端。
扫描驱动器400连接到栅极线G1至Gn，并向栅极线G1至Gn施加栅极信号，该栅极信号是由外部源提供给扫描驱动器400的高电平栅极信号(此后称之为栅极导通电压Von)和低电平栅极信号(此后称之为栅极截止电压Voff)的组合。参照图1，在液晶面板组件300的一侧布置扫描驱动器400，并且栅极线G1至Gn都连接到这些扫描驱动器400。然而，本发明不限于此。也就是说，可以在液晶面板组件300的相对两侧分别布置一个扫描驱动器，并且栅极线G1至Gn都连接到这两个扫描驱动器的每一个。
灰度电压产生器800产生与像素PX的透射率紧密相关的灰度电压。该灰度电压被提供给每个像素PX，并且根据公共电压Vcom而具有正值或负值。
数据驱动器500连接到液晶面板组件300的数据线D1至Dm，并向像素PX施加由灰度电压产生器800产生的灰度电压作为数据电压。如果灰度电压产生器800不是提供所有的灰度电压而是仅提供基准灰度电压，则数据驱动器500可以通过将基准灰度电压分压而产生各种灰度电压，并选择各种灰度电压中的一个作为数据电压。
信号控制器600控制扫描驱动器400和数据驱动器500的操作。
信号控制器600从外部图形控制器(未示出)接收输入图像信号(R、G 和B)以及用于控制输入图像信号的显示的多个输入控制信号，例如垂直同步信号Vsync、水平同步信号Hsync、主时钟信号MCLK、数据使能信号DE。信号控制器600根据输入控制信号适当处理输入图像信号(R、G和B)，从而产生符合液晶面板组件300的操作条件的图像数据DAT。然后，信号控制器600产生栅极控制信号CONT1和数据控制信号CONT2，将栅极控制信号CONT1传送到扫描驱动器400，并将数据控制信号CONT2和图像数据DAT传送到数据驱动器500。
栅极控制信号CONT1可以包括：扫描开始信号STV，用于启动扫描驱动器400的操作、即扫描操作；以及至少一个时钟信号，用于控制何时输出栅极导通电压Von。栅极控制信号CONT1也可以包括输出使能信号OE，用于限制栅极导通电压Von的持续时间。时钟信号可以被用作选择信号SE。
数据控制信号CONT2可以包括：水平同步开始信号STH，其指示图像数据DAT的传输；加载信号LOAD，其请求向数据线D1至Dm施加与图像数据DAT对应的数据电压；以及数据时钟信号HCLK。数据控制信号CONT2也可以包括反转信号RVS，用于反转数据电压相对于公共电压Vcom的极性，这此后被称为“数据电压的极性”。
数据驱动器500响应于数据控制信号CONT2从信号控制器600接收图像数据DAT，通过从由灰度电压产生器800提供的多个灰度电压中选择与图像数据DAT对应的灰度电压而将图像数据转换为数据电压。然后，数据驱动器500将数据电压提供给数据线D1至Dm。
扫描驱动器400通过响应于栅极控制信号CONT1向栅极线G1至Gn施加栅极导通电压Von而导通连接到栅极线G1至Gn的开关器件。然后，提供给数据线D1至Dm的数据电压通过导通的开关器件而被传送到每个像素PX。
提供给每个像素PX的数据电压和公共电压Vcom之间的差可以被解释为是利用其对每个像素PX的液晶电容器充电的电压、即像素电压。液晶层内的液晶分子的排列根据像素电压的幅度而变化，因而通过液晶层传送的光的极性也可以变化，从而导致液晶层的透射率的变化。
图2示出了根据本发明的实施例的数据驱动器的模块图。
参照图2，根据本发明的实施例的数据驱动器500包括：输出模块510、N个选择模块520。
输出模块510向像素PX施加由灰度电压产生器800产生的灰度电压作为数据电压。如果灰度电压产生器800不是提供所有的灰度电压而是仅提供基准灰度电压，则输出模块510可以通过将基准灰度电压分压而产生各种灰度电压，并选择各种灰度电压中的一个作为数据电压。
进一步地，输出模块510响应于数据控制信号CONT2从信号控制器600接收图像数据DAT，通过从由灰度电压产生器800提供的多个灰度电压中选择与图像数据DAT对应的灰度电压而将图像数据转换为数据电压。然后，输出模块510将数据电压提供给数据线D1至Dm。
这里，将m条数据线D1至Dm分为N组数据线组。优选地，每组数据线组包括四条数据线，分别为第一数据线、第二数据线、第三数据线和第四数据线，但本发明并不以此为限。
对应N组数据线组，将提供给m条数据线D1至Dm的m个数据电压也分为N组数据电压组。对应地，每组数据电压组包括第一数据电压、第二数据电压、第三数据电压和第四数据电压，但本发明并不以此为限。
这样，输出模块510输出N组数据电压组到N组数据线组；N个选择模块520中的每一个对应一组数据电压组及一组数据线组。
当对像素以不同的极性反转方式进行驱动时，每个选择模块520根据不同的控制信号B选择其对应的一组数据电压组中的数据电压到其对应的一组数据线组中的数据线。
具体地，当对像素以单点反转方式进行驱动时，每个选择模块520根据不同的控制信号B选择其对应的一组数据电压组中的数据电压到其对应的一组数据线组中的数据线。单点反转方式指的是：每个像素所存储的电压极性都与其上下左右相邻的像素所存储的电压极性相反。
而当对像素以双点反转方式进行驱动时，每个选择模块520根据不同的控制信号B选择其对应的一组数据电压组中的数据电压到其对应的一组数据线 组中的数据线。双点反转方式指的是：每个像素组所存储的电压极性都与其上下左右相邻的像素组所存储的电压极性相反，其中，每个像素组包括至少两个电压极性相同的像素。
图3示出了根据本发明的实施例的选择模块的电路结构图。在图3中，以一个选择模块520对应四条数据线和四个数据电压进行说明，应当理解的是，其他各选择模块520与对应的四条数据线和四个数据电压的电路结构与图3所示的相同。
参照图3，每个选择模块520包括：第一NMOS晶体管521、第一PMOS晶体管522、第二NMOS晶体管523、第二PMOS晶体管524。
第一NMOS晶体管521和第一PMOS晶体管522的输入端用于接收第二数据电压，第一NMOS晶体管521的输出端连接到第二数据线，第一PMOS晶体管522的输出端连接到第三数据线；第二NMOS晶体管523和第二PMOS晶体管524的输入端用于接收第三数据电压，第二NOS晶体管523的输出端连接到第三数据线，第二PMOS晶体管524的输出端连接到第二数据线；第一NMOS晶体管521、第一PMOS晶体管522、第二NMOS晶体管523、第二PMOS晶体管524的控制端均用于接收控制信号B。
在本实施例中，控制信号B包括高电平信号和低电平信号，但本发明并不限制于此。
选择模块520的工作原理是：当对像素以单点反转方式进行驱动时，第一NMOS晶体管521和第二NMOS晶体管523的控制端接收高电平信号而导通，而第一PMOS晶体管522和第二PMOS晶体管524的控制端由于接收到高电平信号而截止，此时第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给第一数据线、第二数据线、第三数据线、第四数据线。
当对像素以双点反转方式进行驱动时，第一NMOS晶体管521和第二NMOS晶体管523的控制端接收低电平信号而截止，而第一PMOS晶体管522和第二PMOS晶体管524的控制端由于接收到低电平信号而导通，此时第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给第一数据线、第三数据线、第二数据线、第四数据线。
图4示出了根据本发明的另一实施例的选择模块的电路结构图。
参照图4，与图3所示的选择模块的电路结构图不同的是：第一NMOS晶体管521和第一PMOS晶体管522的输入端用于接收第二数据电压，第一PMOS晶体管522的输出端连接到第二数据线，第一NMOS晶体管521的输出端连接到第三数据线；第二NMOS晶体管523和第二PMOS晶体管524的输入端用于接收第三数据电压，第二PMOS晶体管524的输出端连接到第三数据线，第二NMOS晶体管523的输出端连接到第二数据线；第一NMOS晶体管521、第一PMOS晶体管522、第二NMOS晶体管523、第二PMOS晶体管524的控制端均用于接收控制信号B。
选择模块520的工作原理是：当对像素以单点反转方式进行驱动时，第一NMOS晶体管521和第二NMOS晶体管523的控制端接收低电平信号而截止，而第一PMOS晶体管522和第二PMOS晶体管524的控制端由于接收到低电平信号而导通，此时第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给第一数据线、第二数据线、第三数据线、第四数据线。
当对像素以双点反转方式进行驱动时，第一NMOS晶体管521和第二NMOS晶体管523的控制端接收高电平信号而导通，而第一PMOS晶体管522和第二PMOS晶体管524的控制端由于接收到高电平信号而截止，此时第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给第一数据线、第三数据线、第二数据线、第四数据线。
综上所述，根据本发明的液晶显示器及其数据驱动器，能够实现在单点极性反转方式和双点极性反转方式之间自由切换的目的。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (18)

  1. 一种用于液晶显示器的数据驱动器，其中，包括：
    输出模块，用于输出N组数据电压组到N组数据线组；
    N个选择模块，每个选择模块对应一组数据电压组及一组数据线组；
    其中，当所述液晶显示器以不同的极性反转方式对像素进行驱动时，每个选择模块根据不同的控制信号选择对应的一组数据电压组中的数据电压提供给对应的一组数据线组中的数据线。
  2. 根据权利要求1所述的数据驱动器，其中，当所述液晶显示器以单点极性反转方式对像素进行驱动时，每个选择模块根据不同的控制信号选择对应的一组数据电压组中的数据电压提供给对应的一组数据线组中的数据线；
    其中，所述单点极性反转方式为：所述液晶显示器中的每个像素所存储的电压极性都与其上下左右相邻的像素所存储的电压极性相反。
  3. 根据权利要求2所述的数据驱动器，其中，当所述液晶显示器以双点极性反转方式对像素进行驱动时，每个选择模块根据不同的控制信号选择对应的一组数据电压组中的数据电压提供给对应的一组数据线组中的数据线；
    其中，所述双点极性反转方式为：所述液晶显示器中的每个像素组所存储的电压极性都与其上下左右相邻的像素组所存储的电压极性相反，其中，每个像素组包括至少两个电压极性相同的像素。
  4. 根据权利要求3所述的数据驱动器，其中，每组数据电压组包括：第一数据电压、第二数据电压、第三数据电压、第四数据电压；每组数据线组包括：第一数据线、第二数据线、第三数据线、第四数据线；所述控制信号包括高电平信号和低电平信号；
    其中，当所述液晶显示器以单点极性反转方式对像素进行驱动时，每个选择模块根据所述高电平信号选择对应的一组数据电压组中的第一数据电压、第 二数据电压、第三数据电压、第四数据电压顺序提供给对应的一组数据线组中的第一数据线、第二数据线、第三数据线、第四数据线。
  5. 根据权利要求4所述的数据驱动器，其中，当所述液晶显示器以双点极性反转方式对像素进行驱动时，每个选择模块根据所述低电平信号选择对应的一组数据电压组中的第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给对应的一组数据线组中的第一数据线、第三数据线、第二数据线、第四数据线。
  6. 根据权利要求3所述的数据驱动器，其中，每组数据电压组包括：第一数据电压、第二数据电压、第三数据电压、第四数据电压；每组数据线组包括：第一数据线、第二数据线、第三数据线、第四数据线；所述控制信号包括高电平信号和低电平信号；
    其中，当所述液晶显示器以单点极性反转方式对像素进行驱动时，每个选择模块根据所述低电平信号选择对应的一组数据电压组中的第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给对应的一组数据线组中的第一数据线、第二数据线、第三数据线、第四数据线。
  7. 根据权利要求6所述的数据驱动器，其中，当所述液晶显示器以双点极性反转方式对像素进行驱动时，每个选择模块根据所述高电平信号选择对应的一组数据电压组中的第一数据电压、第二数据电压、第三数据电压、第四数据电压顺序提供给其对应的一组数据线组中的第一数据线、第三数据线、第二数据线、第四数据线。
  8. 根据权利要求1所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一PMOS晶体管的输出端和第二NMOS晶体管的输出端均连接到第三数据线，第二PMOS晶体管的输出端和第一NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管 和第二PMOS晶体管的控制端均用于接收所述控制信号。
  9. 根据权利要求2所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一PMOS晶体管的输出端和第二NMOS晶体管的输出端均连接到第三数据线，第二PMOS晶体管的输出端和第一NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  10. 根据权利要求3所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一PMOS晶体管的输出端和第二NMOS晶体管的输出端均连接到第三数据线，第二PMOS晶体管的输出端和第一NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  11. 根据权利要求4所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一PMOS晶体管的输出端和第二NMOS晶体管的输出端均连接到第三数据线，第二PMOS晶体管的输出端和第一NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  12. 根据权利要求5所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一PMOS晶体管的输出端和第二NMOS晶体管的输出端均连接到第三数据线，第二PMOS晶体管的输出端和第一NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  13. 根据权利要求1所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一NMOS晶体管的输出端和第二PMOS晶体管的输出端均连接到第三数据线，第一PMOS晶体管的输出端连接到第二NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  14. 根据权利要求2所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一NMOS晶体管的输出端和第二PMOS晶体管的输出端均连接到第三数据线，第一PMOS晶体管的输出端连接到第二NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  15. 根据权利要求3所述的数据驱动器，其中，所述选择模块至少包括： 第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一NMOS晶体管的输出端和第二PMOS晶体管的输出端均连接到第三数据线，第一PMOS晶体管的输出端连接到第二NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  16. 根据权利要求6所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一NMOS晶体管的输出端和第二PMOS晶体管的输出端均连接到第三数据线，第一PMOS晶体管的输出端连接到第二NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  17. 根据权利要求7所述的数据驱动器，其中，所述选择模块至少包括：第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管、第二PMOS晶体管；
    其中，第一NMOS晶体管和第一PMOS晶体管的输入端用于接收第二数据电压，第二NMOS晶体管和第二PMOS晶体管的输入端用于接收第三数据电压，第一NMOS晶体管的输出端和第二PMOS晶体管的输出端均连接到第三数据线，第一PMOS晶体管的输出端连接到第二NMOS晶体管的输出端均连接到第二数据线，第一NMOS晶体管、第一PMOS晶体管、第二NMOS晶体管和第二PMOS晶体管的控制端均用于接收所述控制信号。
  18. 一种液晶显示器，包括数据控制器，其中，所述数据控制器包括：
    输出模块，用于输出N组数据电压组到N组数据线组；
    N个选择模块，每个选择模块对应一组数据电压组及一组数据线组；
    其中，当所述液晶显示器以不同的极性反转方式对像素进行驱动时，每个选择模块根据不同的控制信号选择对应的一组数据电压组中的数据电压提供给对应的一组数据线组中的数据线。
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