WO2017084108A1 - 栅极驱动器及具有该栅极驱动器的触控面板 - Google Patents

栅极驱动器及具有该栅极驱动器的触控面板 Download PDF

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Publication number
WO2017084108A1
WO2017084108A1 PCT/CN2015/095327 CN2015095327W WO2017084108A1 WO 2017084108 A1 WO2017084108 A1 WO 2017084108A1 CN 2015095327 W CN2015095327 W CN 2015095327W WO 2017084108 A1 WO2017084108 A1 WO 2017084108A1
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Prior art keywords
switch tube
output
signal
driving circuit
stage
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PCT/CN2015/095327
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English (en)
French (fr)
Inventor
曹尚操
肖军城
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/909,178 priority Critical patent/US9946394B2/en
Publication of WO2017084108A1 publication Critical patent/WO2017084108A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3262—Power saving in digitizer or tablet
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present invention relates to the field of display technologies, and in particular to a gate driver and a touch panel having the same.
  • the more common capacitive touch screens usually use OGS (One Glass Solution), On-Cell (in-line) and In-Cell (in-line) technologies.
  • OGS One Glass Solution
  • On-Cell in-line
  • In-Cell in-line
  • the capacitive touch screen using In-Cell technology has the advantages of lighter weight, better light transmittance and more stable structure than the capacitive touch screen using OGS technology and On-Cell technology due to its manufacturing process advantages.
  • a liquid crystal panel or an OLED display panel is generally used as a display screen.
  • a gate driver is usually fabricated on an array substrate by using a Gate Driver On Array (GOA) technology to realize progressive scan driving of the gate lines.
  • GOA Gate Driver On Array
  • a conventional capacitive touch screen with a high refresh rate for example, 120 Hz
  • all pixel units on the liquid crystal panel are divided into a plurality of pixel blocks in order from top to bottom.
  • the touch screen enters the touch scanning stage after the corresponding pixel block is driven by the GOA circuit in the display scanning stage, which can improve the sensitivity of the touch, but increases the risk of failure of the GOA circuit. This is because during the touch scanning phase, the GOA circuit suspends the scan driving of the gate lines, thereby increasing the risk of gate leakage of the thin film transistors connected to the gate lines.
  • an object of the present invention is to provide a gate driver including a multi-stage driving unit, wherein each stage driving unit includes: a GOA driving circuit and a multi-stage buffering GOA driving circuit;
  • the GOA driving circuit is configured to output an output signal during a display phase, wherein the output signal is transmitted to the gate line and transmitted to the multi-stage buffered GOA driving circuit;
  • the multi-stage buffering GOA driving circuit outputs an output signal during a touch phase Pass the level and pass the output signal GOA drive circuit to the next stage drive unit.
  • GOA driving circuit and each stage buffered GOA driving circuit have the same circuit structure.
  • the GOA driving circuit includes: a level transmitting module, configured to receive an output signal of the upper stage and a second clock signal, and output a first control signal according to the output signal of the upper stage and the second clock signal; wherein The level transmitting module of the first stage GOA driving circuit receives the preset initial signal and the second clock signal; and the output module is configured to receive the first control signal and the first clock signal, and according to the first control signal and the first clock a signal output output signal, wherein the first clock signal and the second clock signal are reversed; the pull-down module is configured to receive the first control signal and the low level signal, and stop the output module according to the first control signal and the low level signal The output pull-down maintenance module is configured to receive the high-level signal, the low-level signal, and the second clock signal, and output a pull-down control signal according to the high-level signal, the low-level signal, and the second clock signal, wherein the pull-down control signal Leave the pull-down module to keep the output module stop output.
  • the level transfer module includes: a first switch tube; wherein a control end of the first switch tube is configured to receive a second clock signal, and an input end of the first switch tube is configured to receive an output signal of the previous stage, The output of a switch tube is used to output a first control signal.
  • the output module includes: a second switch tube and a third switch tube; wherein the second switch tube control end is connected to the output end of the first switch tube, and the input end of the second switch tube is used to receive the first a clock signal, an output end of the second switch tube is used for outputting an output signal; a control end of the third switch tube is connected to an output end of the first switch tube, and an input end of the third switch tube is used for receiving the first clock signal, and third The output of the switch is used to output the output signal.
  • the pull-down module includes: a fourth switch tube and a fifth switch tube; wherein a control end of the fourth switch tube is configured to receive a pull-down control signal, and an input end of the fourth switch tube is connected to an output of the third switch tube The output end of the fourth switch tube is configured to receive a low level signal; the control end of the fifth switch tube is configured to receive a pull down control signal, and the input end of the fifth switch tube is connected to the output end of the first switch tube, fifth The output of the switch is used to receive low level signals.
  • the pull-down maintaining module includes: a sixth switch tube, a seventh switch tube, an eighth switch tube, and a capacitor; wherein the control end of the sixth switch tube is connected to the output end of the first switch tube, and the sixth switch tube The input end is connected to the control end of the fifth switch tube, and the output end of the sixth switch tube is used to receive low power a flat signal; the control end of the seventh switch tube is connected to the input end of the eighth switch tube, the input end of the seventh switch tube is for receiving a high level signal, and the output end of the seventh switch tube is connected to the control of the fifth switch tube The control end of the eighth switch tube is connected to the output end of the first switch tube, the output end of the eighth switch tube is for receiving a low level signal; one end of the capacitor is for receiving the second clock signal, and the other end of the capacitor is connected Go to the input of the eighth switch.
  • first switch tube to the eighth switch tube are both N-type switch tubes, wherein the control end of each of the first switch tube to the eighth switch tube is the gate of the N-type switch tube, and the first switch tube is The input end of each of the eighth switch tubes is the source of the N-type switch tube, and the output end of each of the first switch tube to the eighth switch tube is the drain of the N-type switch tube.
  • a period of the first clock signal and the second clock signal gradually increases during a touch phase.
  • Another object of the present invention is to provide a touch panel including the above-described gate driver.
  • the invention has the beneficial effects that the invention transmits a signal in the touch phase stage by adding a multi-stage buffering GOA driving circuit, thereby preventing the output signal from being interrupted in the touch phase, thereby reducing the switching device (such as a film) connected to the gate line. The risk of leakage of the transistor).
  • FIG. 1 is a schematic structural view of a touch panel according to an embodiment of the present invention.
  • FIG. 2 is a block diagram of a gate driver in accordance with an embodiment of the present invention.
  • FIG. 3 is a block diagram of a GOA driving circuit in accordance with an embodiment of the present invention.
  • FIG. 4 is a waveform diagram of a clock signal in accordance with an embodiment of the present invention.
  • a capacitive touch screen using In-Cell technology is taken as an example for description.
  • a liquid crystal panel or an organic light emitting diode (OLED) display panel can be exemplified.
  • OLED organic light emitting diode
  • a liquid crystal panel is taken as an example.
  • FIG. 1 is a schematic structural view of a touch panel according to an embodiment of the present invention.
  • a plurality of gate lines arranged transfer gate signals G 1 on the touch panel 100 to a plurality of data lines D G n and data transmission signals 1 to D m.
  • Gate lines G 1 through G n extend in a row direction and are parallel to each other, while the data lines D 1 to D m extend in the column direction and parallel to each other.
  • Each of the pixels PX includes: a switching device connected to a corresponding gate line and a corresponding data line; and a liquid crystal capacitor connected to the switching device.
  • Each pixel PX may also include a storage capacitor, if necessary, wherein the storage capacitor is connected in parallel with the liquid crystal capacitor.
  • the switching device may be a thin film transistor TFT, but the present invention is not limited thereto.
  • the gate driver 200 is connected to the gate lines G 1 to G n .
  • the gate driver 200 is arranged at one side of the touch panel 100, and the gate lines G 1 to G n are connected to the gate driver 200.
  • the invention is not limited thereto. That is, the touch panel 100 can be provided on both sides and the two gate drivers are arranged, and gate lines G 1 to G n are connected to the two gate drivers in each.
  • the touch panel 100 can be provided on both sides and the two gate drivers are arranged, and gate lines G 1 to G n are connected to the two gate drivers in each.
  • a gate driver may be connected to one end of the gate lines G 1 to G n and the other of the gate driver may be connected to the other end of the gate lines G 1 to G n of.
  • the data driver 300 is connected to the data lines D 1 to D m on the touch panel 100, and applies a gray voltage generated by a gray voltage generator (not shown) to the pixel PX as a data voltage. If the gray voltage generator does not supply all of the gray voltages but only the reference gray voltages, the data driver 300 can generate various gray voltages by dividing the reference gray voltages, and select various gray voltages. One of them is used as the data voltage.
  • the difference between the data voltage applied to each of the pixels PX and the common voltage Vcom supplied from the common electrode (not shown) can be interpreted as a voltage with which the liquid crystal capacitor of each pixel PX is charged, that is, the pixel voltage.
  • the arrangement of the liquid crystal molecules in the liquid crystal layer varies depending on the amplitude of the pixel voltage, and thus the polarity of the light transmitted through the liquid crystal layer can also be changed, resulting in a change in the transmittance of the liquid crystal layer.
  • the touch panel 100 adopts display and touch time-sharing scanning: when displaying an image (ie, a display phase), the common electrode provides a common voltage Vcom for the corresponding pixel PX; and the touch scan (ie, touch) In the phase), the common electrode can be used as a drive electrode for generating a drive signal.
  • the gate driver 200 according to an embodiment of the present invention will be described in detail below.
  • 2 is a block diagram of a gate driver in accordance with an embodiment of the present invention.
  • a gate driver 200 includes a multi-level driving unit 210.
  • the nth stage driving unit 210 will be described as an example.
  • the nth stage driving unit 210 includes a GOA driving circuit 211 and a multistage buffering GOA driving circuit 212.
  • the structure of the GOA driving circuit 211 and each level of the buffered GOA driving circuit 212 are the same, but the only difference between the two is that the GOA driving unit 211 outputs an output signal in the display phase, wherein the output signal is on the one hand
  • the pixel of the display area (AA area) of the touch panel is driven as a scan signal, and is transmitted as a level transfer signal to the multi-stage buffer GOA driving unit 212 on the other hand; and the output signal output by each stage of the buffered GOA driving unit 212 is only used as a stage.
  • the pass signal is passed to the next stage buffered GOA drive unit 212.
  • the last stage buffer GOA driving unit 212 delivers the output signal of the output to the GOA driving unit 211 of the next stage driving unit 210.
  • the multi-stage buffering GOA driving circuit 212 maintains the level transfer of the output signal during the touch phase and delivers the output signal to the GOA driving unit 211 of the next stage driving unit 210.
  • the transfer continuity to the output signal is maintained by adding a multi-stage buffered GOA drive circuit 212 to each stage of the drive unit 210.
  • the GOA driver circuit 211 provides an output signal to the gate line; when in the touch phase, the GOA driver circuit 211 is suspended.
  • the output signal is supplied to the gate line, the multi-stage buffering GOA driving circuit 212 maintains the level transmission of the output signal of the GOA driving circuit 211, and the last stage buffering GOA driving circuit 212 transmits the level-outputted output signal to the beginning of the next display phase.
  • the GOA driving circuit 211 of the next stage driving unit 210 when in the display phase, the GOA driver circuit 211 provides an output signal to the gate line; when in the touch phase, the GOA driver circuit 211 is suspended.
  • the output signal is supplied to the gate line, the multi-stage buffering GOA driving circuit 212 maintains the level transmission of the output signal of the GOA driving circuit 211, and the last stage buffering GOA driving circuit 212 transmits the
  • the GOA driving circuit 211 of the nth stage driving unit 210 is selected here for description.
  • the GOA driving circuit 211 receives the low level signal VGL, the high level signal VGH, the output signal of the previous stage (ie, the output signal of the upper stage driving unit 210) Gn-1, the first clock signal CK, and the second clock signal XCK. .
  • the output signal of the upper stage received by the GOA driving circuit 211 of the first stage driving unit 210 is a preset initial signal.
  • each stage of the buffered GOA driving circuit 212 also receives the low level signal VGL, the high level signal VGH, the output signal of the previous stage (ie, the output signal of the GOA driving circuit 211 or the upper level buffered GOA driver).
  • the output signal of circuit 212 the first clock signal CK, and the second clock signal XCK.
  • FIG. 3 is a circuit configuration diagram of a GOA driving circuit according to an embodiment of the present invention.
  • a GOA driving circuit 211 includes a level transfer module 2111, an output module 2112, a pull-down module 2113, and a pull-down maintaining module 2114.
  • the level transfer module 2111 is configured to receive the output signal Gn-1 and the second clock signal XCK of the previous stage, and output the first control signal K1 according to the output signal Gn-1 and the second clock signal XCK of the previous stage.
  • the first control signal K1 is output to the first node Qn, wherein the first node Qn is a point for controlling the output of the drive signal.
  • the output module 2112 is configured to receive the first control signal K1 and the first clock signal CK, and output the output signal Gn according to the first control signal K1 and the first clock signal CK.
  • the first clock signal CK and the second clock signal XCK are reversed.
  • the pull-down module 2113 is configured to receive the first control signal K1 and the low level signal VGL, and pull down the potential of the first node Qn according to the first control signal K1 and the low level signal VGL.
  • the pull-down maintaining module 2114 is configured to receive the high level signal VGH, the low level signal VGL, and the second The clock signal XCK outputs a pull-down control signal C1 according to the high level signal VGH, the low level signal VGL, and the second clock signal XCK, wherein the pull-down control signal C1 is output to the second node Pn, and the second node Pn is used for control The point at which the circuit maintains a stable output during circuit inactivity.
  • the level transfer module 2111 includes a first switch tube T1.
  • the control end of the first switch tube T1 is configured to receive the second clock signal XCK, and the input end of the first switch tube T1 is configured to receive the output signal STn-1 of the previous stage, and the output end of the first switch tube T1 is used for
  • the first control signal K1 is output.
  • the output of the first switching transistor T1 is connected to the first node Qn to output the first control signal K1 to the first node Qn.
  • the output module 2112 includes a second switch tube T2 and a third switch tube T3.
  • the control ends of the second switch tube T2 and the third switch tube T3 are both connected to the first node Qn to receive the first control signal K1 from the first node Qn; the input of the second switch tube T2 and the third switch tube T3
  • the terminals are both configured to receive the first clock signal CK, and the outputs of the second switch transistor T2 and the third switch transistor T3 output an output signal Gn.
  • the output signal Gn outputted by the output end of the second switch tube T2 can be used as a level transmission signal
  • the output signal Gn outputted from the output end of the third switch tube T3 can be used to drive pixels of the display area of the touch panel.
  • the output signals Gn outputted by the output ends of the second switching transistor T2 and the third switching transistor T3 are used as the level-transmitting signals.
  • the pull-down module 2113 includes a fourth switch tube T4 and a fifth switch tube T5.
  • the fourth switch tube T4 and the fifth switch tube T5 are both connected to the second node Pn to receive the pull-down control signal C1 from the second node Pn.
  • the input end of the fourth switch tube T4 is connected to the output end of the third switch tube T3, and the output end of the fourth switch tube T4 is used to receive the low level signal VGL.
  • the input end of the fifth switch T5 is connected to the first node Qn to receive the first control signal K1 from the first node Qn; the output end of the fifth switch T5 is used to receive the low level signal VGL.
  • the pull-down maintaining module 2114 includes a sixth switching transistor T6, a seventh switching transistor T7, an eighth switching transistor T8, and a capacitor C.
  • the control end of the sixth switch T6 is connected to the first node Qn to receive the first control signal K1 from the first node Qn; the input end of the sixth switch T6 is connected to the second node Pn, and the sixth switch T6 The output is used to receive the low level signal VGL.
  • the control end of the seventh switch tube T7 is connected to the input end of the eighth switch tube T8, the input end of the seventh switch tube T7 is for receiving the high level signal VGH, and the output end of the seventh switch tube T7 is connected to the second node Pn. To output a pull-down control signal C1 to the second node Pn.
  • the control end of the eighth switch tube T8 is connected to the first node Qn to be from the first node Qn receives the first control signal K1, and the output of the eighth switch T8 is used to receive the low level signal VGL.
  • One end of the capacitor C is for receiving the second clock signal XCK, and the other end of the capacitor C is connected to the input terminal of the eighth switching transistor T8.
  • the first switch tube T1 to the eighth switch tube T8 are all N-type switch tubes, the control end thereof is the gate of the N-type switch tube, the input end is the source of the N-type switch tube, and the output end is The drain of the N-type switch.
  • FIG. 4 is a waveform diagram of a clock signal in accordance with an embodiment of the present invention.
  • the first clock signal CK and the second clock signal XCK are reversed.
  • the driving of the GOA driving circuit 211 includes four stages:
  • the stage of transmission the second clock signal XCK and the output signal STn-1 of the previous stage are both high, the first switch T1 is turned on, and the high potential signal STn-1 is used as the first control signal K1 to pull the first node Qn high.
  • the control ends of the second switching transistor T2 and the third switching transistor T3 are both at a high potential, so that both the second switching transistor T2 and the third switching transistor T3 are turned on.
  • the control terminals of the eighth switch tube T8 and the sixth switch tube T6 are both at a high potential, so that the eighth switch tube T8 and the sixth switch tube T6 are both turned on.
  • the high-potential second clock signal XCK charges the capacitor C such that the control terminal of the seventh switching transistor T7 is at a low potential, and thus the seventh switching transistor T7 is turned off.
  • the low-potential pull-down control signal C1 is output to the second node Pn, and the control terminals of the fifth switching transistor T5 and the fourth switching transistor T4 are both low, so the fifth switching transistor T5 and the fourth switching transistor T4 are both It is turned off so that the output signal Gn is low.
  • Output phase the first clock signal CK is at a high potential.
  • the first node Qn is maintained at a high potential, and the second switching transistor T2 and the third switching transistor T3 are both turned on, and are outputted by the output terminal of the second switching transistor T2.
  • the output signal Gn is used as a level transmission signal, and the output signal Gn outputted from the output end of the third switching tube T3 drives the pixels of the display area of the touch panel.
  • Pull-down hold phase when the second clock signal XCK is again high, due to capacitor C
  • the other end connected to the input terminal of the eighth switching transistor T8 is open, so that the control terminal of the seventh switching transistor T7 is coupled to a high potential, and the seventh switching transistor T7 is turned on.
  • the high level signal VGH input to the input terminal of the seventh switching transistor T7 is output to the second node Pn as the pull-down control signal C1.
  • the control ends of the fifth switch tube T5 and the fourth switch tube T4 are both high, so the fifth switch tube T5 and the fourth switch tube T4 are both turned on, so that the first node Qn and the second node Pn are respectively kept low. Potential and high potential.
  • each stage of buffered GOA driver circuit 212 maintains the leveling of the output signal using the four stages of driving described above. It should be noted that, in the above output stage, the output signals Gn outputted by the output ends of the second switching transistor T2 and the third switching transistor T3 are used as the level transmission signals.
  • the buffered GOA driving circuit 212 when in the touch phase, the periods of the first clock signal CK and the second clock signal XCK gradually increase, and the first The clock signal CK and the second clock signal XCK are still inverted.
  • the space occupied by the buffered GOA driver circuit 212 can be reduced.

Abstract

一种栅极驱动器，其包括多级驱动单元（210），每一级驱动单元（210）包括：GOA驱动电路（211）和多级缓冲GOA驱动电路（212）；GOA驱动电路（211）在显示阶段用于输出输出信号，其中，输出信号被传递至栅极线且被传递至多级缓冲GOA驱动电路（212）；多级缓冲GOA驱动电路（212）在触控阶段对输出信号进行级传，并将输出信号传递至下一级驱动单元（210）的GOA驱动电路（211）。还提供了一种具有该栅极驱动器的触控面板。通过增加多级缓冲GOA驱动电路在触控阶段级传输出信号，从而避免输出信号在触控阶段被中断，进而降低了与栅极线连接的开关器件（例如薄膜晶体管）的漏电风险。

Description

栅极驱动器及具有该栅极驱动器的触控面板 技术领域
本发明属于显示技术领域，具体地讲，涉及一种栅极驱动器及具有该栅极驱动器的触控面板。
背景技术
目前，较为常见的电容式触控屏通常采用OGS(One Glass Solution，即一体化触控)、On-Cell(外挂式)和In-Cell(内嵌式)三种技术。其中，采用In-Cell技术的电容式触摸屏由于其制作工艺上的优势，相比采用OGS技术和On-Cell技术的电容式触摸屏，具有更加轻薄、透光性更好、结构更加稳定等优点。
在采用In-Cell技术的电容式触控屏中，一般采用液晶面板或OLED显示面板作为显示屏。以液晶面板为例，通常采用阵列基板栅极驱动(Gate Driver On Array，GOA)技术将栅极驱动器制作在阵列基板上，从而实现对栅极线逐行扫描驱动。
在现有的一种采用In-Cell技术的高刷新频率(例如120Hz)的电容式触控屏中，沿着从上到下的顺序将液晶面板上的所有像素单元分为若干像素块。所述触控屏在显示扫描阶段利用GOA电路对相应的像素块进行驱动完毕后进入触控扫描阶段，这样可提高触控的灵敏度，但是会增加GOA电路失效的风险。这是因为在触控扫描阶段，GOA电路会暂停对栅极线进行扫描驱动，从而增加与栅极线连接的薄膜晶体管的栅极漏电的风险。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种栅极驱动器，包括多级驱动单元，其中，每一级驱动单元包括：GOA驱动电路和多级缓冲GOA驱动电路；所述GOA驱动电路在显示阶段用于输出输出信号，其中，输出信号被传递至栅极线且被传递至所述多级缓冲GOA驱动电路；所述多级缓冲GOA驱动电路在触控阶段对输出信号进行级传，并将输出信号传递 至下一级驱动单元的GOA驱动电路。
进一步地，所述GOA驱动电路和每一级缓冲GOA驱动电路具有相同的电路结构。
进一步地，所述GOA驱动电路包括：级传模块，用于接收上一级的输出信号以及第二时钟信号，并根据上一级的输出信号及第二时钟信号输出第一控制信号；其中，第一级GOA驱动电路的级传模块接收的是预设的初始信号以及第二时钟信号；输出模块，用于接收第一控制信号和第一时钟信号，并根据第一控制信号和第一时钟信号输出输出信号，其中，第一时钟信号和第二时钟信号反向；下拉模块，用于接收第一控制信号和低电平信号，并根据第一控制信号和低电平信号使输出模块停止输出；下拉维持模块，用于接收高电平信号、低电平信号和第二时钟信号，并根据高电平信号、低电平信号和第二时钟信号输出下拉控制信号，其中，下拉控制信号使下拉模块保持输出模块停止输出。
进一步地，所述级传模块包括：第一开关管；其中，第一开关管的控制端用于接收第二时钟信号，第一开关管的输入端用于接收上一级的输出信号，第一开关管的输出端用于输出第一控制信号。
进一步地，所述输出模块包括：第二开关管和第三开关管；其中，第二开关管控制端连接到第一开关管的输出端，第二开关管的输入端都用于接收第一时钟信号，第二开关管的输出端用于输出输出信号；第三开关管控制端连接到第一开关管的输出端，第三开关管的输入端都用于接收第一时钟信号，第三开关管的输出端用于输出输出信号。
进一步地，所述下拉模块包括：第四开关管和第五开关管；其中，第四开关管的控制端用于接收下拉控制信号，第四开关管的输入端连接到第三开关管的输出端，第四开关管的输出端用于接收低电平信号；第五开关管的控制端用于接收下拉控制信号，第五开关管的输入端连接到第一开关管的输出端，第五开关管的输出端用于接收低电平信号。
进一步地，所述下拉维持模块包括：第六开关管、第七开关管、第八开关管和电容器；其中，第六开关管的控制端连接到第一开关管的输出端，第六开关管的输入端连接到第五开关管的控制端，第六开关管的输出端用于接收低电 平信号；第七开关管的控制端连接到第八开关管的输入端，第七开关管的输入端用于接收高电平信号，第七开关管的输出端连接到第五开关管的控制端；第八开关管的控制端连接到第一开关管的输出端，第八开关管的输出端用于接收低电平信号；电容器的一端用于接收第二时钟信号，电容器的另一端连接到第八开关管的输入端。
进一步地，第一开关管至第八开关管均为N型开关管，其中，第一开关管至第八开关管中每一个的控制端为N型开关管的栅极，第一开关管至第八开关管中每一个的输入端为N型开关管的源极，第一开关管至第八开关管中每一个的输出端为N型开关管的漏极。
进一步地，所述第一时钟信号和所述第二时钟信号在触控阶段时的周期逐渐增大。
本发明的另一目的还在于提供一种触控面板，其包括上述的栅极驱动器。
本发明的有益效果：本发明通过增加多级缓冲GOA驱动电路在触控阶段级传输出信号，从而避免输出信号在触控阶段被中断，进而降低了与栅极线连接的开关器件(例如薄膜晶体管)的漏电风险。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的触控面板的结构示意图；
图2是根据本发明的实施例的栅极驱动器的模块图；
图3是根据本发明的实施例的GOA驱动电路的模块图；
图4是根据本发明的实施例的时钟信号的波形图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施 例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。相同的标号在附图中始终表示相同的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
需要说明的是，在本实施例中，采用In-Cell技术的电容式触控屏为例进行说明。而在采用的In-Cell技术的电容式触控屏中，可以以液晶面板或有机发光二极管(OLED)显示面板作为示例。在本实施例中，以液晶面板作为示例。
图1是根据本发明的实施例的触控面板的结构示意图。
参照图1，触控面板100上布置传送栅极信号的多条栅极线G1至Gn和传送数据信号的多条数据线D1至Dm。栅极线G1至Gn按行方向延伸并且彼此平行，而数据线D1至Dm按列方向延伸并且彼此平行。
每个像素PX包括：开关器件，连接到相应的栅极线和相应的数据线；以及液晶电容器，连接到该开关器件。如果必要，每个像素PX也可以包括存储电容器，其中，该存储电容器与液晶电容器并联连接。在本实施例中，开关器件可为薄膜晶体管TFT，但本发明并不限制于此。
栅极驱动器200连接到栅极线G1至Gn。继续参照图1，在触控面板100的一侧布置栅极驱动器200，并且栅极线G1至Gn都连接到该栅极驱动器200。然而，本发明不限于此。也就是说，可以在触控面板100的两侧提供和布置两个栅极驱动器，并且栅极线G1至Gn都连接到两个栅极驱动器的每一个。例如，在大尺寸触控面板的情况下，很难仅通过使用一个栅极驱动器就将栅极信号从栅极线G1至Gn的一端传送到另一端。为了解决这个问题，可以提供两个栅极驱动器。一个栅极驱动器可以连接到栅极线G1至Gn的一端，而另一个栅极驱动器可以连接到栅极线G1至Gn的另一端。
数据驱动器300连接到触控面板100上的数据线D1至Dm，并向像素PX 施加由灰度电压产生器(未示出)产生的灰度电压作为数据电压。如果灰度电压产生器不是提供所有的灰度电压而是仅提供基准灰度电压，则数据驱动器300可以通过将基准灰度电压分压而产生各种灰度电压，并选择各种灰度电压中的一个作为数据电压。施加到每个像素PX的数据电压和由公共电极(未示出)提供的公共电压Vcom之间的差可以被解释为是利用其对每个像素PX的液晶电容器充电的电压，即像素电压。液晶层内的液晶分子的排列根据像素电压的幅度而变化，因而通过液晶层传送的光的极性也可以变化，从而导致液晶层的透射率的变化。
根据本发明的实施例的触控面板100采用显示与触控分时扫描：在显示图像(即显示阶段)时，公共电极为相应的像素PX提供公共电压Vcom；在触控扫描(即触控阶段)时，公共电极可作为驱动电极使用，用于产生驱动信号。
以下将对根据本发明的实施例的栅极驱动器200进行详细说明。图2是根据本发明的实施例的栅极驱动器的模块图。
参照图2，根据本发明的实施例的栅极驱动器200包括多级驱动单元210。在本实施例中，由于每一级驱动单元210的结构都相同，因此以下将以其中第n级驱动单元210为例进行介绍。
第n级驱动单元210包括：GOA驱动电路211和多级缓冲GOA驱动电路212。在本实施例中，GOA驱动电路211和每一级缓冲GOA驱动电路212的结构都相同，但是两者仅有的区别在于：GOA驱动单元211在显示阶段输出输出信号，其中，输出信号一方面作为扫描信号驱动触控面板的显示区(AA区)的像素，另一方面作为级传信号传递到多级缓冲GOA驱动单元212；而每一级缓冲GOA驱动单元212输出的输出信号仅作为级传信号被传递到下一级缓冲GOA驱动单元212。这里，最后一级缓冲GOA驱动单元212将输出的输出信号传递到下一级驱动单元210的GOA驱动单元211。这样，多级缓冲GOA驱动电路212在触控阶段保持对输出信号的级传，并把输出信号传递至下一级驱动单元210的GOA驱动单元211。
在本实施例中，通过在每一级驱动单元210中增加多级缓冲GOA驱动电路212来保持对输出信号的传递延续性。例如，当在显示阶段时，GOA驱动电路211向栅极线提供输出信号；当在触控阶段时，GOA驱动电路211暂停 向栅极线提供输出信号，多级缓冲GOA驱动电路212对GOA驱动电路211的输出信号保持级传，并且最后一级缓冲GOA驱动电路212将级传的输出信号在下一次显示阶段开始时传递给下一级驱动单元210的GOA驱动电路211。
由于GOA驱动电路211和每一级缓冲GOA驱动电路212的结构都相同，因此这里选取第n级驱动单元210的GOA驱动电路211进行描述介绍。
GOA驱动电路211接收低电平信号VGL、高电平信号VGH、上一级的输出信号(即上一级驱动单元210的输出信号)Gn-1、第一时钟信号CK以及第二时钟信号XCK。其中，第一级驱动单元210的GOA驱动电路211接收的上一级的输出信号为预设的初始信号。
应当理解的是，每一级缓冲GOA驱动电路212也都接收低电平信号VGL、高电平信号VGH、上一级的输出信号(即GOA驱动电路211的输出信号或者上一级缓冲GOA驱动电路212的输出信号)、第一时钟信号CK以及第二时钟信号XCK。
图3是根据本发明的实施例的GOA驱动电路的电路结构图。
参照图3，根据本发明的实施例的GOA驱动电路211包括：级传模块2111、输出模块2112、下拉模块2113以及下拉维持模块2114。
级传模块2111用于接收上一级的输出信号Gn-1以及第二时钟信号XCK，并根据上一级的输出信号Gn-1及第二时钟信号XCK输出第一控制信号K1。第一控制信号K1输出到第一节点Qn，其中，第一节点Qn为用于控制驱动信号输出的点。
输出模块2112用于接收第一控制信号K1和第一时钟信号CK，并根据第一控制信号K1和第一时钟信号CK输出输出信号Gn。其中，第一时钟信号CK和第二时钟信号XCK反向。
下拉模块2113用于接收第一控制信号K1和低电平信号VGL，并根据第一控制信号K1和低电平信号VGL拉低第一节点Qn的电位。
下拉维持模块2114用于接收高电平信号VGH、低电平信号VGL和第二 时钟信号XCK，并根据高电平信号VGH、低电平信号VGL和第二时钟信号XCK输出下拉控制信号C1，其中，下拉控制信号C1输出到第二节点Pn，第二节点Pn为用于控制在电路非作用期间保持电路稳定输出的点。
可选地，级传模块2111包括第一开关管T1。其中，第一开关管T1的控制端用于接收第二时钟信号XCK，第一开关管T1的输入端用于接收上一级的输出信号STn-1，第一开关管T1的输出端用于输出第一控制信号K1。具体地，第一开关管T1的输出端连接到第一节点Qn，以将第一控制信号K1输出到第一节点Qn。
输出模块2112包括第二开关管T2和第三开关管T3。其中，第二开关管T2和第三开关管T3的控制端均连接到第一节点Qn，以从第一节点Qn接收第一控制信号K1；第二开关管T2和第三开关管T3的输入端都用于接收第一时钟信号CK，第二开关管T2和第三开关管T3的输出端均输出输出信号Gn。其中，第二开关管T2的输出端输出的输出信号Gn可作为级传信号，第三开关管T3的输出端输出的输出信号Gn可用于驱动触控面板的显示区的像素。这里，应当说明的是，针对缓冲GOA驱动电路212而言，第二开关管T2和第三开关管T3的输出端输出的输出信号Gn都作为级传信号。
下拉模块2113包括第四开关管T4和第五开关管T5。其中，第四开关管T4和第五开关管T5都连接到第二节点Pn，以从第二节点Pn接收下拉控制信号C1。第四开关管T4的输入端连接到第三开关管T3的输出端，第四开关管T4的输出端用于接收低电平信号VGL。第五开关管T5的输入端连接到第一节点Qn，以从第一节点Qn接收第一控制信号K1；第五开关管T5的输出端用于接收低电平信号VGL。
下拉维持模块2114包括第六开关管T6、第七开关管T7、第八开关管T8和电容器C。其中，第六开关管T6的控制端连接到第一节点Qn，以从第一节点Qn接收第一控制信号K1；第六开关管T6的输入端连接到第二节点Pn，第六开关管T6的输出端用于接收低电平信号VGL。第七开关管T7的控制端连接到第八开关管T8的输入端，第七开关管T7的输入端用于接收高电平信号VGH，第七开关管T7的输出端连接到第二节点Pn，以向第二节点Pn输出下拉控制信号C1。第八开关管T8的控制端连接到第一节点Qn，以从第一节点 Qn接收第一控制信号K1，第八开关管T8的输出端用于接收低电平信号VGL。电容器C的一端用于接收第二时钟信号XCK，电容器C的另一端连接到第八开关管T8的输入端。
在本实施例中，第一开关管T1至第八开关管T8均为N型开关管，其控制端为N型开关管的栅极，输入端为N型开关管的源极，输出端为N型开关管的漏极。
图4是根据本发明的实施例的时钟信号的波形图。其中，第一时钟信号CK和第二时钟信号XCK反向。
参照图3和图4，在显示阶段时，GOA驱动电路211的驱动包括四个阶段：
级传阶段：第二时钟信号XCK和上一级的输出信号STn-1都为高电位，第一开关管T1打开，高电位信号STn-1作为第一控制信号K1将第一节点Qn拉高到高电位。第二开关管T2和第三开关管T3的控制端都为高电位，因此第二开关管T2和第三开关管T3均被打开。第八开关管T8和第六开关管T6的控制端都为高电位，因此第八开关管T8和第六开关管T6都被打开。此时，高电位的第二时钟信号XCK对电容器C进行充电，使第七开关管T7的控制端为低电位，因此第七开关管T7被关闭。此时，低电位的下拉控制信号C1被输出到第二节点Pn，第五开关管T5和第四开关管T4的控制端都为低电位，因此第五开关管T5和第四开关管T4都被关闭，使得输出信号Gn为低电位。
输出阶段：第一时钟信号CK为高电位，此时，第一节点Qn被保持为高电位，第二开关管T2和第三开关管T3均被打开，由第二开关管T2的输出端输出的输出信号Gn作为级传信号，而由第三开关管T3的输出端输出的输出信号Gn驱动触控面板的显示区的像素。
下拉阶段：第二时钟信号XCK再次为高电位时，第一开关管T1再次被打开，此时低电位的第一控制信号K1将第一节点Qn拉低到低电位。此时，第二开关管T2和第三开关管T3的控制端都为低电位，因此第二开关管T2和第三开关管T3均被关闭。这时，第二开关管T2和第三开关管T3的输出端的输出被截止。
下拉保持阶段：而当第二时钟信号XCK再次为高电位时，由于电容器C 与第八开关管T8的输入端连接的另一端为断路，因此第七开关管T7的控制端被耦合为高电位，第七开关管T7被打开。第七开关管T7的输入端输入的高电平信号VGH作为下拉控制信号C1被输出到第二节点Pn。第五开关管T5和第四开关管T4的控制端都为高电位，因此第五开关管T5和第四开关管T4都被打开，从而使第一节点Qn和第二节点Pn分别保持在低电位和高电位。
在触控阶段时，每一级缓冲GOA驱动电路212利用上述的四个阶段的驱动保持对输出信号的级传。应当说明的是，在上述的输出阶段，第二开关管T2和第三开关管T3的输出端输出的输出信号Gn都作为级传信号。
此外，为了减少缓冲GOA驱动电路212的级数(即数量)，在本实施例中，当在触控阶段时，第一时钟信号CK和第二时钟信号XCK的周期逐渐增大，并且第一时钟信号CK和第二时钟信号XCK仍然反向。这样，在延续缓冲GOA驱动电路212级传信号能力的同时，可以减少缓冲GOA驱动电路212所占的空间。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (10)

  1. 一种栅极驱动器，包括多级驱动单元，其中，每一级驱动单元包括：GOA驱动电路和多级缓冲GOA驱动电路；
    所述GOA驱动电路在显示阶段用于输出输出信号，其中，输出信号被传递至栅极线且被传递至所述多级缓冲GOA驱动电路；
    所述多级缓冲GOA驱动电路在触控阶段对输出信号进行级传，并将输出信号传递至下一级驱动单元的GOA驱动电路。
  2. 根据权利要求1所述的栅极驱动器，其中，所述GOA驱动电路和每一级缓冲GOA驱动电路具有相同的电路结构。
  3. 根据权利要求2所述的栅极驱动器，其中，所述GOA驱动电路包括：
    级传模块，用于接收上一级的输出信号以及第二时钟信号，并根据上一级的输出信号及第二时钟信号输出第一控制信号；其中，第一级GOA驱动电路的级传模块接收的是预设的初始信号以及第二时钟信号；
    输出模块，用于接收第一控制信号和第一时钟信号，并根据第一控制信号和第一时钟信号输出输出信号，其中，第一时钟信号和第二时钟信号反向；
    下拉模块，用于接收第一控制信号和低电平信号，并根据第一控制信号和低电平信号使输出模块停止输出；
    下拉维持模块，用于接收高电平信号、低电平信号和第二时钟信号，并根据高电平信号、低电平信号和第二时钟信号输出下拉控制信号，其中，下拉控制信号使下拉模块保持输出模块停止输出。
  4. 根据权利要求3所述的栅极驱动器，其中，所述级传模块包括：第一开关管；
    其中，第一开关管的控制端用于接收第二时钟信号，第一开关管的输入端用于接收上一级的输出信号，第一开关管的输出端用于输出第一控制信号。
  5. 根据权利要求4所述的栅极驱动器，其中，所述输出模块包括：第二开关管和第三开关管；
    其中，第二开关管控制端连接到第一开关管的输出端，第二开关管的输入端都用于接收第一时钟信号，第二开关管的输出端用于输出输出信号；
    第三开关管控制端连接到第一开关管的输出端，第三开关管的输入端都用于接收第一时钟信号，第三开关管的输出端用于输出输出信号。
  6. 根据权利要求5所述的栅极驱动器，其中，所述下拉模块包括：第四开关管和第五开关管；
    其中，第四开关管的控制端用于接收下拉控制信号，第四开关管的输入端连接到第三开关管的输出端，第四开关管的输出端用于接收低电平信号；
    第五开关管的控制端用于接收下拉控制信号，第五开关管的输入端连接到第一开关管的输出端，第五开关管的输出端用于接收低电平信号。
  7. 根据权利要求6所述的栅极驱动器，其中，所述下拉维持模块包括：第六开关管、第七开关管、第八开关管和电容器；
    其中，第六开关管的控制端连接到第一开关管的输出端，第六开关管的输入端连接到第五开关管的控制端，第六开关管的输出端用于接收低电平信号；
    第七开关管的控制端连接到第八开关管的输入端，第七开关管的输入端用于接收高电平信号，第七开关管的输出端连接到第五开关管的控制端；
    第八开关管的控制端连接到第一开关管的输出端，第八开关管的输出端用于接收低电平信号；
    电容器的一端用于接收第二时钟信号，电容器的另一端连接到第八开关管的输入端。
  8. 根据权利要求7所述的栅极驱动器，其中，第一开关管至第八开关管均为N型开关管，其中，第一开关管至第八开关管中每一个的控制端为N型开关管的栅极，第一开关管至第八开关管中每一个的输入端为N型开关管的源 极，第一开关管至第八开关管中每一个的输出端为N型开关管的漏极。
  9. 根据权利要求3所述的栅极驱动器，其中，所述第一时钟信号和所述第二时钟信号在触控阶段时的周期逐渐增大。
  10. 一种触控面板，包括栅极驱动器，其中，所述栅极驱动器包括多级驱动单元，每一级驱动单元包括：GOA驱动电路和多级缓冲GOA驱动电路；
    所述GOA驱动电路在显示阶段用于输出输出信号，其中，输出信号被传递至栅极线且被传递至所述多级缓冲GOA驱动电路；
    所述多级缓冲GOA驱动电路在触控阶段对输出信号进行级传，并将输出信号传递至下一级驱动单元的GOA驱动电路。
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