WO2017166409A1 - 扫描驱动电路及具有该扫描驱动电路的显示装置 - Google Patents

扫描驱动电路及具有该扫描驱动电路的显示装置 Download PDF

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Publication number
WO2017166409A1
WO2017166409A1 PCT/CN2016/083322 CN2016083322W WO2017166409A1 WO 2017166409 A1 WO2017166409 A1 WO 2017166409A1 CN 2016083322 W CN2016083322 W CN 2016083322W WO 2017166409 A1 WO2017166409 A1 WO 2017166409A1
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Prior art keywords
switch tube
scan driving
scan
driving circuit
scanning
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PCT/CN2016/083322
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English (en)
French (fr)
Inventor
黄笑宇
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/119,698 priority Critical patent/US10062348B2/en
Publication of WO2017166409A1 publication Critical patent/WO2017166409A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a scan driving circuit and a display device having the same.
  • LCDs liquid crystal displays
  • the scan driving circuit is used to provide scanning signals to a plurality of scanning lines in a certain scanning direction.
  • different customers and different applications require the scan driving circuit to achieve different scanning directions. Therefore, how to make the scanning driving circuit realize different scanning directions is a technical problem that needs to be solved.
  • an object of the present invention is to provide a scan driving circuit including: cascaded N scan driving units, at least one first switching tube, at least one second switching tube, and at least one a third switch tube; wherein the first switch tube, the second switch tube, and the third switch tube each include a control end, an input end, and an output end; the first switch tube and the second switch And a control end of the third switch tube is connected to the first node, the first node receives a first high level signal or a first low level signal; the first switch tube and the second switch The input end of the tube is configured to receive a scan start signal, the output end of the first switch tube is connected to the first scan drive unit, and the output end of the second switch tube is connected to the Nth scan drive unit; The input end of the three switch tube is configured to receive a second high level signal, the output end of the third switch tube is connected to the second node and electrically grounded, and the N scan drive units are all connected to the second node .
  • the output end of the third switch tube is electrically grounded through a resistor.
  • first switch tube and the third switch tube are NMOS transistors
  • second switch tube is a PMOS transistor
  • the first node receives the first high level signal.
  • the first node receives the first low level signal.
  • first switch tube and the third switch tube are PMOS transistors
  • second switch tube is an NMOS transistor
  • the first node receives the first low level signal.
  • the first node receives the first high level signal.
  • the scan driving unit is a scan driving chip packaged on the film.
  • Another object of the present invention is to provide a display device including the above-described scan driving circuit.
  • the invention has the beneficial effects that the invention realizes the function of the forward and reverse bidirectional scanning by controlling the level of the level signal received by the first node, and only needs the signal controller to output a scan start signal, and does not need the printed circuit board.
  • the resistor is set on the scanning direction of the scan driving unit, thereby reducing the cost.
  • FIG. 1 shows a block diagram of a liquid crystal display according to an embodiment of the present invention
  • FIG. 2 shows a circuit configuration diagram of a scan driving circuit according to an embodiment of the present invention.
  • FIG. 1 shows a block diagram of a liquid crystal display according to an embodiment of the present invention.
  • a liquid crystal display includes: a liquid crystal panel assembly 300; a scan driving circuit 400 and a source driving circuit 500, both of which are connected to the liquid crystal panel assembly 300; a gray voltage generator 800, connected to The source driving circuit 500; and the signal controller 600 for controlling the liquid crystal panel assembly 300, the scan driving circuit 400, the source driving circuit 500, and the gray voltage generator 800.
  • the liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in an array.
  • the liquid crystal panel assembly 300 may include a lower display panel (not shown) and an upper display panel (not shown) facing each other, and a liquid crystal layer (not shown) interposed between the lower display panel and the upper display panel.
  • a display signal line can be arranged on the lower display panel.
  • the display signal line may include a plurality of gate lines G1 to Gn that transmit gate signals and a plurality of data lines D1 to Dm that transmit data signals.
  • the gate lines G1 to Gn extend in the row direction and are substantially parallel to each other, and the data lines D1 to Dm extend in the column direction and are substantially parallel to each other.
  • Each of the pixels PX includes: a switching device connected to a corresponding gate line and a corresponding data line; and a liquid crystal capacitor connected to the switching device.
  • Each pixel PX can also include storage if necessary A capacitor connected in parallel with the liquid crystal capacitor.
  • the switching device of each pixel PX is a three-terminal device, thus having a control terminal connected to the corresponding gate line, an input terminal connected to the corresponding data line, and an output terminal connected to the corresponding liquid crystal capacitor.
  • the scan driving circuit 400 is connected to the gate lines G1 to Gn, and applies a gate signal to the gate lines G1 to Gn, which is a high-level gate signal applied to the scan driving circuit 400 by an external source (hereinafter referred to as This is a combination of the gate-on voltage Von) and the low-level gate signal (hereinafter referred to as the gate-off voltage Voff).
  • a scan driving circuit 400 is disposed on one side of a liquid crystal panel assembly 300, and gate lines G1 to Gn are both connected to these scan driving circuits 400.
  • the invention is not limited thereto. That is, one scan driving circuit may be respectively disposed on opposite sides of the liquid crystal panel assembly 300, and the gate lines G1 to Gn are both connected to each of the two scan driving circuits.
  • the gray voltage generator 800 generates a gray voltage that is closely related to the transmittance of the pixel PX. This gray voltage is supplied to each pixel PX and has a positive value or a negative value according to the common voltage Vcom.
  • the source driving circuit 500 is connected to the data lines D1 to Dm of the liquid crystal panel assembly 300, and applies the gradation voltage generated by the gradation voltage generator 800 to the pixel PX as a data voltage. If the gray voltage generator 800 does not supply all of the gray voltages but only the reference gray voltages, the source driving circuit 500 can generate various gray voltages by dividing the reference gray voltages, and select various One of the gray voltages is used as the data voltage.
  • the source driving circuit 500 may be composed of a source chip-on-Film (S-COF) packaged on a plurality of diaphragms, but the invention is not limited thereto.
  • the signal controller 600 controls the operations of the scan driving circuit 400 and the source driving circuit 500.
  • the signal controller 600 is formed on a printed circuit board (not shown), wherein the printed circuit board is electrically connected to the source driving circuit 500.
  • the signal controller 600 receives input image signals (R, G, and B) and a plurality of input control signals for controlling display of the input image signals, such as a vertical sync signal Vsync, a horizontal sync signal, from an external graphics controller (not shown). Hsync, main clock signal MCLK, data enable signal DE.
  • the signal controller 600 appropriately processes the input image signals (R, G, and B) in accordance with the input control signals, thereby generating image data DAT that conforms to the operating conditions of the liquid crystal panel assembly 300.
  • the signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 to turn the gate control signal
  • the CONT 1 is transferred to the scan driving circuit 400, and the data control signal CONT2 and the image data DAT are transferred to the source driving circuit 500.
  • the gate control signal CONT1 may include a scan start signal STV for starting an operation of the scan driving circuit 400, that is, a scan operation, and at least one clock signal for controlling when the gate-on voltage Von is output.
  • the gate control signal CONT1 may also include an output enable signal OE for limiting the duration of the gate-on voltage Von.
  • the clock signal can be used as the selection signal SE.
  • the data control signal CONT2 may include a horizontal synchronization start signal STH indicating transmission of the image data DAT, a load signal LOAD requesting application of a data voltage corresponding to the image data DAT to the data lines D1 to Dm, and a data clock signal HCLK.
  • the data control signal CONT2 may also include an inversion signal RVS for inverting the polarity of the data voltage with respect to the common voltage Vcom, which is hereinafter referred to as "polarity of the data voltage.”
  • the source driving circuit 500 receives the image data DAT from the signal controller 600 in response to the data control signal CONT2, and selects a gray voltage corresponding to the image data DAT from among a plurality of gray voltages supplied from the gray voltage generator 800. The image data is converted to a data voltage. Then, the source driving circuit 500 applies a data voltage to the data lines D1 to Dm.
  • the scan driving circuit 400 turns on the switching devices connected to the gate lines G1 to Gn by applying the gate-on voltage Von to the gate lines G1 to Gn in response to the gate control signal CONT1. Then, the data voltages applied to the data lines D1 to Dm are transmitted to each of the pixels PX through the turned-on switching devices.
  • the difference between the data voltage applied to each pixel PX and the common voltage Vcom can be interpreted as a voltage with which the liquid crystal capacitor of each pixel PX is charged, that is, a pixel voltage.
  • the arrangement of the liquid crystal molecules in the liquid crystal layer varies depending on the amplitude of the pixel voltage, and thus the polarity of the light transmitted through the liquid crystal layer can also be changed, resulting in a change in the transmittance of the liquid crystal layer.
  • FIG. 2 shows a circuit configuration diagram of a scan driving circuit according to an embodiment of the present invention.
  • a scan driving circuit 400 includes: cascaded N scan driving units 4101, 4102, 4103, . . . 410N, a first switching transistor 420, a second switching transistor 430, and a third switch. Tube 440 and resistor 450.
  • the first switch tube 420, the second switch tube 430, and the third switch tube 440 are not limited to the number shown in FIG. 2.
  • the first switch tube 420, the second switch tube 430, and the third switch tube 440 are all three-terminal devices, and thus have a control terminal, an input terminal, and an output terminal.
  • the control ends of the first switch tube 420, the second switch tube 430 and the third switch tube 440 are both connected to the first node A; wherein the first node A is according to the first switch tube 420, the second switch tube 430 and the third switch
  • the type of tube 440 receives a first high level signal or a first low level signal, as will be explained below.
  • the input ends of the first switch tube 420 and the second switch tube 430 are for receiving the scan start signal STV, the output end of the first switch tube 420 is connected to the first scan drive unit 4101, and the output end of the second switch tube 430 is connected to The Nth scan driving unit 410N.
  • the input end of the third switch 440 is for receiving the second high level signal VDD (such as but not limited to 3.3V), the output end of the third switch tube 440 is connected to the second node B and electrically grounded, and N scan drives Units 4101, 4102, 4103, ... 410N are each connected to a second node B.
  • VDD high level signal
  • N scan drives Units 4101, 4102, 4103, ... 410N are each connected to a second node B.
  • the output end of the third switch tube 440 is connected to one end of the resistor 450, and the other end of the resistor 450 is electrically grounded; that is, the output end of the third switch tube 440 passes through the resistor 450. Electrical grounding.
  • the first switching transistor 420 and the third switching transistor 440 are NMOS transistors, and the second switching transistor 430 is a PMOS transistor.
  • the first node A receives the first high level signal
  • the first switch tube 420 and the third switch tube 440 are turned on, and the second switch tube 430 is turned off, so that the input end of the first switch tube 420 receives the scan start signal.
  • the second node B is the second high level signal VDD, so that the scan direction setting signals of the respective scan driving units 4101, 4102, 4103, ... 410N are the second high level signal VDD, and the scan driving circuit is at this time
  • the drive scan is performed in the order from the first scan driving unit 4101 to the Nth scan driving unit 410N.
  • the first node A When the first node A receives the first low level signal, the first switch tube 420 and the third switch tube 440 are turned off, and the second switch tube 430 is turned on, so that the input end of the second switch tube 430 receives the scan start signal STV,
  • the second node B is electrically grounded such that the scan direction setting signals of the respective scan driving units 4101, 4102, 4103, ... 410N are the second low level signals, and at this time, the scan driving circuit 400 is driven from the Nth scan.
  • the drive scanning is performed in the order of the unit 410N to the first scan driving unit 4101.
  • the first switching transistor 420 and the third switching transistor 440 are PMOS transistors, and the second switching transistor 430 is an NMOS transistor.
  • the first node A receives the first high level signal
  • the first switch tube 420 and the third switch tube 440 are turned off, and the second switch tube 430 is turned on, so that the input end of the second switch tube 430 receives the scan start signal.
  • the second node B is electrically grounded, so that the scanning direction setting signals of the respective scanning driving units 4101, 4102, 4103, ..., 410N are the second low level signals, and at this time, the scanning driving circuit 400 is driven from the Nth The scan scan unit 410N to the first scan drive unit 4101 sequentially performs drive scanning.
  • the second node B is the second high level signal VDD, so that the scan direction setting signals of the respective scan driving units 4101, 4102, 4103, ..., 410N are the second high level signal VDD, and the scan driving circuit 400 is The drive scan is performed in the order from the first scan driving unit 4101 to the Nth scan driving unit 410N.
  • the scan driving circuit realizes the function of forward and reverse bidirectional scanning, and only needs the signal controller to output a scan start signal, and does not need to scan on the printed circuit board.
  • the driving direction of the drive unit sets the resistance, thereby reducing the cost.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

提供了一种显示装置及其扫描驱动电路（400）。扫描驱动电路（400）包括：级联的且均连接至第二节点（B）的N个扫描驱动单元（4101、4102、……、410N）、第一开关管（420）、第二开关管（430）、第三开关管（440）；第一开关管（420）、第二开关管（430）和第三开关管（440）的控制端均连接至第一节点（A）；第一开关管（420）和第二开关管（430）的输入端用于接收扫描开始信号（STV），第一开关管（420）的输出端连接至第一个扫描驱动单元（4101），第二开关管（430）的输出端连接至第N个扫描驱动单元（410N）；第三开关管（440）的输入端用于接收第二高电平信号（VDD），第三开关管（440）的输出端连接至第二节点（B）并电性接地。通过控制第一节点（A）接收的电平信号的高低，使扫描驱动电路（400）实现正反双向扫描的功能。

Description

扫描驱动电路及具有该扫描驱动电路的显示装置 技术领域
本发明属于显示技术领域，具体地讲，涉及一种扫描驱动电路及具有该扫描驱动电路的显示装置。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，简称LCD)因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已被应用于生产生活的各个方面。
目前，在现有的液晶显示器中，均采用扫描驱动电路按照一定的扫描方向向多条扫描线提供扫描信号。然而，在实际应用过程中，不同客户及不同应用场合要求扫描驱动电路能够实现不同的扫描方向，因此如何使扫描驱动电路实现不同的扫描方向是亟需解决的一个技术问题。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种扫描驱动电路，其包括：级联的N个扫描驱动单元、至少一个第一开关管、至少一个第二开关管和至少一个第三开关管；其中，所述第一开关管、所述第二开关管和所述第三开关管均包括控制端、输入端和输出端；所述第一开关管、所述第二开关管和所述第三开关管的控制端均连接至第一节点，所述第一节点接收第一高电平信号或第一低电平信号；所述第一开关管和所述第二开关管的输入端用于接收扫描开始信号，所述第一开关管的输出端连接至第一个扫描驱动单元，所述第二开关管的输出端连接至第N个扫描驱动单元；所述第三开关管的输入端用于接收第二高电平信号，所述第三开关管的输出端连接至第二节点并电性接地，所述N个扫描驱动单元均连接至所述第二节点。
进一步地，所述第三开关管的输出端通过一电阻器电性接地。
进一步地，所述第一开关管和所述第三开关管为NMOS晶体管，所述第二开关管为PMOS晶体管。
进一步地，当所述扫描驱动电路以从第一个扫描驱动单元至第N个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一高电平信号。
进一步地，当所述扫描驱动电路以从第N个扫描驱动单元至第一个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一低电平信号。
进一步地，所述第一开关管和所述第三开关管为PMOS晶体管，所述第二开关管为NMOS晶体管。
进一步地，当所述扫描驱动电路以从第一个扫描驱动单元至第N个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一低电平信号。
进一步地，当所述扫描驱动电路以从第N个扫描驱动单元至第一个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一高电平信号。
进一步地，所述扫描驱动单元为膜片上封装的扫描驱动芯片。
本发明的另一目的还在于提供一种显示装置，其包括上述的扫描驱动电路。
本发明的有益效果：本发明通过控制第一节点接收的电平信号的高低，使扫描驱动电路实现正反双向扫描的功能，并且仅需信号控制器输出一个扫描开始信号，不需要印刷电路板上对扫描驱动单元的扫描方向设定电阻，从而降低成本。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1示出了根据本发明的实施例的液晶显示器的框图；
图2示出了根据本发明的实施例的扫描驱动电路的电路结构图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚元件，夸大了层和区域的厚度。相同的标号在附图中始终表示相同的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
图1示出了根据本发明的实施例的液晶显示器的框图。
参照图1，根据本发明的实施例的液晶显示器包括：液晶面板组件300；扫描驱动电路400和源极驱动电路500，二者都连接到液晶面板组件300；灰度电压产生器800，连接到源极驱动电路500；以及信号控制器600，用于控制液晶面板组件300、扫描驱动电路400、源极驱动电路500和灰度电压产生器800。
液晶面板组件300包括多条显示信号线和连接到显示信号线并按阵列排列的多个像素PX。液晶面板组件300可以包括：彼此面对的下显示面板(未示出)和上显示面板(未示出)，以及被插入在下显示面板和上显示面板之间的液晶层(未示出)。
可以在下显示面板上布置显示信号线。显示信号线可以包括传送栅极信号的多条栅极线G1至Gn和传送数据信号的多条数据线D1至Dm。栅极线G1至Gn按行方向延伸并且彼此大致平行，并且数据线D1至Dm按列方向延伸并且彼此大致平行。
每个像素PX包括：开关器件，连接到相应的栅极线和相应的数据线；以及液晶电容器，连接到该开关器件。如果必要，每个像素PX也可以包括存储 电容器，其与液晶电容器并联连接。
每个像素PX的开关器件是三端器件，因此具有连接到相应栅极线的控制端、连接到相应数据线的输入端和连接到相应液晶电容器的输出端。
扫描驱动电路400连接到栅极线G1至Gn，并向栅极线G1至Gn施加栅极信号，该栅极信号是由外部源施加到扫描驱动电路400的高电平栅极信号(此后称之为栅极导通电压Von)和低电平栅极信号(此后称之为栅极截止电压Voff)的组合。参照图1，在液晶面板组件300的一侧布置扫描驱动电路400，并且栅极线G1至Gn都连接到这些扫描驱动电路400。然而，本发明不限于此。也就是说，可以在液晶面板组件300的相对两侧分别布置一个扫描驱动电路，并且栅极线G1至Gn都连接到这两个扫描驱动电路的每一个。
灰度电压产生器800产生与像素PX的透射率紧密相关的灰度电压。该灰度电压被提供给每个像素PX，并且根据公共电压Vcom而具有正值或负值。
源极驱动电路500连接到液晶面板组件300的数据线D1至Dm，并向像素PX施加由灰度电压产生器800产生的灰度电压作为数据电压。如果灰度电压产生器800不是提供所有的灰度电压而是仅提供基准灰度电压，则源极驱动电路500可以通过将基准灰度电压分压而产生各种灰度电压，并选择各种灰度电压中的一个作为数据电压。在本实施例中，源极驱动电路500可以由多个膜片上封装的源极驱动芯片(Source Chip-on-Film，S-COF)构成，但本发明并不限制于此。
信号控制器600控制扫描驱动电路400和源极驱动电路500的操作。在本实施例中，信号控制器600形成在印刷电路板(未示出)上，其中，该印刷电路板与源极驱动电路500电连接。
信号控制器600从外部图形控制器(未示出)接收输入图像信号(R、G和B)以及用于控制输入图像信号的显示的多个输入控制信号，例如垂直同步信号Vsync、水平同步信号Hsync、主时钟信号MCLK、数据使能信号DE。信号控制器600根据输入控制信号适当处理输入图像信号(R、G和B)，从而产生符合液晶面板组件300的操作条件的图像数据DAT。然后，信号控制器600产生栅极控制信号CONT1和数据控制信号CONT2，将栅极控制信号 CONT1传送到扫描驱动电路400，并将数据控制信号CONT2和图像数据DAT传送到源极驱动电路500。
栅极控制信号CONT1可以包括：扫描开始信号STV，用于启动扫描驱动电路400的操作、即扫描操作；以及至少一个时钟信号，用于控制何时输出栅极导通电压Von。栅极控制信号CONT1也可以包括输出使能信号OE，用于限制栅极导通电压Von的持续时间。时钟信号可以被用作选择信号SE。
数据控制信号CONT2可以包括：水平同步开始信号STH，其指示图像数据DAT的传输；加载信号LOAD，其请求向数据线D1至Dm施加与图像数据DAT对应的数据电压；以及数据时钟信号HCLK。数据控制信号CONT2也可以包括反转信号RVS，用于反转数据电压相对于公共电压Vcom的极性，这此后被称为“数据电压的极性”。
源极驱动电路500响应于数据控制信号CONT2从信号控制器600接收图像数据DAT，通过从由灰度电压产生器800提供的多个灰度电压中选择与图像数据DAT对应的灰度电压而将图像数据转换为数据电压。然后，源极驱动电路500将数据电压施加到数据线D1至Dm。
扫描驱动电路400通过响应于栅极控制信号CONT1向栅极线G1至Gn施加栅极导通电压Von而导通连接到栅极线G1至Gn的开关器件。然后，施加到数据线D1至Dm的数据电压通过导通的开关器件而被传送到每个像素PX。
施加到每个像素PX的数据电压和公共电压Vcom之间的差可以被解释为是利用其对每个像素PX的液晶电容器充电的电压、即像素电压。液晶层内的液晶分子的排列根据像素电压的幅度而变化，因而通过液晶层传送的光的极性也可以变化，从而导致液晶层的透射率的变化。
图2示出了根据本发明的实施例的扫描驱动电路的电路结构图。
参照图2，根据本发明的实施例的扫描驱动电路400包括：级联的N个扫描驱动单元4101、4102、4103、……410N、第一开关管420、第二开关管430、第三开关管440和电阻器450。在本发明中，第一开关管420、第二开关管430、第三开关管440并不以图2所示的数量为限。
在本实施例中，第一开关管420、第二开关管430和第三开关管440均为三端器件，因此具有控制端、输入端和输出端。
第一开关管420、第二开关管430和第三开关管440的控制端均连接至第一节点A；其中，第一节点A根据第一开关管420、第二开关管430和第三开关管440的类型接收第一高电平信号或第一低电平信号，这将在下面说明。
第一开关管420和第二开关管430的输入端用于接收扫描开始信号STV，第一开关管420的输出端连接至第一个扫描驱动单元4101，第二开关管430的输出端连接至第N个扫描驱动单元410N。
第三开关管440的输入端用于接收第二高电平信号VDD(例如但不限于3.3V)，第三开关管440的输出端连接至第二节点B并电性接地，N个扫描驱动单元4101、4102、4103、……410N均连接至第二节点B。
进一步地，在本实施例中，第三开关管440的输出端连接电阻器450的一端，电阻器450的另一端电性接地；也就是说，第三开关管440的输出端通过电阻器450电性接地。
在本实施例中，第一开关管420和第三开关管440为NMOS晶体管，而第二开关管430为PMOS晶体管。
这样，当第一节点A接收第一高电平信号时，第一开关管420和第三开关管440导通，第二开关管430关闭，这样第一开关管420的输入端接收扫描开始信号STV，第二节点B为第二高电平信号VDD，从而使各个扫描驱动单元4101、4102、4103、……410N的扫描方向设定信号为第二高电平信号VDD，此时扫描驱动电路400以从第一个扫描驱动单元4101至第N个扫描驱动单元410N的顺序进行驱动扫描。
当第一节点A接收第一低电平信号时，第一开关管420和第三开关管440关闭，第二开关管430导通，这样第二开关管430的输入端接收扫描开始信号STV，第二节点B电性接地，从而使各个扫描驱动单元4101、4102、4103、……410N的扫描方向设定信号为第二低电平信号，此时扫描驱动电路400以从第N个扫描驱动单元410N至第一个扫描驱动单元4101的顺序进行驱动扫描。
作为本发明的另一实施方式，第一开关管420和第三开关管440为PMOS晶体管，而第二开关管430为NMOS晶体管。
这样，当第一节点A接收第一高电平信号时，第一开关管420和第三开关管440关闭，第二开关管430导通，这样第二开关管430的输入端接收扫描开始信号STV，第二节点B电性接地，从而使各个扫描驱动单元4101、4102、4103、……410N的扫描方向设定信号为第二低电平信号，此时扫描驱动电路400以从第N个扫描驱动单元410N至第一个扫描驱动单元4101的顺序进行驱动扫描。
当第一节点A接收第一低电平信号时，第一开关管420和第三开关管440导通，第二开关管430关闭，这样第一开关管420的输入端接收扫描开始信号STV，第二节点B为第二高电平信号VDD，从而使各个扫描驱动单元4101、4102、4103、……410N的扫描方向设定信号为第二高电平信号VDD，此时扫描驱动电路400以从第一个扫描驱动单元4101至第N个扫描驱动单元410N的顺序进行驱动扫描。
综上所述，通过控制第一节点接收的电平信号的高低，使扫描驱动电路实现正反双向扫描的功能，并且仅需信号控制器输出一个扫描开始信号，不需要印刷电路板上对扫描驱动单元的扫描方向设定电阻，从而降低成本。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (16)

  1. 一种扫描驱动电路，其中，包括：级联的N个扫描驱动单元、至少一个第一开关管、至少一个第二开关管和至少一个第三开关管；
    其中，所述第一开关管、所述第二开关管和所述第三开关管均包括控制端、输入端和输出端；
    所述第一开关管、所述第二开关管和所述第三开关管的控制端均连接至第一节点，所述第一节点接收第一高电平信号或第一低电平信号；
    所述第一开关管和所述第二开关管的输入端用于接收扫描开始信号，所述第一开关管的输出端连接至第一个扫描驱动单元，所述第二开关管的输出端连接至第N个扫描驱动单元；
    所述第三开关管的输入端用于接收第二高电平信号，所述第三开关管的输出端连接至第二节点并电性接地，所述N个扫描驱动单元均连接至所述第二节点。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述第三开关管的输出端通过一电阻器电性接地。
  3. 根据权利要求1所述的扫描驱动电路，其中，所述第一开关管和所述第三开关管为NMOS晶体管，所述第二开关管为PMOS晶体管。
  4. 根据权利要求2所述的扫描驱动电路，其中，所述第一开关管和所述第三开关管为NMOS晶体管，所述第二开关管为PMOS晶体管。
  5. 根据权利要求3所述的扫描驱动电路，其中，当所述扫描驱动电路以从第一个扫描驱动单元至第N个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一高电平信号。
  6. 根据权利要求4所述的扫描驱动电路，其中，当所述扫描驱动电路以从第一个扫描驱动单元至第N个扫描驱动单元的顺序进行驱动扫描时，所述第 一节点接收所述第一高电平信号。
  7. 根据权利要求3所述的扫描驱动电路，其中，当所述扫描驱动电路以从第N个扫描驱动单元至第一个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一低电平信号。
  8. 根据权利要求4所述的扫描驱动电路，其中，当所述扫描驱动电路以从第N个扫描驱动单元至第一个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一低电平信号。
  9. 根据权利要求1所述的扫描驱动电路，其中，所述第一开关管和所述第三开关管为PMOS晶体管，所述第二开关管为NMOS晶体管。
  10. 根据权利要求2所述的扫描驱动电路，其中，所述第一开关管和所述第三开关管为PMOS晶体管，所述第二开关管为NMOS晶体管。
  11. 根据权利要求9所述的扫描驱动电路，其中，当所述扫描驱动电路以从第一个扫描驱动单元至第N个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一低电平信号。
  12. 根据权利要求10所述的扫描驱动电路，其中，当所述扫描驱动电路以从第一个扫描驱动单元至第N个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一低电平信号。
  13. 根据权利要求9所述的扫描驱动电路，其中，当所述扫描驱动电路以从第N个扫描驱动单元至第一个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一高电平信号。
  14. 根据权利要求10所述的扫描驱动电路，其中，当所述扫描驱动电路以从第N个扫描驱动单元至第一个扫描驱动单元的顺序进行驱动扫描时，所述第一节点接收所述第一高电平信号。
  15. 根据权利要求1所述的扫描驱动电路，其中，所述扫描驱动单元为膜片上封装的扫描驱动芯片。
  16. 一种显示装置，包括扫描驱动电路，其中，所述扫描驱动电路包括： 级联的N个扫描驱动单元、至少一个第一开关管、至少一个第二开关管和至少一个第三开关管；
    其中，所述第一开关管、所述第二开关管和所述第三开关管均包括控制端、输入端和输出端；
    所述第一开关管、所述第二开关管和所述第三开关管的控制端均连接至第一节点，所述第一节点接收第一高电平信号或第一低电平信号；
    所述第一开关管和所述第二开关管的输入端用于接收扫描开始信号，所述第一开关管的输出端连接至第一个扫描驱动单元，所述第二开关管的输出端连接至第N个扫描驱动单元；
    所述第三开关管的输入端用于接收第二高电平信号，所述第三开关管的输出端连接至第二节点并电性接地，所述N个扫描驱动单元均连接至所述第二节点。
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