WO2017173713A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2017173713A1
WO2017173713A1 PCT/CN2016/082951 CN2016082951W WO2017173713A1 WO 2017173713 A1 WO2017173713 A1 WO 2017173713A1 CN 2016082951 W CN2016082951 W CN 2016082951W WO 2017173713 A1 WO2017173713 A1 WO 2017173713A1
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Prior art keywords
layer
metal layer
array substrate
substrate
liquid crystal
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PCT/CN2016/082951
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English (en)
French (fr)
Inventor
王勐
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/124,365 priority Critical patent/US20180149934A1/en
Publication of WO2017173713A1 publication Critical patent/WO2017173713A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/08—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 light absorbing layer
    • G02F2201/086—UV absorbing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/124—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode interdigital
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • the existing liquid crystal display panel comprises an array substrate and a color film substrate.
  • the array substrate is provided with a thin film transistor including a gate, a source and a drain, and an active layer (for forming a channel).
  • the material of the edge layer is Oxide semiconductor material.
  • the oxide semiconductor material is irradiated with ultraviolet light, the charging performance of the thin film transistor is lowered, as shown in FIG.
  • the charging performance of the thin film transistor gives the charging performance of the thin film transistor after illumination.
  • the abscissa indicates the voltage value
  • the ordinate indicates the capacitance value. Comparing the two figures, it is not difficult to find that The threshold voltage of the thin film transistor becomes small, that is, the charging performance is lowered, and the display effect is lowered.
  • an array substrate which includes:
  • a first metal layer on the substrate substrate including a gate region of the thin film transistor
  • a gate insulating layer partially on the first metal layer for isolating the first metal layer and the second metal layer;
  • An active layer partially located on the gate insulating layer for forming a channel
  • the second metal layer is located on the ohmic contact layer, including a drain region and a source region of the thin film transistor;
  • the third metal layer includes a light protection zone, the light protection zone corresponding to a position of the channel; the light protection zone is on the substrate
  • the projected area on the substrate is slightly larger than the projected area of the channel on the substrate.
  • the third metal layer further includes a pixel electrode, and the illumination protection region and the pixel electrode are obtained in the same process.
  • the array substrate further includes a transparent conductive layer, the transparent conductive layer is located on the third metal layer, and the transparent conductive layer includes a pixel electrode.
  • the array substrate further includes a flat layer, and the flat layer is on the third metal layer.
  • the material of the ohmic contact layer is silicon nitride.
  • an array substrate which includes:
  • a first metal layer on the substrate substrate including a gate region of the thin film transistor
  • a gate insulating layer partially on the first metal layer for isolating the first metal layer and the second metal layer;
  • An active layer partially located on the gate insulating layer for forming a channel
  • the second metal layer is disposed on the active layer, including a drain region and a source region of the thin film transistor;
  • a third metal layer is disposed on the first insulating layer, the third metal layer includes a light protection zone, and the light protection zone corresponds to a position of the channel.
  • the third metal layer further includes a pixel electrode, and the illumination protection region and the pixel electrode are obtained in the same process.
  • the array substrate further includes a transparent conductive layer, the transparent conductive layer is located on the third metal layer, and the transparent conductive layer includes a pixel electrode.
  • a projected area of the illumination protection area on the base substrate is slightly larger than a projected area of the channel on the base substrate.
  • the array substrate further includes a flat layer, and the flat layer is on the third metal layer.
  • the array substrate further includes an ohmic contact layer between the active layer and the second metal layer.
  • the material of the ohmic contact layer may be silicon nitride.
  • the invention also provides a liquid crystal display panel comprising:
  • the array substrate includes:
  • a first metal layer on the substrate substrate including a gate region of the thin film transistor
  • a gate insulating layer partially on the first metal layer for isolating the first metal layer and the second metal layer;
  • An active layer partially located on the gate insulating layer for forming a channel
  • the second metal layer is disposed on the active layer, including a drain region and a source region of the thin film transistor;
  • a third metal layer is disposed on the first insulating layer, the third metal layer includes a light protection zone, and the light protection zone corresponds to a position of the channel.
  • the third metal layer further includes a pixel electrode, and the light protection region and the pixel electrode are obtained in the same process.
  • the array substrate further includes a transparent conductive layer, the transparent conductive layer is located on the third metal layer, and the transparent conductive layer includes a pixel electrode.
  • a projected area of the light protection zone on the base substrate is slightly larger than a projected area of the channel on the base substrate.
  • the array substrate further includes a flat layer, and the flat layer is on the third metal layer.
  • the array substrate further includes an ohmic contact layer between the active layer and the second metal layer.
  • the material of the ohmic contact layer may be silicon nitride.
  • the illumination protection area is disposed at a position corresponding to the channel, the channel is prevented from being irradiated with ultraviolet light, and the charging performance and display effect of the thin film transistor are improved.
  • FIG. 1 is a schematic diagram showing charging performance of a thin film transistor before illumination in the prior art
  • FIG. 2 is a schematic diagram of charging performance of a thin film transistor after illumination in the prior art
  • FIG. 3 is a schematic structural view of an array substrate of the present invention.
  • FIG. 4 is a top plan view of an array substrate of the present invention.
  • FIG. 3 is a schematic structural view of an array substrate according to the present invention.
  • the array substrate 10 of the present invention includes a base substrate 11, a first metal layer 12, a gate insulating layer 13, an active layer 14, a second metal layer 15, a first insulating layer 16, and a third metal.
  • Layer 17, may also include an ohmic contact layer (not shown);
  • the first metal layer 12 is located on the base substrate 11 and includes a gate region of the thin film transistor, and the first metal layer 12 is patterned to form a gate, and the first portion other than the gate region The metal layer is etched away during the process; the material of the first metal layer 12 may be chromium, molybdenum, aluminum or copper.
  • the gate insulating layer 13 is disposed on the first metal layer 12, The gate insulating layer 13 is provided only in the gate region of the first metal layer 12, and the remaining gate insulating layer 13 is disposed on the base substrate.
  • the active layer 14 is partially located on the gate insulating layer 13 for forming a channel between the drain and the source of the thin film transistor;
  • the ohmic contact layer may be located on the active layer 14 for turning on the source and the drain when the gate of the thin film transistor is closed.
  • the material of the ohmic contact layer may be silicon nitride.
  • the second metal layer 15 is located on the ohmic contact layer, including a drain region 151 and a source region 152 of a thin film transistor and a data line; and the second metal layer 15 is patterned to form a drain 151 and a source The pole 152, and the data line; the drain and the source and the second metal layer other than the data line are etched away during the process.
  • the first insulating layer 16 is configured to isolate the second metal layer 15 and the third metal layer 17; wherein the third metal layer 17 is patterned to obtain a light protection area; the light protection area and the The position of the channel corresponds to that the portion of the third metal layer 17 other than the position of the channel can be etched away, leaving only the illumination protection region.
  • a projected area of the illumination protection area on the base substrate 11 is slightly larger than a projected area of the channel on the base substrate 11. That is, in the vertical projection direction, the area of the illumination protection area is larger than the area of the channel, so that the channel is better protected from ultraviolet light.
  • the overall thickness of the array substrate is increased, so that the parasitic capacitance can be reduced, and the display effect is further improved.
  • the light protection zone is used to prevent the channel from being exposed to ultraviolet light, thereby preventing the charging performance of the thin film transistor from being well prevented.
  • a transparent conductive layer may be formed on the third metal layer 17, the transparent conductive layer including a pixel electrode, and the transparent conductive layer may be formed by a sputter coating method, the pixel electrode Connected to the drain through a via.
  • a flat layer may be provided on the transparent conductive layer.
  • the liquid crystal molecules are more uniformly diffused, and at the same time, it is advantageous to obtain a more accurate optimal liquid crystal amount in the process of manufacturing the liquid crystal display panel (the liquid crystal display panel achieves the best display effect, and the required liquid crystal molecules quantity).
  • the above structure can be applied to an IPS type panel in order to further reduce the production cost.
  • the third metal layer 17 is patterned to form a light protection area 21 and a pixel electrode 22, respectively, wherein the light protection area 21 is located on the channel due to The pixel electrode and the light protection zone are produced in the same process, thereby reducing production costs.
  • the pixel electrode and the drain are connected by a via.
  • a flat layer may be provided on the third metal layer 17.
  • a first alignment film may also be disposed on the flat layer.
  • the array substrate further includes a scan line, and the data line and the scan line define a plurality of pixel units.
  • the illumination protection region is disposed at a position corresponding to the channel, the channel is prevented from being irradiated with ultraviolet light, and the charging performance of the thin film transistor is improved.
  • the present invention also provides a liquid crystal display panel comprising a color filter substrate and an array substrate, and a liquid crystal layer between the array substrate and the color filter substrate, the color filter substrate may include a color resist layer and a common electrode, and the array substrate of the present invention 10, as shown in FIG. 3, comprising a base substrate 11, a first metal layer 12, a gate insulating layer 13, an active layer 14, a second metal layer 15, a first insulating layer 16, and a third metal layer 17, Including an ohmic contact layer (not shown);
  • the first metal layer 12 is located on the base substrate 11 and includes a gate region of the thin film transistor, and the first metal layer 12 is patterned to form a gate, and the first portion other than the gate region The metal layer is etched away during the process; the material of the first metal layer 12 may be chromium, molybdenum, aluminum or copper.
  • the gate insulating layer 13 is disposed on the first metal layer 12, The gate insulating layer 13 is provided only in the gate region of the first metal layer 12, and the remaining gate insulating layer 13 is disposed on the base substrate.
  • the active layer 14 is partially located on the gate insulating layer 13 for forming a channel between the drain and the source of the thin film transistor;
  • the ohmic contact layer may be located on the active layer 14 for turning on the source and the drain when the gate of the thin film transistor is closed.
  • the material of the ohmic contact layer may be silicon nitride.
  • the second metal layer 15 is located on the ohmic contact layer, including a drain region 151 and a source region 152 of a thin film transistor and a data line; and the second metal layer 15 is patterned to form a drain 151 and a source The pole 152, and the data line; the drain and the source and the second metal layer other than the data line are etched away during the process.
  • the first insulating layer 16 is configured to isolate the second metal layer 15 and the third metal layer 17; wherein the third metal layer 17 is patterned to obtain a light protection area; the light protection area and the The position of the channel corresponds to that the portion of the third metal layer 17 other than the position of the channel can be etched away, leaving only the illumination protection region.
  • a projected area of the illumination protection area on the base substrate 11 is slightly larger than a projected area of the channel on the base substrate 11. That is, in the vertical projection direction, the area of the illumination protection area is larger than the area of the channel, so that the channel is better protected from ultraviolet light.
  • the overall thickness of the array substrate is increased, so that the parasitic capacitance can be reduced, and the display effect is further improved.
  • the light protection zone is used to prevent the channel from being exposed to ultraviolet light, thereby preventing the charging performance of the thin film transistor from being well prevented.
  • a transparent conductive layer may be formed on the third metal layer 17, the transparent conductive layer including a pixel electrode, and the transparent conductive layer may be formed by a sputter coating method, the pixel electrode Connected to the drain through a via.
  • a flat layer may be provided on the transparent conductive layer.
  • the liquid crystal molecules are more uniformly diffused, and at the same time, it is advantageous to obtain a more accurate optimal liquid crystal amount in the process of manufacturing the liquid crystal display panel (the liquid crystal display panel achieves the best display effect, and the required liquid crystal molecules quantity).
  • the above structure can be applied to an IPS type panel in order to further reduce the production cost.
  • the third metal layer 17 is patterned to form a light protection area 21 and a pixel electrode 22, respectively, wherein the light protection area 21 is located on the channel due to The pixel electrode and the light protection zone are produced in the same process, thereby reducing production costs.
  • the pixel electrode and the drain are connected by a via.
  • a flat layer may be provided on the third metal layer 17.
  • a first alignment film may also be disposed on the flat layer.
  • the array substrate further includes a scan line, and the data line and the scan line define a plurality of pixel units.
  • the illumination protection area is disposed at a position corresponding to the channel, the channel is prevented from being irradiated with ultraviolet light, and the charging performance of the thin film transistor is improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
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Abstract

一种阵列基板（10）及液晶显示面板，所述阵列基板（10）包括：依次设置的衬底基板（11）、第一金属层（12）、栅绝缘层（13）、有源层（14）、第二金属层（15）、第一绝缘层（16）、第三金属层（17）；有源层（14）用于形成沟道；所述第二金属层（15）包括所述薄膜晶体管的漏极区（151）和源极区（152）；所述第三金属层（17）包括光照保护区（21），所述光照保护区（21）与所述沟道的位置相对应。

Description

一种阵列基板及液晶显示面板 技术领域
本发明涉及液晶显示器技术领域，特别是涉及一种阵列基板及液晶显示面板。
 背景技术
现有液晶显示面板包括阵列基板和彩膜基板，阵列基板上设置有薄膜晶体管，薄膜晶体管包括栅极，源极和漏极以及有源层（用于形成沟道），该有缘层的材料为氧化物半导体材料。
现有液晶显示面板的制作过程中，不可避免地用到紫外光照射，由于氧化物半导体材料在受到紫外光照射时，会降低薄膜晶体管的充电性能，如图1所示，给出光照前的薄膜晶体管的充电性能，如图2所示，给出光照后的薄膜晶体管的充电性能，图1和图2中横坐标表示电压值，纵坐标表示电容值，对比两张图，不难发现，薄膜晶体管的阈值电压变小，也即充电性能下降，降低了显示效果。
因此，有必要提供一种阵列基板及液晶显示面板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种阵列基板及液晶显示面板，以解决现有技术的薄膜晶体管的沟道在紫外光照射下，导致其充电性能降低，显示效果差的技术问题。
 技术解决方案
为解决上述技术问题，本发明构造了一种阵列基板，其包括：
衬底基板；
第一金属层，位于所述衬底基板上，包括薄膜晶体管的栅极区；
栅绝缘层，部分位于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
有源层，部分位于所述栅绝缘层上，用于形成沟道；
欧姆接触层，位于所述有源层上；
所述第二金属层，位于所述欧姆接触层上，包括所述薄膜晶体管的漏极区和源极区；
第一绝缘层，位于所述第二金属层上；以及
第三金属层，位于所述第一绝缘层上，所述第三金属层包括光照保护区，所述光照保护区与所述沟道的位置相对应；所述光照保护区在所述衬底基板上的投影面积略大于所述沟道在所述衬底基板上的投影面积。
在本发明的阵列基板中，所述第三金属层还包括像素电极，所述光照保护区与所述像素电极是在同一制程工序中得到的。
在本发明的阵列基板中，所述阵列基板还包括透明导电层，所述透明导电层位于所述第三金属层上，所述透明导电层包括像素电极。
在本发明的阵列基板中，所述阵列基板还包括平坦层，所述平坦层位于所述第三金属层上。
在本发明的阵列基板中，所述欧姆接触层的材料为氮化硅。
为解决上述技术问题，本发明构造了一种阵列基板，其包括：
衬底基板；
第一金属层，位于所述衬底基板上，包括薄膜晶体管的栅极区；
栅绝缘层，部分位于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
有源层，部分位于所述栅绝缘层上，用于形成沟道；
所述第二金属层，位于所述有源层上，包括所述薄膜晶体管的漏极区和源极区；
第一绝缘层，位于所述第二金属层上；以及
第三金属层，位于所述第一绝缘层上，所述第三金属层包括光照保护区，所述光照保护区与所述沟道的位置相对应。
在本发明的阵列基板中，所述第三金属层还包括像素电极，所述光照保护区与所述像素电极是在同一制程工序中得到的。
在本发明的阵列基板中，所述阵列基板还包括透明导电层，所述透明导电层位于所述第三金属层上，所述透明导电层包括像素电极。
在本发明的阵列基板中，所述光照保护区在所述衬底基板上的投影面积略大于所述沟道在所述衬底基板上的投影面积。
在本发明的阵列基板中，所述阵列基板还包括平坦层，所述平坦层位于所述第三金属层上。
在本发明的阵列基板中，所述阵列基板还包括欧姆接触层，所述欧姆接触层位于所述有源层和所述第二金属层之间。
在本发明的阵列基板中，所述欧姆接触层的材料可为氮化硅。
本发明还提供一种液晶显示面板，其包括：
彩膜基板，与阵列基板相对设置；
液晶层，位于所述彩膜基板和所述阵列基板之间，以及
所述阵列基板，其包括：
衬底基板；
第一金属层，位于所述衬底基板上，包括薄膜晶体管的栅极区；
栅绝缘层，部分位于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
有源层，部分位于所述栅绝缘层上，用于形成沟道；
所述第二金属层，位于所述有源层上，包括所述薄膜晶体管的漏极区和源极区；
第一绝缘层，位于所述第二金属层上；以及
第三金属层，位于所述第一绝缘层上，所述第三金属层包括光照保护区，所述光照保护区与所述沟道的位置相对应。
在本发明的液晶显示面板中，所述第三金属层还包括像素电极，所述光照保护区与所述像素电极是在同一制程工序中得到的。
在本发明的液晶显示面板中，所述阵列基板还包括透明导电层，所述透明导电层位于所述第三金属层上，所述透明导电层包括像素电极。
在本发明的液晶显示面板中，所述光照保护区在所述衬底基板上的投影面积略大于所述沟道在所述衬底基板上的投影面积。
在本发明的液晶显示面板中，所述阵列基板还包括平坦层，所述平坦层位于所述第三金属层上。
在本发明的液晶显示面板中，所述阵列基板还包括欧姆接触层，所述欧姆接触层位于所述有源层和所述第二金属层之间。
在本发明的液晶显示面板中，所述欧姆接触层的材料可为氮化硅。
 有益效果
本发明的阵列基板及液晶显示面板，由于在于沟道对应的位置上设置光照保护区，从而避免沟道受到紫外光照射，提高了薄膜晶体管的充电性能和显示效果。
 附图说明
图1为现有技术光照前的薄膜晶体管的充电性能示意图；
图2为现有技术光照后的薄膜晶体管的充电性能示意图；
图3为本发明阵列基板的结构示意图；
图4为本发明阵列基板的俯视图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图3，图3为本发明阵列基板的结构示意图。
本发明的阵列基板10，如图3所示，包括衬底基板11、第一金属层12、栅绝缘层13、有源层14、第二金属层15、第一绝缘层16，第三金属层17，还可以包括欧姆接触层（图中未示出）；
所述第一金属层12位于所述衬底基板11上，包括薄膜晶体管的栅极区，对所述第一金属层12进行图形化处理形成栅极，所述栅极区部分以外的第一金属层在制程过程中被刻蚀掉；所述第一金属层12的材料可为铬、钼、铝或铜等。
为了隔离所述第一金属层12和所述第二金属层15、以及隔离所述第一金属层12和有源层14，在所述第一金属层12上设置所述栅绝缘层13，仅在所述第一金属层12的栅极区设置有所述栅绝缘层13，其余所述栅绝缘层13设置在所述衬底基板上。所述有源层14部分位于所述栅绝缘层13上，用于形成所述薄膜晶体管的漏极和源极之间的沟道；
所述欧姆接触层可位于所述有源层14上，用于在所述薄膜晶体管的栅极闭合时，导通源极和漏极。所述欧姆接触层的材料可为氮化硅。
所述第二金属层15位于所述欧姆接触层上，包括薄膜晶体管的漏极区151和源极区152以及数据线；对所述第二金属层15进行图形化处理形成漏极151和源极152、以及数据线；所述漏极和源极以及数据线以外的第二金属层在制程过程中被刻蚀掉。
所述第一绝缘层16用于隔离所述第二金属层15和第三金属层17；其中对所述第三金属层17进行图形化处理得到光照保护区；所述光照保护区与所述沟道的位置相对应，也即可以将第三金属层17中与沟道的位置相对应以外的部分刻蚀掉，仅保留光照保护区。
优选地，所述光照保护区在所述衬底基板11上的投影面积略大于所述沟道在所述衬底基板11上的投影面积。也即在竖直投影方向上，光照保护区的面积大于所述沟道的面积，从而能更好地防止沟道受到紫外光照射。
此外，由于在现有阵列基板的基础上，增加了第一绝缘层16和第三金属层17，使得阵列基板的整体厚度增加，从而可以降低寄生电容，进一步提高了显示效果。
该光照保护区用于防止沟道受到紫外光的照射，从而很好地防止降低薄膜晶体管的充电性能。
当然可以理解的是，上述结构可以应用在FFS型面板中。当用在FFS型面板中时，可以在所述第三金属层17上制作透明导电层，所述透明导电层包括像素电极，可以利用溅射镀膜法形成所述透明导电层，所述像素电极与所述漏极之间通过过孔连接。
当然，为了使液晶显示面板的显示效果更佳，还可以在透明导电层上设置平坦层。当阵列基板的表面更加平整时，使液晶分子扩散更加均匀，同时有利于在制作液晶显示面板过程中，获取更加准确的最佳液晶量（液晶显示面板达到最佳显示效果，所需要的液晶分子的数量）。
当然可以理解的是，为了进一步降低生产成本，上述结构可以应用在IPS型面板中。当用在IPS型面板中时，如图4所示，对所述第三金属层17进行图形化处理分别形成光照保护区21和像素电极22，其中光照保护区21位于所述沟道上，由于像素电极和光照保护区在同一制程工艺中制得，从而降低生产成本。所述像素电极与所述漏极之间通过过孔连接。
为了使液晶显示面板的显示效果更佳，还可以在第三金属层17上设置平坦层。优选地，在平坦层上还可设置第一配向膜。当然所述阵列基板还包括扫描线，所述数据线和所述扫描线限定形成多个像素单元。
本发明的阵列基板，由于在于沟道对应的位置上设置光照保护区，从而避免沟道受到紫外光照射，提高了薄膜晶体管的充电性能。
本发明还提供一种液晶显示面板，其包括彩膜基板和阵列基板，以及位于阵列基板和彩膜基板之间的液晶层，彩膜基板可以包括色阻层和公共电极，本发明的阵列基板10，如图3所示，包括衬底基板11、第一金属层12、栅绝缘层13、有源层14、第二金属层15、第一绝缘层16，第三金属层17，还可以包括欧姆接触层（图中未示出）；
所述第一金属层12位于所述衬底基板11上，包括薄膜晶体管的栅极区，对所述第一金属层12进行图形化处理形成栅极，所述栅极区部分以外的第一金属层在制程过程中被刻蚀掉；所述第一金属层12的材料可为铬、钼、铝或铜等。
为了隔离所述第一金属层12和所述第二金属层15、以及隔离所述第一金属层12和有源层14，在所述第一金属层12上设置所述栅绝缘层13，仅在所述第一金属层12的栅极区设置有所述栅绝缘层13，其余所述栅绝缘层13设置在所述衬底基板上。所述有源层14部分位于所述栅绝缘层13上，用于形成所述薄膜晶体管的漏极和源极之间的沟道；
所述欧姆接触层可位于所述有源层14上，用于在所述薄膜晶体管的栅极闭合时，导通源极和漏极。所述欧姆接触层的材料可为氮化硅。
所述第二金属层15位于所述欧姆接触层上，包括薄膜晶体管的漏极区151和源极区152以及数据线；对所述第二金属层15进行图形化处理形成漏极151和源极152、以及数据线；所述漏极和源极以及数据线以外的第二金属层在制程过程中被刻蚀掉。
所述第一绝缘层16用于隔离所述第二金属层15和第三金属层17；其中对所述第三金属层17进行图形化处理得到光照保护区；所述光照保护区与所述沟道的位置相对应，也即可以将第三金属层17中与沟道的位置相对应以外的部分刻蚀掉，仅保留光照保护区。
优选地，所述光照保护区在所述衬底基板11上的投影面积略大于所述沟道在所述衬底基板11上的投影面积。也即在竖直投影方向上，光照保护区的面积大于所述沟道的面积，从而能更好地防止沟道受到紫外光照射。
此外，由于在现有阵列基板的基础上，增加了第一绝缘层16和第三金属层17，使得阵列基板的整体厚度增加，从而可以降低寄生电容，进一步提高了显示效果。
该光照保护区用于防止沟道受到紫外光的照射，从而很好地防止降低薄膜晶体管的充电性能。
当然可以理解的是，上述结构可以应用在FFS型面板中。当用在FFS型面板中时，可以在所述第三金属层17上制作透明导电层，所述透明导电层包括像素电极，可以利用溅射镀膜法形成所述透明导电层，所述像素电极与所述漏极之间通过过孔连接。
当然，为了使液晶显示面板的显示效果更佳，还可以在透明导电层上设置平坦层。当阵列基板的表面更加平整时，使液晶分子扩散更加均匀，同时有利于在制作液晶显示面板过程中，获取更加准确的最佳液晶量（液晶显示面板达到最佳显示效果，所需要的液晶分子的数量）。
当然可以理解的是，为了进一步降低生产成本，上述结构可以应用在IPS型面板中。当用在IPS型面板中时，如图4所示，对所述第三金属层17进行图形化处理分别形成光照保护区21和像素电极22，其中光照保护区21位于所述沟道上，由于像素电极和光照保护区在同一制程工艺中制得，从而降低生产成本。所述像素电极与所述漏极之间通过过孔连接。
为了使液晶显示面板的显示效果更佳，还可以在第三金属层17上设置平坦层。优选地，在平坦层上还可设置第一配向膜。当然所述阵列基板还包括扫描线，所述数据线和所述扫描线限定形成多个像素单元。
本发明的液晶显示面板，由于在于沟道对应的位置上设置光照保护区，从而避免沟道受到紫外光照射，提高了薄膜晶体管的充电性能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种阵列基板，其包括：
    衬底基板；
    第一金属层，位于所述衬底基板上，包括薄膜晶体管的栅极区；
    栅绝缘层，部分位于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    有源层，部分位于所述栅绝缘层上，用于形成沟道；
    欧姆接触层，位于所述有源层上；
    所述第二金属层，位于所述欧姆接触层上，包括所述薄膜晶体管的漏极区和源极区；
    第一绝缘层，位于所述第二金属层上；以及
    第三金属层，位于所述第一绝缘层上，所述第三金属层包括光照保护区，所述光照保护区与所述沟道的位置相对应；所述光照保护区在所述衬底基板上的投影面积略大于所述沟道在所述衬底基板上的投影面积。
  2. 根据权利要求1所述的阵列基板，其中所述第三金属层还包括像素电极，所述光照保护区与所述像素电极是在同一制程工序中得到的。
  3. 根据权利要求1所述的阵列基板，其中所述阵列基板还包括透明导电层，所述透明导电层位于所述第三金属层上，所述透明导电层包括像素电极。
  4. 根据权利要求1所述的阵列基板，其中所述阵列基板还包括平坦层，所述平坦层位于所述第三金属层上。
  5. 根据权利要求1所述的阵列基板，其中所述欧姆接触层的材料为氮化硅。
  6. 一种阵列基板，其包括：
    衬底基板；
    第一金属层，位于所述衬底基板上，包括薄膜晶体管的栅极区；
    栅绝缘层，部分位于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    有源层，部分位于所述栅绝缘层上，用于形成沟道；
    所述第二金属层，位于所述有源层上，包括所述薄膜晶体管的漏极区和源极区；
    第一绝缘层，位于所述第二金属层上；以及
    第三金属层，位于所述第一绝缘层上，所述第三金属层包括光照保护区，所述光照保护区与所述沟道的位置相对应。
  7. 根据权利要求6所述的阵列基板，其中所述第三金属层还包括像素电极，所述光照保护区与所述像素电极是在同一制程工序中得到的。
  8. 根据权利要求6所述的阵列基板，其中所述阵列基板还包括透明导电层，所述透明导电层位于所述第三金属层上，所述透明导电层包括像素电极。
  9. 根据权利要求6所述的阵列基板，其中所述光照保护区在所述衬底基板上的投影面积略大于所述沟道在所述衬底基板上的投影面积。
  10. 根据权利要求6所述的阵列基板，其中所述阵列基板还包括平坦层，所述平坦层位于所述第三金属层上。
  11. 根据权利要求6所述的阵列基板，其中所述阵列基板还包括欧姆接触层，所述欧姆接触层位于所述有源层和所述第二金属层之间。
  12. 根据权利要求11所述的阵列基板，其中所述欧姆接触层的材料可为氮化硅。
  13. 一种液晶显示面板，其包括：
    彩膜基板，与阵列基板相对设置；
    液晶层，位于所述彩膜基板和所述阵列基板之间，以及
    所述阵列基板，其包括：
    衬底基板；
    第一金属层，位于所述衬底基板上，包括薄膜晶体管的栅极区；
    栅绝缘层，部分位于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    有源层，部分位于所述栅绝缘层上，用于形成沟道；
    所述第二金属层，位于所述有源层上，包括所述薄膜晶体管的漏极区和源极区；
    第一绝缘层，位于所述第二金属层上；以及
    第三金属层，位于所述第一绝缘层上，所述第三金属层包括光照保护区，所述光照保护区与所述沟道的位置相对应。
  14. 根据权利要求13所述的液晶显示面板，其中
    所述第三金属层还包括像素电极，所述光照保护区与所述像素电极是在同一制程工序中得到的。
  15. 根据权利要求13所述的液晶显示面板，其中所述阵列基板还包括透明导电层，所述透明导电层位于所述第三金属层上，所述透明导电层包括像素电极。
  16. 根据权利要求13所述的液晶显示面板，其中所述光照保护区在所述衬底基板上的投影面积略大于所述沟道在所述衬底基板上的投影面积。
  17. 根据权利要求13所述的液晶显示面板，其中所述阵列基板还包括平坦层，所述平坦层位于所述第三金属层上。
  18. 根据权利要求13所述的液晶显示面板，其中所述阵列基板还包括欧姆接触层，所述欧姆接触层位于所述有源层和所述第二金属层之间。
  19. 根据权利要求18所述的液晶显示面板，其中所述欧姆接触层的材料可为氮化硅。
PCT/CN2016/082951 2016-04-05 2016-05-23 一种阵列基板及液晶显示面板 Ceased WO2017173713A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112185984A (zh) * 2020-09-17 2021-01-05 武汉华星光电半导体显示技术有限公司 一种阵列基板及显示面板

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109509757B (zh) * 2018-11-29 2024-04-12 福建华佳彩有限公司 液晶显示器Demux结构、制作方法及液晶显示器
CN111564452B (zh) * 2020-05-07 2024-02-23 Tcl华星光电技术有限公司 阵列基板及母板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1397829A (zh) * 2001-07-18 2003-02-19 Lg.菲利浦Lcd株式会社 液晶显示装置的阵列基板及其制造方法
US20040135148A1 (en) * 2003-01-10 2004-07-15 Chiao-Ju Lin [top emission active matrix oled and fabricating method thereof]
CN101726947A (zh) * 2008-10-10 2010-06-09 乐金显示有限公司 用于液晶显示器件的阵列基板、其制造方法、以及具有其的液晶显示器件
CN101887897A (zh) * 2009-05-13 2010-11-17 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN103337497A (zh) * 2013-06-28 2013-10-02 北京京东方光电科技有限公司 一种阵列基板及其制造方法、显示装置
CN104952881A (zh) * 2015-05-06 2015-09-30 合肥京东方光电科技有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1148600C (zh) * 1996-11-26 2004-05-05 三星电子株式会社 薄膜晶体管基片及其制造方法
US7027109B2 (en) * 2001-08-03 2006-04-11 Nec Corporation TFT array substrate and active-matrix addressing liquid-crystal display device
KR20060001662A (ko) * 2004-06-30 2006-01-06 엘지.필립스 엘시디 주식회사 수평전계방식 액정표시소자 및 그 제조방법
US7521356B2 (en) * 2005-09-01 2009-04-21 Micron Technology, Inc. Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1397829A (zh) * 2001-07-18 2003-02-19 Lg.菲利浦Lcd株式会社 液晶显示装置的阵列基板及其制造方法
US20040135148A1 (en) * 2003-01-10 2004-07-15 Chiao-Ju Lin [top emission active matrix oled and fabricating method thereof]
CN101726947A (zh) * 2008-10-10 2010-06-09 乐金显示有限公司 用于液晶显示器件的阵列基板、其制造方法、以及具有其的液晶显示器件
CN101887897A (zh) * 2009-05-13 2010-11-17 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN103337497A (zh) * 2013-06-28 2013-10-02 北京京东方光电科技有限公司 一种阵列基板及其制造方法、显示装置
CN104952881A (zh) * 2015-05-06 2015-09-30 合肥京东方光电科技有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112185984A (zh) * 2020-09-17 2021-01-05 武汉华星光电半导体显示技术有限公司 一种阵列基板及显示面板
CN112185984B (zh) * 2020-09-17 2022-07-12 武汉华星光电半导体显示技术有限公司 一种阵列基板及显示面板

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