WO2017173685A1 - 阵列基板及制作方法 - Google Patents

阵列基板及制作方法 Download PDF

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Publication number
WO2017173685A1
WO2017173685A1 PCT/CN2016/080435 CN2016080435W WO2017173685A1 WO 2017173685 A1 WO2017173685 A1 WO 2017173685A1 CN 2016080435 W CN2016080435 W CN 2016080435W WO 2017173685 A1 WO2017173685 A1 WO 2017173685A1
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Prior art keywords
layer
drain
source
disposed
insulating layer
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Ceased
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PCT/CN2016/080435
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English (en)
French (fr)
Inventor
夏慧
黄添钧
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/123,064 priority Critical patent/US10120252B2/en
Publication of WO2017173685A1 publication Critical patent/WO2017173685A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate and a method of fabricating the same.
  • the contact electrode hole is used to turn on the pixel electrode layer and the drain metal layer.
  • the contact hole method easily brings the following problems: to ensure a certain contact contact hole is large, thereby reducing the aperture ratio, the terrain It is easy to form bubbles or the like by forming pits thereon.
  • An object of the present invention is to provide an array substrate and a manufacturing method thereof, which solve the technical problem of low aperture ratio of the array substrate in the prior art.
  • An embodiment of the present invention provides an array substrate, including:
  • the source is disposed on the flat layer and the semiconductor layer;
  • a drain disposed on the planar layer and the semiconductor layer
  • a pixel electrode layer disposed on the flat layer and the drain;
  • a second insulating layer disposed on the flat layer, the semiconductor layer, the source, and the drain.
  • the semiconductor layer comprises:
  • a doped semiconductor layer is disposed on the amorphous silicon layer.
  • the first insulating layer is made of silicon nitride and/or silicon dioxide.
  • the second insulating layer is made of silicon nitride and/or silicon dioxide.
  • the flat layer is formed by using 3D printing using a nano-powder material or a liquid insulating material.
  • the side wall surface of the drain away from the source side is inclined toward the source, and the pixel electrode layer covers the side wall surface.
  • the invention provides an array substrate comprising:
  • the source is disposed on the flat layer and the semiconductor layer;
  • a drain disposed on the planar layer and the semiconductor layer
  • a pixel electrode layer disposed on the flat layer and the drain;
  • the semiconductor layer includes:
  • the side wall surface of the drain away from the source side is inclined toward the source, and the pixel electrode layer covers the side wall surface.
  • the invention also provides a method for fabricating an array substrate, comprising the following steps:
  • a second insulating layer is deposited on the planarization layer, the semiconductor layer, the source, and the drain.
  • the flat layer is formed by using 3D printing using a nano-powder material or a liquid insulating material.
  • the side wall surface of the drain away from the source side is inclined toward the source, and the pixel electrode layer covers the side wall surface.
  • both the first insulating layer and the second insulating layer are made of silicon nitride and/or silicon dioxide.
  • the array substrate provided by the present invention provides a flat layer on the first insulating layer, and then the source and the drain are disposed on the flat layer and the semiconductor layer, without setting the source via and the drain.
  • the hole can realize the electrical connection between the source and the drain and the semiconductor layer, and directly set the pixel electrode layer on the flat layer and the drain, and the electrical connection between the drain and the pixel electrode layer can be realized without providing a via hole.
  • the effect of forming bubbles at the opening and increasing the aperture ratio is avoided, and the flat layer also increases the distance between the source, the drain and the gate electrode, and the antistatic ability can be improved.
  • FIG. 1 is a schematic structural view of an array substrate in a preferred embodiment of the present invention.
  • FIG. 2 is a flow chart of a method of fabricating an array substrate in accordance with a preferred embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a preferred embodiment of an array substrate of the present invention.
  • An array substrate of the preferred embodiment includes: a glass substrate 10, a gate electrode 20, a first insulating layer 30, a semiconductor layer 40, a flat layer 50, a source 70, a drain 60, a pixel electrode layer 80, and a second insulation. Layer 90.
  • the gate electrode 20 is disposed on the glass substrate 10.
  • a gate electrode layer is deposited on the glass substrate 10 by physical weather precipitation, and then the gate electrode layer is imaged.
  • the gate electrode 20 is formed.
  • the first insulating layer 30 is deposited on the glass substrate 10 and the gate electrode 20.
  • the first insulating layer 30 is used to insulate the gate electrode 20 and the semiconductor layer 40.
  • the inorganic insulating material such as silicon nitride or silicon oxide may be used.
  • the first insulating layer 30 is deposited on the glass substrate 10 and the gate electrode 20 by chemical weather precipitation.
  • the semiconductor layer 40 is disposed on the first insulating layer 30 and above the gate electrode 20, and includes an amorphous silicon layer deposited on the first insulating layer 30 and a doped semiconductor layer 40 disposed on the amorphous silicon layer. .
  • a layer of amorphous silicon is deposited on the first insulating layer 30 by a meteorological precipitation method, and then the amorphous silicon layer is imaged to form an amorphous silicon layer 41 at the bottom and located at the bottom.
  • the first contact portion and the second contact portion on the crystalline silicon layer 41 are doped to dope the first contact portion and the second contact portion to form the doped semiconductor layer 42.
  • the doped semiconductor layer 42 is used to electrically connect the source 70 and the drain 60 to the amorphous silicon layer 41, respectively.
  • the flat layer 50 is disposed on the first insulating layer 30, and may be an inorganic insulating material such as silicon nitride or silicon oxide, or an organic insulating material.
  • the planarization layer 50 is deposited on the first insulating layer 30 by chemical weather precipitation.
  • the flat layer 50 is formed using 3D printing using a nano-powder material or a liquid insulating material.
  • the flat layer 50 is flush with the end faces of the first contact portion and the second contact portion away from the end of the amorphous silicon layer 41, facilitating the formation of the subsequent source 70 and drain 60.
  • the source 70 and the drain 60 are both disposed on the flat layer 50 and the semiconductor layer 40. Specifically, the source 70 is disposed on the first contact portion and the flat layer 50, and the drain 60 is disposed on the second contact. And the flat layer 50.
  • the pixel electrode layer 80 is disposed on the flat layer 50 and the drain 60, and a pixel electrode is formed thereon.
  • the side wall surface of the drain 60 away from the source 70 side is inclined toward the source 70, and the pixel electrode layer 80 covers the side wall surface and covers a portion of the upper end surface of the drain 70.
  • the second insulating layer 90 is disposed on the planar layer 50, the semiconductor layer 40, the source 70, and the drain 60.
  • the second insulating layer 90 may be formed by chemical vapor deposition using a material such as silicon nitride and/or silicon dioxide.
  • the array substrate provided by the preferred embodiment is provided with a flat layer 50 on the first insulating layer 30, and then the source 70 and the drain 60 are disposed on the flat layer 50 and the semiconductor layer 40 without setting source vias and drains.
  • the electrode 70 and the drain electrode 60 are electrically connected to the semiconductor layer 40, and the pixel electrode layer 80 is directly disposed on the flat layer 50 and the drain 60.
  • the drain can be realized without providing a via hole.
  • the electrical connection between the 60 and the pixel electrode layer 80 has the beneficial effect of avoiding the formation of bubbles at the opening and increasing the aperture ratio, and the flat layer 50 also increases the distance between the source, the drain and the gate electrode 20, Improve antistatic ability.
  • FIG. 2 is a flow chart of a preferred embodiment of a method for fabricating an array substrate according to the present invention.
  • the method for fabricating the array substrate in the preferred embodiment includes the following steps:
  • step S201 when the gate electrode 20 is formed, a gate electrode layer is first deposited on the glass substrate 10 by physical weather precipitation, and then the gate electrode layer is imaged to form the gate electrode 20.
  • step S202 the first insulating layer 30 is deposited on the glass substrate 10 and the gate electrode 20 by chemical weather precipitation; the inorganic insulating material such as silicon nitride or silicon oxide may be used.
  • the semiconductor layer 40 includes an amorphous silicon layer deposited on the first insulating layer 30 and a doped semiconductor layer 42 disposed on the amorphous silicon layer.
  • a layer of amorphous silicon is deposited on the first insulating layer 30 by a meteorological precipitation method, and then the amorphous silicon layer is imaged to form an amorphous silicon layer 41 at the bottom and located at the bottom.
  • the first contact portion and the second contact portion on the crystalline silicon layer 41 are doped to dope the first contact portion and the second contact portion to form the doped semiconductor layer 42.
  • the doped semiconductor layer 40 is used to electrically connect the source 70 and the drain 60 to the amorphous silicon layer 41, respectively.
  • the flat layer 50 may be made of an inorganic insulating material such as silicon nitride or silicon oxide, or an organic insulating material.
  • the planarization layer 50 can be deposited on the first insulating layer 30 by chemical weather precipitation.
  • the flat layer 50 can also be formed by 3D printing using a nano-powder material or a liquid insulating material.
  • the flat layer 50 is flush with the end faces of the first contact portion and the second contact portion away from the end of the amorphous silicon layer 41, facilitating the formation of the subsequent source 70 and drain 60.
  • step S205 and step S206 the source electrode 70 is disposed on the first contact portion and the flat layer 50.
  • the drain is disposed on the second contact portion and the flat layer 50.
  • the pixel electrode layer 80 is formed with a plurality of pixel electrodes thereon.
  • the sidewall surface of the drain 60 away from the source 70 side is inclined toward the source 70, and the pixel electrode layer 80 covers the sidewall surface and covers a portion of the upper end surface of the drain 60, and the drain 60
  • This shape setting is advantageous for increasing the contact area of the pixel electrode layer 80 with the drain electrode 60, thereby improving conductivity.
  • the second insulating layer 90 may be formed by chemical vapor deposition using a material such as silicon nitride and/or silicon dioxide.
  • the method for fabricating the array substrate provides a planarization layer 50 on the first insulating layer 30, and then the source and the drain are disposed on the planarization layer 50 and the semiconductor layer 40, without providing a source via and
  • the drain via can electrically connect the source and the drain to the semiconductor layer 40, and directly disposed the pixel electrode layer 80 on the flat layer 50 and the drain 60, and the drain 60 can be realized without providing a via hole.
  • the electrical connection with the pixel electrode layer 80 has the beneficial effect of avoiding the formation of bubbles at the opening and increasing the aperture ratio, and the planarization layer 50 also increases the distance between the source 70, the drain 60 and the gate electrode 20, Can improve the antistatic ability.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明提供一种阵列基板及制作方法，该阵列基板包括：一玻璃基板；栅电极；第一绝缘层;半导体层；平坦层，其设置于第一绝缘层上；源极和漏极；像素电极层，其设置于平坦层以及该漏极上；第二绝缘层，其设置于平坦层、半导体层、源极以及漏极上。本发明具有避免在开孔处形成气泡、提高开口率的有益效果，并且该平坦层还增大了源极、漏极与栅电极之间的距离，可以提高抗静电能力。

Description

阵列基板及制作方法 技术领域
本发明涉及液晶显示领域，特别是涉及一种阵列基板及制作方法。
 背景技术
目前LCD显示器制造中，多采用接触孔的方式导通像素电极层与漏极金属层，接触孔的方式容易带来以下问题：为保证一定的接触性接触孔较大从而降低了开口率，地形上形成坑状容易形成气泡等。
现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种阵列基板及制作方法；以解决现有技术中阵列基板的开口率低的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种阵列基板，包括：
一玻璃基板；
栅电极，其设置于该玻璃基板上；
第一绝缘层，其沉积于该玻璃基板以及栅电极上；
半导体层，其设置于该第一绝缘层上并位于栅电极上方；
平坦层，其设置于第一绝缘层上；
源极，该源极设置于平坦层以及半导体层上；
漏极，该漏极设置于平坦层以及半导体层上；
像素电极层，其设置于平坦层以及该漏极上；
第二绝缘层，其设置于平坦层、半导体层、源极以及漏极上。
在本发明所述的阵列基板中，所述半导体层包括：
非晶硅层，其沉积于所述第一绝缘层上；
掺杂半导体层，其设置于所述非晶硅层上。
在本发明所述的阵列基板中，所述第一绝缘层采用氮化硅和/或二氧化硅。
在本发明所述的阵列基板中，所述第二绝缘层采用氮化硅和/或二氧化硅。
在本发明所述的阵列基板中，所述平坦层采用纳米粉末状材料或液态绝缘材料采用3D打印形成。
在本发明所述的阵列基板中，所述漏极的远离源极一侧的侧壁面朝向源极的方向倾斜，该像素电极层将该侧壁面覆盖。
本发明提供了一种阵列基板，包括：
一玻璃基板；
栅电极，其设置于该玻璃基板上；
第一绝缘层，其沉积于该玻璃基板以及栅电极上；
半导体层，其设置于该第一绝缘层上并位于栅电极上方；
平坦层，其设置于第一绝缘层上；
源极，该源极设置于平坦层以及半导体层上；
漏极，该漏极设置于平坦层以及半导体层上；
像素电极层，其设置于平坦层以及该漏极上；
第二绝缘层，其设置于平坦层、半导体层、源极以及漏极上；所述半导体层包括：
非晶硅层，其沉积于所述第一绝缘层上；
掺杂半导体层，其设置于所述非晶硅层上；
所述漏极的远离源极一侧的侧壁面朝向源极的方向倾斜，该像素电极层将该侧壁面覆盖。
本发明还提供了一种阵列基板的制作方法，包括以下步骤：
在玻璃基板上设置栅电极；
在玻璃基板以及栅电极上沉积第一绝缘层；
在第一绝缘层上沉积半导体层，该半导体层位于栅电极上方；
在第一绝缘层上设置平坦层；
在平坦层以及半导体层上设置源极；
在平坦层以及半导体层上设置漏极；
在平坦层以及该漏极上设置像素电极层；
在平坦层、半导体层、源极以及漏极上沉积第二绝缘层。
在本发明所述的阵列基板的制作方法中，所述平坦层采用纳米粉末状材料或液态绝缘材料采用3D打印形成。
在本发明所述的阵列基板的制作方法中，所述漏极的远离源极一侧的侧壁面朝向源极的方向倾斜，该像素电极层将该侧壁面覆盖。
在本发明所述的阵列基板的制作方法中，所述第一绝缘层以及第二绝缘层均采用氮化硅和/或二氧化硅。
 有益效果
相对于现有技术，本发明提供的阵列基板通过在第一绝缘层上设置平坦层，然后将源极以及漏极设置在该平坦层以及半导体层上，无需设置源极过孔以及漏极过孔即可实现源极、漏极与半导体层的电连接，并且直接将像素电极层设置于平坦层以及该漏极上，无需设置过孔即可实现漏极与像素电极层的电连接，具有避免在开孔处形成气泡、提高开口率的有益效果，并且该平坦层还增大了源极、漏极与栅电极之间的距离，可以提高抗静电能力。
 附图说明
图1为本发明一优选实施例中的阵列基板的结构示意图；
图2为本发明一优选实施例中阵列基板的制作方法的流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的阵列基板的优选实施例的结构示意图。本优选实施例的一种阵列基板，包括：玻璃基板10、栅电极20、第一绝缘层30、半导体层40、平坦层50、源极70、漏极60、像素电极层80以及第二绝缘层90。
其中，该栅电极20设置于该玻璃基板10上，形成该栅电极20时，先采用物理气象沉淀法在玻璃基板10上沉积形成栅电极层，然后对该栅电极层进行图像化处理，从而形成该栅电极20。
该第一绝缘层30沉积于该玻璃基板10以及栅电极20上，该第一绝缘层30用于将栅电极20以及半导体层40绝缘开，其可以采用氮化硅、氧化硅等无机绝缘材料；该第一绝缘层30采用化学气象沉淀法沉积于该玻璃基板10以及该栅电极20上。
该半导体层40设置于该第一绝缘层30上并位于栅电极20上方，其包括沉积于第一绝缘层30上的非晶硅层以及设置于该非晶硅层上的掺杂半导体层40。制作该半导体层40时，先采用气象沉淀法在第一绝缘层30上沉积一层非晶硅，然后对该一层非晶硅进行图像化处理形成位于底部的非晶硅层41以及位于非晶硅层41上的第一接触部以及第二接触部，并对该第一接触部以及第二接触部进行掺杂，以形成掺杂半导体层42。该掺杂半导体层42用于将源极70以及漏极60分别与非晶硅层41电连接。
该平坦层50设置于第一绝缘层30上，其可以采用氮化硅、氧化硅等无机绝缘材料，也可以采用有机绝缘材料。该平坦层50采用化学气象沉淀法沉积于该第一绝缘层30上。该平坦层50采用纳米粉末状材料或液态绝缘材料采用3D打印形成。
该平坦层50与该第一接触部以及第二接触部的远离该非晶硅层41的一端的端面齐平，便于后续的源极70以及漏极60的形成。
该源极70和漏极60均设置于平坦层50以及半导体层40上，具体地，该源极70设置于该第一接触部以及平坦层50上，该漏极60设置于该第二接触部以及该平坦层50上。
该像素电极层80设置于平坦层50以及该漏极60上，其上形成有像素电极。优选地，漏极60的远离源极70一侧的侧壁面朝向源极70的方向倾斜，该像素电极层80将该侧壁面覆盖并覆盖该漏极70的上端面的部分。
该第二绝缘层90设置于于平坦层50、半导体层40、源极70以及漏极60上。该第二绝缘层90可以采用氮化硅和/或二氧化硅等材料进行化学气相沉淀形成。
本优选实施例提供的阵列基板通过在第一绝缘层30上设置平坦层50，然后将源极70以及漏极60设置在该平坦层50以及半导体层40上，无需设置源极过孔以及漏极过孔即可实现源极70、漏极60与半导体层40的电连接，并且直接将像素电极层80设置于于平坦层50以及该漏极60上，无需设置过孔即可实现漏极60与像素电极层80的电连接，具有避免在开孔处形成气泡、提高开口率的有益效果，并且该平坦层50还增大了源极、漏极与栅电极20之间的距离，可以提高抗静电能力。
请参照图2，图2为本发明的阵列基板的制作方法优选实施例的流程图。本优选实施例中的阵列基板的制作方法包括以下步骤：
S201、在玻璃基板上设置栅电极；
S202、在玻璃基板以及栅电极上沉积第一绝缘层；
S203、在第一绝缘层上沉积半导体层，该半导体层位于栅电极上方；
S204、在第一绝缘层上设置平坦层；
S205、在平坦层以及半导体层上设置源极；
S206、在平坦层以及半导体层上设置漏极；
S207、在平坦层以及该漏极上设置像素电极层；
S208、在平坦层、半导体层、源极以及漏极上沉积第二绝缘层。
下面对该阵列基板的制作方法的各个步骤进行详细的说明。
在步骤S201中，形成该栅电极20时，先采用物理气象沉淀法在玻璃基板10上沉积形成栅电极层，然后对该栅电极层进行图像化处理，从而形成该栅电极20。
在步骤S202中，该第一绝缘层30采用化学气象沉淀法沉积于该玻璃基板10以及该栅电极20上；其可以采用氮化硅、氧化硅等无机绝缘材料。
在步骤S203中，该半导体层40包括沉积于第一绝缘层30上的非晶硅层以及设置于该非晶硅层上的掺杂半导体层42。制作该半导体层40时，先采用气象沉淀法在第一绝缘层30上沉积一层非晶硅，然后对该一层非晶硅进行图像化处理形成位于底部的非晶硅层41以及位于非晶硅层41上的第一接触部以及第二接触部，并对该第一接触部以及第二接触部进行掺杂，以形成掺杂半导体层42。该掺杂半导体层40用于将源极70以及漏极60分别与非晶硅层41电连接。
在步骤S204中，该平坦层50可以采用氮化硅、氧化硅等无机绝缘材料，也可以采用有机绝缘材料。该平坦层50可以采用化学气象沉淀法沉积于该第一绝缘层30上。该平坦层50也可以采用纳米粉末状材料或液态绝缘材料采用3D打印形成。该平坦层50与该第一接触部以及第二接触部的远离该非晶硅层41的一端的端面齐平，便于后续的源极70以及漏极60的形成。
在步骤S205以及步骤S206中，该源极70设置于该第一接触部以及平坦层50上，该漏极设置于该第二接触部以及该平坦层50上。
在步骤S207中，该像素电极层80其上形成有多个像素电极。优选地，漏极60的远离源极70一侧的侧壁面朝向源极70的方向倾斜，该像素电极层80将该侧壁面覆盖并覆盖该漏极60的上端面的部分，漏极60的这种形状设置有利于提高该像素电极层80与该漏极60的接触面积，从而提高导电性。
在步骤S208中，该第二绝缘层90可以采用氮化硅和/或二氧化硅等材料进行化学气相沉淀形成。
本优选实施例提供的阵列基板的制作方法通过在第一绝缘层30上设置平坦层50，然后将源极以及漏极设置在该平坦层50以及半导体层40上，无需设置源极过孔以及漏极过孔即可实现源极、漏极与半导体层40的电连接，并且直接将像素电极层80设置于于平坦层50以及该漏极60上，无需设置过孔即可实现漏极60与像素电极层80的电连接，具有避免在开孔处形成气泡、提高开口率的有益效果，并且该平坦层50还增大了源极70、漏极60与栅电极20之间的距离，可以提高抗静电能力。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种阵列基板，其包括：
    一玻璃基板；
    栅电极，其设置于该玻璃基板上；
    第一绝缘层，其沉积于该玻璃基板以及栅电极上；
    半导体层，其设置于该第一绝缘层上并位于栅电极上方；
    平坦层，其设置于第一绝缘层上；
    源极，该源极设置于平坦层以及半导体层上；
    漏极，该漏极设置于平坦层以及半导体层上；
    像素电极层，其设置于平坦层以及该漏极上；
    第二绝缘层，其设置于平坦层、半导体层、源极以及漏极上。
  2. 根据权利要求1所述的阵列基板，其中，所述半导体层包括：
    非晶硅层，其沉积于所述第一绝缘层上；
    掺杂半导体层，其设置于所述非晶硅层上。
  3. 根据权利要求1所述的阵列基板，其中，所述第一绝缘层采用氮化硅和/或二氧化硅。
  4. 根据权利要求1所述的阵列基板，其中，所述第二绝缘层采用氮化硅和/或二氧化硅。
  5. 根据权利要求1所述的阵列基板，其中，所述平坦层采用纳米粉末状材料或液态绝缘材料采用3D打印形成。
  6. 根据权利要求1所述的阵列基板，其中，所述漏极的远离源极一侧的侧壁面朝向源极的方向倾斜，该像素电极层将该侧壁面覆盖。
  7. 一种阵列基板，其包括：
    一玻璃基板；
    栅电极，其设置于该玻璃基板上；
    第一绝缘层，其沉积于该玻璃基板以及栅电极上；
    半导体层，其设置于该第一绝缘层上并位于栅电极上方；
    平坦层，其设置于第一绝缘层上；
    源极，该源极设置于平坦层以及半导体层上；
    漏极，该漏极设置于平坦层以及半导体层上；
    像素电极层，其设置于平坦层以及该漏极上；
    第二绝缘层，其设置于平坦层、半导体层、源极以及漏极上；所述半导体层包括：
    非晶硅层，其沉积于所述第一绝缘层上；
    掺杂半导体层，其设置于所述非晶硅层上；
    所述漏极的远离源极一侧的侧壁面朝向源极的方向倾斜，该像素电极层将该侧壁面覆盖。
  8. 一种阵列基板的制作方法，其包括以下步骤：
    在玻璃基板上设置栅电极；
    在玻璃基板以及栅电极上沉积第一绝缘层；
    在第一绝缘层上沉积半导体层，该半导体层位于栅电极上方；
    在第一绝缘层上设置平坦层；
    在平坦层以及半导体层上设置源极；
    在平坦层以及半导体层上设置漏极；
    在平坦层以及该漏极上设置像素电极层；
    在平坦层、半导体层、源极以及漏极上沉积第二绝缘层。
  9. 根据权利要求8所述的阵列基板的制作方法，其中，所述平坦层采用纳米粉末状材料或液态绝缘材料采用3D打印形成。
  10. 根据权利要求8所述的阵列基板的制作方法，其中，所述漏极的远离源极一侧的侧壁面朝向源极的方向倾斜，该像素电极层将该侧壁面覆盖。
  11. 根据权利要求8所述的阵列基板的制作方法，其中，所述第一绝缘层以及第二绝缘层均采用氮化硅和/或二氧化硅。
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