WO2014026342A1 - 一种基于双电层电容的晶体管及其应用 - Google Patents

一种基于双电层电容的晶体管及其应用 Download PDF

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WO2014026342A1
WO2014026342A1 PCT/CN2012/080192 CN2012080192W WO2014026342A1 WO 2014026342 A1 WO2014026342 A1 WO 2014026342A1 CN 2012080192 W CN2012080192 W CN 2012080192W WO 2014026342 A1 WO2014026342 A1 WO 2014026342A1
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electric double
dielectric layer
double layer
layer capacitor
based transistor
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PCT/CN2012/080192
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English (en)
French (fr)
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戴明志
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中国科学院宁波材料技术与工程研究所
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Priority to PCT/CN2012/080192 priority Critical patent/WO2014026342A1/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel

Definitions

  • the invention belongs to the field of microelectronics, and particularly relates to a transistor based on an electric double layer capacitor and an application thereof.
  • Transistors are an important part of large-scale integrated circuits. Among them, field effect transistors are a very important class of transistors, thin film transistors ( Thin-film transistors , TFT It is an important class of semiconductor devices. Due to its wide application value in the fields of flat panel display and sensors, it has attracted the interest of scientists at home and abroad. K. Nomura and other researchers are entitled Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors ( Nature Materials , 432 , 488-492 , 2004 A full transparent TFT with an IGZO (indium gallium zinc oxide) film as a channel is disclosed in the literature. The advantage is that it is a low temperature process, which can be fabricated on inexpensive substrates such as glass and plastic in a large area, but its disadvantage is that the electron mobility is less than 10 Cm 2 /(V ⁇ s).
  • IGZO indium gallium zinc oxide
  • TFTs use SiO 2 or the like as the gate dielectric, and their dielectric constant ⁇ is low, resulting in weak gate/channel coupling, channel carrier concentration of up to 10 12 ⁇ 10 13 cm -2 , and unit capacitance is also compared.
  • Small (200 nm thick thermally grown SiO 2 has a unit capacitance of only 17 nF/cm 2 ), resulting in a thin film transistor operating voltage typically greater than 10 V.
  • the existing TFT generally adopts a gate dielectric having a high dielectric constant ⁇ , and the effect of lowering the operating voltage is achieved by increasing the channel capacitance.
  • JB Kim et al. proposed a document in the literature entitled High-Performance InGaZnO Thin-Film Transistors with High-k Amorphous Ba 0.5 Sr 0.5 TiO 3 Gate Insulator ( Appl. Phys. Lett. 93 , 242111 , 2008 ).
  • High ⁇ TFTs can operate down to 3 V. H. Xu et al.
  • TFT Electric-Double-Layer
  • EDL Electric-Double-Layer
  • the device's gate electrode/channel coupling is extremely strong, resulting from its large capacitance value, which is much larger than the traditional dielectric unit capacitance value by at least an order of magnitude. Due to its large capacitance value, even with a reduced operating voltage, it has a very high carrier concentration (10 14 cm -2 ).
  • a typical structure of this type of TFT is shown in Figure 1.
  • TFTs based on EDL structure mainly studied in the world use organic materials as insulating dielectrics to obtain TFT double-layer capacitors.
  • JH Cho et al. proposed an ionic liquid and copolymer in the literature titled Printable Ion-Gel Gate Dielectrics for Low-Voltage Polymer Thin-Film Transistors on Plastic (Nature Materials, 7, 900-906, 2008).
  • the composition of the ion gel is a gate dielectric, and a TFT having a semiconductor of poly-3-hexylthiophene or the like has a capacitance of more than 1 ⁇ F/cm 2 .
  • Styrene sulfonic acid is a semiconductor electric double layer thin film transistor having an electric double layer capacitance of 10 ⁇ F/cm 2 .
  • TFTs fabricated using organic double-layer gate dielectrics often operate at voltages of only 1.0 V to 2.0 V.
  • the use of organic matter as a medium cannot be compatible with conventional semiconductor processes, and the fabrication is complicated, and the mobility of device carriers is relatively low.
  • the present invention provides a transistor based on an electric double layer capacitor, which can improve the current switching ratio of the device, thereby improving the electrical performance of the adjusting device, and is simple to prepare.
  • a transistor based on an electric double layer capacitor comprising a substrate and a dielectric layer, wherein the dielectric layer is provided with a source region and a drain region and a channel region, and the interface between the dielectric layer and the channel region is formed with a double Electrical layer capacitance; the dielectric layer is provided with two gate electrodes, and the two gate electrodes are coplanar.
  • the two gate electrodes are coplanar with the source and drain regions, and the two gate electrodes are respectively located on both sides of the channel region.
  • the source region, the drain region and the gate electrode are all conductor materials, including metals, alloys, conductive polymers or conductive carbon nanotubes, and materials which may be used include: aluminum, copper, tungsten, molybdenum, gold, rhenium or Any combination of alloys, and Indium tin oxide (ITO) or indium gallium zinc oxide (IGZO).
  • ITO Indium tin oxide
  • IGZO indium gallium zinc oxide
  • the channel region is a semiconductor material, and the semiconductor material comprises an oxide semiconductor (such as ITO) , zinc oxide nanowires, carbon nanotubes, other organic material semiconductors or inorganic material semiconductors.
  • oxide semiconductor such as ITO
  • the source region, the drain region, the gate electrode and the channel region are all made of ITO It is made by self-assembly to form electrodes and channels by a single mask method, and the process is simple.
  • the substrate is a conductor material, a semiconductor material or an insulating material, and commonly used materials include glass, quartz, ceramic, diamond,
  • a material such as plastic, resin, paper or silicon wafer is preferably provided with a conductive layer between the substrate and the dielectric layer, and the conductive layer is made of a conductive material such as ITO or IGZO. The effect of capacitive coupling can be enhanced, making it easier for the gate electrode to regulate the channel.
  • the channel region has a length of 0.01 to 150 ⁇ m and a width of 0.001 to 1000 ⁇ m.
  • the equivalent electrical thickness is 0.1 ⁇ 500nm.
  • the dielectric layer is an insulating material such as one or more of silicon dioxide, benzocyclobutene, polyester, acrylic resin, aluminum oxide, silicon oxynitride, silicon nitride, and high ⁇ materials.
  • Insulating material preferably, the dielectric layer is porous silica, which enables the device to have an electric double layer capacitance effect, which can effectively increase the unit capacitance of the dielectric layer (from nF/cm 2 to ⁇ F/cm 2 ).
  • the actual physical thickness of the dielectric layer is 0.01 ⁇ 300 ⁇ m, and the electric double layer capacitance formed between the dielectric layer and the channel region is equivalent to the thermal growth silicon dioxide electrical unit area capacitance of 1 ⁇ 5 nm thickness, and the capacitance per unit area. It can be on the order of ⁇ F/cm 2 .
  • the minimum lateral distance between the source region or the drain region and the adjacent gate electrode is 0.01 to 100 ⁇ m.
  • the invention also proposes a temperature sensor, which is the above-mentioned electric double layer capacitor based transistor; a conductive layer is arranged between the substrate and the dielectric layer of the temperature sensor.
  • the invention also proposes a humidity sensor, which is the above-mentioned electric double layer capacitor based transistor; a conductive layer is arranged between the substrate and the dielectric layer of the humidity sensor.
  • the invention also provides a biosensor, which is the above-mentioned electric double layer capacitor-based transistor; a conductive layer is arranged between the substrate and the dielectric layer of the biosensor; the channel region of the biosensor is made of biological material ( Perceive The amount of DNA in semiconductor materials).
  • the transistor of the present invention adopts a dielectric layer having an electric double layer capacitance effect, and simultaneously introduces a planar double gate structure, which has a conventional electric double layer Under the premise of the large capacitance of the transistor, low operating voltage, and high current-carrying concentration, the current switching ratio of the device can be improved.
  • the electrical performance (threshold voltage, leakage current, etc.) of the device is adjusted to improve the electrical performance of the device.
  • the inorganic dielectric layer is compatible with conventional semiconductor processes, and the preparation is relatively simple, and the carrier mobility of the device is high.
  • Figure 1 is a schematic diagram showing the structure of an existing low-voltage-based, double-layer capacitor-based transistor.
  • FIG. 2 is a schematic structural view of an embodiment of a thin film transistor of the present invention.
  • Fig. 3(a) is a schematic view showing the electrical performance between V G1 and the on current when the thin film transistor V G2 of the present invention is zero.
  • Fig. 3(b) is a schematic view showing the electrical performance between V G2 and the on-current when the thin film transistor V G1 is 0.
  • Fig. 3(c) is a schematic view showing the electrical performance between V G1 and the on-current when the thin film transistor V G2 of the present invention has different values.
  • FIG. 4 is a schematic structural view of another embodiment of a thin film transistor of the present invention.
  • Fig. 5 is a structural schematic view of a field effect transistor of the present invention.
  • a thin film transistor based on an electric double layer capacitor includes a substrate 1; a conductive layer 2 is disposed on the substrate 1, and a conductive layer is disposed. 2
  • the upper layer is provided with a dielectric layer 3, and the dielectric layer 3 is provided with a source region 5, a drain region 6 and two gate electrodes 4a ⁇ 4b, and the left gate electrode 4a and the right gate electrode 4b are coplanar and respectively located in the dielectric layer 3
  • a channel region 7 is provided between the source region 5 and the drain region 6, and an electric double layer capacitor is formed at the interface between the dielectric layer 3 and the channel region 7.
  • the substrate 1 is made of glass, and the conductive layer 2 is made of indium tin oxide ITO;
  • the dielectric layer 3 is porous silica, and the actual physical thickness of the dielectric layer 3 is 300 ⁇ m; the electrical equivalent capacitance of the electric double layer capacitor is a thermal growth silicon dioxide electrical unit area capacitance of 1 nm thickness, and the capacitance per unit area can be achieved. On the order of ⁇ F/cm 2 ;
  • the source region 5, the drain region 6, the gate electrodes 4a-4b, and the channel region 7 are all made of indium tin oxide ITO;
  • the length of 7 is 50 ⁇ m , the width is 100 ⁇ m , and the equivalent electrical thickness is 30 nm ;
  • the minimum lateral distance between the source or drain and the adjacent gate electrode is 10 ⁇ m.
  • a porous silica (dielectric layer) is deposited by PECVD on ITO conductive glass: SiH 4 and O 2 are introduced into the reaction chamber with a degree of vacuum of 2-3 Pa (passing at 1:6 flow rate) And introducing argon gas to make the reaction chamber gas pressure of about 50 Pa and sputtering power of 100 W to deposit the silica formed on the substrate;
  • argon gas is introduced to make the reaction chamber pressure about 0.5 Pa and the sputtering power 100 W.
  • the argon gas is ionized to generate argon ions, and the argon ions are bombarded with the ITO target; the channel region of the ITO and the source region, the drain region, and the gate electrode are deposited on the dielectric layer by a mask method.
  • the dielectric layer of the present embodiment contains H + , OH - plasma.
  • the ions move to the boundary of the dielectric layer, so that a large amount of electrons are attracted to the boundary interface of the channel region, thereby forming a double electron at the interface of the dielectric layer/channel region.
  • Layer get a huge electric double layer capacitor.
  • a conductive layer is disposed between the substrate and the dielectric layer in the embodiment, and an equivalent capacitance is between the conductive layer and the two gate electrodes, and between the conductive layer and the channel region, and the conductive layer and the channel region
  • the inter-capacitance is equivalent to a thermally grown silicon dioxide electrical capacitance of about 1 nm thickness.
  • the equivalent capacitance C1 corresponding to the left gate electrode 4a and the equivalent capacitance corresponding to the right gate electrode 4b are shown.
  • the equivalent capacitance C2 corresponding to the channel region is connected in series; this is equivalent to a capacitance C2 per unit area between the dielectric layer and the channel region, and the electrical thickness of the capacitor is about 1 to 2 nm.
  • a conductive layer may not be disposed between the glass substrate of the present invention and the dielectric layer, as shown in FIG. 4, wherein the left gate electrode 4a Corresponding equivalent capacitor C4 and equivalent capacitance C5 corresponding to the right gate electrode 4b; through capacitors C4 and C5 Coupling, the gate electrode can effectively regulate the carrier concentration of the channel, thereby adjusting the threshold voltage, leakage current, current switching ratio and other electrical properties of the thin film transistor based on the electric double layer capacitor planar double gate structure of the present invention.
  • the dielectric layer of the embodiment is prepared by using an inorganic material, and has relatively good stability and reliability compared with the preparation of the organic material, and is compatible with the conventional semiconductor process line, and the preparation is relatively simple.
  • the thin film transistor based on the electric double layer capacitor has a double gate structure.
  • the present invention is based on an electric double layer capacitor thin film transistor.
  • the relationship between the on-current I DS at both ends of the source and drain and the voltage V G2 of the right gate electrode 4b is as shown in Fig. 3(b); the two figures are basically identical, indicating that the gate electrodes on both the left and right sides have the function of regulating the channel. , the function is similar.
  • the threshold voltage V TH of the thin film transistor based on the electric double layer capacitor of the present invention is 0.78V, 0.5V, 0.1V, -0.55V, respectively, and the current switch Significant regulatory changes were also made.
  • the two gate electrodes of the present invention have the function of regulating the channel, so that the gate voltage can be controlled while controlling the two gate electrodes to control the electrical characteristics of the thin film transistor to a greater extent (such as changing the threshold voltage and reducing the leakage current, Improve current switching ratio, etc.).
  • a field effect transistor based on an electric double layer capacitor includes a substrate; a conductive layer is laid on the substrate, and a dielectric layer is disposed on the conductive layer, and a source region S, a drain region D and two gates are disposed on the dielectric layer Electrode G1 ⁇ G2
  • the left gate electrode G1 and the right gate electrode G2 are coplanar and respectively located on both sides of the dielectric layer; a channel region is disposed between the source region S and the drain region D, and an electric double layer is formed at an interface between the dielectric layer and the channel region. capacitance.
  • the substrate and the conductive layer are combined with ITO conductive glass;
  • the dielectric layer is porous silica, and the actual physical thickness of the dielectric layer is 200 ⁇ m;
  • the electrical equivalent capacitance of the electric double layer capacitor is 1 nm, and the thickness is Thermally grown silicon dioxide electrical unit area capacitance, capacitance per unit area can reach the order of ⁇ F / cm 2 ;
  • the gate electrodes G1 ⁇ G2 are made of ITO, and the source region S, the drain region D and the channel region are all masked.
  • the doping process is performed on the silicon substrate; the channel region is doped with p-type boron, the source region S and the drain region D are doped with n+ type phosphorus, and the distance between the source region S and the drain region D is 50 ⁇ .
  • m width is At 100 ⁇ m, the equivalent electrical thickness of the channel region is 30 nm; the minimum lateral distance between the source or drain region and the adjacent gate electrode is 15 ⁇ m.
  • ions such as H + , OH - etc.
  • H + is driven by the voltage and migrates to the dielectric layer and the trench.
  • the interface of the channel region is concentrated at the interface of the medium to form a positron layer, which attracts high concentration electron carriers to the channel region, forming high-concentration carriers at the interface of the channel region, and forming a interface between the dielectric layer and the channel region.
  • the large capacitance of the double electron layer therefore, H + ⁇ OH - in the porous dielectric layer is the main factor leading to the electric double layer.
  • transistor dielectric layer may be used as a humidity sensor or a humidity
  • the core component of the sensor in the same humidity environment, the amount of H + ⁇ OH - plasma decomposition also changes with the ambient temperature, so the transistor with the porous dielectric layer containing H + ⁇ OH - plasma as the dielectric layer can be used as the temperature
  • the core component of a sensor or temperature sensor in the same humidity environment, the amount of H + ⁇ OH - plasma decomposition also changes with the ambient temperature, so the transistor with the porous dielectric layer containing H + ⁇ OH - plasma as the dielectric layer can be used as the temperature
  • the transistor acts as a sensor core component with a suitable physical and chemical transducer (such as an oxygen electrode, a phototube, a field effect transistor, a piezoelectric crystal, etc.) and a signal amplifying device to form a temperature and humidity analysis tool or system as a sensor.
  • a suitable physical and chemical transducer such as an oxygen electrode, a phototube, a field effect transistor, a piezoelectric crystal, etc.
  • the immobilized bio-sensitive material is used as a recognition component (including enzymes, antibodies, antigens, microorganisms, cells, tissues, nucleic acids, etc.).
  • the transistor with the porous dielectric layer containing H + ⁇ OH - plasma as the dielectric layer can be used as the core component of the biosensor, with appropriate physical and chemical transducers (such as oxygen electrodes, photosensitive tubes, field effect transistors) , a piezoelectric crystal, etc.) and a signal amplifying device comprising a biosensor analysis tool or system; the biosensor has the function of a receiver and a converter.
  • the transistor of the electric double layer capacitor of the present invention or a part of other structures of the transistor can be used for a logic circuit (such as an inverter, an AND gate, OR gate, NAND gate, etc.).

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Abstract

一种基于双电层电容的晶体管，包括基板（1）；基板上铺设有介质层（3），介质层（3）上设有一源区（5）、一漏区（6）和两个栅电极（4a、4b），两个栅电极（4a、4b）共平面且分别位于介质层（3）上两侧；源区（5）和漏区（6）通过沟道区（7）隔离。本发明晶体管采用具有双电层电容效应的介质层，同时引入共平面双栅结构，在具备传统双电层电容晶体管的大电容、低工作电压、高载流浓度的优点的前提下，能够提高器件的电流开关比，使得器件的电学性能可调，从而改善器件的电学性能；同时本发明还公开了采用上述晶体管的温度传感器、湿度传感器和生物传感器。

Description

一种基于双电层电容的晶体管及其应用 Technical Field
本发明属于微电子技术领域，具体涉及一种基于双电层电容的晶体管及其应用。
Background Art
晶体管是大规模集成电路的重要部件。其中场效应晶体管是颇为重要的一类晶体管， 薄膜晶体管（ Thin-film transistors ， TFT ）是一类重要的半导体器件，由于在平板显示、传感器等领域具有广泛的应用价值，所以引起了国内外科学家们的研究兴趣。 K. Nomura 等 科研人员标题为 Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors （ Nature Materials ， 432 ， 488-492 ， 2004 ）的文献中公开了一种以 IGZO （ indium gallium zinc oxide ，铟镓锌氧化物）薄膜为沟道的全透明 TFT ，其优点是低温工艺，可以大面积制作在玻璃、塑料等廉价衬底上，但其缺点是电子迁移率小于 10 cm 2 /(V·s) 。
当代便携式电子产品要求 TFT 工作电压不宜过高，为此科学家们付出了不少努力。传统 TFT 采用 SiO2 等作为栅介质，其介电常数 κ 较低，导致栅电极 / 沟道耦合较弱，沟道载流子浓度最多在 1012~1013cm-2 ；且单位电容也比较小（ 200 nm 厚的热生长 SiO2 的单位电容只有 17nF/cm2 ），导致薄膜晶体管的工作电压一般都大于 10 V 。
故现有 TFT 通常采用高介电常数 κ 的栅介质，通过增大沟道电容，达到降低工作电压的效果。例如， J.B. Kim 等人在标题为 High-Performance InGaZnO Thin-Film Transistors with High-k Amorphous Ba0.5Sr0.5TiO3 Gate Insulator （ Appl. Phys. Lett. 93 ， 242111 ， 2008 ）的文献中 提出了一种高 κ 的 TFT ，其工作电压可降至 3 V 。 H. Xu 等 人也在标题为 Quantum Capacitance Limited Vertical Scaling of Graphene Field-Effect Transistor （ ACS Nano 5 (3) ， 2340 ， 2011 ）的文献中也 提出了一种具有量子效应的高 κ 材料的 TFT ；这些采用高介电常数 κ 栅介质的 TFT 往往需要成本较高的材料。
最近，一种基于双电层 （ Electric-Double-Layer ， EDL ）结构的 TFT 由于工作电压低（小于 2 V ），被认为是 可 用于低功率、低能耗、便携式传感器等领域的理想器件；该器件的 栅电极 / 沟道耦合作用极强，源自其 具有较大的电容值，远大于传统的介质 单位 电容值在至少一个数量级以上。由于其电容值大， 即使工作电压降低，也仍具备极高的载流子浓度（ 1014cm -2 ）。 这类 TFT 的典型结构如图 1 所示，其在绝缘介质 / 半导体界面形成 厚度仅为 1nm 的双电子层，使其具有极大的双电层电容 （ > 1 μF/cm2 ），但是其也存在由于漏电流较大导致的电流开关比较小等电学性能有待改善；对于低功率便携式传感器而言，其开关频率在赫兹量级（而非兆赫量级），故注重的是低电压与低成本，而不是开关速度，因此 这类 双电层 TFT 颇具吸引力。
目前，国际上主要研究的基于 EDL 结构的 TFT 大多采用有机物为绝缘介质以使 TFT 获得双电层电容。比如， J.H. Cho 等在标题为 Printable Ion-Gel Gate Dielectrics for Low-Voltage Polymer Thin-Film Transistors on Plastic （ Nature Materials ， 7 ， 900-906 ， 2008 ）的文献中 提出了一种以 离子液和共聚物组成的 离子凝胶为栅介质、 以聚 3- 己基噻吩等为半导体的 TFT ，其电容均大于 1 μF/cm2 。
而 O. Larsson 等研究人员在标题为 Insulator Polarization Mechanisms in Polyelectrolyte-Gated Organic Field-Effect Transistors （ Advanced Functional Materials ， 19 ， 3334-3341 ， 2009 ）提出了一种 以聚合物电解液为绝缘介质、以聚苯乙烯磺酸为半导体的双电层 薄膜晶体管，其双电层电容为 10 μF/cm2 。
采用有机物双电层栅介质研制的 TFT ，工作电压往往仅为 1.0 V~2.0 V ，但采用有机物作为介质不能与传统的半导体工艺相兼容，制造比较复杂，器件载流子的迁移率比较低。
 Technical Problem
针对现有技术所存在的上述技术缺陷，本发明提供了一种基于双电层电容的晶体管，能够提高器件的电流开关比，从而改善调整器件的 电学性能，制备简单 。
Technical Solution
一种基于双电层电容的晶体管，包括基板和介质层，所述的介质层上设有一源区和一漏区和沟道区，所述的介质层与沟道区之间界面形成有双电层电容；所述的介质层上设有两个栅电极，所述的两个栅电极共平面。
进一步地，所述的两个栅电极与源区和漏区共平面，所述的两个栅电极分别位于所述的沟道区两侧。
所述的源区、漏区和栅电极均为导体材料，包括金属、合金、导电聚合物或导电性碳纳米管，可以采用的材料包括：铝、铜、钨、钼、金、铯或其任意组合的合金，以及 铟锡氧化物（ ITO ）或 铟镓锌氧化物（ IGZO ）等。
所述的沟道区为半导体材料，所述的半导体材料包括氧化物半导体（如 ITO ） 、氧化锌纳米线、碳纳米管、其他有机材料半导体或无机材料半导体等。
优选地， 所述的源区、漏区、栅电极和沟道区均采用 ITO 制成；采用一次掩膜法自组装形成电极和沟道，工艺简单。
所述的基板为导体材料、半导体材料或绝缘材料，常用的材料包括 玻璃、 石英、陶瓷、金刚石、 塑料、树脂、纸张或硅片等材料，优选地， 所述的基板与介质层之间设有导电层， 所述的 导电层 采用导电材料，如 ITO 或 IGZO 等 ， 能够增强电容耦合的效果，使得栅电极更易于调控沟道。
所述的 沟道区的长度为 0.01~150 μ m ，宽度为 0.001~1000 μ m ，等效电学厚度为 0.1~500nm 。
所述的介质层为绝缘材料，例如二氧化硅、苯并环丁烯、聚酯、丙烯酸树脂、氧化铝、氮氧化硅、氮化硅、高 κ 材料中的一种或两种及以上的绝缘材料，优选地，所述的介质层为多孔二氧化硅，能够 使得器件具有 双电层电容效应，能有效提高 介质层 的单位电容 （ 从 nF/cm2 增加到 μF/cm2 ）。
所述的 介质层的实际物理厚度为 0.01~300 μ m ，其与沟道区之间形成的双电层电容等效于 1~5nm 厚度的热生长二氧化硅电学 单位面积 电容，单位面积电容可以达到 μF/cm2 数量级。
所述的源区或漏区与相邻栅电极的最小横向距离为 0.01~100 μ m 。
本发明还提出了一种温度传感器，所述温度传感器为上述基于双电层电容的晶体管；所述温度传感器的基板与介质层之间设有导电层。
本发明还提出了一种湿度传感器，所述湿度传感器为上述基于双电层电容的晶体管；所述湿度传感器的基板与介质层之间设有导电层。
本发明还提出了一种生物传感器，所述生物传感器为上述基于双电层电容的晶体管；所述生物传感器的基板与介质层之间设有导电层；生物传感器的沟道区采用生物材料（如感知 DNA 数量的半导体材料）。
 Advantageous Effects
本发明的有益技术效果为：
（ 1 ）本发明晶体管 采用具有双电层电容效应的 介质层， 同时引入平面双栅结构，在具备传统双电层 晶体管 的大电容、低工作电压、 高载流浓度的优点的前提下，能够提高器件的电流开关比， 使得器件的电学性能（阈值电压、漏电流等）可调，从而改善器件的电学性能。
（ 2 ）本发明晶体管 采用无机材质的介质层，可与传统的半导体工艺相兼容，制备相对比较简单，且器件的载流子的迁移率较高。
 Description of Drawings
图 1 为现有低工作电压的基于双电层电容结构的晶体管 的结构示意图。
图 2 为本发明薄膜晶体管 一种实施方式的结构示意图。
图 3(a) 为本发明薄膜晶体管 VG2 为 0 时 VG1 与导通电流间的电学性能示意图。
图 3(b) 为本发明薄膜晶体管 VG1 为 0 时 VG2 与导通电流间的电学性能示意图。
图 3(c) 为本发明薄膜晶体管 VG2 为各不同值时 VG1 与导通电流间的电学性能示意图。
图 4 为本发明薄膜晶体管 另一种实施方式的结构示意图。
图 5 为本发明场效应晶体管 的结构示意图。
 Mode for Invention
为了更为具体地描述本发明，下面结合附图及具体实施方式对本发明的技术方案及其相关原理进行详细说明。
实施例 1 ：
如图 2 所示，一种基于双电层电容的薄膜晶体管，包括基板 1 ；基板 1 上铺设有导电层 2 ，导电层 2 上铺设有介质层 3 ，介质层 3 上设有一源区 5 、一漏区 6 和两个栅电极 4a~4b ，左栅电极 4a 和右栅电极 4b 共平面且分别位于介质层 3 上两侧；源区 5 和漏区 6 之间设有沟道区 7 ，介质层 3 与沟道区 7 之间界面形成有双电层电容。
本实施方式中：基板 1 采用玻璃 ； 导电层 2 采用 铟锡氧化物 ITO ；
介质层 3 为多孔二氧化硅，且介质层 3 的实际物理厚度为 300 μ m ；双电层电容的电学等效电容为 1nm 厚度的热生长二氧化硅电学 单位面积 电容，单位面积电容可以达到 μF/cm2 数量级；
源区 5 、漏区 6 、栅电极 4a~4b 和沟道区 7 均采用 铟锡氧化物 ITO 制成； 沟道区 7 的长度为 50 μ m ，宽度为 100 μ m ，等效电学厚度为 30 nm ；
源区或漏区与相邻栅电极的最小横向距离为 10 μ m 。
本实施方式薄膜晶体管的制备方法为：
首先，在 ITO 导电玻璃上采用 PECVD 方法沉积多孔二氧化硅（介质层）：在真空度为 2-3 Pa 量级的反应腔内通入 SiH4 和 O2 （按 1:6 流量通入），并通入氩气使反应腔气压约为 50 Pa 、溅射功率为 100 W 的条件下使反应生成的 二氧化硅 在基板上进行沉积；
然后，采用直流溅射方法，再通入氩气使反应腔气压约为 0.5 Pa 、溅射功率为 100 W 的条件下使氩气电离生成氩离子，并使氩离子轰击 ITO 靶；用掩膜法在介质层上沉积 ITO 的沟道区和源区、漏区、栅电极。
本实施方式的介质层中含有 H+ 、 OH- 等离子，当施加电压，离子移动到介质层边界，使大量电子被吸引到沟道区边界界面，从而在介质层 / 沟道区界面形成双电子层，获得巨大的 双电层电容。 本实施方式基板与介质层之间设有导电层，在该导电层与两个栅电极之间、该导电层与沟道区之间都有一个等效电容，该导电层与沟道区之间电容等效于约 1nm 厚度的热生长二氧化硅电学电容。
如图 2 所示，其中 左栅电极 4a 对应的 等效电容 C1 与 右栅电极 4b 对应的 等效电容 C3 并联后，与 沟道区对应的 等效电容 C2 串联；这样就相当于，介质层与沟道区之间对应一个单位面积电容 C2 ，该电容电学厚度约为 1 ～ 2nm 厚度热生长二氧化硅的等效单位面积电容； 通过电容耦合，栅电极能够有效调控沟道的载流子浓度，从而调节本发明基于双电层电容平面双栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。
需要说明的是，本发明的玻璃基板与介质层之间可以不设置导电层，如图 4 所示， 其中 左栅电极 4a 对应的 等效电容 C4 与 右栅电极 4b 对应的 等效电容 C5 ； 通过电容 C4 与 C5 耦合，栅电极能够有效调控沟道的载流子浓度，从而调节本发明基于双电层电容平面双栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。
同时本实施方式的介质层采用无机材料制备，相对于有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施方式基于双电层电容的薄膜晶体管 具有双栅结构 ，当器件右栅电极 4b 的电压为 VG2=0V ，源漏电压 VDS=1.5V ，则本发明基于双电层电容的薄膜晶体管源漏两端的导通电流 IDS 与左栅电极 4a 的电压 VG1 的关系如图 3(a) 所示；当左栅电极 4a 的电压为 VG1=0V ，源漏电压 VDS=1.5V ，则源漏两端的导通电流 IDS 与右栅电极 4b 的电压 VG2 的关系如图 3(b) 所示； 两图基本一致，说明左右两侧的栅电极均具有调控沟道的作用，功能类似。
当改变右栅电极 4b 的电压 VG2 为 -1V 、 -0.5V 、 0V 、 0.5V ，源漏电压 VDS=1.5V ，则源漏两端的导通电流 IDS 与左栅电极 4a 的电压 VG1 的关系如图 3(c) 所示，四种情况下，本发明基于双电层电容的薄膜晶体管的阈值电压 VTH 分别为 0.78V 、 0.5V 、 0.1V 、 -0.55V ，同时电流开关比也得到显著的调控改变。
故本发明的两个栅电极都具有可以调控沟道的功能，因此可以通过改变栅电压同时控制两个栅电极，更大限度地调控薄膜晶体管的电学特性（如改变阈值电压，降低漏电流，提高电流开关比等）。
实施例 2 ：
如图 5 所示，一种基于双电层电容的场效应晶体管，包括基板；基板上铺设有导电层，导电层上铺设有介质层，介质层上设有一源区 S 、一漏区 D 和两个栅电极 G1~G2 ，左栅电极 G1 和右栅电极 G2 共平面且分别位于介质层上两侧；源区 S 和漏区 D 之间设有沟道区，介质层与沟道区之间界面形成有双电层电容。
本实施方式中，基板与导电层合并采用 ITO 导电玻璃； 介质层为多孔二氧化硅，且介质层的实际物理厚度为 200 μ m ；双电层电容的电学等效电容厚度为 1nm ，厚度的热生长二氧化硅电学 单位面积 电容，单位面积电容可以达到 μF/cm2 数量级；
栅电极 G1~G2 采用 ITO 制成， 源区 S 、漏区 D 和沟道区均采用掩膜版 在硅衬底上运用掺杂工艺制成； 沟道区为 p 型硼掺杂，源区 S 和漏区 D 为 n+ 型磷掺杂，源区 S 与漏区 D 之间的距离为 50 μ m ，宽度为 100 μ m ，沟道区的等效电学厚度为 30 nm ；源区或漏区与相邻栅电极的最小横向距离为 15 μ m 。
本发明在生长介质层时在介质层中引入了离子（如 H+ 、 OH- 等），当在沟道区与介质层之间施加电压， H+ 会被电压驱动、迁移到介质层与沟道区界面、聚集在介质界面，形成一层正电子层，吸引了高浓度电子载流子到沟道区，形成沟道区界面的高浓度载流子，使介质层与沟道区界面形成双电子层的巨大电容，因此，多孔介质层中的 H+\OH- 为导致双电层的主要因素。同时多孔介质层中的 H+\OH- 等离子的浓度，受空气中的水汽影响而改变，因此由该种含 H+\OH- 等离子的多孔介质层为介质层的晶体管可以作为湿度传感器或者湿度传感器的核心部件；相同湿度环境下， H+\OH- 等离子的分解数量也随环境温度变化而变化，因此由该种含 H+\OH- 等离子的多孔介质层为介质层的晶体管可以作为温度传感器或者温度传感器的核心部件。晶体管作为传感器核心部件 与适当的理化换能器（如氧电极、光敏管、场效应管、压电晶体等等）及信号放大装置构成温湿度分析工具或系统作为 传感器。
另外，如果晶体管中的沟道区采用生物材料（如感知 DNA 数量的半导体材料）， 由固定化的生物敏感材料作识别元件（包括 酶 、 抗体 、 抗原 、 微生物 、 细胞 、 组织 、 核酸 等生物活性物质）， 那么由该种含 H+\OH- 等离子的多孔介质层为介质层的晶体管可以用作生物传感器的核心部件， 与适当的理化换能器（如氧电极、光敏管、场效应管、压电晶体等等）及信号放大装置构成的 生物传感器 分析工具或系统；该种生物传感器或具有接收器与转换器的功能。
需要说明的是，以本发明双电层电容的晶体管，或者以该晶体管的部分其他结构（如去掉一栅极的平面单栅结构），可以用于逻辑电路（如反相器、与门、或门、与非门等）。
以上所述的实施例对本发明的技术方案和有益效果进行了详细说明，应理解的是以上所述仅为本发明的具体实施例，并不用于限制本发明，凡在本发明的原则范围内所做的任何修改和改进等，均应包含在本发明的保护范围之内。

Claims (34)

  1. 一种基于双电层电容的晶体管，包括基板和介质层，所述的介质层上设有一源区、一漏区和沟道区，所述的介质层与沟道区之间界面形成有双电层电容；其特征在于：所述的介质层上设有两个栅电极，所述的两个栅电极共平面。
  2. 根据权利要求 1 所述的基于双电层电容的晶体管，其特征在于：所述的两个栅电极与源区和漏区共平面，所述的两个栅电极分别位于所述的沟道区两侧。
  3. 根据权利要求 1 所述的基于双电层电容的晶体管，其特征在于：所述的源区、漏区和栅电极均为导体材料，所述的沟道区为半导体材料，所述介质层是绝缘材料。
  4. 根据权利要求 3 所述的基于双电层电容的晶体管，其特征在于：所述的导体材料包括金属、合金、导电聚合物或导电性碳纳米管，所述的半导体材料包括氧化物半导体、氧化锌纳米线、碳纳米管。
  5. 根据权利要求 1 所述的基于双电层电容的晶体管，其特征在于：所述基板的材料为导体材料、半导体材料或绝缘材料。
  6. 根据权利要求 5 所述的基于双电层电容的晶体管，其特征在于：所述的基板材料为玻璃、石英、陶瓷、金刚石、纸张、硅片、塑料或树脂。
  7. 根据权利要求 1-6 任一权利要求所述的基于双电层电容的晶体管，其特征在于：所述的基板与介质层之间设有导电层。
  8. 根据权利要求 1-6 任一权利要求所述的基于双电层电容的晶体管，其特征在于： 所述的 沟道区的长度为 0.01~150 μ m ，宽度为 0.001~1000 μ m ，等效电学厚度与实际物理厚度为 0.1~500nm 。
  9. 根据权利要求 1-6 任一权利要求所述的基于双电层电容的晶体管，其特征在于： 所述的 介质层为多孔绝缘材料，其实际物理厚度为 0.01~300 μ m 。
  10. 根据权利要求 9 所述的基于双电层电容的晶体管，其特征在于，所述的介质层为二氧化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂、氧化铝、氮氧化硅或高 κ 材料。
  11. 根据权利要求 1 所述的基于双电层电容的晶体管，其特征在于：所述的双电层电容等效于 1 ～ 5nm 厚度的热生长二氧化硅电学单位面积电容 。
  12. 根据权利要求 1 所述的基于双电层电容的晶体管，其特征在于：所述的源区或漏区与相邻栅电极的最小横向距离为 0.01~100 μ m 。
  13. 根据权利要求 1-6 任一权利要求所述的基于双电层电容的晶体管，其特征在于：所述晶体管为薄膜晶体管。
  14. 一种温度传感器，其特征在于：所述温度传感器为权利要求 1-6 任一权利要求所述的基于双电层电容的晶体管。
  15. 根据权利要求 14 所述的温度传感器，其特征在于，所述温度传感器的基板与介质层之间设有导电层。
  16. 根据权利要求 14 所述的温度传感器，其特征在于： 所述的 沟道区的长度为 0.01~150 μ m ，宽度为 0.001~1000 μ m ，等效电学厚度为 0.1~500nm 。
  17. 根据权利要求 14 所述的温度传感器，其特征在于： 所述的 介质层为多孔绝缘材料，其实际物理厚度为 0.01~300 μ m 。
  18. 根据权利要求 17 所述的温度传感器，其特征在于，所述的介质层为二氧化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂、氧化铝、氮氧化硅或高 κ 材料。。
  19. 根据权利要求 14 所述的温度传感器，其特征在于：所述的双电层电容等效于 1 ～ 5nm 厚度的热生长二氧化硅电学单位面积电容 。
  20. 根据权利要求 14 所述的温度传感器，其特征在于：所述的源区或漏区与相邻栅电极的最小横向距离为 0.01~100 μ m 。
  21. 一种湿度传感器，其特征在于：所述湿度传感器为权利要求 1-6 任一权利要求所述的基于双电层电容的晶体管。
  22. 根据权利要求 21 所述的湿度传感器，其特征在于，所述湿度传感器的基板与介质层之间设有导电层。
  23. 根据权利要求 21 所述的湿度传感器，其特征在于： 所述的 沟道区的长度为 0.01~150 μ m ，宽度为 0.001~1000 μ m ，等效电学厚度为 0.1~500nm 。
  24. 根据权利要求 21 所述的湿度传感器，其特征在于： 所述的 介质层为多孔绝缘材料，其实际物理厚度为 0.01~300 μ m 。
  25. 根据权利要求 24 所述的湿度传感器，其特征在于，所述的介质层为二氧化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂、氧化铝、氮氧化硅或高 κ 材料。
  26. 根据权利要求 21 所述的湿度传感器，其特征在于：所述的双电层电容等效于 1 ～ 5nm 厚度的热生长二氧化硅电学单位面积电容 。
  27. 根据权利要求 21 所述的湿度传感器，其特征在于：所述的源区或漏区与相邻栅电极的最小横向距离为 0.01~100 μ m 。
  28. 一种生物传感器，其特征在于：所述生物传感器为权利要求 1-6 任一权利要求所述的基于双电层电容的晶体管；所述的沟道区采用生物材料。
  29. 根据权利要求 28 所述的生物传感器，其特征在于，所述生物传感器的基板与介质层之间设有导电层。
  30. 根据权利要求 28 所述的生物传感器，其特征在于： 所述的 沟道区的长度为 0.01~150 μ m ，宽度为 0.001~1000 μ m ，等效电学厚度为 0.1~500nm 。
  31. 根据权利要求 28 所述的生物传感器，其特征在于： 所述的 介质层为多孔绝缘材料，其实际物理厚度为 0.01~300 μ m 。
  32. 根据权利要求 31 所述的生物传感器，其特征在于，所述的介质层为二氧化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂、氧化铝、氮氧化硅或高 κ 材料。
  33. 根据权利要求 28 所述的生物传感器，其特征在于：所述的双电层电容等效于 1 ～ 5nm 厚度的热生长二氧化硅电学单位面积电容 。
  34. 根据权利要求 28 所述的生物传感器，其特征在于：所述的源区或漏区与相邻栅电极的最小横向距离为 0.01~100 μm 。
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