WO2017159401A1 - 液体を用いて基板に対するチップ部品のアライメントを行う方法 - Google Patents

液体を用いて基板に対するチップ部品のアライメントを行う方法 Download PDF

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Publication number
WO2017159401A1
WO2017159401A1 PCT/JP2017/008482 JP2017008482W WO2017159401A1 WO 2017159401 A1 WO2017159401 A1 WO 2017159401A1 JP 2017008482 W JP2017008482 W JP 2017008482W WO 2017159401 A1 WO2017159401 A1 WO 2017159401A1
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Prior art keywords
region
liquid
area
chip component
mounting
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Application number
PCT/JP2017/008482
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English (en)
French (fr)
Japanese (ja)
Inventor
真也 菊田
星野　聡彦
誉史 福島
小柳　光正
康旭 李
Original Assignee
東京エレクトロン株式会社
国立大学法人東北大学
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Application filed by 東京エレクトロン株式会社, 国立大学法人東北大学 filed Critical 東京エレクトロン株式会社
Priority to CN201780015668.5A priority Critical patent/CN108780760B/zh
Priority to JP2018505811A priority patent/JP6600922B2/ja
Priority to US16/085,205 priority patent/US10553455B2/en
Priority to KR1020187026430A priority patent/KR102349884B1/ko
Publication of WO2017159401A1 publication Critical patent/WO2017159401A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02307—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02343—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a liquid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
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    • H01L21/67248—Temperature monitoring
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08237—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80004—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a permanent auxiliary member being left in the finished device, e.g. aids for protecting the bonding area during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012—Aligning
    • H01L2224/80143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques

Definitions

  • the chip component and the mounting area usually have a rectangular planar shape extending in one direction.
  • the chip component may be displaced with respect to the mounting region.
  • the wettability of the first region with respect to the liquid is higher than the wettability of the second region with respect to the liquid.
  • the first region is provided symmetrically with respect to the first center line orthogonal to the long side of the mounting region, and is provided symmetrically with respect to the second center line orthogonal to the short side of the mounting region. And has a plurality of partial regions each having a rectangular shape. In the step of supplying the liquid, the liquid is supplied to the first region.
  • the liquid is divided into a plurality of liquid masses by being supplied to the plurality of partial regions. Since the chip component is held by the plurality of liquid masses, the inclination of the chip component during mounting is reduced. Therefore, according to this method, the accuracy of alignment of the chip component with respect to the mounting area is improved.
  • the liquid is supplied to the first area constituting the lyophilic area in the chip part.
  • the accuracy of alignment of the chip component with respect to the mounting area is improved.
  • the first region is made of silicon oxide, and the liquid may contain dilute hydrofluoric acid.
  • the chip component and the substrate are bonded to each other after the liquid is evaporated by silicon oxide dissolved by dilute hydrofluoric acid.
  • the liquid may include water and / or ethylene glycol.
  • the mounting area 10 m includes a first area 101 and a second area 102.
  • the second area 102 is an area other than the first area 101 in the mounting area 10m.
  • the first region 101 has higher wettability than the wettability of the second region 102 with respect to the liquid LQ. That is, the first region 101 is a lyophilic region having lyophilicity, and the second region 102 is a lyophobic region having lyophobic properties. Further, the surface 10a provides a lyophobic region having lyophobic properties even around the mounting region 10m.
  • “lyophilic” means “hydrophilic” for water
  • “lyophobic” means “hydrophobic” for water.
  • the first region 101 is made of, for example, silicon oxide.
  • region 102 and the surface 10a is formed from polytetrafluoroethylene, for example.
  • a mask that covers the first region 101 is formed on the surface of the base material made of silicon oxide, and the surface is coated with polytetrafluoroethylene, and then the mask is lifted off. . Thereby, the board
  • FIG. 4 is a diagram illustrating a second step of a method for aligning chip components with respect to a substrate using a liquid according to an embodiment.
  • the second step is performed after the liquid LQ is supplied onto the first region 101.
  • the chip component 12 is placed on the liquid LQ.
  • the first area 121 includes a plurality of partial areas 121p provided in the same layout as the plurality of partial areas 101p.
  • the shape of each of the plurality of partial regions 121p substantially matches the shape of each of the plurality of partial regions 101p, and the area of each of the plurality of partial regions 121p is substantially the same as the area of each of the plurality of partial regions 101p. I'm doing it.
  • the plurality of partial regions 121p are in contact with the long side 12L and the short side 12S of the surface 12a and have a square shape. Similar to the first region 101, the first region 121 may be formed of, for example, silicon oxide.
  • the chip component 12 when the chip component 12 is disposed on the liquid LQ, the chip component 12 is automatically aligned with the mounting area 10m by capillary force.
  • the chip component 12 Since the amount of liquid that protrudes to the side of the chip component 12 at a location along the long side 10L of the mounting area 10m increases, the resistance force in the direction orthogonal to the long side 12L of the surface 12a of the chip component 12 increases, The driving force in the direction orthogonal to the long side 12L of the surface 12a of the chip component 12 may be larger. Furthermore, since the supplied liquid LQ forms a single liquid mass having an upwardly convex surface shape on the mounting area 10m, the chip component 12 can be disposed in an inclined state on the liquid LQ. When the chip component 12 is disposed on the liquid LQ in a tilted state, the chip component 12 may slide down from the liquid LQ in a tilted state and come into contact with the substrate 10. Thereby, sufficient capillary force does not work on the chip component 12. As a result, the positional deviation between the mounting area 10m and the chip component 12 cannot be eliminated.
  • the amount of liquid protruding from the side of the chip component 12 at a location along the long side 10L of the mounting area 10m is reduced, and the resistance force in the direction orthogonal to the long side 12L of the surface 12a of the chip component 12 is reduced.
  • the difference between the driving force in the direction orthogonal to the long side 12L of the surface 12a of the chip component 12 and the driving force in the direction orthogonal to the short side 12S of the surface 12b of the chip component 12 is reduced.
  • the first region 101 is provided symmetrically with respect to both the first center line CA and the second center line CB, the driving force for the chip component 12 is relative to the first center line CA. And symmetrically with respect to the second center line CB.
  • the chip component 12 When the liquid LQ evaporates, the chip component 12 is directly disposed on the mounting area 10m as shown in FIG. Thereafter, the chip component 12 may be fixed to the substrate 10 using any bonding material.
  • the chip component 12 and the substrate 10 are evaporated after the liquid LQ is evaporated by silicon oxide dissolved by dilute hydrofluoric acid. Are joined.
  • the second step is executed.
  • the mounting area 10m of the substrate 10 is disposed on the liquid LQ.
  • the entire mounting area 10m of the substrate 10 may be configured as a lyophilic area.
  • the mounting area 10m may have the first area 101 provided in the layout shown in FIG. In this case, the mounting area 10m of the substrate 10 is disposed on the liquid LQ so that the first area 101 is in contact with the liquid LQ.
  • each of the plurality of partial regions 121p has a square shape
  • the difference with the sum of the lengths is further reduced.
  • the difference between the resistance force in the direction orthogonal to the long side 12L of the chip component 12 and the resistance force in the direction orthogonal to the short side 12S of the chip component 12 is reduced, and orthogonal to the long side 12L of the chip component 12
  • the difference between the driving force in the direction and the driving force in the direction orthogonal to the short side 12S of the chip component 12 is reduced. Therefore, the accuracy of alignment of the chip component 12 with respect to the mounting area 10m is further improved.
  • the pattern of the lyophilic area and the lyophobic area in the mounting area 10m may be the pattern shown in FIG. 9 or FIG. That is, as shown in FIG. 9, the plurality of partial regions 101p may not be in contact with the long side 10L of the mounting region 10m. Further, the plurality of partial regions 101p may not be in contact with the short side 10S of the mounting region 10m. Further, the partial region 101p may be provided at a location including a position where the first center line CA and the second center line CB are orthogonal to each other.
  • connection region 101c may be formed so that there is no isolated partial region 101p, that is, a partial region 101p that is not connected to another partial region 101p, and all the partial regions 101p are connected to each other. It may be formed as follows. Further, as shown in FIG. 10, two or more partial regions 101p may be provided on each of one side and the other side with respect to the first center line CA. Furthermore, two or more partial regions 101p may be provided on each of one side and the other side with respect to the second center line CB.
  • the pattern of the lyophilic area and the lyophobic area on the surface 12a of the chip component 12 may be the pattern shown in FIG. 11 or FIG. That is, as shown in FIG. 11, the plurality of partial regions 121p may not be in contact with the long side 12L of the surface 12a. The plurality of partial regions 121p may not be in contact with the short side 12S of the surface 12a. Further, the partial region 121p may be provided at a location including a position where the first center line CC and the second center line CD are orthogonal to each other. The first region 121 may include a connection region 121c that connects the plurality of partial regions 121p.
  • connection region 121c is a lyophilic region and can be formed from the same material as the partial region 121p. Further, the connection region 121c has a width narrower than the length of the shortest side of the plurality of partial regions 121p. According to the connection area 121c, even if the liquid LQ is insufficient on a part of the plurality of partial areas 121p, the liquid LQ is supplemented to the part from the other partial areas 121p via the connection area 121c. . Also, as shown in FIG. 12, two or more partial regions 121p may be provided on each of one side and the other side with respect to the first center line CC. Furthermore, two or more partial regions 121p may be provided on each of one side and the other side with respect to the second center line CD.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
PCT/JP2017/008482 2016-03-17 2017-03-03 液体を用いて基板に対するチップ部品のアライメントを行う方法 WO2017159401A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201780015668.5A CN108780760B (zh) 2016-03-17 2017-03-03 使用液体进行的芯片部件相对于基板的校准的方法
JP2018505811A JP6600922B2 (ja) 2016-03-17 2017-03-03 液体を用いて基板に対するチップ部品のアライメントを行う方法
US16/085,205 US10553455B2 (en) 2016-03-17 2017-03-03 Method for aligning chip components relative to substrate by using liquid
KR1020187026430A KR102349884B1 (ko) 2016-03-17 2017-03-03 액체를 사용해서 기판에 대한 칩 부품의 얼라인먼트를 행하는 방법

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JP2016053712 2016-03-17
JP2016-053712 2016-03-17

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WO2017159401A1 true WO2017159401A1 (ja) 2017-09-21

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US (1) US10553455B2 (ko)
JP (1) JP6600922B2 (ko)
KR (1) KR102349884B1 (ko)
CN (1) CN108780760B (ko)
TW (1) TWI708313B (ko)
WO (1) WO2017159401A1 (ko)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006077739A1 (ja) * 2004-12-28 2006-07-27 Mitsumasa Koyanagi 自己組織化機能を用いた集積回路装置の製造方法及び製造装置
JP2011517104A (ja) * 2008-04-09 2011-05-26 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ 基板によるチップの自己組立
JP2011192663A (ja) * 2010-03-11 2011-09-29 Tokyo Electron Ltd 実装方法及び実装装置
JP2013251405A (ja) * 2012-05-31 2013-12-12 Tadatomo Suga 金属領域を有する基板の接合方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6261337A (ja) * 1985-09-11 1987-03-18 Fuji Electric Co Ltd 加圧接触型半導体装置
JPH057127A (ja) 1991-06-26 1993-01-14 Kawasaki Steel Corp 可変遅延回路
JP3193198B2 (ja) * 1993-07-30 2001-07-30 京セラ株式会社 半導体素子の実装方法
US5904545A (en) * 1993-12-17 1999-05-18 The Regents Of The University Of California Apparatus for fabricating self-assembling microstructures
SG91870A1 (en) * 2000-05-26 2002-10-15 Casem Asia Pte Ltd Method and device for bleed out control in solder bonding
US6762509B2 (en) * 2001-12-11 2004-07-13 Celerity Research Pte. Ltd. Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material
JP2006135236A (ja) * 2004-11-09 2006-05-25 Seiko Epson Corp 電子デバイスの実装方法、回路基板、及び電子機器
JP4808642B2 (ja) * 2006-02-02 2011-11-02 パナソニック株式会社 電子部品の実装方法および電子部品の実装装置
JP5378707B2 (ja) * 2008-05-29 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
CN102272909B (zh) * 2008-12-13 2015-04-08 米尔鲍尔股份公司 制造电子组装的方法和设备,采用该方法或在该设备中制造的电子组装
US8580612B2 (en) * 2009-02-12 2013-11-12 Infineon Technologies Ag Chip assembly
JP5389490B2 (ja) * 2009-03-23 2014-01-15 東京エレクトロン株式会社 三次元集積回路の製造方法及び装置
JP2013187529A (ja) * 2012-03-12 2013-09-19 National Institute Of Advanced Industrial & Technology チップ部品の組立方法
JP6044885B2 (ja) * 2012-08-08 2016-12-14 パナソニックＩｐマネジメント株式会社 実装方法
EP2889900B1 (en) * 2013-12-19 2019-11-06 IMEC vzw Method for aligning micro-electronic components using an alignment liquid and electrostatic alignment as well as corresponding assembly of aligned micro-electronic components
JP6278760B2 (ja) * 2014-03-11 2018-02-14 株式会社ディスコ チップ整列方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006077739A1 (ja) * 2004-12-28 2006-07-27 Mitsumasa Koyanagi 自己組織化機能を用いた集積回路装置の製造方法及び製造装置
JP2011517104A (ja) * 2008-04-09 2011-05-26 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ 基板によるチップの自己組立
JP2011192663A (ja) * 2010-03-11 2011-09-29 Tokyo Electron Ltd 実装方法及び実装装置
JP2013251405A (ja) * 2012-05-31 2013-12-12 Tadatomo Suga 金属領域を有する基板の接合方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
T. FUKUSHIMA ET AL.: "New Heterogeneous Multi-Chip Module Integration Technology Using Self-Assembly Method", IEEE IEDM 2008, 15 December 2008 (2008-12-15), pages 1 - 4, XP055601676, ISBN: 978-1-4244-2377-4, DOI: 10.1109/IEDM.2008.4796735 *

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