WO2017152502A1 - 阵列基板及其制备方法和显示面板 - Google Patents

阵列基板及其制备方法和显示面板 Download PDF

Info

Publication number
WO2017152502A1
WO2017152502A1 PCT/CN2016/082966 CN2016082966W WO2017152502A1 WO 2017152502 A1 WO2017152502 A1 WO 2017152502A1 CN 2016082966 W CN2016082966 W CN 2016082966W WO 2017152502 A1 WO2017152502 A1 WO 2017152502A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
insulating layer
substrate
array substrate
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/082966
Other languages
English (en)
French (fr)
Inventor
孙雁飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US15/519,954 priority Critical patent/US10374062B2/en
Publication of WO2017152502A1 publication Critical patent/WO2017152502A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display panel.
  • a thin film transistor is covered with a passivation layer (PVX) 1 , and a pixel electrode 7 is disposed on the passivation layer 1 and passes through a passivation layer.
  • the via 19 in 1 is connected to the drain 8 of the thin film transistor.
  • the via 19 in the passivation layer 1 is formed by an etching process. Due to the characteristics of the etching process, the via 19 must be in the form of a small upper end and a lower end, so that the via 19 has a certain slope angle ⁇ (ie, the hole wall). The angle between the upper surface of the drain 8 and the upper surface of the substrate 9 is parallel to the upper surface of the substrate 9, so that the angle between the wall of the hole and the upper surface of the drain 8 in the figure represents the slope angle ⁇ ) . According to the existing etching process, the slope angle ⁇ is too large (that is, the via wall is close to the substrate 9), which causes the pixel electrode 7 to easily break at the via 19 (the cross in the figure), thereby failing to complete the signal transmission. And cause problems such as poor display.
  • the present invention provides an array substrate, a method for fabricating the same, and a display panel in which a via hole in an insulating layer is provided, which is caused by an excessively large slope angle of a via hole in an insulating layer of an existing array substrate.
  • the slope angle is small.
  • Embodiments of the present invention provide an array substrate including a substrate and an insulating layer on the substrate, the insulating layer including a via formed by etching, wherein
  • the insulating layer includes a plurality of stacked sub-insulating layers, the further the sub-insulation away from the substrate in the plurality of sub-insulating layers under the etching conditions for forming the via holes
  • the etch rate of the layer is larger.
  • the “etching rate” of the sub-insulating layer refers to the thickness of the sub-insulating layer which is etched away per unit time when subjected to the etching treatment”, and the greater the etching rate, the faster the sub-insulating layer is etched;
  • the etch rate of the same sub-insulating layer may be different under different etching conditions, and the etch rate of each sub-insulating layer of the present invention is required to be the farther away from the sub-insulating layer of the substrate under the same etching condition.
  • the etch rate is larger.
  • the insulating layer includes only a first sub-insulating layer and a second sub-insulating layer on a side of the first sub-insulating layer away from the substrate.
  • the etching rate of the first sub-insulating layer is The etching rate of the second sub-insulating layer is
  • the ratio of the thickness of the first sub-insulating layer to the thickness of the second sub-insulating layer is greater than or equal to 4:1.
  • the thickness of the first sub-insulating layer is And the thickness of the second sub-insulating layer is
  • each of the sub-insulating layers is a silicon nitride-containing layer; the ratio of the number of silicon-nitrogen bonds to the number of silicon-hydrogen bonds in the sub-insulating layer farther from the substrate is smaller.
  • the insulating layer is a passivation layer
  • the array substrate further includes a thin film transistor covered by the insulating layer and located on the substrate, and a pixel disposed on a side of the insulating layer away from the substrate And an electrode connected to a drain of the thin film transistor through the via hole in the insulating layer.
  • Embodiments of the present invention provide a display panel including the above array substrate.
  • Embodiments of the present invention provide a method of fabricating an array substrate, the method comprising the steps of:
  • the plurality of sub-insulating layers in the insulating layer are etched under the same etching condition to form via holes.
  • the greater the etching rate of the sub-insulating layer farther from the substrate means that in any two sub-insulating layers, the etching rate of the sub-insulating layer farther from the substrate is higher than that of the substrate.
  • the etch rate of the nearest sub-insulator layer is greater, and does not mean that different portions of the same sub-insulator layer have different etch rates.
  • the plurality of sub-insulating layers are all silicon nitride-containing layers, and the ratio of the number of silicon-nitrogen bonds to the number of silicon-hydrogen bonds in the sub-insulating layer farther from the substrate is smaller.
  • the plurality of sub-insulating layers are formed by a plasma enhanced chemical vapor deposition process, wherein a mixed gas of silane and ammonia is used as a process gas, and the following condition is satisfied in forming the plurality of sub-insulating layers. And at least one of the conditions C2:
  • the insulating layer includes at least two sub-insulating layers having different etching rates, and the higher the etching rate of the sub-insulating layer on the upper side (ie, the farther away from the substrate).
  • the inventors have found that in the case of forming via holes by etching, such vias in the insulating layer having a specific etching rate have a small slope angle, thereby facilitating the passage of the conductive structures on the insulating layer through the vias.
  • the conductive structures under the insulating layer are connected to prevent defects such as breakage of the conductive structure on the insulating layer due to excessively large slope angle of the via.
  • FIG. 1 is a schematic cross-sectional view showing a portion of a conventional array substrate including a via hole
  • FIG. 2 is a cross-sectional view showing a portion of an array substrate including a via hole according to an embodiment of the present invention
  • FIG. 3 is a scanning electron micrograph of a cross section of a portion of a conventional array substrate including a via hole;
  • FIG. 4 is a scanning electron micrograph of a cross section of a portion of an array substrate including a via hole according to an embodiment of the present invention.
  • this embodiment provides an array substrate.
  • the array substrate can be used in a liquid crystal display device, an organic light emitting diode (OLED) display device, or the like.
  • OLED organic light emitting diode
  • These display devices may have a variety of specific structures known to those skilled in the art and will not be described in detail herein.
  • the array substrate of the present embodiment includes a substrate 9 and an insulating layer on the substrate 9, the insulating layer including via holes 19 formed by etching; the insulating layer includes a plurality of stacked sub-insulating layers, in order to form the via holes 19 Under etch conditions, the etch rate of the sub-insulating layer farther away from the substrate 9 is greater.
  • an insulating layer such as the passivation layer 1 for isolating the conductive structures on the upper and lower sides thereof; and the insulating layer is provided in the insulating layer.
  • the holes 19 and the via holes 19 are used to connect the conductive structures on the upper and lower sides of the insulating layer (such as the pixel electrode 7 and the drain electrode 8 of the thin film transistor) at desired positions.
  • the insulating layer of the present invention includes a plurality of sub-insulating layers, wherein under the same etching conditions, the sub-insulating layers are etched at different rates, the upper (ie, the farther away from the substrate) The faster the sub-insulating layer of 9) is etched, that is, the etch rate of the sub-insulating layer farther away from the substrate 9 is greater.
  • a functional layer means that the insulating layer functions as a layer as a whole, and thus there is no other structure between the respective sub-insulating layers.
  • the two sub-insulating layers may be in direct contact, but the combination of the two sub-insulating layers directly contacting at a partial position is not It belongs to the insulating layer of the present invention.
  • the insulating layer includes at least two etching rates.
  • the inventors have found that in the case where the via 19 is formed by etching, such a via 19 in the insulating layer having a specific etching rate (i.e., the etching rate of the sub-insulating layer farther from the substrate 9 is larger)
  • the utility model has a small slope angle ⁇ , so that the conductive structure on the insulating layer is connected to the conductive structure under the insulating layer through the via hole 19, and the conductive structure on the insulating layer is prevented from being broken due to excessive slope angle ⁇ of the via hole 19. .
  • the insulating layer is a passivation layer 1.
  • the array substrate further includes a thin film transistor covered by the insulating layer and located on the substrate 9, and a pixel electrode 7 disposed on a side of the insulating layer (eg, the passivation layer 1) away from the substrate 9.
  • the pixel electrode 7 is connected to the drain 8 of the thin film transistor through a via 19 in the insulating layer.
  • the insulating layer of the present embodiment can be used for an array substrate of a liquid crystal display device, in which case the insulating layer is a passivation layer (PVX) 1.
  • the passivation layer 1 is overlying the thin film transistor, and the pixel electrode 7 is disposed on the passivation layer 1 and is connected to the drain 8 of the thin film transistor through the via 19 above. Since the passivation layer 1 generally has a large thickness, and the pixel electrode 7 generally has a relatively thin thickness, the pixel electrode 7 is connected to the drain electrode 8 through the via hole 19 in the passivation layer 1 (ie, the pixel electrode 7 is extended).
  • the insulating layer for example, the passivation layer 1 of the present invention makes the via angle ⁇ of the via hole 19 small, so that the pixel electrode 7 is less likely to be broken.
  • the pixel electrode 7 is disposed on the partial passivation layer 1, but the invention is not limited thereto.
  • the array substrate of the present invention may further include a gate (gate line), a gate insulating layer, an active region, a source (data line), a common electrode, and the like, as needed, and will not be described in detail herein.
  • a gate gate line
  • a gate insulating layer an active region
  • a source data line
  • a common electrode and the like, as needed, and will not be described in detail herein.
  • the array substrate of the present embodiment is not limited to the array substrate of the liquid crystal display device, and may be an array substrate of an OLED display device or the like.
  • the insulating layer in the array substrate is not limited to the passivation layer 1 as long as a via hole (for example, a via hole 19) formed by etching is provided in the insulating layer.
  • the insulating layer may also be a gate insulating layer or a flat layer. Other layers such as layers.
  • each of the sub-insulating layers is a silicon nitride-containing layer (ie, a layer including silicon nitride);
  • the ratio of the number of silicon-nitrogen bonds to the number of silicon-hydrogen bonds in the sub-insulating layer farther away from the substrate 9 is smaller.
  • the actual silicon nitride-containing layer necessarily contains silicon-nitrogen bonds (Si-N) and silicon-hydrogen bonds (Si-H).
  • Si-N silicon-nitrogen bonds
  • Si-H silicon-hydrogen bonds
  • the silicon-hydrogen bond is "impurity" to a certain extent, so the more the number of silicon-hydrogen bonds means that the more defects containing the silicon nitride layer, the easier it is to be etched, that is, engraved The greater the eclipse rate.
  • the ratio of the number of silicon-nitrogen bonds to the number of silicon-hydrogen bonds in the upper sub-insulating layer should be smaller ( That is, the fewer the silicon-nitrogen bonds and the more silicon-hydrogen bonds.
  • the silicon nitride-containing layer having a ratio of the number of silicon-nitrogen bonds to the number of silicon-hydrogen bonds can be manufactured by the same process, as long as the specific process parameters are adjusted.
  • a silicon nitride-containing layer is prepared by a plasma enhanced chemical vapor deposition (PECVD) process
  • the amount of silicon nitrogen bonds and silicon can be changed by adjusting process gas flow rate, plasma RF power (RF), temperature, pressure, and the like.
  • RF plasma RF power
  • the above sub-insulating layer is not limited to a silicon nitride-containing layer, and may be made of other materials (such as silicon oxide or silicon oxynitride); or, different sub-insulating layers may be made of different materials as long as they are engraved.
  • the etch rate meets the above requirements (ie, the etch rate of the sub-insulating layer that is farther away from the substrate 9 is larger).
  • the insulating layer includes only the first sub-insulating layer 11 and the second sub-insulating layer 12 on the side of the first sub-insulating layer 11 away from the substrate 9.
  • the insulating layer (such as the passivation layer 1) may be composed of only two sub-insulating layers 11 and 12, and under the same etching condition, the second sub-insulating layer 12 is more than the first sub-insulating layer 11 has a larger etch rate.
  • the insulating layer is optionally composed of only two sub-insulating layers.
  • the etching rate of the first sub-insulating layer 11 is The etching rate of the second sub-insulating layer 12 is
  • the insulating layer (such as the passivation layer 1) is composed of two sub-insulating layers, the etching rates of the two are optionally controlled within the above range, respectively. Good effect is to reduce the slope angle ⁇ of the via 19 .
  • the ratio of the thickness of the first sub-insulating layer 11 to the thickness of the second sub-insulating layer 12 is greater than or equal to 4:1; further optionally, the thickness of the first sub-insulating layer 11 is The thickness of the second sub-insulating layer 12 is
  • the thickness relationship of the two sub-insulation layers also has an effect on the slope angle ⁇ of the via 19 formed. It has been found that the effect of reducing the slope angle ⁇ of the via 19 can be better when the second sub-insulating layer 12 is relatively thin, between the thickness of the first sub-insulating layer 11 and the thickness of the second sub-insulating layer 12. The relationship can be as described above.
  • the insulating layer is not limited to including only two sub-insulating layers, and may further include a third sub-insulating layer, a fourth sub-insulating layer, and the like sequentially disposed on the second sub-insulating layer, as long as the sub-insulating layers are etched therein.
  • the rate meets the above requirements (ie, the etch rate of the sub-insulating layer that is farther away from the substrate 9 is larger).
  • the embodiment further provides a method for preparing the above array substrate, which includes the following steps S1 and S2.
  • Step S1 sequentially forming a plurality of sub-insulating layers stacked on the substrate 9 such that the plurality of sub-insulating layers form an insulating layer, and in the plurality of sub-insulating layers, the farther away from the sub-insulating layer of the substrate is etched The greater the rate;
  • the plurality of sub-insulating layers in the insulating layer are etched under the same etching condition to form via holes 19.
  • a plurality of stacked sub-insulating layers (such as the first sub-insulating layer 11 and the second sub-insulating layer 12) are sequentially formed, and then subjected to an etching process in the same etching condition.
  • the via holes 19 are formed in the plurality of sub-insulating layers of the insulating layer. Since the etching rate of each sub-insulating layer satisfies the above conditions, the slope angle ⁇ of the via holes 19 obtained at this time is higher than that of a uniform material. The slope angle ⁇ of the via 19 of the insulating layer is significantly lowered.
  • the etching may be performed by a conventional process, such as a dry etching process in which sulfur hexafluoride (SF 6 ) and ozone (O 3 ) gases are used, and the molar ratio of sulfur hexafluoride to ozone is 1:2. .
  • SF 6 sulfur hexafluoride
  • O 3 ozone
  • the plurality of sub-insulating layers are each containing a silicon nitride layer and formed by a plasma enhanced chemical vapor deposition (PECVD) process, wherein a mixed gas of silane (SiH 4 ) and ammonia (NH 3 ) is used as a process.
  • PECVD plasma enhanced chemical vapor deposition
  • a mixed gas of silane (SiH 4 ) and ammonia (NH 3 ) is used as a process.
  • the gas, using nitrogen (N 2 ) as a carrier gas the deposition apparatus is a 20KPX type produced by AKT Corporation; and at least one of the following conditions C1 and C2 is satisfied in the process of forming a plurality of sub-insulation layers:
  • the etching rate of the sub-insulating layer can also be changed by adjusting other process parameters such as pressure and temperature; or, for the sub-insulating layer formed by other materials or other processes, other process parameters can be adjusted.
  • the etch rate is controlled; alternatively, different sub-insulation layers can be formed using different types of materials having different etch rates.
  • the specific process type, process parameters, materials, etc. No longer described in detail.
  • FIG. 3 is a scanning electron micrograph of a cross section of a portion of a conventional array substrate including a via 19 in an insulating layer (eg, a silicon nitride-containing layer), showing the existing The slope angle of the via in the insulating layer of the array substrate.
  • the slope angle ⁇ is the angle formed by the edge of the thin layer in the "PVX Slope Angle" box in Figure 3.
  • the thickness of the insulating layer (excluding the sub-layer) is The etching rate of the insulating layer is The slice of the conventional array substrate was analyzed by an electron microscope, and the slope angle ⁇ of the via 19 in the insulating layer was measured to be 73.4 degrees.
  • the insulating layer is composed of a first sub-insulating layer 11 (containing a silicon nitride layer) and a second sub-insulating layer 12 (including a silicon nitride layer). The thickness of the first sub-insulating layer 11 is tested.
  • the thickness of the second sub-insulating layer 12 is The etching rate of the first sub-insulating layer 11 is The etching rate of the second sub-insulating layer 12 is The slice of the array substrate of this example was analyzed by an electron microscope, and the slope angle ⁇ of the via 19 in the insulating layer was measured to be 34.8 degrees.
  • the slope angle ⁇ of the via holes 19 in the insulating layer can be effectively reduced, thereby avoiding the conductive structure on the insulating layer. Defects such as breakage occur at the via hole 19 to achieve a better display effect.
  • the embodiment provides a display panel including the array substrate provided in Embodiment 1.
  • the display device can be a liquid crystal display panel, an OLED panel, or the like, and can be used in any product having a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

提供一种阵列基板及其制备方法和一种显示面板。阵列基板包括基底（9）和位于基底（9）上的绝缘层（1），绝缘层（1）包括通过刻蚀形成的过孔（19）。绝缘层（1）还包括叠置的多个子绝缘层（11，12），在用于形成过孔（19）的刻蚀条件下，在多个子绝缘层（11，12）中越远离基底（9）的子绝缘层（12）的刻蚀速率越大。

Description

阵列基板及其制备方法和显示面板 技术领域
本发明属于显示技术领域，具体涉及一种阵列基板及其制备方法和一种显示面板。
背景技术
如图1所示，在液晶显示装置的一种现有的阵列基板中，薄膜晶体管上覆盖有钝化层(PVX)1，像素电极7则设于钝化层1上，并通过钝化层1中的过孔19与薄膜晶体管的漏极8连接。
钝化层1中的过孔19是通过刻蚀工艺形成的，由于刻蚀工艺的特点，过孔19必然为上端大下端小的形式，从而过孔19具有一定的坡度角α(即孔壁与基底9的上表面之间的夹角，因漏极8的上表面与基底9的上表面平行，故图中用孔壁与漏极8的上表面之间的夹角代表坡度角α)。根据现有刻蚀工艺，坡度角α过大(即过孔壁接近与基底9垂直)，会导致像素电极7容易在过孔19处发生断裂(图中画叉处)，从而无法完成信号传输而引起显示不良等问题。
发明内容
针对现有的阵列基板的绝缘层中的过孔的坡度角过大而造成的上述技术问题，本发明提供一种阵列基板及其制备方法和一种显示面板，其中，绝缘层中的过孔的坡度角较小。
本发明的实施例提供了一种阵列基板，该阵列基板包括基底和位于所述基底上的绝缘层，所述绝缘层包括通过刻蚀形成的过孔，其中，
所述绝缘层包括叠置的多个子绝缘层，在用于形成所述过孔的刻蚀条件下，在所述多个子绝缘层中越远离所述基底的子绝缘 层的刻蚀速率越大。
其中，子绝缘层的“刻蚀速率”是指子绝缘层在经受刻蚀处理时单位时间内被刻蚀掉的厚度”，刻蚀速率越大表示子绝缘层被刻蚀的越快；当然，同一子绝缘层在不同刻蚀条件下的刻蚀速率可能不同，而本发明对各子绝缘层的刻蚀速率的要求是：在同一刻蚀条件下，越远离所述基底的子绝缘层的刻蚀速率越大。
可选的是，所述绝缘层仅包括第一子绝缘层和位于所述第一子绝缘层远离所述基底一侧的第二子绝缘层。
进一步可选的是，在用于形成所述过孔的刻蚀条件下，所述第一子绝缘层的刻蚀速率在
Figure PCTCN2016082966-appb-000001
所述第二子绝缘层的刻蚀速率在
Figure PCTCN2016082966-appb-000002
进一步可选的是，所述第一子绝缘层的厚度与所述第二子绝缘层的厚度的比大于等于4∶1。
进一步可选的是，所述第一子绝缘层的厚度在
Figure PCTCN2016082966-appb-000003
并且所述第二子绝缘层的厚度在
Figure PCTCN2016082966-appb-000004
可选的是，各所述子绝缘层均为含氮化硅层；越远离所述基底的子绝缘层中硅氮键数量与硅氢键数量的比值越小。
可选的是，所述绝缘层为钝化层，所述阵列基板还包括被所述绝缘层覆盖且位于所述基底上的薄膜晶体管和设于所述绝缘层远离所述基底一侧的像素电极，所述像素电极通过所述绝缘层中的所述过孔与所述薄膜晶体管的漏极连接。
本发明的实施例提供了一种显示面板，该显示面板其包括上述的阵列基板。
本发明的实施例提供了一种阵列基板的制备方法，该制备方法包括以下步骤：
在基底上依次形成叠置的多个子绝缘层，使得所述多个子绝缘层形成绝缘层，并且在所述多个子绝缘层中，越远离所述基底的子绝缘层的刻蚀速率越大；以及
在同一刻蚀条件下对所述绝缘层中的所述多个子绝缘层进行刻蚀，以形成过孔。
其中，“越远离所述基底的子绝缘层的刻蚀速率越大”是指在任意两个子绝缘层中，离所述基底较远的那个子绝缘层的刻蚀速率比离所述基底较近的那个子绝缘层的刻蚀速率更大，而并不是指同一个子绝缘层内的不同部分具有不同的刻蚀速率。
可选的是，所述多个子绝缘层均为含氮化硅层，并且越远离所述基底的子绝缘层中硅氮键数量与硅氢键数量的比值越小。
可选的是，所述多个子绝缘层均通过等离子体增强化学气相沉积工艺形成，其中使用硅烷和氨气的混合气体为工艺气体，在形成所述多个子绝缘层的过程中满足以下条件C1和条件C2中的至少一种：
C1：形成越远离所述基底的子绝缘层时，硅烷流量越小，氨气流量越小，硅烷流量与氨气流量的比值越小；以及
C2：形成越远离所述基底的子绝缘层时，等离子射频功率越小。
在本发明的阵列基板中，绝缘层包括至少两个刻蚀速率不同的子绝缘层，且越靠上(即越远离基底)的子绝缘层刻蚀速率越大。发明人发现，在通过刻蚀形成过孔的情况下，这种具有特定刻蚀速率的绝缘层中的过孔具有较小的坡度角，从而便于绝缘层上的导电结构通过所述过孔与绝缘层下的导电结构连接，避免绝缘层上的导电结构因所述过孔的坡度角过大而发生断裂等缺陷。
附图说明
图1为一种现有的阵列基板的包括过孔在内的部分的剖面示意图；
图2为本发明的实施例提供的一种阵列基板的包括过孔在内的部分的剖面示意图；
图3为一种现有的阵列基板的包括过孔在内的部分的剖面的扫描电镜照片；以及
图4为本发明的实施例提供的一种阵列基板的包括过孔在内的部分的剖面的扫描电镜照片。
附图标记说明：α、坡度角；1、钝化层；11、第一子绝缘层；12、第二子绝缘层；7、像素电极；8、漏极；9、基底。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
如图2和图4所示，本实施例提供一种阵列基板。
该阵列基板可用于液晶显示装置、有机发光二极管(OLED)显示装置等中。这些显示装置可以具有本领域技术人员已知的多种具体结构，在此不详细描述。
本实施例的阵列基板包括基底9和位于基底9上的绝缘层，绝缘层包括通过刻蚀形成的过孔19；绝缘层包括叠置的多个子绝缘层，在用于形成过孔19的刻蚀条件下，越远离基底9的子绝缘层的刻蚀速率越大。
也就是说，不论阵列基板的其他结构是什么形式，但其中必然包括绝缘层(如钝化层1)，该绝缘层用于隔离其上下两侧的导电结构；而在绝缘层中设置有过孔19，过孔19用于使绝缘层上下两侧的导电结构(如像素电极7与薄膜晶体管的漏极8)在需要的位置相互连接。与常规绝缘层不同，作为一个功能层，本发明的绝缘层包括多个子绝缘层，其中在相同的刻蚀条件下，各子绝缘层被刻蚀的速率不同，越靠上(即越远离基底9)的子绝缘层被刻蚀得越快，即，越远离基底9的子绝缘层的刻蚀速率越大。
其中，“一个功能层”是指，该绝缘层整体上是作为一个层起作用的，故其中各子绝缘层之间没有其他结构。对于在两个子绝缘层之间设有其他结构的常规绝缘层来说，在部分位置处，两个子绝缘层可能会直接接触，但这种在部分位置处直接接触的两个子绝缘层的合并不属于本发明的绝缘层。
在本实施例的阵列基板中，绝缘层包括至少两个刻蚀速率不 同的子绝缘层，且越靠上的子绝缘层刻蚀速率越大。发明人发现，在通过刻蚀形成过孔19的情况下，这种具有特定的刻蚀速率(即，越远离基底9的子绝缘层的刻蚀速率越大)的绝缘层中的过孔19具有较小的坡度角α，从而便于绝缘层上的导电结构通过过孔19与绝缘层下的导电结构连接，避免绝缘层上的导电结构因过孔19坡度角α过大而发生断裂等缺陷。
可选的，绝缘层为钝化层1，阵列基板还包括被绝缘层覆盖且位于基底9上的薄膜晶体管和设于绝缘层(例如，钝化层1)远离基底9一侧的像素电极7，像素电极7通过绝缘层中的过孔19与薄膜晶体管的漏极8连接。
也就是说，本实施例的绝缘层可以用于液晶显示装置的阵列基板，在此情况下，绝缘层为钝化层(PVX)1。该钝化层1覆盖在薄膜晶体管上，而像素电极7则设于钝化层1上，并通过以上过孔19与薄膜晶体管的漏极8相连。由于钝化层1一般具有较大的厚度，而像素电极7一般具有较薄的厚度，因此在像素电极7通过钝化层1中的过孔19与漏极8相连(即，像素电极7延伸至漏极8的通过过孔19暴露的表面上)的情况下，若过孔19坡度角α过大则像素电极7容易发生断裂。本发明的绝缘层(例如，钝化层1)使得过孔19坡度角α较小，从而使得像素电极7不容易发生断裂。在图2中，像素电极7设置在部分钝化层1上，但是本发明不限于此。
当然，根据需要，本发明的阵列基板还可包括栅极(栅线)、栅绝缘层、有源区、源极(数据线)、公共电极等其他结构，在此不再详细描述。
当然，本实施例的阵列基板不限于液晶显示装置的阵列基板，还可以为OLED显示装置等的阵列基板。阵列基板中的绝缘层也不限于钝化层1，只要绝缘层中设有通过刻蚀形成的过孔(例如，过孔19)即可，例如，绝缘层也可为诸如栅绝缘层、平坦化层等的其他层。
可选的，各子绝缘层均为含氮化硅层(即，包含氮化硅的层)； 且越远离基底9的子绝缘层中硅氮键数量与硅氢键数量的比值越小。
经研究发现，实际的含氮化硅层中必然含有硅氮键(Si-N)和硅氢键(Si-H)。而对含氮化硅层，硅氢键在一定程度上是“杂质”，故硅氢键的数量越多则意味着含氮化硅层的缺陷越多，越容易被刻蚀，即，刻蚀速率越大。因此，为实现越靠上(越远离基底9)的子绝缘层刻蚀速率越大的目的，则越靠上的子绝缘层中硅氮键数量与硅氢键数量的比值就应越小(即硅氮键越少而硅氢键越多)。
其中，具有不同的硅氮键数量与硅氢键数量的比值的含氮化硅层可通过同种工艺制造，只要调整具体的工艺参数即可。例如，当通过等离子体增强化学气相沉积(PECVD)工艺来制备含氮化硅层时，可通过调整工艺气体流量、等离子射频功率(RF)、温度、压力等参数来改变硅氮键数量与硅氢键数量的比值。
当然，以上子绝缘层并不限于含氮化硅层，其也可由其他材料(如氧化硅、氮氧化硅)制成；或者，不同子绝缘层也可由不同类材料制成，只要它们的刻蚀速率符合以上要求(即，越远离基底9的子绝缘层的刻蚀速率越大)即可。
可选的，绝缘层仅包括第一子绝缘层11和位于第一子绝缘层11远离基底9一侧的第二子绝缘层12。
也就是说，作为可选方案，绝缘层(如钝化层1)可仅由两个子绝缘层11和12构成，并且在同一刻蚀条件下，第二子绝缘层12比第一子绝缘层11具有更大的刻蚀速率。显然，子绝缘层数量越多则绝缘层的制备工艺越复杂。经研究发现，只要两个子绝缘层就可起到很好的降低坡度角α的效果。故绝缘层可选地仅由两个子绝缘层构成。
进一步可选的，在用于形成过孔19的刻蚀条件下，第一子绝缘层11的刻蚀速率在
Figure PCTCN2016082966-appb-000005
第二子绝缘层12的刻蚀速率在
Figure PCTCN2016082966-appb-000006
具体的，经研究发现，当绝缘层(如钝化层1)由两个子绝缘层构成时，二者的刻蚀速率可选地被分别控制在以上范围内，以更 好的起到减小过孔19坡度角α的效果。
可选的，第一子绝缘层11的厚度与第二子绝缘层12的厚度的比值大于等于4∶1；进一步可选的，第一子绝缘层11的厚度在
Figure PCTCN2016082966-appb-000007
第二子绝缘层12的厚度在
Figure PCTCN2016082966-appb-000008
两个子绝缘层的厚度关系对所形成的过孔19的坡度角α也有影响。经研究发现，第二子绝缘层12相对较薄时可更好的起到减小过孔19坡度角α的效果，第一子绝缘层11的厚度与第二子绝缘层12的厚度之间的关系可以如上所述。
当然，绝缘层并不限于仅包括两个子绝缘层，其还可包括依次设于第二子绝缘层上的第三子绝缘层、第四子绝缘层等，只要其中各子绝缘层的刻蚀速率符合以上要求(即，越远离基底9的子绝缘层的刻蚀速率越大)即可。
如图2和图4所示，本实施例还提供一种上述阵列基板的制备方法，其包括以下步骤S1和S2。
步骤S1：在基底9上依次形成叠置的多个子绝缘层，使得所述多个子绝缘层形成绝缘层，并且在所述多个子绝缘层中，越远离所述基底的子绝缘层的刻蚀速率越大；
在同一刻蚀条件下对所述绝缘层中的所述多个子绝缘层进行刻蚀，以形成过孔19。
也就是说，制备以上阵列基板时，先依次形成叠置的多个子绝缘层(如第一子绝缘层11和第二子绝缘层12)，之后再通过一次刻蚀工艺，在同一刻蚀条件下，在绝缘层的多个子绝缘层中形成过孔19，由于各子绝缘层的刻蚀速率满足以上条件，故此时得到的过孔19的坡度角α会比由一种统一材料制成的绝缘层的过孔19的坡度角α明显降低。
其中，刻蚀可采用常规工艺进行，如采用干法刻蚀工艺，其中使用六氟化硫(SF6)和臭氧(O3)气体，六氟化硫和臭氧的摩尔配比为1∶2。
具体的，以上多个子绝缘层均为含氮化硅层，并通过等离子体增强化学气相沉积工艺(PECVD)工艺形成，其中使用硅烷(SiH4) 和氨气(NH3)的混合气体为工艺气体，使用氮气(N2)为载气，沉积设备为AKT公司生产的20KPX型；且在形成多个子绝缘层的过程中满足以下条件C1和条件C2中的至少一种：
C1：形成越远离基底9的子绝缘层时，使得硅烷流量越小，氨气流量越小，且硅烷流量与氨气流量的比值越小；这样的条件可降低硅氮键数量与硅氢键数量的比值，从而提高子绝缘层的刻蚀速率；以及
C2：形成越远离基底9的子绝缘层时，使得等离子射频功率(RF)越小；当射频功率小时，则所得到的子绝缘层比较疏松，从而其更容易被刻蚀，即，具有更大的刻蚀速率。
当然，在PECVD工艺中，也可通过调整压力、温度等其他工艺参数来改变子绝缘层的刻蚀速率；或者，对于由其他材料或其他工艺形成的子绝缘层，可通过调整其他工艺参数来控制其刻蚀速率；或者，也可使用具有不同刻蚀速率的不同类材料形成不同的子绝缘层。总之，只要最终得到的各子绝缘层符合以上的刻蚀速率要求(即，越远离基底9的子绝缘层的刻蚀速率越大)即可，其具体工艺类型、工艺参数、材料等在此不再详细描述。
作为一种比较，图3为一种现有的阵列基板的包括绝缘层(例如，含氮化硅层)中的过孔19在内的部分的剖面的扫描电镜照片，其示出了现有阵列基板的绝缘层中的过孔的坡度角。坡度角α为图3中“PVX坡度角”框中的薄层边缘所成的角。其中，经测试得到，绝缘层(不包括子层)的厚度为
Figure PCTCN2016082966-appb-000009
而该绝缘层的刻蚀速率为
Figure PCTCN2016082966-appb-000010
经过利用电子显微镜对该现有阵列基板的切片进行分析，测出该绝缘层中的过孔19的坡度角α为73.4度。
图4为本实施例的阵列基板的包括绝缘层中的过孔19在内的部分的剖面的扫描电镜照片。坡度角α为图4中“PVX坡度角”框中的薄层边缘所成的角。在图4中，绝缘层由第一子绝缘层11(含氮化硅层)和第二子绝缘层12(含氮化硅层)构成。经测试得到，该第一子绝缘层11的厚度为
Figure PCTCN2016082966-appb-000011
第二子绝缘层12的厚度为
Figure PCTCN2016082966-appb-000012
第一子绝缘层11的刻蚀速率为
Figure PCTCN2016082966-appb-000013
第二子绝缘层 12的刻蚀速率为
Figure PCTCN2016082966-appb-000014
经过利用电子显微镜对本实施例的阵列基板的切片进行分析，测出该绝缘层中的过孔19的坡度角α为34.8度。
由此可见，通过将绝缘层分为具有特定刻蚀速率关系的多个子绝缘层，确实可有效的降低该绝缘层中的过孔19的坡度角α，从而避免该绝缘层上的导电结构在过孔19处发生断裂等缺陷，以实现更好的显示效果。
实施例2：
本实施例提供一种显示面板，其包括实施例1所提供的阵列基板。
具体的，该显示装置可为液晶显示面板或OLED面板等，并且可用于电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品中。
应当理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也属于本发明的保护范围。

Claims (11)

  1. 一种阵列基板，包括基底和位于所述基底上的绝缘层，所述绝缘层包括通过刻蚀形成的过孔，其中，
    所述绝缘层包括叠置的多个子绝缘层，在用于形成所述过孔的刻蚀条件下，在所述多个子绝缘层中越远离所述基底的子绝缘层的刻蚀速率越大。
  2. 根据权利要求1所述的阵列基板，其中，
    所述绝缘层仅包括第一子绝缘层和位于所述第一子绝缘层远离所述基底一侧的第二子绝缘层。
  3. 根据权利要求2所述的阵列基板，其中，
    在用于形成所述过孔的刻蚀条件下，所述第一子绝缘层的刻蚀速率在
    Figure PCTCN2016082966-appb-100001
    并且所述第二子绝缘层的刻蚀速率在
    Figure PCTCN2016082966-appb-100002
  4. 根据权利要求2所述的阵列基板，其中，
    所述第一子绝缘层的厚度与所述第二子绝缘层的厚度的比大于等于4∶1。
  5. 根据权利要求4所述的阵列基板，其中，
    所述第一子绝缘层的厚度在
    Figure PCTCN2016082966-appb-100003
    并且所述第二子绝缘层的厚度在
    Figure PCTCN2016082966-appb-100004
  6. 根据权利要求1所述的阵列基板，其中，
    各所述子绝缘层均为含氮化硅层；并且
    越远离所述基底的子绝缘层中硅氮键数量与硅氢键数量的比值越小。
  7. 根据权利要求1所述的阵列基板，其中，
    所述绝缘层为钝化层，所述阵列基板还包括被所述绝缘层覆盖且位于所述基底上的薄膜晶体管和设于所述绝缘层远离所述基底一侧的像素电极，所述像素电极通过所述绝缘层中的所述过孔与所述薄膜晶体管的漏极连接。
  8. 一种显示面板，包括：
    根据权利要求1至7中任意一项所述的阵列基板。
  9. 一种阵列基板的制备方法，包括以下步骤：
    在基底上依次形成叠置的多个子绝缘层，使得所述多个子绝缘层形成绝缘层，并且在所述多个子绝缘层中，越远离所述基底的子绝缘层的刻蚀速率越大；以及
    在同一刻蚀条件下对所述绝缘层中的所述多个子绝缘层进行刻蚀，以形成过孔。
  10. 根据权利要求9所述的制备方法，其中，所述多个子绝缘层均为含氮化硅层，并且越远离所述基底的子绝缘层中硅氮键数量与硅氢键数量的比值越小。
  11. 根据权利要求10所述的制备方法，其中，所述多个子绝缘层均通过等离子体增强化学气相沉积工艺形成，其中使用硅烷和氨气的混合气体为工艺气体，在形成所述多个子绝缘层的过程中满足以下条件C1和条件C2中的至少一种：
    C1：形成越远离所述基底的子绝缘层时，硅烷流量越小，氨气流量越小，硅烷流量与氨气流量的比值越小；以及
    C2：形成越远离所述基底的子绝缘层时，等离子射频功率越小。
PCT/CN2016/082966 2016-03-09 2016-05-23 阵列基板及其制备方法和显示面板 Ceased WO2017152502A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/519,954 US10374062B2 (en) 2016-03-09 2016-05-23 Array substrate, manufacturing method thereof and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610133351.9 2016-03-09
CN201610133351.9A CN105552091A (zh) 2016-03-09 2016-03-09 阵列基板及其制备方法、显示面板

Publications (1)

Publication Number Publication Date
WO2017152502A1 true WO2017152502A1 (zh) 2017-09-14

Family

ID=55831180

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/082966 Ceased WO2017152502A1 (zh) 2016-03-09 2016-05-23 阵列基板及其制备方法和显示面板

Country Status (3)

Country Link
US (1) US10374062B2 (zh)
CN (1) CN105552091A (zh)
WO (1) WO2017152502A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105552091A (zh) 2016-03-09 2016-05-04 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN106653697B (zh) * 2017-01-03 2019-11-05 京东方科技集团股份有限公司 阵列基板及其制造方法和显示面板
CN109817531B (zh) 2019-02-02 2021-03-12 合肥鑫晟光电科技有限公司 一种阵列基板及其制作方法
CN109962078B (zh) * 2019-03-28 2021-02-09 合肥鑫晟光电科技有限公司 一种显示基板及其制备方法、显示面板
CN110828479A (zh) * 2019-10-30 2020-02-21 武汉华星光电半导体显示技术有限公司 柔性显示面板及其制备方法
CN112259554B (zh) * 2020-10-12 2024-04-30 昆山龙腾光电股份有限公司 薄膜晶体管阵列基板及其制作方法
CN112687617B (zh) * 2020-12-24 2022-07-22 中国电子科技集团公司第十三研究所 绝缘子针的制备方法及绝缘子针
CN114460772A (zh) * 2022-01-26 2022-05-10 武汉华星光电技术有限公司 阵列基板和显示面板
CN119907569A (zh) * 2024-06-07 2025-04-29 合肥维信诺科技有限公司 显示面板、显示面板的制备方法及电子设备

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6334928A (ja) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp スル−ホ−ルの形成方法
US6396078B1 (en) * 1995-06-20 2002-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with a tapered hole formed using multiple layers with different etching rates
CN1509127A (zh) * 2002-12-11 2004-06-30 ��ʽ����������ʾ�� 有机el显示装置
CN1945855A (zh) * 2005-10-03 2007-04-11 Nec液晶技术株式会社 薄膜晶体管、tft阵列基板、液晶显示器及其制造方法
CN101546746A (zh) * 2008-03-25 2009-09-30 上海广电Nec液晶显示器有限公司 保证顺锥形接触孔的绝缘层及其制造方法
CN101677104A (zh) * 2008-09-17 2010-03-24 瀚宇彩晶股份有限公司 感光元件、光传感器及其制造方法
CN101789402A (zh) * 2009-01-27 2010-07-28 卡西欧计算机株式会社 多层膜的形成方法、显示面板的制造方法及显示面板
CN104835827A (zh) * 2014-02-11 2015-08-12 群创光电股份有限公司 显示面板
CN105552091A (zh) * 2016-03-09 2016-05-04 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3686721D1 (de) * 1986-10-08 1992-10-15 Ibm Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.
KR100643404B1 (ko) * 2005-09-22 2006-11-10 삼성전자주식회사 디스플레이장치 및 그 제조방법
JP5352333B2 (ja) * 2009-04-23 2013-11-27 株式会社ジャパンディスプレイ アクティブマトリクス型表示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6334928A (ja) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp スル−ホ−ルの形成方法
US6396078B1 (en) * 1995-06-20 2002-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with a tapered hole formed using multiple layers with different etching rates
CN1509127A (zh) * 2002-12-11 2004-06-30 ��ʽ����������ʾ�� 有机el显示装置
CN1945855A (zh) * 2005-10-03 2007-04-11 Nec液晶技术株式会社 薄膜晶体管、tft阵列基板、液晶显示器及其制造方法
CN101546746A (zh) * 2008-03-25 2009-09-30 上海广电Nec液晶显示器有限公司 保证顺锥形接触孔的绝缘层及其制造方法
CN101677104A (zh) * 2008-09-17 2010-03-24 瀚宇彩晶股份有限公司 感光元件、光传感器及其制造方法
CN101789402A (zh) * 2009-01-27 2010-07-28 卡西欧计算机株式会社 多层膜的形成方法、显示面板的制造方法及显示面板
CN104835827A (zh) * 2014-02-11 2015-08-12 群创光电股份有限公司 显示面板
CN105552091A (zh) * 2016-03-09 2016-05-04 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板

Also Published As

Publication number Publication date
US10374062B2 (en) 2019-08-06
CN105552091A (zh) 2016-05-04
US20180097087A1 (en) 2018-04-05

Similar Documents

Publication Publication Date Title
WO2017152502A1 (zh) 阵列基板及其制备方法和显示面板
US11264323B2 (en) Semiconductor device and method for fabricating the same
EP3249687B1 (en) Manufacturing method of a display panel
US20120034451A1 (en) Substrate for flexible display and method of manufacturing the substrate
CN111276496A (zh) 显示背板和显示装置
CN111341849A (zh) 显示基板及其制备方法、显示面板
US20150097179A1 (en) Display substrate and method of manufacturing a display substrate
WO2019227964A1 (zh) 阵列基板、显示装置以及形成阵列基板的方法
WO2019148579A1 (zh) 薄膜晶体管阵列基板及其制造方法
CN103531593B (zh) 像素结构、阵列基板、显示装置及像素结构的制造方法
CN103872139B (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
CN105470195B (zh) Tft基板的制作方法
CN104465670B (zh) 一种阵列基板及其制作方法、显示装置
US11646280B2 (en) Method for fabricating semiconductor device
CN105552084A (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
WO2023030108A1 (zh) 金属氧化物薄膜晶体管及其制备方法、显示面板
CN106920812B (zh) 一种oled显示面板及其制备方法
CN104835827B (zh) 显示面板
US20240234428A9 (en) Array substrate, manufacturing method thereof, and display panel
WO2017128554A1 (zh) Tft阵列基板及其制造方法
US20200403102A1 (en) Electrode structure and manufacturing method thereof, thin film transistor, and array substrate
US10825930B2 (en) Thin film transistor and manufacture method thereof
WO2018014248A1 (zh) 薄膜晶体管制造方法、tft阵列基板及柔性显示屏
WO2017143636A1 (zh) 一种薄膜晶体管及其制备方法
CN104701326A (zh) 阵列基板及其制造方法和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15519954

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16893150

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16893150

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 10.05.2019)

122 Ep: pct application non-entry in european phase

Ref document number: 16893150

Country of ref document: EP

Kind code of ref document: A1