WO2017143741A1 - Circuit d'attaque de panneau d'affichage et procédé de test de qualité associé - Google Patents

Circuit d'attaque de panneau d'affichage et procédé de test de qualité associé Download PDF

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Publication number
WO2017143741A1
WO2017143741A1 PCT/CN2016/095664 CN2016095664W WO2017143741A1 WO 2017143741 A1 WO2017143741 A1 WO 2017143741A1 CN 2016095664 W CN2016095664 W CN 2016095664W WO 2017143741 A1 WO2017143741 A1 WO 2017143741A1
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WIPO (PCT)
Prior art keywords
voltage
driving circuit
turn
input
switching element
Prior art date
Application number
PCT/CN2016/095664
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English (en)
Chinese (zh)
Inventor
张蒙蒙
黄世帅
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/127,387 priority Critical patent/US10026345B2/en
Publication of WO2017143741A1 publication Critical patent/WO2017143741A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a driving circuit for a display panel and a quality testing method thereof.
  • the life of the display panel is an important indicator to measure its quality, and the life test of the display panel is an important means to evaluate the life of the panel.
  • the usual life test method is to perform an accelerated life test to accelerate the aging of a thin film transistor (TFT) in a display panel by a high temperature and high humidity environment, and estimate the lifetime of the panel according to an acceleration coefficient, which usually requires hundreds of times. It can be completed in thousands of hours.
  • TFT thin film transistor
  • the prior art adopts a test method for online accelerated aging, called DC pressurization (DC). Stress).
  • the test method is as follows: the scan line (Gate line) of the display panel before the group is connected to the turn-on voltage (VGH), and all the data lines (Data lines) are always turned on, and the tens of hours of DC plus After pressing, the panel pair is performed. Subsequently, gradually lowering VGH, when the brightness of the gray level of the corresponding panel 255 is reduced to 60% of the initial brightness, the magnitude of the VGH reduction is called the VGH margin (VGH). Margin), the size of the VGH margin is an indirect parameter that characterizes the life of the display panel.
  • This online accelerated aging test method allows the TFT to accelerate aging in a near-normal panel display mode, while the temperature and humidity are also close to normal display.
  • the method is performed before the panel pairing group, and after the aging, the pairing group needs to be performed, and then the normal lighting measurement is performed, and the operation process is complicated.
  • this test method requires online testing, which requires occupying the production line machine for dozens of hours, which seriously affects production efficiency and productivity.
  • the technical problem to be solved by the present invention is to provide a driving circuit for a display panel and a quality testing method thereof, so as to simplify the testing process and improve the testing efficiency without affecting the production efficiency and the productivity.
  • one technical solution adopted by the present invention is to provide a driving circuit for a display panel, the driving circuit including a control circuit and a gate driving circuit, the control circuit including a first control output for outputting a first control signal And a second control output for outputting the second control signal, the gate driving circuit includes a driving input terminal, and in the normal display mode, the driving input terminal receives the first control signal from the first control output terminal to enable the gate The driving circuit drives the switching element on the display panel to be turned on by the first timing. In the test mode, the driving input receives the second control signal from the second control output, so that the gate driving circuit drives the display panel on the second timing.
  • the switching element is turned on, wherein a ratio of an opening time of the switching element at the second timing is greater than a ratio of an opening time of the switching element at the first timing; wherein the display panel includes a plurality of switching elements arranged in an array manner, in a normal display
  • the gate driving circuit drives the switching elements in a first timing to turn on line by row or column by column.
  • the gate driving circuit drives the switching elements all at the second timing; wherein the driving circuit further comprises an switching component, the switching component is connected to the first control output and the driving input in the normal display mode, and In the test mode, the second control output and the drive input are connected.
  • the driving input end is a closing voltage input end of the gate driving circuit
  • the first control output end is a closing voltage output end for outputting a closing voltage
  • the second control output end is an opening voltage output end for outputting an opening voltage
  • the off voltage input terminal receives the turn-off voltage output from the off voltage output terminal, so that the gate drive circuit periodically outputs the turn-on voltage and the turn-off voltage.
  • the turn-off voltage input terminal receives the turn-on voltage output terminal output. The turn-on voltage is such that the gate drive circuit continues to output the turn-on voltage.
  • the driving input end is a global open input end of the gate driving circuit
  • the first control output end is a global open output end for outputting a global control signal.
  • the global open input end receives the global open output end output.
  • Global control signal such that when the global control signal is at the first level, the gate drive circuit periodically outputs the turn-on voltage and the turn-off voltage, and when the global turn-on output is at the second level, the gate drive circuit continues to output the turn-on voltage
  • the second control output is a voltage output terminal that continuously outputs the second level. In the test mode, the global open input terminal receives the second level from the voltage output terminal, so that the gate drive circuit continuously outputs the turn-on voltage.
  • the switching component is a zero resistance component, and the two ends of the zero resistance component are respectively connected to the first control output end and the driving input end in the normal display mode, and are respectively connected to the second control output end and the driving input end in the test mode.
  • the switching component is a single-pole double-throw switching component
  • the single-pole double-throwing switching component comprises a moving end, a first fixed end and a second fixed end, wherein the moving end is connected to the driving input end, and the first fixed end is connected to the first control The output end is connected to the second control output end.
  • the movable end In the normal display mode, the movable end is connected to the first fixed end. In the test mode, the movable end is connected to the second fixed end.
  • the switching component includes a first switch and a second switch, wherein the two ends of the first switch are respectively connected to the first control output end and the driving input end, and the two ends of the second switch are respectively connected to the second control output end and the driving input end
  • the first switch is turned on and the second switch is turned off.
  • the test mode the first switch is turned off and the second switch is turned on.
  • a driving circuit for a display panel including a control circuit and a gate driving circuit, the control circuit including a first control signal for outputting a first control output and a second control output for outputting a second control signal, the gate drive circuit comprising a drive input, the drive input being from the first control output in a normal display mode
  • the second control signal is configured to cause the gate driving circuit to drive the switching element on the display panel to be turned on at a second timing, wherein a ratio of an opening time of the switching element at the second timing is greater than the The ratio of the turn-on time of the switching element at the first timing.
  • the gate driving circuit drives the switching elements at the first timing to be row by row or by row
  • the column mode is turned on, in the test mode, the gate driving circuit drives the switching elements all on at the second timing.
  • the driving input end is a closed voltage input end of the gate driving circuit
  • the first control output end is a closed voltage output end for outputting a shutdown voltage
  • the second control output end is for outputting Turning on an open voltage output terminal of the voltage
  • the shutdown voltage input terminal receives a shutdown voltage output by the shutdown voltage output terminal, so that the gate driving circuit periodically outputs an on voltage and a shutdown voltage
  • the shutdown voltage input terminal receives the turn-on voltage output by the turn-on voltage output terminal, so that the gate drive circuit continuously outputs the turn-on voltage.
  • the driving input end is a global open input end of the gate driving circuit
  • the first control output end is a global open output end for outputting a global control signal, in the normal display mode, a global open input receiving a global control signal output by the global open output, such that when the global control signal is at a first level, the gate drive circuit periodically outputs an open voltage and a turn-off voltage, and When the globally enabled output terminal is at the second level, the gate driving circuit continuously outputs the turn-on voltage, and the second control output terminal is a voltage output terminal that continuously outputs the second level, in the test mode,
  • the global open input receives the second level from the voltage output to cause the gate drive circuit to continuously output an on voltage.
  • the driving circuit further includes an switching element, wherein the switching element connects the first control output end and the driving input end in the normal display mode, and connects the first in the test mode Two control outputs and the drive input.
  • the switching element is a zero resistance element, and both ends of the zero resistance element are respectively connected to the first control output end and the driving input end in the normal display mode, and in the test mode The second control output and the drive input are respectively connected.
  • the switching element is a single-pole double-throw switching element
  • the single-pole double-throw switching element includes a moving end, a first fixed end and a second fixed end, wherein the moving end is connected to the driving input end, The first fixed end is connected to the first control output end, and the second fixed end is connected to the second control output end.
  • the dynamic end is connected to the first fixed position.
  • the moving end is connected to the second fixed end.
  • the switching element includes a first switch and a second switch, wherein two ends of the first switch are respectively connected to the first control output end and the driving input end, and two ends of the second switch are respectively Connecting the second control output end and the driving input end, in the normal display mode, the first switch is turned on, the second switch is turned off, and in the test mode, the first switch is turned off The second switch is turned on.
  • another technical solution adopted by the present invention is to provide a quality testing method for a display panel, the quality testing method comprising the following steps:
  • the ratio of the turn-on time of the switching element in the second timing is greater than the ratio of the turn-on time of the switching component in the first timing.
  • the gate driving circuit drives the switching elements at the first timing to be row by row or by row
  • the column mode is turned on, in the test mode, the gate driving circuit drives the switching elements all on at the second timing.
  • the invention has the beneficial effects that the driving circuit of the display panel and the quality testing method thereof provided by the invention can realize the switching between the test mode and the normal display mode by changing the input signal of the specific input end of the gate driving circuit, and can be in the mode After the group is completed, the offline quality test can be completed, which can simplify the test process and improve the test efficiency without affecting the production efficiency and productivity.
  • FIG. 1 is a schematic structural view of a first embodiment of a driving circuit provided by the present invention
  • 2a is a schematic structural view of an array arrangement formed by a plurality of switching elements in a display panel
  • Figure 2b is a first timing diagram of the drive output of the drive circuit of the present invention.
  • Figure 2c is a second timing diagram of the drive output of the drive circuit of the present invention.
  • FIG. 3 is a schematic structural view of various common input and output channels of the gate driving circuit of the present invention.
  • FIG. 4 is a schematic structural view showing the output voltage of each output channel of the gate driving circuit when the global open input terminal ⁇ XAO of the gate driving circuit of the present invention is at a low potential;
  • FIG. 5 is a schematic structural view of a second embodiment of a driving circuit provided by the present invention.
  • FIG. 6 is a schematic structural view of a third embodiment of a driving circuit provided by the present invention.
  • FIG. 7 is a schematic structural view of a fourth embodiment of a driving circuit provided by the present invention.
  • FIG. 8 is a schematic structural view of a fifth embodiment of a driving circuit provided by the present invention.
  • FIG. 9 is a flow chart of a method for testing quality of a display panel of the present invention.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a driving circuit provided by the present invention.
  • the driving circuit 100 includes a control circuit 101 and a gate driving circuit 102.
  • the control circuit 101 includes The first control output 1011 for outputting the first control signal and the second control output 1012 for outputting the second control signal
  • the gate drive circuit 102 includes a specific drive input 1021, which is driven in the normal display mode.
  • the input terminal 1021 receives the first control signal from the first control output terminal 1011 to cause the gate driving circuit 102 to drive the switching element 103 on the display panel 10 to be turned on at the first timing, and in the test mode, the driving input terminal 1021 is from the second
  • the control output terminal 1012 receives the second control signal to cause the gate driving circuit 102 to drive the switching element 103 on the display panel 10 to be turned on at a second timing, wherein the ratio of the turn-on time of the switching element 103 at the second timing is greater than The ratio of the turn-on time of the switching element 103 at a time.
  • the proportion of the turn-off time is correspondingly reduced, so that the ratio of the turn-on time of the switching element 103 at the second timing is greater than the turn-on time of the switching component 103 at the first timing. proportion.
  • the display panel includes a plurality of switching elements 103 arranged in an array, as shown in FIG. 2a, a schematic structural diagram of an array arrangement formed by a plurality of switching elements in the display panel; in the normal display mode, the gate driving circuit The driving of the switching element 103 in the first timing is performed in a row-by-row or column-by-column manner. In the test mode, the gate driving circuit 102 drives the switching element 103 to be fully turned on at the second timing.
  • the number of switching elements included on the display panel is related to the resolution of the display panel. For example, if the resolution of the display panel is m ⁇ n, the display panel is composed of m columns multiplied by n rows of pixels, each of which is composed of pixels. Each of the pixels includes at least one switching element 103; when the display panel is normally displayed, if the m ⁇ n switches are turned on line by line, as shown in FIG.
  • the first timing diagram of the driving output of the driving circuit of the present invention is Wherein VGH is the turn-on voltage of the switching element 103, and VGL is the turn-off voltage of the switching element 103; when the display panel is tested, the output voltage of the gate driving circuit 102 is the turn-on voltage VGH, and is driven by the second timing
  • the array of switching elements 103 is all turned on, as shown in Figure 2c, which is a second timing diagram of the drive output of the drive circuit of the present invention.
  • the refresh rate of the display panel is 60 Hz and the time resolution is 1920 ⁇ 1080, that is, the number of frames per second is 60, the appearance time of each frame is 1/60 s. , that is, 16.67s, the resolution is 1920x1080.
  • the switching element 103 is turned on line by line, the opening time of each line is 16.67/1080s, that is, 15.43 ⁇ s; but when the display panel is in the test mode The turn-on voltage is always on.
  • the turn-on mode in which the turn-on voltage is always on is equivalent to the acceleration factor of 1080 times in the normal display state, which can greatly improve Test efficiency.
  • the gate driving circuit 102 may be a gate driving chip attached to the display panel 10, or may be a GOA driving circuit formed on the display panel 10 in a GOA manner.
  • the existing gate drive circuit has a plurality of input and output channels, as shown in FIG. 3, which is a schematic diagram of the common input and output channels of the gate drive circuit 102.
  • the control circuit 101 changes the output signal of the output channel by controlling the input signals of the respective input channels of the gate drive circuit 102.
  • the display panel 10 is controlled to switch between the normal display mode and the test mode by changing the input signal of the input channel.
  • the gate drive circuit 102 typically includes a turn-off voltage input terminal VGL and an turn-on voltage input terminal VGH.
  • the turn-off voltage input terminal VGL and the turn-on voltage input terminal VGH receive the turn-off voltage and the turn-on voltage from the control circuit 101, respectively, and are set by the shift register group internally set by the gate drive circuit 102 (not shown).
  • the shifting operation of the display causes the output terminals OUT1-OUTn to sequentially output the turn-on voltage and the turn-off voltage in sequence, thereby controlling the switching elements 103 of the display panel 10 to be turned on line by row or column by column.
  • the shutdown voltage input terminal VGL of the gate driving circuit 102 is used as the driving input terminal 1021 of the present invention, and the shutdown voltage output terminal for outputting the shutdown voltage is used as the first control output terminal 1011.
  • the turn-on voltage output terminal for outputting the turn-on voltage is used as the second control output terminal 1012.
  • the shutdown voltage input terminal VGL is in communication with the first control output terminal 1011, and the turn-on voltage input terminal VGH is in communication with the second control output terminal 1012, that is, respectively applied to the turn-on voltage input terminal VGH and the turn-off voltage input terminal VGL.
  • the turn-on voltage and the turn-off voltage cause the output terminals OUT1-OUTn to periodically output the turn-on voltage and the turn-off voltage.
  • the shutdown voltage input terminal VGL is disconnected from the first control output terminal 1011 and is in communication with the second control output terminal 1012, that is, the turn-on voltage VGH is simultaneously applied to the turn-on voltage input terminal VGH and the turn-off voltage input terminal VGL.
  • gate drive circuit 102 typically includes a global open input ⁇ XAO.
  • the global open input port ⁇ XAO is used to receive the global control signal, and its function is to control all the switching elements of the display panel 10 to be turned on after the display ends, thereby accelerating the rapid discharge of the display panel 10.
  • the global open input terminal ⁇ XAO of the gate drive circuit 102 is used as the drive input terminal 1021 of the present invention, and the global open output terminal for outputting the global control signal is used as the first control output.
  • the terminal 1011 in the normal display mode, the global open input port ⁇ XAO receives the global control signal output by the first control output terminal 1011, so that when the global control signal is at the first level, the gate drive circuit 102 periodically outputs the turn-on voltage. And turning off the voltage, and when the global control signal is at the second level, the gate driving circuit 102 continues to output the turn-on voltage. Further, the voltage output terminal of the second level is continuously output as the second control output terminal 1012. In the test mode, the global enable input ⁇ XAO receives a second level from the second control output 1012 such that the gate drive circuit 102 continues to output the turn-on voltage.
  • the priority of the ⁇ XAO input signal of the global open input terminal ⁇ XAO of the gate drive circuit 102 is higher than that of the OE input signal, and when the /XAO input signal is at a high potential (eg, 3V), the gate drive The circuit 102 periodically outputs the turn-on voltage and the turn-off voltage; when /XAO is at a low level (such as 0V), the gate drive circuit 102 continues to output the turn-on voltage, that is, all OUTs only output the VGH voltage, as shown in FIG.
  • the output circuit of each output channel of the gate drive circuit outputs a turn-on voltage.
  • FIG. 5 is a schematic structural diagram of a second embodiment of a driving circuit provided by the present invention.
  • the drive circuit 400 includes the same control circuit 401 and gate drive circuit 402 as in FIG.
  • the driving circuit 400 further includes an switching element 404 that connects the first control output 4011 and the driving input 4021 in the normal display mode such that the driving input 4021 receives the first from the first control output 4011.
  • the control signal drives the switching element 403 on the display panel 40 to turn on at the first timing.
  • the switching element 404 is coupled to the second control output 4012 and the drive input 4021 such that the drive input 4021 receives a second control signal from the second control output 4012, thereby driving the display panel 40 at a second timing.
  • the upper switching element 403 is turned on.
  • FIG. 6 is a schematic structural diagram of a third embodiment of a driving circuit provided by the present invention.
  • the drive circuit 500 includes the same control circuit 501, gate drive circuit 502, and switching element 504 as in FIG.
  • the switching element 504 is specifically zero resistance element 504.
  • the two ends of the zero resistance element 504 are respectively connected to the first control output end 5011 and the drive input end 5021, so that the drive input end 5021 receives the first control signal from the first control output end 5011, and thus the first The switching element 503 on the timing driving display panel 50 is turned on.
  • the zero resistance element 504 is coupled to the second control output 5012 and the drive input 5021, respectively, such that the drive input 5021 receives the second control signal from the second control output 5012, thereby driving the display panel at the second timing.
  • the switching element 503 on 50 is turned on. It should be noted that the zero resistance element 504 functions as a jumper in this embodiment and does not affect the overall effect of the circuit.
  • FIG. 7 is a schematic structural diagram of a fourth embodiment of a driving circuit provided by the present invention.
  • the drive circuit 600 includes the same control circuit 601, gate drive circuit 602, and switching element 604 as in FIG.
  • the switching element 604 is specifically a single-pole double-throw switching element 604.
  • the single-pole double-throw switching element 604 includes a movable end 6041, a first fixed end 6042 and a second fixed end 6043.
  • the movable end 6041 is connected to the driving input end 6021.
  • a fixed end 6042 is coupled to the first control output 6011, and a second fixed end 6043 is coupled to the second control output 6012.
  • the movable end 6041 of the single-pole double-throw switching element 604 is connected to the first fixed end 6042 so that the driving input end 6021 receives the first control signal from the first control output terminal 6011, thereby driving the display at the first timing.
  • the switching element 603 on the panel 60 is turned on.
  • the movable end 6041 of the single-pole double-throw switch element 604 is connected to the second fixed end 6043 so that the drive input end 6021 receives the second control signal from the second control output end 6012, thereby driving the display panel at the second timing.
  • the switching element 603 on 60 is turned on.
  • FIG. 8 is a schematic structural diagram of a fifth embodiment of a driving circuit provided by the present invention.
  • the driving circuit 700 includes the same control circuit 701, gate driving circuit 702, and switching element 704 as in FIG.
  • the switching element 704 includes a first switch 7041 and a second switch 7042.
  • the two ends of the first switch 7041 are respectively connected to the first control output 7011 and the driving input end 7021.
  • the two ends of the second switch 7042 are respectively connected to the second switch. Control output 1012 and drive input 7021.
  • the first switch 7041 is turned on, and the second switch 7042 is turned off, so that the driving input terminal 7021 receives the first control signal from the first control output terminal 7011, thereby driving the switching element on the display panel 70 at the first timing. 703 is turned on.
  • the first switch 7041 is turned off, and the second switch 7042 is turned on, so that the driving input terminal 7021 receives the second control signal from the second control output terminal 7012, thereby driving the switching element 703 on the display panel 70 at the second timing. Open.
  • the driving circuit provided by the present invention can switch between the test mode and the normal display mode by changing the input signal of the specific input end of the gate driving circuit, and can perform the offline quality test after the module pair is completed. It can simplify the testing process and improve the testing efficiency without affecting production efficiency and productivity.
  • FIG. 9 is a flow chart of a quality testing method for a display panel of the present invention. As shown in FIG. 9, the quality testing method specifically includes the following steps (corresponding to the reference numeral 1):
  • the ratio of the turn-on time of the switching element 103 at the second timing is greater than the ratio of the turn-on time of the switching component 103 at the first timing.
  • the display panel 10 includes a plurality of switching elements 103 arranged in an array.
  • the first control output terminal 1011 is in communication with the driving input terminal 1021 such that the driving input terminal 1021 is from the first control output terminal 1011.
  • the gate driving circuit 1021 drives the switching element 103 to turn on in a row-by-row or column-by-column manner in a first timing.
  • the second control output terminal 1012 is in communication with the driving input terminal 1021 to enable the driving input.
  • the terminal 1021 receives the second control signal from the second control output 1012, and the gate driving circuit 1021 drives the switching element 103 all on at the second timing.
  • the quality testing method of the embodiment can be performed after the module pair group is completed, that is, can be completed offline, which simplifies the testing process of the existing testing technology, does not occupy the production time on the cable, and thus does not Impact on capacity.

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  • General Physics & Mathematics (AREA)
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Abstract

La présente invention se rapporte à un circuit d'attaque (100) d'un panneau d'affichage et à un procédé de test de qualité associé. Le circuit d'attaque (100) comprend un circuit de commande (101) et un circuit d'attaque de grille (102). Le circuit de commande (101) comprend une première extrémité de sortie de commande (1011) utilisée pour délivrer un premier signal de commande et une seconde extrémité de sortie de commande (1012) utilisée pour délivrer un second signal de commande. Le circuit d'attaque de grille (102) comprend une extrémité d'entrée d'excitation (1021). Dans un mode d'affichage normal, l'extrémité d'entrée d'excitation (1021) reçoit le premier signal de commande provenant de la première extrémité de sortie de commande (1011); dans un mode de test, l'extrémité d'entrée d'excitation reçoit le second signal de commande provenant de la seconde extrémité de sortie de commande (1012).
PCT/CN2016/095664 2016-02-23 2016-08-17 Circuit d'attaque de panneau d'affichage et procédé de test de qualité associé WO2017143741A1 (fr)

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