WO2017140014A1 - 一种goa电路及液晶显示装置 - Google Patents

一种goa电路及液晶显示装置 Download PDF

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Publication number
WO2017140014A1
WO2017140014A1 PCT/CN2016/078005 CN2016078005W WO2017140014A1 WO 2017140014 A1 WO2017140014 A1 WO 2017140014A1 CN 2016078005 W CN2016078005 W CN 2016078005W WO 2017140014 A1 WO2017140014 A1 WO 2017140014A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
control
voltage
gate driving
Prior art date
Application number
PCT/CN2016/078005
Other languages
English (en)
French (fr)
Inventor
黄笑宇
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/307,219 priority Critical patent/US10037740B2/en
Publication of WO2017140014A1 publication Critical patent/WO2017140014A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit and a liquid crystal display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal With the continuous development of Display
  • TFT-LCD has become an important display platform in modern IT and video products, and it has made users more and more demanding.
  • GOA Gate On Array
  • the gate drive chip is integrated in the array substrate
  • FIG. 1 is an output waveform diagram of a gate voltage after being chamfered, for example, V2 (for example, 33 V) and a low level of V1 (for example, -7 V).
  • the GOA technology is formed on the array substrate due to its gate input voltage, the output voltage of the gate cannot be chamfered by the design of the PCB end, so that the reference voltage of the liquid crystal display device of the existing GOA technology is easily affected and reduced. The display effect.
  • An object of the present invention is to provide a GOA circuit and a liquid crystal display device for solving the liquid crystal display device of the GOA technology of the prior art, which can not affect the falling time of the gate input voltage, thereby easily affecting the reference voltage and reducing the display effect.
  • Technical problem is to provide a GOA circuit and a liquid crystal display device for solving the liquid crystal display device of the GOA technology of the prior art, which can not affect the falling time of the gate input voltage, thereby easily affecting the reference voltage and reducing the display effect.
  • the present invention constructs a GOA circuit comprising: a plurality of gate driving modules for inputting scanning signals to scan lines, the gate driving modules comprising:
  • a first control branch for controlling the gate driving module to output a switching scan voltage associated with the initial scan voltage;
  • the first control branch comprising a first thin film transistor;
  • a second control branch for controlling the gate driving module to output a switching scan voltage not associated with the initial scan voltage; the second control branch comprising a second thin film transistor;
  • a third control branch configured to control the first control branch to be turned on when the gate driving module is in a first working mode; and to control the gate driving module when in the second working mode Opening of the second control branch; wherein the gate driving module has the first operating mode, the second operating mode, and the third operating mode; and the third control branch includes a third thin film transistor;
  • a fourth control branch configured to control outputting the initial scan voltage when the gate driving module is in the third working mode;
  • the fourth control branch comprises a fourth thin film transistor;
  • control voltage has a high level and a low level; the initial scan voltage also has a high level and a low level; the first thin film transistor is a PNP type thin film transistor, and the second thin film transistor is an NPN type thin film a transistor; the third thin film transistor is an NPN type thin film transistor, and the fourth thin film transistor is a PNP type thin film transistor.
  • the output control unit has a control voltage and a high level power supply
  • the first thin film transistor has a first input end, a first control end, and a first output end;
  • the second thin film transistor has a second input end, a second control end, and a second output end;
  • the third thin film transistor has a fourth input end, a fourth control end, and a fourth output end;
  • the first control end and the second control end are connected to the control voltage, the first input end is connected to the initial scan voltage; the first output end is respectively connected to the second output end and the first a third input terminal is connected; the second input terminal is connected to the high level power supply; the third control terminal and the fourth control terminal are connected to the initial scan voltage; and the fourth input terminal is connected to the fourth input terminal
  • the control terminal is connected to the fourth output end, and the fourth output end is further connected to the scan line.
  • the initial scan voltage is a high level, and the control voltage is a low level, and the switching scan voltage is equal to The initial scan voltage
  • the initial scanning voltage is a high level
  • the control voltage is a high level
  • the switching scanning voltage is equal to a voltage of the high level power supply ;as well as
  • the initial scanning voltage is a low level, and the switching scanning voltage is equal to the initial scanning voltage.
  • the gate driving module when the gate driving module is in the first operating mode, the first thin film transistor is closed, the second thin film transistor is turned off; and the third thin film transistor is closed. Said fourth thin film transistor is turned off;
  • the gate driving module When the gate driving module is in the second operating mode, the first thin film transistor is turned off, the second thin film transistor is closed; the third thin film transistor is closed, and the fourth thin film transistor is turned off; as well as
  • the third thin film transistor is turned off, and the fourth thin film transistor is turned off.
  • the present invention constructs a GOA circuit comprising: a plurality of gate driving modules for inputting scanning signals to scan lines, the gate driving modules comprising:
  • a first control branch for controlling the gate driving module to output a switching scan voltage associated with the initial scan voltage
  • a second control branch configured to control the gate driving module to output a switching scan voltage that is not associated with the initial scan voltage
  • a third control branch configured to control the first control branch to be turned on when the gate driving module is in a first working mode; and to control the gate driving module when in the second working mode Opening of the second control branch; wherein the gate driving module has the first working mode, the second working mode, and the third working mode;
  • a fourth control branch configured to control outputting the initial scan voltage when the gate driving module is in the third operating mode.
  • the output control unit has a control voltage and a high level power supply
  • the first control branch includes a first thin film transistor
  • the second control branch includes a second thin film transistor
  • the third control branch includes a third thin film transistor
  • the fourth control branch includes a fourth thin film
  • the first thin film transistor has a first input end, a first control end, and a first output end
  • the second thin film transistor has a second input end, a second control end, and a second output end
  • the thin film transistor has a third input end, a third control end, and a third output end
  • the fourth thin film transistor has a fourth input end, a fourth control end, and a fourth output end;
  • the first control end and the second control end are connected to the control voltage, the first input end is connected to the initial scan voltage; the first output end is respectively connected to the second output end and the first a third input terminal is connected; the second input terminal is connected to the high level power supply; the third control terminal and the fourth control terminal are connected to the initial scan voltage; and the fourth input terminal is connected to the fourth input terminal
  • the control terminal is connected to the fourth output end, and the fourth output end is further connected to the scan line.
  • the first thin film transistor is a PNP type thin film transistor
  • the second thin film transistor is an NPN type thin film transistor
  • the third thin film transistor is an NPN type thin film transistor
  • the fourth thin film transistor It is a PNP type thin film transistor.
  • control voltage has a high level and a low level
  • initial scan voltage also has a high level and a low level
  • the initial scanning voltage is a high level, and the control voltage is a low level, and the switching scanning voltage is equal to the initial scanning voltage
  • the initial scanning voltage is a high level
  • the control voltage is a high level
  • the switching scanning voltage is equal to a voltage of the high level power supply ;
  • the initial scanning voltage is a low level, and the switching scanning voltage is equal to the initial scanning voltage.
  • the gate driving module when the gate driving module is in the first operating mode, the first thin film transistor is closed, the second thin film transistor is turned off; and the third thin film transistor is closed. Said fourth thin film transistor is turned off;
  • the gate driving module When the gate driving module is in the second operating mode, the first thin film transistor is turned off, the second thin film transistor is closed; the third thin film transistor is closed, and the fourth thin film transistor is turned off;
  • the third thin film transistor is turned off, and the fourth thin film transistor is turned off.
  • the invention also provides a liquid crystal display device comprising:
  • GOA circuit which includes:
  • the gate driving module comprising:
  • a first control branch for controlling the gate driving module to output a switching scan voltage associated with the initial scan voltage
  • a second control branch configured to control the gate driving module to output a switching scan voltage that is not associated with the initial scan voltage
  • a third control branch configured to control the first control branch to be turned on when the gate driving module is in a first working mode; and to control the gate driving module when in the second working mode Opening of the second control branch; wherein the gate driving module has the first working mode, the second working mode, and the third working mode;
  • a fourth control branch configured to control outputting the initial scan voltage when the gate driving module is in the third operating mode.
  • the output control unit has a control voltage and a high level power supply
  • the first control branch includes a first thin film transistor
  • the second control branch includes a second thin film transistor
  • the third control branch includes a third thin film transistor
  • the fourth control branch includes a fourth thin film
  • the first thin film transistor has a first input end, a first control end, and a first output end
  • the second thin film transistor has a second input end, a second control end, and a second output end
  • the thin film transistor has a third input end, a third control end, and a third output end
  • the fourth thin film transistor has a fourth input end, a fourth control end, and a fourth output end;
  • the first control end and the second control end are connected to the control voltage, the first input end is connected to the initial scan voltage; the first output end is respectively connected to the second output end and the first a third input terminal is connected; the second input terminal is connected to the high level power supply; the third control terminal and the fourth control terminal are connected to the initial scan voltage; and the fourth input terminal is connected to the fourth input terminal
  • the control terminal is connected to the fourth output end, and the fourth output end is further connected to the scan line.
  • the first thin film transistor is a PNP type thin film transistor
  • the second thin film transistor is an NPN type thin film transistor
  • the third thin film transistor is an NPN type thin film transistor
  • the fourth thin film The transistor is a PNP type thin film transistor.
  • control voltage has a high level and a low level
  • initial scan voltage also has a high level and a low level
  • the initial scanning voltage is a high level, and the control voltage is a low level, and the switching scanning voltage is equal to the initial scanning voltage
  • the initial scanning voltage is a high level
  • the control voltage is a high level
  • the switching scanning voltage is equal to a voltage of the high level power supply ;
  • the initial scanning voltage is a low level, and the switching scanning voltage is equal to the initial scanning voltage.
  • the gate driving module when the gate driving module is in the first operation mode, the first thin film transistor is turned off, the second thin film transistor is turned off; and the third thin film transistor is turned off, The fourth thin film transistor is turned off;
  • the gate driving module When the gate driving module is in the second operating mode, the first thin film transistor is turned off, the second thin film transistor is closed; the third thin film transistor is closed, and the fourth thin film transistor is turned off;
  • the third thin film transistor is turned off, and the fourth thin film transistor is turned off.
  • the falling time is prolonged when the scanning voltage is lowered, thereby avoiding influence on the reference voltage and improving display. effect.
  • 1 is an output waveform diagram of a gate voltage after chamfering in the prior art
  • FIG. 2 is a schematic structural view of a gate driving module of the present invention
  • FIG. 3 is a circuit diagram of an output control unit of the present invention.
  • FIG. 4 is a waveform diagram of an output voltage of a GOA circuit of the present invention.
  • FIG. 2 is a schematic structural diagram of a gate driving module according to the present invention.
  • the GOA circuit of the present invention includes a plurality of gate driving modules for inputting scanning signals to the scanning lines.
  • the number of the gate driving modules is the same as the number of scanning lines, as shown in FIG. 2 .
  • the gate driving module 10 includes a GOA unit 11 and an output control unit 12; wherein the gate driving module 10 has a first working mode, a second working mode, and a third working mode;
  • the GOA unit 11 is configured to provide an initial scan voltage; the output control unit 12 is connected to the GOA unit 11, and the output control unit 12 is configured to extend the decrease of the initial scan voltage during the initial scan voltage drop
  • the output control unit 12 includes: a first control branch 121 and a second control branch 122, a third control branch 123, and a fourth control branch 124, wherein the first control branch 121 is used to control the
  • the gate driving module outputs a switching scan voltage associated with the initial scan voltage
  • the second control branch 122 is configured to control the gate driving module to output a switching scan voltage that is not associated with the initial scan voltage;
  • the third control branch 123 is configured to control the first control branch 121 to be turned on when the gate driving module is in the first working mode; and when the gate driving module is in the second working mode Controlling the opening of the second control branch 122;
  • the fourth control branch 124 is configured to control outputting the initial scan voltage when the gate driving module is in the third operating mode.
  • the output control unit 12 is input with a control voltage Um and a high level power supply;
  • the first control branch 121 includes a first thin film transistor T1
  • the second control branch 122 includes a second thin film transistor T2
  • the third control branch 123 includes a third thin film transistor T3, and the fourth control
  • the branch 124 includes a fourth thin film transistor T4;
  • the first thin film transistor T1 has a first input end, a first control end, and a first output end;
  • the second thin film transistor T2 has a second input end, a second control end, and a second output end;
  • the thin film transistor T3 has a third input end, a third control end, and a third output end;
  • the fourth thin film transistor T4 has a fourth input end, a fourth control end, and a fourth output end;
  • the first control end and the second control end are connected to the control voltage Um, the first input end is connected to the initial scan voltage Ui; the first output end is respectively connected to the second output end and the The third input terminal is connected; the second input terminal is connected to the high level power supply; the third control terminal and the fourth control terminal are connected to the initial scan voltage Ui; and the fourth input terminal is connected to a fourth control end, the third output end is connected to the fourth output end, and the fourth output end is further connected to the scan line (not shown), that is, the output control unit 12 outputs a switching scan
  • the voltage UO, the voltage value VGH of the high-level power source is, for example, 15V.
  • the first thin film transistor T1 is a PNP type thin film transistor
  • the second thin film transistor T2 is an NPN type thin film transistor
  • the third thin film transistor T3 is an NPN type thin film transistor
  • the fourth thin film transistor T4 is a PNP type thin film. Transistor.
  • control voltage Um has a high level and a low level;
  • initial scan voltage Ui also has a high level and a low level;
  • the initial scanning voltage Ui is a high level
  • the control voltage Um is a low level
  • the third control branch is The road 123 is in a connected state
  • the fourth control branch 124 is in an open state
  • the first control branch 121 is in a connected state
  • the second control branch 122 is in an open state
  • the switching scan voltage UO is Is equal to the initial scan voltage Ui; for example, the period t0-t1, Ui is 33V, Um is 0V, UO is 33V;
  • the initial scanning voltage Ui is at a high level, and the control voltage Um is also a high level, and the third control branch 123 is in a connected state.
  • the fourth control branch 124 is in an off state, the first control branch 121 is in an off state, the second control branch 122 is in a connected state, and the switching scan voltage UO is equal to the high power
  • the voltage of the flat power supply VGH such as the period t1-t2, Ui is 33V, Um is 33V, UO is 15V;
  • the initial scanning voltage Ui is at a low level
  • the third control branch 123 is in an off state
  • the fourth control branch 124 is in an off state.
  • the switching scan voltage UO is equal to the initial scan voltage Ui, such as the period t2-t3, Ui is -7V, and UO is -7V.
  • the control voltage Um has a high level and a low level; when the gate driving module is in the first operating mode, the first thin film transistor T1 is closed, and the second thin film transistor T2 is off. Opening; the third thin film transistor T3 is closed, and the fourth thin film transistor T4 is turned off;
  • the first thin film transistor T1 is turned off, the second thin film transistor T2 is closed; the third thin film transistor T3 is closed, and the fourth thin film transistor is closed. T4 is disconnected;
  • the third thin film transistor T3 is turned off, and the fourth thin film transistor T4 is closed.
  • the output voltage of the GOA unit changes from a high level to a low level
  • the output voltage of the GOA unit is first lowered to an intermediate value by the output control unit, and then reduced to a minimum value, thereby prolonging the fall time of the output voltage of the GOA circuit.
  • the influence of the reference voltage of the liquid crystal display device can be avoided, and the display effect is improved.
  • the GOA circuit of the present invention increases the fall time when the scan voltage is lowered by adding an output control unit to the output end of the existing GOA unit, thereby avoiding the influence on the reference voltage and improving the display effect.
  • the present invention also provides a liquid crystal display device including an array substrate, a color filter substrate, the array substrate including a plurality of data lines and a plurality of scan lines, and a plurality of pixels defined by the data lines and the scan lines
  • the array substrate further includes a GOA circuit, the GOA circuit includes a plurality of gate driving modules, and the gate driving module is configured to input a scanning signal to the scan line, the number of the gate driving module and the number of scanning lines Consistent
  • the gate driving module 10 includes a GOA unit 11 and an output control unit 12; wherein the gate driving module 10 has the first working mode, the second working mode, and the third working mode. ;
  • the GOA unit 11 is configured to provide an initial scan voltage; the output control unit 12 is connected to the GOA unit 11, and the output control unit 12 is configured to extend the decrease of the initial scan voltage during the initial scan voltage drop
  • the output control unit 12 includes: a first control branch 121 and a second control branch 122, a third control branch 123, and a fourth control branch 124, wherein the first control branch 121 is used to control the
  • the gate driving module outputs a switching scan voltage associated with the initial scan voltage
  • the second control branch 122 is configured to control the gate driving module to output a switching scan voltage that is not associated with the initial scan voltage;
  • the third control branch 123 is configured to control the first control branch 121 to be turned on when the gate driving module is in the first working mode; and when the gate driving module is in the second working mode Controlling the opening of the second control branch 122;
  • a fourth control branch configured to control outputting the initial scan voltage when the gate driving module is in the third operating mode.
  • the output control unit 12 is input with a control voltage Um and a high level power supply;
  • the first control branch 121 includes a first thin film transistor T1
  • the second control branch 122 includes a second thin film transistor T2
  • the third control branch 123 includes a third thin film transistor T3, and the fourth control
  • the branch 124 includes a fourth thin film transistor T4;
  • the first thin film transistor T1 has a first input end, a first control end, and a first output end;
  • the second thin film transistor T2 has a second input end, a second control end, and a second output end;
  • the thin film transistor T3 has a third input end, a third control end, and a third output end;
  • the fourth thin film transistor T4 has a fourth input end, a fourth control end, and a fourth output end;
  • the first control end and the second control end are connected to the control voltage Um, the first input end is connected to the initial scan voltage Ui; the first output end is respectively connected to the second output end and the The third input terminal is connected; the second input terminal is connected to the high level power supply; the third control terminal and the fourth control terminal are connected to the initial scan voltage Ui; and the fourth input terminal is connected to a fourth control end, the third output end is connected to the fourth output end, and the fourth output end is further connected to the scan line (not shown), that is, the output control unit 12 outputs a switching scan Voltage UO.
  • the voltage value VGH of the high-level power source is, for example, 15V.
  • the first thin film transistor T1 is a PNP type thin film transistor
  • the second thin film transistor T2 is an NPN type thin film transistor
  • the third thin film transistor T3 is an NPN type thin film transistor
  • the fourth thin film transistor T4 is a PNP type thin film. Transistor.
  • control voltage Um has a high level and a low level;
  • initial scan voltage Ui also has a high level and a low level;
  • the initial scanning voltage Ui is a high level
  • the control voltage Um is a low level
  • the third control branch is The road 123 is in a connected state
  • the fourth control branch 124 is in an open state
  • the first control branch 121 is in a connected state
  • the second control branch 122 is in an open state
  • the switching scan voltage UO is Is equal to the initial scan voltage Ui; for example, the period t0-t1, Ui is 33V, Um is 0V, UO is 33V;
  • the initial scanning voltage Ui is at a high level
  • the control voltage Um is at a high level
  • the third control branch 123 is in a connected state.
  • the fourth control branch 124 is in an off state
  • the first control branch 121 is in an off state
  • the second control branch 122 is in a connected state
  • the switching scan voltage UO is equal to the high level.
  • the voltage of the power supply VGH such as the period t1-t2, Ui is 33V, Um is 33V, UO is 15V;
  • the initial scanning voltage Ui is at a low level
  • the third control branch 123 is in an off state
  • the fourth control branch 124 is in an off state.
  • the switching scan voltage UO is equal to the initial scan voltage Ui, such as the period t2-t3, Ui is -7V, and UO is -7V.
  • the control voltage Um has a high level and a low level; when the gate driving module is in the first operating mode, the first thin film transistor T1 is closed, and the second thin film transistor T2 is off. Opening; the third thin film transistor T3 is closed, and the fourth thin film transistor T4 is turned off;
  • the first thin film transistor T1 is turned off, the second thin film transistor T2 is closed; the third thin film transistor T3 is closed, and the fourth thin film transistor is closed. T4 is disconnected;
  • the third thin film transistor T3 is turned off, and the fourth thin film transistor T4 is closed.
  • the output voltage of the GOA unit changes from a high level to a low level
  • the output voltage of the GOA unit is first lowered to an intermediate value by the output control unit, and then reduced to a minimum value, thereby prolonging the fall time of the output voltage of the GOA circuit.
  • the influence of the reference voltage of the liquid crystal display device can be avoided, and the display effect is improved.
  • the falling time is prolonged when the scanning voltage is lowered, thereby avoiding the influence on the reference voltage and improving the display effect.

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Abstract

提供了一种GOA电路及液晶显示装置。GOA电路包括多个用于向扫描线输入扫描信号的栅极驱动模块（10），栅极驱动模块（10）包括GOA单元（11）、输出控制单元（12）；输出控制单元（12）包括第一控制支路（121）、第二控制支路（122）、第三控制支路（123）、第四控制支路（124）。

Description

一种GOA电路及液晶显示装置 技术领域
本发明涉及显示器技术领域，特别是涉及一种GOA电路及液晶显示装置。
 背景技术
随着薄膜晶体管液晶显示器（TFT-LCD，Thin Film Transistor Liquid Crystal Display）的不断发展，TFT-LCD已经成为了现代IT、视讯产品中重要的显示平台，也使得用户对其要求越来越高。为了满足超窄边框及低成本的需求，使得GOA（Gate On Array，栅级驱动芯片集成于阵列基板）技术得到了飞速发展。
在实际驱动过程中，栅极电压输出的下降沿变化过快会影响面板内部的基准电压，且影响的程度与单位时间内电压的变化正相关。传统架构的设计中，会通过PCB端的设计对栅极的输出进行削角，即将高电平下降到低电平的时间延长，以减小对基准电压影响。图1为经过削角后的栅极电压的输出波形图，该高电平例如为V2（比如为33V），低电平为V1（比如为-7V）。然而GOA技术由于其栅极输入电压是在阵列基板上形成，所以无法通过PCB端的设计对栅极的输出电压进行削角，从而使得现有的GOA技术的液晶显示装置基准电压容易受到影响，降低了显示效果。
因此，有必要提供一种GOA电路及液晶显示装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种GOA电路及液晶显示装置，以解决现有技术的GOA技术的液晶显示装置，由于无法延长栅极输入电压的下降时间，从而导致容易影响基准电压，降低了显示效果的技术问题。
 技术解决方案
为解决上述技术问题，本发明构造了一种GOA电路，其包括：多个用于向扫描线输入扫描信号的栅极驱动模块，所述栅极驱动模块包括：
GOA单元，用于提供初始扫描电压； 以及
输出控制单元，与所述GOA单元连接；所述输出控制单元包括：
第一控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压相关联的切换扫描电压；所述第一控制支路包括第一薄膜晶体管；
第二控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压不关联的切换扫描电压；所述第二控制支路包括第二薄膜晶体管；
第三控制支路，用于当所述栅极驱动模块处于第一工作模式时，控制所述第一控制支路开启；以及当所述栅极驱动模块处于第二工作模式时，控制所述第二控制支路的开启；其中所述栅极驱动模块具有所述第一工作模式、所述第二工作模式、第三工作模式；所述第三控制支路包括第三薄膜晶体管；以及
第四控制支路，用于当所述栅极驱动模块处于所述第三工作模式时，控制输出所述初始扫描电压；所述第四控制支路包括第四薄膜晶体管；
其中，所述控制电压具有高电平和低电平；所述初始扫描电压也具有高电平和低电平；所述第一薄膜晶体管为PNP型薄膜晶体管，所述第二薄膜晶体管为NPN型薄膜晶体管；所述第三薄膜晶体管为NPN型薄膜晶体管，所述第四薄膜晶体管为PNP型薄膜晶体管。
在本发明的GOA电路中，所述输出控制单元具有控制电压和高电平电源；
所述第一薄膜晶体管具有第一输入端、第一控制端、第一输出端；所述第二薄膜晶体管具有第二输入端、第二控制端、第二输出端；所述第三薄膜晶体管具有第三输入端、第三控制端、第三输出端；所述第四薄膜晶体管具有第四输入端、第四控制端、第四输出端；
所述第一控制端和所述第二控制端连接所述控制电压，所述第一输入端连接所述初始扫描电压；所述第一输出端分别与所述第二输出端以及所述第三输入端连接；所述第二输入端连接所述高电平电源；所述第三控制端和所述第四控制端连接所述初始扫描电压；所述第四输入端连接所述第四控制端，所述第三输出端连接所述第四输出端，所述第四输出端还连接所述扫描线。
在本发明的GOA电路中，当所述栅极驱动模块处于所述第一工作模式时，所述初始扫描电压为高电平，且所述控制电压为低电平，所述切换扫描电压等于所述初始扫描电压；
当所述栅极驱动模块处于所述第二工作模式时，所述初始扫描电压为高电平，且所述控制电压为高电平，所述切换扫描电压等于所述高电平电源的电压；以及
当所述栅极驱动模块处于所述第三工作模式时，所述初始扫描电压为低电平，所述切换扫描电压等于所述初始扫描电压。
在本发明的GOA电路中，当所述栅极驱动模块处于所述第一工作模式时，所述第一薄膜晶体管闭合，所述第二薄膜晶体管断开；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；
当所述栅极驱动模块处于所述第二工作模式时，所述第一薄膜晶体管断开，所述第二薄膜晶体管闭合；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；以及
当所述栅极驱动模块处于所述第三工作模式时，所述第三薄膜晶体管断开，所述第四薄膜晶体管闭合。
为解决上述技术问题，本发明构造了一种GOA电路，其包括：多个用于向扫描线输入扫描信号的栅极驱动模块，所述栅极驱动模块包括：
GOA单元，用于提供初始扫描电压；
输出控制单元，与所述GOA单元连接；所述输出控制单元包括：
第一控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压相关联的切换扫描电压；
第二控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压不关联的切换扫描电压；
第三控制支路，用于当所述栅极驱动模块处于第一工作模式时，控制所述第一控制支路开启；以及当所述栅极驱动模块处于第二工作模式时，控制所述第二控制支路的开启；其中所述栅极驱动模块具有所述第一工作模式、所述第二工作模式、第三工作模式；
第四控制支路，用于当所述栅极驱动模块处于所述第三工作模式时，控制输出所述初始扫描电压。
在本发明的GOA电路中，所述输出控制单元具有控制电压和高电平电源；
所述第一控制支路包括第一薄膜晶体管、所述第二控制支路包括第二薄膜晶体管、所述第三控制支路包括第三薄膜晶体管、所述第四控制支路包括第四薄膜晶体管；所述第一薄膜晶体管具有第一输入端、第一控制端、第一输出端；所述第二薄膜晶体管具有第二输入端、第二控制端、第二输出端；所述第三薄膜晶体管具有第三输入端、第三控制端、第三输出端；所述第四薄膜晶体管具有第四输入端、第四控制端、第四输出端；
所述第一控制端和所述第二控制端连接所述控制电压，所述第一输入端连接所述初始扫描电压；所述第一输出端分别与所述第二输出端以及所述第三输入端连接；所述第二输入端连接所述高电平电源；所述第三控制端和所述第四控制端连接所述初始扫描电压；所述第四输入端连接所述第四控制端，所述第三输出端连接所述第四输出端，所述第四输出端还连接所述扫描线。
在本发明的GOA电路中，所述第一薄膜晶体管为PNP型薄膜晶体管，所述第二薄膜晶体管为NPN型薄膜晶体管；所述第三薄膜晶体管为NPN型薄膜晶体管，所述第四薄膜晶体管为PNP型薄膜晶体管。
在本发明的GOA电路中，所述控制电压具有高电平和低电平；所述初始扫描电压也具有高电平和低电平；
当所述栅极驱动模块处于所述第一工作模式时，所述初始扫描电压为高电平，且所述控制电压为低电平，所述切换扫描电压等于所述初始扫描电压；
当所述栅极驱动模块处于所述第二工作模式时，所述初始扫描电压为高电平，且所述控制电压为高电平，所述切换扫描电压等于所述高电平电源的电压；
当所述栅极驱动模块处于所述第三工作模式时，所述初始扫描电压为低电平，所述切换扫描电压等于所述初始扫描电压。
在本发明的GOA电路中，当所述栅极驱动模块处于所述第一工作模式时，所述第一薄膜晶体管闭合，所述第二薄膜晶体管断开；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；
当所述栅极驱动模块处于所述第二工作模式时，所述第一薄膜晶体管断开，所述第二薄膜晶体管闭合；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；
当所述栅极驱动模块处于所述第三工作模式时，所述第三薄膜晶体管断开，所述第四薄膜晶体管闭合。
本发明还提供一种液晶显示装置，其包括：
GOA电路，其包括：
多个用于向扫描线输入扫描信号的栅极驱动模块，所述栅极驱动模块包括：
GOA单元，用于提供初始扫描电压；
输出控制单元，与所述GOA单元连接；所述输出控制单元包括：
第一控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压相关联的切换扫描电压；
第二控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压不关联的切换扫描电压；
第三控制支路，用于当所述栅极驱动模块处于第一工作模式时，控制所述第一控制支路开启；以及当所述栅极驱动模块处于第二工作模式时，控制所述第二控制支路的开启；其中所述栅极驱动模块具有所述第一工作模式、所述第二工作模式、第三工作模式；
第四控制支路，用于当所述栅极驱动模块处于所述第三工作模式时，控制输出所述初始扫描电压。
在本发明的液晶显示装置中，所述输出控制单元具有控制电压和高电平电源；
所述第一控制支路包括第一薄膜晶体管、所述第二控制支路包括第二薄膜晶体管、所述第三控制支路包括第三薄膜晶体管、所述第四控制支路包括第四薄膜晶体管；所述第一薄膜晶体管具有第一输入端、第一控制端、第一输出端；所述第二薄膜晶体管具有第二输入端、第二控制端、第二输出端；所述第三薄膜晶体管具有第三输入端、第三控制端、第三输出端；所述第四薄膜晶体管具有第四输入端、第四控制端、第四输出端；
所述第一控制端和所述第二控制端连接所述控制电压，所述第一输入端连接所述初始扫描电压；所述第一输出端分别与所述第二输出端以及所述第三输入端连接；所述第二输入端连接所述高电平电源；所述第三控制端和所述第四控制端连接所述初始扫描电压；所述第四输入端连接所述第四控制端，所述第三输出端连接所述第四输出端，所述第四输出端还连接所述扫描线。
在本发明的液晶显示装置中，所述第一薄膜晶体管为PNP型薄膜晶体管，所述第二薄膜晶体管为NPN型薄膜晶体管；所述第三薄膜晶体管为NPN型薄膜晶体管，所述第四薄膜晶体管为PNP型薄膜晶体管。
在本发明的液晶显示装置中，所述控制电压具有高电平和低电平；所述初始扫描电压也具有高电平和低电平；
当所述栅极驱动模块处于所述第一工作模式时，所述初始扫描电压为高电平，且所述控制电压为低电平，所述切换扫描电压等于所述初始扫描电压；
当所述栅极驱动模块处于所述第二工作模式时，所述初始扫描电压为高电平，且所述控制电压为高电平，所述切换扫描电压等于所述高电平电源的电压；
当所述栅极驱动模块处于所述第三工作模式时，所述初始扫描电压为低电平，所述切换扫描电压等于所述初始扫描电压。
在本发明的液晶显示装置中，当所述栅极驱动模块处于所述第一工作模式时，所述第一薄膜晶体管闭合，所述第二薄膜晶体管断开；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；
当所述栅极驱动模块处于所述第二工作模式时，所述第一薄膜晶体管断开，所述第二薄膜晶体管闭合；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；
当所述栅极驱动模块处于所述第三工作模式时，所述第三薄膜晶体管断开，所述第四薄膜晶体管闭合。
有益效果
本发明的GOA电路及液晶显示装置，通过在现有的GOA单元的输出端增加输出控制单元，从而使得在扫描电压下降时，延长其下降时间，从而避免了对基准电压造成影响，提高了显示效果。
 附图说明
图1为现有技术的经过削角后的栅极电压的输出波形图；
图2为本发明的栅极驱动模块的结构示意图；
图3为本发明的输出控制单元的电路图；
图4为本发明的GOA电路的输出电压的波形图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明的栅极驱动模块的结构示意图；
本发明的GOA电路包括多个栅极驱动模块，该栅极驱动模块用于向扫描线输入扫描信号，该栅极驱动模块的个数与扫描线的条数一致，如图2所示，所述栅极驱动模块10包括GOA单元11和输出控制单元12；其中所述栅极驱动模块10具有第一工作模式、第二工作模式、第三工作模式；
该GOA单元11，用于提供初始扫描电压；该输出控制单元12与该GOA单元11连接，所述输出控制单元12用于在所述初始扫描电压下降过程中，延长所述初始扫描电压的下降时间；该输出控制单元12包括：第一控制支路121和第二控制支路122、第三控制支路123和第四控制支路124，所述第一控制支路121用来控制所述栅极驱动模块输出与所述初始扫描电压相关联的切换扫描电压，所述第二控制支路122用来控制所述栅极驱动模块输出与所述初始扫描电压不关联的切换扫描电压；
所述第三控制支路123，用于当所述栅极驱动模块处于第一工作模式时，控制所述第一控制支路121开启；以及当所述栅极驱动模块处于第二工作模式时，控制所述第二控制支路122的开启；
第四控制支路124，用于当所述栅极驱动模块处于所述第三工作模式时，控制输出所述初始扫描电压。
具体地，如图3所示，该输出控制单元12输入有控制电压Um和高电平电源；
所述第一控制支路121包括第一薄膜晶体管T1，所述第二控制支路122包括第二薄膜晶体管T2；所述第三控制支路123包括第三薄膜晶体管T3、所述第四控制支路124包括第四薄膜晶体管T4；
所述第一薄膜晶体管T1具有第一输入端、第一控制端、第一输出端；所述第二薄膜晶体管T2具有第二输入端、第二控制端、第二输出端；所述第三薄膜晶体管T3具有第三输入端、第三控制端、第三输出端；所述第四薄膜晶体管T4具有第四输入端、第四控制端、第四输出端；
所述第一控制端和所述第二控制端连接所述控制电压Um，所述第一输入端连接所述初始扫描电压Ui；所述第一输出端分别与所述第二输出端以及所述第三输入端连接；所述第二输入端连接所述高电平电源；所述第三控制端和所述第四控制端连接所述初始扫描电压Ui；所述第四输入端连接所述第四控制端，所述第三输出端连接所述第四输出端，所述第四输出端还连接所述扫描线（图中未示出），也即该输出控制单元12输出切换扫描电压UO，该高电平电源的电压值VGH例如为15V。
所述第一薄膜晶体管T1为PNP型薄膜晶体管，所述第二薄膜晶体管T2为NPN型薄膜晶体管；所述第三薄膜晶体管T3为NPN型薄膜晶体管，所述第四薄膜晶体管T4为PNP型薄膜晶体管。
结合图2，所述控制电压Um具有高电平和低电平；所述初始扫描电压Ui也具有高电平和低电平；
如图4所示，当所述栅极驱动模块处于所述第一工作模式时，所述初始扫描电压Ui为高电平，且所述控制电压Um为低电平，所述第三控制支路123处于连通状态，所述第四控制支路124处于断开状态，所述第一控制支路121处于连通状态，所述第二控制支路122处于断开状态，所述切换扫描电压UO等于所述初始扫描电压Ui；比如t0-t1时段，Ui为33V，Um为0V，UO为33V；
当所述栅极驱动模块处于所述第二工作模式时，所述初始扫描电压Ui为高电平，且所述控制电压Um也为高电平，所述第三控制支路123处于连通状态，所述第四控制支路124处于断开状态，所述第一控制支路121处于断开状态，所述第二控制支路122处于连通状态，所述切换扫描电压UO等于所述高电平电源的电压VGH，比如t1-t2时段，Ui为33V，Um为33V，UO为15V；
当所述栅极驱动模块处于所述第三工作模式时，所述初始扫描电压Ui为低电平，此时所述第三控制支路123处于断开状态，所述第四控制支路124处于连通状态，无论所述控制电压Um为高电平还是低电平，所述切换扫描电压UO等于所述初始扫描电压Ui，比如t2-t3时段，Ui为-7V，UO为-7V。
结合图3，所述控制电压Um具有高电平和低电平；当所述栅极驱动模块处于所述第一工作模式时，所述第一薄膜晶体管T1闭合，所述第二薄膜晶体管T2断开；所述第三薄膜晶体T3管闭合，所述第四薄膜晶体管T4断开；
当所述栅极驱动模块处于所述第二工作模式时，所述第一薄膜晶体管T1断开，所述第二薄膜晶体管T2闭合；所述第三薄膜晶体管T3闭合，所述第四薄膜晶体管T4断开；
当所述栅极驱动模块处于所述第三工作模式时，所述第三薄膜晶体管T3断开，所述第四薄膜晶体管T4闭合。
由于在GOA单元的输出电压由高电平变为低电平时，通过输出控制单元将GOA单元的输出电压先降到中间值，再降至最小值，从而延长了GOA电路的输出电压的下降时间，可以避免了对液晶显示装置的基准电压造成影响，提高了显示效果。
本发明的GOA电路，通过在现有的GOA单元的输出端增加输出控制单元，从而使得在扫描电压下降时，延长其下降时间，从而避免了对基准电压造成影响，提高了显示效果。
本发明还提供一种液晶显示装置，其包括阵列基板、彩膜基板，所述阵列基板包括多条数据线和多条扫描线，以及由所述数据线和所述扫描线限定的多个像素单元，所述阵列基板还包括GOA电路，该GOA电路包括多个栅极驱动模块，该栅极驱动模块用于向扫描线输入扫描信号，该栅极驱动模块的个数与扫描线的条数一致；
如图2所示，所述栅极驱动模块10包括GOA单元11和输出控制单元12；其中所述栅极驱动模块10具有所述第一工作模式、所述第二工作模式、第三工作模式；
该GOA单元11，用于提供初始扫描电压；该输出控制单元12与该GOA单元11连接，所述输出控制单元12用于在所述初始扫描电压下降过程中，延长所述初始扫描电压的下降时间；该输出控制单元12包括：第一控制支路121和第二控制支路122、第三控制支路123和第四控制支路124，所述第一控制支路121用来控制所述栅极驱动模块输出与所述初始扫描电压相关联的切换扫描电压，所述第二控制支路122用来控制所述栅极驱动模块输出与所述初始扫描电压不关联的切换扫描电压；
所述第三控制支路123，用于当所述栅极驱动模块处于第一工作模式时，控制所述第一控制支路121开启；以及当所述栅极驱动模块处于第二工作模式时，控制所述第二控制支路122的开启；
第四控制支路，用于当所述栅极驱动模块处于所述第三工作模式时，控制输出所述初始扫描电压。
具体地，如图3所示，该输出控制单元12输入有控制电压Um和高电平电源；
所述第一控制支路121包括第一薄膜晶体管T1，所述第二控制支路122包括第二薄膜晶体管T2；所述第三控制支路123包括第三薄膜晶体管T3、所述第四控制支路124包括第四薄膜晶体管T4；
所述第一薄膜晶体管T1具有第一输入端、第一控制端、第一输出端；所述第二薄膜晶体管T2具有第二输入端、第二控制端、第二输出端；所述第三薄膜晶体管T3具有第三输入端、第三控制端、第三输出端；所述第四薄膜晶体管T4具有第四输入端、第四控制端、第四输出端；
所述第一控制端和所述第二控制端连接所述控制电压Um，所述第一输入端连接所述初始扫描电压Ui；所述第一输出端分别与所述第二输出端以及所述第三输入端连接；所述第二输入端连接所述高电平电源；所述第三控制端和所述第四控制端连接所述初始扫描电压Ui；所述第四输入端连接所述第四控制端，所述第三输出端连接所述第四输出端，所述第四输出端还连接所述扫描线（图中未示出），也即该输出控制单元12输出切换扫描电压UO。该高电平电源的电压值VGH例如为15V。
所述第一薄膜晶体管T1为PNP型薄膜晶体管，所述第二薄膜晶体管T2为NPN型薄膜晶体管；所述第三薄膜晶体管T3为NPN型薄膜晶体管，所述第四薄膜晶体管T4为PNP型薄膜晶体管。
结合图2，所述控制电压Um具有高电平和低电平；所述初始扫描电压Ui也具有高电平和低电平；
如图4所示，当所述栅极驱动模块处于所述第一工作模式时，所述初始扫描电压Ui为高电平，且所述控制电压Um为低电平，所述第三控制支路123处于连通状态，所述第四控制支路124处于断开状态，所述第一控制支路121处于连通状态，所述第二控制支路122处于断开状态，所述切换扫描电压UO等于所述初始扫描电压Ui；比如t0-t1时段，Ui为33V，Um为0V，UO为33V；
当所述栅极驱动模块处于所述第二工作模式时，所述初始扫描电压Ui为高电平，且所述控制电压Um为高电平，所述第三控制支路123处于连通状态，所述第四控制支路124处于断开状态，所述第一控制支路121处于断开状态，所述第二控制支路122处于连通状态，所述切换扫描电压UO等于所述高电平电源的电压VGH，比如t1-t2时段，Ui为33V，Um为33V，UO为15V；
当所述栅极驱动模块处于所述第三工作模式时，所述初始扫描电压Ui为低电平，此时所述第三控制支路123处于断开状态，所述第四控制支路124处于连通状态，无论所述控制电压Um为高电平还是低电平，所述切换扫描电压UO等于所述初始扫描电压Ui，比如t2-t3时段，Ui为-7V，UO为-7V。
结合图3，所述控制电压Um具有高电平和低电平；当所述栅极驱动模块处于所述第一工作模式时，所述第一薄膜晶体管T1闭合，所述第二薄膜晶体管T2断开；所述第三薄膜晶体T3管闭合，所述第四薄膜晶体管T4断开；
当所述栅极驱动模块处于所述第二工作模式时，所述第一薄膜晶体管T1断开，所述第二薄膜晶体管T2闭合；所述第三薄膜晶体管T3闭合，所述第四薄膜晶体管T4断开；
当所述栅极驱动模块处于所述第三工作模式时，所述第三薄膜晶体管T3断开，所述第四薄膜晶体管T4闭合。
由于在GOA单元的输出电压由高电平变为低电平时，通过输出控制单元将GOA单元的输出电压先降到中间值，再降至最小值，从而延长了GOA电路的输出电压的下降时间，可以避免了对液晶显示装置的基准电压造成影响，提高了显示效果。
本发明的液晶显示装置，通过在现有的GOA单元的输出端增加输出控制单元，从而使得在扫描电压下降时，延长其下降时间，从而避免了对基准电压造成影响，提高了显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种GOA电路，其包括：多个用于向扫描线输入扫描信号的栅极驱动模块，所述栅极驱动模块包括：
    GOA单元，用于提供初始扫描电压； 以及
    输出控制单元，与所述GOA单元连接；所述输出控制单元包括：
    第一控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压相关联的切换扫描电压；所述第一控制支路包括第一薄膜晶体管；
    第二控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压不关联的切换扫描电压；所述第二控制支路包括第二薄膜晶体管；
    第三控制支路，用于当所述栅极驱动模块处于第一工作模式时，控制所述第一控制支路开启；以及当所述栅极驱动模块处于第二工作模式时，控制所述第二控制支路的开启；其中所述栅极驱动模块具有所述第一工作模式、所述第二工作模式、第三工作模式；所述第三控制支路包括第三薄膜晶体管；以及
    第四控制支路，用于当所述栅极驱动模块处于所述第三工作模式时，控制输出所述初始扫描电压；所述第四控制支路包括第四薄膜晶体管；
    其中，所述控制电压具有高电平和低电平；所述初始扫描电压也具有高电平和低电平；所述第一薄膜晶体管为PNP型薄膜晶体管，所述第二薄膜晶体管为NPN型薄膜晶体管；所述第三薄膜晶体管为NPN型薄膜晶体管，所述第四薄膜晶体管为PNP型薄膜晶体管。
  2. 根据权利要求1所述的GOA电路，其中所述输出控制单元具有控制电压和高电平电源；
    所述第一薄膜晶体管具有第一输入端、第一控制端、第一输出端；所述第二薄膜晶体管具有第二输入端、第二控制端、第二输出端；所述第三薄膜晶体管具有第三输入端、第三控制端、第三输出端；所述第四薄膜晶体管具有第四输入端、第四控制端、第四输出端；
    所述第一控制端和所述第二控制端连接所述控制电压，所述第一输入端连接所述初始扫描电压；所述第一输出端分别与所述第二输出端以及所述第三输入端连接；所述第二输入端连接所述高电平电源；所述第三控制端和所述第四控制端连接所述初始扫描电压；所述第四输入端连接所述第四控制端，所述第三输出端连接所述第四输出端，所述第四输出端还连接所述扫描线。
  3. 根据权利要求1所述的GOA电路，其中当所述栅极驱动模块处于所述第一工作模式时，所述初始扫描电压为高电平，且所述控制电压为低电平，所述切换扫描电压等于所述初始扫描电压；
    当所述栅极驱动模块处于所述第二工作模式时，所述初始扫描电压为高电平，且所述控制电压为高电平，所述切换扫描电压等于所述高电平电源的电压；以及
    当所述栅极驱动模块处于所述第三工作模式时，所述初始扫描电压为低电平，所述切换扫描电压等于所述初始扫描电压。
  4. 根据权利要求1所述的GOA电路，其中
    当所述栅极驱动模块处于所述第一工作模式时，所述第一薄膜晶体管闭合，所述第二薄膜晶体管断开；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；
    当所述栅极驱动模块处于所述第二工作模式时，所述第一薄膜晶体管断开，所述第二薄膜晶体管闭合；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；以及
    当所述栅极驱动模块处于所述第三工作模式时，所述第三薄膜晶体管断开，所述第四薄膜晶体管闭合。
  5. 一种GOA电路，其包括：多个用于向扫描线输入扫描信号的栅极驱动模块，所述栅极驱动模块包括：
    GOA单元，用于提供初始扫描电压；以及
    输出控制单元，与所述GOA单元连接；所述输出控制单元包括：
    第一控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压相关联的切换扫描电压；
    第二控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压不关联的切换扫描电压；
    第三控制支路，用于当所述栅极驱动模块处于第一工作模式时，控制所述第一控制支路开启；以及当所述栅极驱动模块处于第二工作模式时，控制所述第二控制支路的开启；其中所述栅极驱动模块具有所述第一工作模式、所述第二工作模式、第三工作模式；以及
    第四控制支路，用于当所述栅极驱动模块处于所述第三工作模式时，控制输出所述初始扫描电压。
  6. 根据权利要求5所述的GOA电路，其中
    所述输出控制单元具有控制电压和高电平电源；
    所述第一控制支路包括第一薄膜晶体管、所述第二控制支路包括第二薄膜晶体管、所述第三控制支路包括第三薄膜晶体管、所述第四控制支路包括第四薄膜晶体管；所述第一薄膜晶体管具有第一输入端、第一控制端、第一输出端；所述第二薄膜晶体管具有第二输入端、第二控制端、第二输出端；所述第三薄膜晶体管具有第三输入端、第三控制端、第三输出端；所述第四薄膜晶体管具有第四输入端、第四控制端、第四输出端；
    所述第一控制端和所述第二控制端连接所述控制电压，所述第一输入端连接所述初始扫描电压；所述第一输出端分别与所述第二输出端以及所述第三输入端连接；所述第二输入端连接所述高电平电源；所述第三控制端和所述第四控制端连接所述初始扫描电压；所述第四输入端连接所述第四控制端，所述第三输出端连接所述第四输出端，所述第四输出端还连接所述扫描线。
  7. 根据权利要求6所述的GOA电路，其中所述第一薄膜晶体管为PNP型薄膜晶体管，所述第二薄膜晶体管为NPN型薄膜晶体管；所述第三薄膜晶体管为NPN型薄膜晶体管，所述第四薄膜晶体管为PNP型薄膜晶体管。
  8. 根据权利要求6所述的GOA电路，其中所述控制电压具有高电平和低电平；所述初始扫描电压也具有高电平和低电平；
    当所述栅极驱动模块处于所述第一工作模式时，所述初始扫描电压为高电平，且所述控制电压为低电平，所述切换扫描电压等于所述初始扫描电压；
    当所述栅极驱动模块处于所述第二工作模式时，所述初始扫描电压为高电平，且所述控制电压为高电平，所述切换扫描电压等于所述高电平电源的电压；以及
    当所述栅极驱动模块处于所述第三工作模式时，所述初始扫描电压为低电平，所述切换扫描电压等于所述初始扫描电压。
  9. 根据权利要求6所述的GOA电路，其中
    当所述栅极驱动模块处于所述第一工作模式时，所述第一薄膜晶体管闭合，所述第二薄膜晶体管断开；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；
    当所述栅极驱动模块处于所述第二工作模式时，所述第一薄膜晶体管断开，所述第二薄膜晶体管闭合；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；以及
    当所述栅极驱动模块处于所述第三工作模式时，所述第三薄膜晶体管断开，所述第四薄膜晶体管闭合。
  10. 一种液晶显示装置，其包括：
    GOA电路，其包括：多个用于向扫描线输入扫描信号的栅极驱动模块，所述栅极驱动模块包括：
    GOA单元，用于提供初始扫描电压；以及
    输出控制单元，与所述GOA单元连接；所述输出控制单元包括：
    第一控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压相关联的切换扫描电压；
    第二控制支路，用于控制所述栅极驱动模块输出与所述初始扫描电压不关联的切换扫描电压；
    第三控制支路，用于当所述栅极驱动模块处于第一工作模式时，控制所述第一控制支路开启；以及当所述栅极驱动模块处于第二工作模式时，控制所述第二控制支路的开启；其中所述栅极驱动模块具有所述第一工作模式、所述第二工作模式、第三工作模式；以及
    第四控制支路，用于当所述栅极驱动模块处于所述第三工作模式时，控制输出所述初始扫描电压。
  11. 根据权利要求10所述的液晶显示装置，其中所述输出控制单元具有控制电压和高电平电源；
    所述第一控制支路包括第一薄膜晶体管、所述第二控制支路包括第二薄膜晶体管、所述第三控制支路包括第三薄膜晶体管、所述第四控制支路包括第四薄膜晶体管；所述第一薄膜晶体管具有第一输入端、第一控制端、第一输出端；所述第二薄膜晶体管具有第二输入端、第二控制端、第二输出端；所述第三薄膜晶体管具有第三输入端、第三控制端、第三输出端；所述第四薄膜晶体管具有第四输入端、第四控制端、第四输出端；
    所述第一控制端和所述第二控制端连接所述控制电压，所述第一输入端连接所述初始扫描电压；所述第一输出端分别与所述第二输出端以及所述第三输入端连接；所述第二输入端连接所述高电平电源；所述第三控制端和所述第四控制端连接所述初始扫描电压；所述第四输入端连接所述第四控制端，所述第三输出端连接所述第四输出端，所述第四输出端还连接所述扫描线。
  12. 根据权利要求11所述的液晶显示装置，其中所述第一薄膜晶体管为PNP型薄膜晶体管，所述第二薄膜晶体管为NPN型薄膜晶体管；所述第三薄膜晶体管为NPN型薄膜晶体管，所述第四薄膜晶体管为PNP型薄膜晶体管。
  13. 根据权利要求11所述的液晶显示装置，其中所述控制电压具有高电平和低电平；所述初始扫描电压也具有高电平和低电平；
    当所述栅极驱动模块处于所述第一工作模式时，所述初始扫描电压为高电平，且所述控制电压为低电平，所述切换扫描电压等于所述初始扫描电压；
    当所述栅极驱动模块处于所述第二工作模式时，所述初始扫描电压为高电平，且所述控制电压为高电平，所述切换扫描电压等于所述高电平电源的电压；以及
    当所述栅极驱动模块处于所述第三工作模式时，所述初始扫描电压为低电平，所述切换扫描电压等于所述初始扫描电压。
  14. 根据权利要求11所述的液晶显示装置，其中当所述栅极驱动模块处于所述第一工作模式时，所述第一薄膜晶体管闭合，所述第二薄膜晶体管断开；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；
    当所述栅极驱动模块处于所述第二工作模式时，所述第一薄膜晶体管断开，所述第二薄膜晶体管闭合；所述第三薄膜晶体管闭合，所述第四薄膜晶体管断开；以及
    当所述栅极驱动模块处于所述第三工作模式时，所述第三薄膜晶体管断开，所述第四薄膜晶体管闭合。
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