WO2017128780A1 - 放电电路、阵列基板、液晶显示面板及显示装置 - Google Patents

放电电路、阵列基板、液晶显示面板及显示装置 Download PDF

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Publication number
WO2017128780A1
WO2017128780A1 PCT/CN2016/102957 CN2016102957W WO2017128780A1 WO 2017128780 A1 WO2017128780 A1 WO 2017128780A1 CN 2016102957 W CN2016102957 W CN 2016102957W WO 2017128780 A1 WO2017128780 A1 WO 2017128780A1
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Prior art keywords
discharge
transistor
signal line
voltage power
signal
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PCT/CN2016/102957
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English (en)
French (fr)
Inventor
郝学光
马永达
吴新银
乔勇
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京东方科技集团股份有限公司
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Priority to US15/541,572 priority Critical patent/US10564493B2/en
Publication of WO2017128780A1 publication Critical patent/WO2017128780A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • Embodiments of the present disclosure relate to a discharge circuit, an array substrate, a liquid crystal display panel, and a display device.
  • the array substrate in the liquid crystal display panel of the LCD includes a pixel unit and a data line, and the data line is connected to the pixel unit, and the pixel unit is controlled to operate by the data line.
  • charge accumulation may occur on the data line, resulting in delay of operation of the pixel unit, flashing of the LCD, poor crosstalk, or damage of the electrostatic discharge. Therefore, the discharge of the data line is required by the discharge circuit.
  • the existing discharge circuit includes a discharge thin film transistor and a switching signal line.
  • the gate of the discharge thin film transistor is connected to the switching signal line, one of the source and the drain is connected to the data line, and the other is common to the array substrate.
  • the electrodes are connected, and the discharge thin film transistor is controlled by the switching signal line to discharge the electric charge on the data line to the common electrode.
  • the common electrode is usually disposed on the frame of the LCD, with the development trend of the narrow frame design of the LCD, the width of the common electrode is also narrower, the ability to withstand electric charges is weaker, and the charge on the data line cannot be completely Rapid release to the common electrode can also easily lead to pixel unit operation delay, LCD flashing, poor crosstalk or electrostatic discharge damage.
  • an embodiment of the present disclosure provides a discharge circuit including a discharge transistor, a signal control terminal, and a low voltage power supply terminal, a gate of the discharge transistor being connected to the signal control terminal, the discharge transistor
  • the first electrode is electrically connected to the signal line
  • the second electrode is electrically connected to the low voltage power terminal;
  • the discharge transistor is configured to discharge a charge on the signal line to the low voltage power supply terminal by a control signal outputted by the signal control terminal.
  • an embodiment of the present disclosure provides an array substrate, the array substrate including the discharge circuit.
  • an embodiment of the present disclosure provides a liquid crystal display panel, wherein the liquid crystal display panel includes the array substrate.
  • an embodiment of the present disclosure provides a display device, the display device including the liquid crystal display panel.
  • FIG. 1 is a schematic structural diagram of a discharge circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a discharge circuit according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of an electrostatic discharge protection module according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a discharge circuit according to still another embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a discharge circuit including a discharge transistor 1 , a signal control terminal 2 and a low voltage power supply terminal 3 .
  • the gate 11 of the discharge transistor 1 is connected to the signal control terminal 2 and discharged.
  • the first electrode 12 of the transistor 1 is electrically connected to the signal line 4, and the second electrode 13 of the discharge transistor 1 is electrically connected to the low voltage power terminal 3;
  • the discharge transistor 1 is configured to discharge the charge on the signal line 4 to the low voltage power supply terminal 3 by the control signal output from the signal control terminal 2.
  • the array substrate includes a substrate substrate, a pixel unit, and a data line and a gate line formed on the base substrate.
  • the signal line 4 may be a data line or a gate line, wherein one end of the data line and the control pixel The source of the pixel thin film transistor is connected, the other end of the data line is connected to the pixel unit, the pixel thin film transistor controls the pixel unit to work through the data line, and one end of the gate line on the array substrate is connected to the gate signal control end, and the gate line The other end is connected to the gate of the pixel thin film transistor, and the gate signal control terminal operates through the gate line to control the pixel thin film transistor.
  • the gate signal control terminal controls the pixel thin film transistor to be turned off via the gate line. If charge accumulation occurs on the data line, the pixel unit cannot immediately stop working, which may cause flicker, crosstalk, or electrostatic discharge of the display device. In the case of damage or the like; if charge accumulation occurs on the gate line, the signal from the gate signal control terminal that controls the closing of the thin film transistor of the pixel cannot be quickly transmitted to the pixel thin film transistor through the gate line, which also causes the pixel unit to operate with delay and display. The device has flicker, poor crosstalk, or electrostatic discharge damage.
  • the gate 11 of the discharge transistor is connected to the signal control terminal 2 via the signal control line 8, and the second electrode 13 of the discharge transistor is electrically connected to the low voltage power supply terminal 3 via the low voltage power supply line 9, the signal control line 8 and The low voltage power supply line 9 is formed on the base substrate of the array substrate.
  • the discharge circuit provided by the embodiment of the present disclosure is used on the array substrate, if charge accumulation occurs on the signal line 4 during the power-off of the display device, the signal control terminal 2 outputs a control signal to control the discharge transistor 1 to be turned on, and the signal line 4 is turned on. The charge on the discharge is discharged to the low-voltage power supply terminal 3 via the discharge transistor 1.
  • the present disclosure is connected to the signal control terminal 2 through the gate 11 of the discharge transistor, the first electrode 12 of the discharge transistor is electrically connected to the signal line 4, and the second electrode 13 of the discharge transistor is electrically connected to the low voltage power supply terminal 3, and the display device is powered off.
  • the signal control terminal 2 controls the first electrode 12 of the discharge transistor and the second electrode 13 of the discharge transistor to be turned on by the gate 11 of the discharge transistor, and the signal line 4 is turned on.
  • the charge is quickly released to the low-voltage power supply terminal 3, so as to prevent the charge on the signal line 4 from being completely and quickly released, resulting in a delay in the operation of the pixel unit, and a flashing, crosstalk, or electrostatic discharge damage occurs in the display device.
  • the operator, the machine or the detecting instrument may be electrostatically charged, which may cause static electricity to be generated in each process of fabricating the array substrate, and the generated on the array substrate.
  • Accumulation of static electricity onto the signal line 4 causes electrostatic discharge damage to the display device.
  • the control signal can also be output through the signal control terminal 2, so that the discharge transistor 1 is turned on, and the charge on the signal line 4 is released to the low-voltage power terminal. 3.
  • the discharge circuit provided by the embodiment of the present disclosure further includes a high voltage power supply terminal 7 and an electrostatic discharge protection module A.
  • the electrostatic discharge protection module A is electrically connected to the signal line 4, the low voltage power supply terminal 3 and the high voltage power supply terminal 7;
  • the ESD protection module A is configured to release the charge on the signal line 4 to the low voltage power terminal 3 when the voltage on the signal line 4 is lower than the voltage of the low voltage power terminal 3.
  • the ESD protection module A is electrically connected to the low-voltage power supply terminal 3 via the low-voltage power supply line 9, and the ESD protection module A is electrically connected to the high-voltage power supply terminal 7 via the high-voltage power supply line 10, and the high-voltage power supply line 10 is formed on the array substrate. On the base substrate.
  • a positive charge may be accumulated when charge accumulation occurs on the signal line 4, and a negative charge may also be accumulated.
  • the electrostatic discharge protection module A when the display device is not in the power-off process, if the amount of positive charge accumulated on the signal line 4 causes the voltage on the signal line 4 to be higher than the voltage of the high-voltage power terminal 7, the electrostatic discharge protection module A is passed. The positive charge accumulated on the signal line 4 is automatically released to the high voltage power supply terminal 7; if the amount of negative charge accumulated on the signal line 4 causes the voltage on the signal line 4 to be lower than the voltage of the low voltage power supply terminal 3, the electrostatic discharge protection module A is passed. The negative charge accumulated on the signal line 4 is automatically released to the low voltage power supply terminal 3, thereby preventing electrostatic discharge damage of the display device.
  • the signal control terminal 2 issues a control signal to control the discharge transistor 1 to be turned on, and the charge on the signal line 4 can be discharged not only to the low-voltage power supply terminal 3 via the discharge transistor 1, but also to the electrostatic discharge protection module A. Automatically released to the low voltage power terminal 3 or the high voltage power terminal 7.
  • the embodiment of the present disclosure is improved by the arrangement of the electrostatic discharge protection module A and the high voltage power supply terminal 7
  • the discharge efficiency of the supplied discharge circuit prevents the display device from being electrostatically discharged due to the accumulation of electric charge on the signal line 4.
  • the voltage of the high voltage power supply terminal 7 is a positive value
  • the voltage of the low voltage power supply terminal 3 is a negative value
  • the voltage of the high voltage power supply terminal 7 and the low voltage power supply terminal 3 can avoid the signal line 4
  • the accumulation of positive and negative charges accumulated on the display will not cause electrostatic discharge damage to the display device.
  • the ESD protection module A includes a first ESD protection transistor 5 and a second ESD protection transistor 6;
  • the gate 51 of the first electrostatic discharge protection transistor 5 and the first electrode 52 of the first electrostatic discharge protection transistor 5 are electrically connected to the low voltage power supply terminal 3, respectively, and the second electrode 53 of the first electrostatic discharge protection transistor 5 is electrically connected to the signal line 4. connection;
  • the gate electrode 61 of the second electrostatic discharge protection transistor 6 and the first electrode 62 of the second electrostatic discharge protection transistor 6 are electrically connected to the signal line 4, respectively, and the second electrode 63 of the second electrostatic discharge protection transistor 6 is electrically connected to the high voltage power supply terminal 7. connection.
  • the first electrostatic discharge protection transistor 5 is a P-type thin film transistor
  • the second electrostatic discharge protection transistor 6 is an N-type thin film transistor.
  • the gate 51 of the first ESD protection transistor and the first electrode 52 of the first ESD protection transistor are electrically connected to the low voltage power supply terminal 3 through the low voltage power supply line 9, respectively, and the second electrode 63 of the second ESD protection transistor is passed through the high voltage power supply.
  • the wire 10 is electrically connected to the high voltage power supply terminal 7.
  • the signal control terminal 2 controls the discharge transistor 1 to be turned on, and the positive charge on the signal line 4 is discharged to the low-voltage power supply terminal 3 through the discharge transistor 1, if the signal line 4 When the voltage on the voltage is higher than the voltage of the high voltage power supply terminal 7, the second electrostatic discharge protection transistor 6 is turned on, and the electric charge on the signal line 4 is discharged to the high voltage power supply terminal 7 via the second electrostatic discharge protection transistor 6; if the signal line 4 accumulates negative The charge, the signal control terminal 2 controls the discharge transistor 1 to be turned on, the charge on the signal line 4 is discharged to the low voltage power supply terminal 3 via the discharge transistor 1, and if the voltage on the signal line 4 is lower than the voltage of the low voltage power supply terminal 3, the first electrostatic discharge The guard transistor 5 is turned on, and the negative charge accumulated on the signal line 4 is discharged to the low-voltage power supply terminal 3 via the first electrostatic discharge protection transistor 5.
  • the display device is in a non-power-off process, charge accumulation occurs on the signal line 4. If a positive charge is accumulated on the signal line 4, when the voltage on the signal line 4 is higher than the voltage of the high-voltage power terminal 7, the second static electricity The discharge protection transistor 1 is turned on, and the charge on the signal line 4 passes through the second electrostatic discharge protection crystal The body tube 1 is released to the high voltage power supply terminal 7; if a negative charge is accumulated on the signal line 4, when the voltage on the signal line 4 is lower than the voltage of the low voltage power supply terminal 3, the first electrostatic discharge protection transistor 5 is turned on, on the signal line 4. The negative charge is discharged to the low voltage power supply terminal 3 via the first electrostatic discharge protection transistor 5.
  • the active layers of the discharge transistor 1, the first electrostatic discharge protection transistor 5, and the second electrostatic discharge protection transistor 6 are each made of amorphous silicon or polycrystalline silicon.
  • the polysilicon is low-temperature polysilicon, so that the discharge transistor 1, the first electrostatic discharge protection transistor 5, and the second electrostatic discharge protection transistor 6 are small in size, simple in structure, and high in stability.
  • the active layers of the discharge transistor 1, the first electrostatic discharge protection transistor 5 and the second electrostatic discharge protection transistor 6 can also be made of other semiconductor materials.
  • the discharge circuit further includes a signal control module B.
  • the input end of the signal control module B is electrically connected to the signal line 4, and the output end of the signal control module B is electrically connected to the signal control terminal 2. ;
  • the signal control module B is configured such that when the charge on the signal line 4 reaches a predetermined value, the control signal control terminal 2 issues a control signal.
  • the input end of the signal control module B is electrically connected to the signal line 4 through the charge detecting line B1
  • the output end of the signal control module B is electrically connected to the signal control terminal 2 through the signal output line B2.
  • the charge detecting line B1 and the signal output line B2 may be formed on the base substrate of the array substrate or may be disposed on the periphery of the array substrate.
  • the signal control module B includes a charge detection module and a pulse signal generator.
  • the charge detection module is electrically connected to the signal line 4, and the charge detection module detects whether the amount of charge on the signal line 4 is Reach the preset value;
  • the input end of the pulse signal generator is electrically connected to the charge detecting module, and the output end of the pulse signal generator is connected to the gate 11 of the discharge transistor;
  • the charge detecting module is configured to, when the charge on the signal line 4 exceeds a predetermined value, issue a pulse signal through the pulse signal generator to control the first electrode 12 of the discharge transistor and the second electrode 13 of the discharge transistor to be turned on.
  • the charge detecting module is electrically connected to the signal line 4 through the charge detecting line B1, and the output end of the pulse signal generator is electrically connected to the signal controlling terminal 2 through the signal output line B2.
  • the charge detecting module detects that the charge on the signal line 4 exceeds a preset value, the information is transmitted to the pulse signal generator, and the pulse signal generator sends a pulse signal to turn on the discharge transistor 1 to release the charge on the signal line 4.
  • the structure is simple, the electrostatic discharge efficiency is improved, and the electrostatic discharge damage of the display device is prevented.
  • the discharge transistor 1 is a thin film transistor, and the discharge transistor 1 may be an N-type thin film transistor or a P-type thin film transistor. If the discharge transistor 1 is an N-type thin film transistor, the discharge transistor 1 is turned on when the signal control terminal 2 emits a high level signal; and if the discharge transistor 1 is a P-type thin film transistor, the signal control terminal 2 emits a low level signal when the discharge transistor 1 conduction.
  • the discharge transistor 1 is an N-type thin film transistor.
  • An embodiment of the present disclosure provides an array substrate including the discharge circuit described in Embodiment 1.
  • the structure of the discharge circuit is as shown in FIG. 1 , and can also be seen in FIG. 2 to FIG. 4 .
  • the discharge circuit is formed on the base substrate of the array substrate and connected to the signal line 4 on the array substrate, wherein the signal line 4 on the array substrate includes the data line and the gate line.
  • the present disclosure is connected to the signal control terminal 2 through the gate 11 of the discharge transistor, the first electrode 12 of the discharge transistor is electrically connected to the signal line 4, and the second electrode 13 of the discharge transistor is electrically connected to the low voltage power supply terminal 3, and the display device is powered off.
  • the signal control terminal 2 controls the first electrode 12 of the discharge transistor and the second electrode 13 of the discharge transistor to be turned on by the gate 11 of the discharge transistor, and the charge on the signal line 4 is quickly released to the low-voltage power terminal 3, thereby avoiding The charge on the signal line 4 cannot be completely released quickly, resulting in a delay in the operation of the pixel unit, and a flashing, crosstalk, or electrostatic discharge damage occurs in the display device.
  • the ESD protection module A of the discharge circuit is disposed on the periphery of the array substrate to reduce the thickness of the array substrate, and conforms to the current trend of thin and light production of the liquid crystal display.
  • An embodiment of the present disclosure provides a liquid crystal display panel including the array substrate described in Embodiment 2.
  • the present disclosure forms a discharge circuit as shown in FIG. 1, FIG. 2, FIG. 3 or FIG. 4 on a base substrate of an array substrate, and the gate 11 of the discharge transistor of the discharge circuit is connected to the signal control terminal 2, and the discharge transistor is An electrode 12 is electrically connected to the signal line 4, and the second electrode 13 of the discharge transistor is electrically connected to the low-voltage power terminal 3, and the display device of the liquid crystal display panel provided by the present disclosure uses the discharge transistor during the power-off process.
  • the gate 11 controls the first electrode 12 of the discharge transistor and the second electrode 13 of the discharge transistor to be turned on, and the charge on the signal line 4 is quickly released to the low-voltage power supply terminal 3, so as to prevent the charge on the signal line 4 from being completely and quickly released. This causes the pixel unit to operate at a delay, and the display device is flickering, crosstalk, or electrostatic discharge damage.
  • An embodiment of the present disclosure provides a display device including the liquid crystal display panel described in Embodiment 3.
  • a discharge circuit is disposed on the array substrate in the liquid crystal display panel.
  • the structure of the discharge circuit is as shown in FIG. 1 to FIG. 4, and the gate 11 of the discharge transistor through the discharge circuit is connected to the signal control terminal 2, and the discharge transistor is The first electrode of 1 is electrically connected to the signal line 4, and the second electrode is electrically connected to the low-voltage power terminal 3, and during the power-off of the display device, the signal control terminal 2 controls the first electrode of the discharge transistor 1 through the gate 11 of the discharge transistor and The second electrode is turned on, and the electric charge on the signal line 4 is quickly released to the low-voltage power supply terminal 3, so as to prevent the charge on the signal line 4 from being completely released quickly, causing the pixel unit to work delay, the display device is flickering, the crosstalk is poor, or The condition of electrostatic discharge damage.

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Abstract

一种放电电路、阵列基板、液晶显示面板及显示装置。放电电路包括放电晶体管(1)、信号控制端(2)和低压电源端(3)。放电晶体管(1)的栅极(11)与信号控制端(2)连接，放电晶体管(1)的第一电极(12)与信号线(4)电连接，第二电极(13)与低压电源端(3)电连接。放电晶体管(1)，被配置为在信号控制端(2)输出的控制信号的作用下将信号线(4)上的电荷释放到低压电源端(3)。

Description

放电电路、阵列基板、液晶显示面板及显示装置 技术领域
本公开实施例涉及一种放电电路、阵列基板、液晶显示面板及显示装置。
背景技术
LCD(Liquid Crystal Display，液晶显示器)因具有轻、薄、功耗低、亮度高以及画质高等优点，在平板显示领域占据了重要的地位。LCD的液晶显示面板中的阵列基板包括像素单元和数据线，数据线与像素单元连接，通过数据线控制像素单元工作。在显示装置断电过程中，数据线上可能出现电荷积累，导致像素单元工作延时，LCD出现闪烁、串扰不良或静电放电损伤的情况，因此需通过放电电路对数据线上的电荷进行释放。
现有的放电电路包括放电薄膜晶体管和开关信号线，放电薄膜晶体管的栅极与开关信号线连接，其源极和漏极中的一者与数据线连接，另一者与阵列基板上的公共电极连接，通过开关信号线控制放电薄膜晶体管将数据线上的电荷释放到公共电极上。然而，由于公共电极通常设置在LCD的边框上，随着LCD窄边框设计的发展趋势，公共电极的宽度也越来越窄，可承受电荷的能力越来越弱，数据线上的电荷不能完全迅速释放到公共电极上，也容易导致像素单元工作延时，LCD出现闪烁、串扰不良或静电放电损伤的状况。
发明内容
第一方面，本公开实施例提供了一种放电电路，所述放电电路包括放电晶体管、信号控制端和低压电源端，所述放电晶体管的栅极与所述信号控制端连接，所述放电晶体管的第一电极与信号线电连接，第二电极与所述低压电源端电连接；
所述放电晶体管，被配置为在所述信号控制端输出的控制信号的作用下将所述信号线上的电荷释放到所述低压电源端。
第二方面，本公开实施例提供了一种阵列基板，所述阵列基板包括所述放电电路。
第三方面，本公开实施例提供了一种液晶显示面板，所述液晶显示面板包括所述阵列基板。
第四方面，本公开实施例提供了一种显示装置，所述显示装置包括所述液晶显示面板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开一实施例提供的放电电路的结构示意图；
图2是本公开又一实施例提供的放电电路的结构示意图；
图3是本公开又一实施例提供的静电放电防护模块的结构示意图；
图4是本公开又一实施例提供的放电电路的结构示意图。
附图标记：
1-放电晶体管，11-放电晶体管的栅极，12-放电晶体管的第一电极，13-放电晶体管的第二电极，2-信号控制端，3-低压电源端，4-信号线，5-第一静电放电防护晶体管，51-第一静电放电防护晶体管的栅极，52-第一静电放电防护晶体管的第一电极，53-第一静电放电防护晶体管的第二电极，6-第二静电放电防护晶体管，61-第二静电放电防护晶体管的栅极，62-第二静电放电防护晶体管的第一电极，63-第二静电放电防护晶体管的第二电极，7-高压电源端，8-信号控制线，9-低压电源线，10-高压电源线，A-静电放电防护模块,B-信号控制模块，B1-电荷检测线，B2-信号输出线。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。实施例一
如图1所示，本公开实施例提供了一种放电电路，该放电电路包括放电晶体管1、信号控制端2和低压电源端3，放电晶体管1的栅极11与信号控制端2连接，放电晶体管1的第一电极12与信号线4电连接，放电晶体管1的第二电极13与低压电源端3电连接；
放电晶体管1，被配置为在信号控制端2输出的控制信号的作用下将信号线4上的电荷释放到低压电源端3。
阵列基板包括衬底基板、像素单元以及形成在衬底基板上的数据线和栅线，在本公开实施例中，信号线4可以为数据线或栅线，其中，数据线的一端与控制像素单元工作的像素薄膜晶体管的源极连接，数据线的另一端与像素单元连接，像素薄膜晶体管通过数据线控制像素单元工作，阵列基板上的栅线的一端与栅极信号控制端连接，栅线的另一端与像素薄膜晶体管的栅极连接，栅极信号控制端经栅线控制像素薄膜晶体管工作。
在显示装置断电过程中，栅极信号控制端经栅线控制像素薄膜晶体管关闭，如果数据线上出现电荷积累，则像素单元不能立即停止工作，会导致显示装置出现闪烁、串扰不良或静电放电损伤等情况；如果栅线上出现电荷积累，栅极信号控制端发出的控制像素薄膜晶体管关闭的信号也不能迅速通过栅线传递到像素薄膜晶体管上，一样也会导致像素单元工作延时，显示装置出现闪烁、串扰不良或静电放电损伤等情况。
在本公开实施例中，放电晶体管的栅极11经信号控制线8与信号控制端2连接，放电晶体管的第二电极13经低压电源线9与低压电源端3电连接，信号控制线8和低压电源线9形成在阵列基板的衬底基板上。当在阵列基板上使用本公开实施例提供的放电电路时，如果显示装置断电过程中信号线4上出现了电荷积累，则信号控制端2输出控制信号，控制放电晶体管1打开，信号线4上的电荷经放电晶体管1释放到低压电源端3。
本公开通过放电晶体管的栅极11与信号控制端2连接，放电晶体管的第一电极12与信号线4电连接，放电晶体管的第二电极13与低压电源端3电连接，在显示装置断电过程中，信号控制端2通过放电晶体管的栅极11控制放电晶体管的第一电极12和放电晶体管的第二电极13导通，将信号线4上 的电荷快速释放到低压电源端3，避免因信号线4上的电荷不能完全迅速释放，导致像素单元工作延时，显示装置出现闪烁、串扰不良或静电放电损伤的状况发生。
当然，本领域技术人员可知，由于在制作阵列基板的过程中，操作人员、机台或检测仪器都可能带有静电，导致制作阵列基板的每一工序都有可能产生静电，阵列基板上产生的静电累积到信号线4上会导致显示装置发生静电放电损伤。在显示装置正常工作过程中，当信号线4上的电荷积累到一定程度时，也可通过信号控制端2输出控制信号，使放电晶体管1打开，将信号线4上的电荷释放到低压电源端3。
如图2所示，本公开实施例提供的放电电路还包括高压电源端7和静电放电防护模块A，静电放电防护模块A与信号线4、低压电源端3及高压电源端7电连接；
静电放电防护模块A，被配置为在信号线4上的电压低于低压电源端3的电压时，将信号线4上的电荷释放到低压电源端3；
在信号线4上的电压高于高压电源端7的电压时，将信号线4上的电荷释放到高压电源端7。
在本公开实施例中，静电防护模块A经低压电源线9与低压电源端3电连接，静电放电防护模块A经高压电源线10与高压电源端7电连接，高压电源线10形成在阵列基板的衬底基板上。
可以理解的是，信号线4上出现电荷积累时可能积累正电荷，也可能积累负电荷。在本公开实施例中，当显示装置非处于断电过程时，如果信号线4上积累正电荷的量使信号线4上的电压高于高压电源端7的电压，则通过静电放电防护模块A将信号线4上积累的正电荷自动释放到高压电源端7；如果信号线4上积累负电荷的量使信号线4上的电压低于低压电源端3的电压，则通过静电放电防护模块A将信号线4上积累的负电荷自动释放到低压电源端3，从而防止显示装置发生静电放电损伤。
而当显示装置处于断电过程时，信号控制端2发出控制信号控制放电晶体管1打开，信号线4上的电荷不仅可以经放电晶体管1释放到低压电源端3，还可通过静电放电防护模块A自动释放到低压电源端3或高压电源端7。
通过静电放电防护模块A及高压电源端7的设置，提高本公开实施例提 供的放电电路的放电效率，且防止显示装置因信号线4上积累电荷而发生静电放电损伤。
在本公开实施例中，可以理解的是，高压电源端7的电压为正值，低压电源端3的电压为负值，高压电源端7和低压电源端3的电压大小以能避免信号线4上积累的正电荷和负电荷的释放不会对显示装置造成静电放电损伤为准。
如图3所示(也可参见图2)，在本公开实施例中，静电放电防护模块A包括第一静电放电防护晶体管5和第二静电放电防护晶体管6；
第一静电放电防护晶体管5的栅极51和第一静电放电防护晶体管5的第一电极52分别与低压电源端3电连接，第一静电放电防护晶体管5的第二电极53与信号线4电连接；
第二静电放电防护晶体管6的栅极61和第二静电放电防护晶体管6的第一电极62分别与信号线4电连接，第二静电放电防护晶体管6的第二电极63与高压电源端7电连接。
在本公开实施例中，第一静电放电防护晶体管5为P型薄膜晶体管，第二静电放电防护晶体管6为N型薄膜晶体管。第一静电放电防护晶体管的栅极51和第一静电放电防护晶体管的第一电极52分别通过低压电源线9与低压电源端3电连接，第二静电放电防护晶体管的第二电极63通过高压电源线10与高压电源端7电连接。
在显示装置断电过程中，如果信号线4上积累正电荷，则信号控制端2控制放电晶体管1打开，信号线4上的正电荷通过放电晶体管1释放到低压电源端3，若信号线4上的电压高于高压电源端7的电压，则第二静电放电防护晶体管6打开，信号线4上的电荷经第二静电放电防护晶体管6释放到高压电源端7；如果信号线4上积累负电荷，信号控制端2控制放电晶体管1打开，信号线4上的电荷经放电晶体管1释放到低压电源端3，若信号线4上的电压低于低压电源端3的电压，则第一静电放电防护晶体管5打开，信号线4上积累的负电荷经第一静电放电防护晶体管5释放到低压电源端3。
同理，若显示装置处于非断电过程时信号线4上出现电荷积累，如果信号线4上积累正电荷，则当信号线4上的电压高于高压电源端7的电压时，第二静电放电防护晶体管1打开，信号线4上的电荷经第二静电放电防护晶 体管1释放到高压电源端7；如果信号线4上积累负电荷，则当信号线4上的电压低于低压电源端3的电压时，第一静电放电防护晶体管5打开，信号线4上的负电荷经第一静电放电防护晶体管5释放到低压电源端3。
在本公开实施例中，放电晶体管1、第一静电放电防护晶体管5和第二静电放电防护晶体管6的有源层均由非晶硅或多晶硅制成。例如，多晶硅为低温多晶硅，使得放电晶体管1、第一静电放电防护晶体管5和第二静电放电防护晶体管6体积较小，且结构简单，稳定性高。当然，本领域技术人员可知，放电晶体管1、第一静电放电防护晶体管5和第二静电放电防护晶体管6的有源层还可由其他半导体材料制成。
如图4所示，在本公开实施例中，放电电路还包括信号控制模块B，信号控制模块B的输入端与信号线4电连接，信号控制模块B的输出端与信号控制端2电连接；
信号控制模块B被配置为在信号线4上的电荷达到预设数值时，控制信号控制端2发出控制信号。
在本公开实施例中，信号控制模块B的输入端通过电荷检测线B1与信号线4电连接，信号控制模块B的输出端通过信号输出线B2与信号控制端2电连接。例如，电荷检测线B1和信号输出线B2可以形成在阵列基板的衬底基板上，也可以设置在阵列基板的外围。
通过信号控制模块B在信号线4上的电荷达到预设数值时发出控制信号，使放电晶体管1打开，将信号线4上的电荷释放到低压电源端3，在显示装置处于非断电过程时，通过放电晶体管1将信号线4上的电荷释放到低压电源端3，提高静电放电效率，防止显示装置发生静电放电损伤。
如图3所示，在本公开实施例中，信号控制模块B包括电荷检测模块和脉冲信号发生器，电荷检测模块与信号线4电连接，通过电荷检测模块检测信号线4上的电荷量是否达到预设数值；
脉冲信号发生器的输入端与电荷检测模块电连接，脉冲信号发生器的输出端与放电晶体管的栅极11连接；
电荷检测模块被配置为在信号线4上的电荷超过预设数值时，通过脉冲信号发生器发出脉冲信号，控制放电晶体管的第一电极12和放电晶体管的第二电极13导通。
在本公开实施例中，电荷检测模块通过电荷检测线B1与信号线4电连接，脉冲信号发生器的输出端通过信号输出线B2与信号控制端2电连接。当电荷检测模块检测到信号线4上的电荷超过预设数值时，将该信息传递给脉冲信号发生器，脉冲信号发生器发出脉冲信号，使放电晶体管1打开，将信号线4上的电荷释放到低压电源端3，结构简单，提高静电放电效率，防止显示装置发生静电放电损伤。
在本公开实施例中，放电晶体管1为薄膜晶体管，其中，放电晶体管1可以为N型薄膜晶体管或P型薄膜晶体管。若放电晶体管1为N型薄膜晶体管，则信号控制端2发出高电平信号时放电晶体管1导通；若放电晶体管1为P型薄膜晶体管，则信号控制端2发出低电平信号时放电晶体管1导通。例如，放电晶体管1为N型薄膜晶体管。
实施例二
本公开实施例提供了一种阵列基板，该阵列基板包括实施例一中所述的放电电路，该放电电路的结构图如图1所示，也可参见图2-图4，在本公开实施例中，放电电路形成在阵列基板的衬底基板上，与阵列基板上的信号线4连接，其中，阵列基板上的信号线4包括数据线和栅线。
本公开通过放电晶体管的栅极11与信号控制端2连接，放电晶体管的第一电极12与信号线4电连接，放电晶体管的第二电极13与低压电源端3电连接，在显示装置断电过程中，信号控制端2通过放电晶体管的栅极11控制放电晶体管的第一电极12和放电晶体管的第二电极13导通，将信号线4上的电荷快速释放到低压电源端3，避免因信号线4上的电荷不能完全迅速释放，导致像素单元工作延时，显示装置出现闪烁、串扰不良或静电放电损伤的状况发生。
在本公开实施例中，放电电路的静电放电防护模块A设置在阵列基板的外围，减小阵列基板的厚度，顺应当前液晶显示器轻薄化生产的趋势。
实施例三
本公开实施例提供了一种液晶显示面板，该液晶显示面板包括实施例二中所述的阵列基板。
本公开通过在阵列基板的衬底基板上形成如图1、图2、图3或图4所示的放电电路，放电电路的放电晶体管的栅极11与信号控制端2连接，放电晶体管的第一电极12与信号线4电连接，放电晶体管的第二电极13与低压电源端3电连接，使用本公开提供的液晶显示面板的显示装置在断电过程中，信号控制端2通过放电晶体管的栅极11控制放电晶体管的第一电极12和放电晶体管的第二电极13导通，将信号线4上的电荷快速释放到低压电源端3，避免因信号线4上的电荷不能完全迅速释放，导致像素单元工作延时，显示装置出现闪烁、串扰不良或静电放电损伤的状况发生。
实施例四
本公开实施例提供了一种显示装置，该显示装置包括实施例三中所述的液晶显示面板。
本公开实施例通过在液晶显示面板中的阵列基板上设置放电电路，放电电路的结构如图1-图4所示，通过放电电路的放电晶体管的栅极11与信号控制端2连接，放电晶体管1的第一电极与信号线4电连接，第二电极与低压电源端3电连接，显示装置断电过程中，信号控制端2通过放电晶体管的栅极11控制放电晶体管1的第一电极和第二电极导通，将信号线4上的电荷快速释放到低压电源端3，避免出现信号线4上的电荷因不能完全迅速释放，导致像素单元工作延时，显示装置出现闪烁、串扰不良或静电放电损伤的状况。
在本文中，诸如“第一”和“第二”等关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年1月29日递交的中国专利申请第201610065459.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种放电电路，包括放电晶体管、信号控制端和低压电源端，其中：
    所述放电晶体管的栅极与所述信号控制端连接，所述放电晶体管的第一电极与信号线电连接，第二电极与所述低压电源端电连接；
    所述放电晶体管，被配置为在所述信号控制端输出的控制信号的作用下将所述信号线上的电荷释放到所述低压电源端。
  2. 根据权利要求1所述的放电电路，还包括高压电源端和静电放电防护模块，其中：
    所述静电放电防护模块与所述信号线、所述低压电源端及所述高压电源端电连接；
    所述静电放电防护模块，被配置为：
    在所述信号线上的电压低于所述低压电源端的电压时，将所述信号线上的电荷释放到所述低压电源端；
    在所述信号线上的电压高于所述高压电源端的电压时，将所述信号线上的电荷释放到所述高压电源端。
  3. 根据权利要求2所述的放电电路，其中，所述静电放电防护模块包括第一静电放电防护晶体管和第二静电放电防护晶体管；
    所述第一静电放电防护晶体管的栅极和第一电极分别与所述低压电源端电连接，所述第一静电放电防护晶体管的第二电极与所述信号线电连接；
    所述第二静电放电防护晶体管的栅极和第一电极分别与所述信号线电连接，所述第二静电放电防护晶体管的第二电极与所述高压电源端电连接。
  4. 根据权利要求3所述的放电电路，其中，所述放电晶体管、所述第一静电放电防护晶体管和所述第二静电放电防护晶体管的有源层均由非晶硅或多晶硅制成。
  5. 根据权利要求4所述的放电电路，其中，所述多晶硅为低温多晶硅。
  6. 根据权利要求1所述的放电电路，还包括信号控制模块，其中：
    所述信号控制模块的输入端与所述信号线电连接，所述信号控制模块的输出端与所述信号控制端电连接；
    所述信号控制模块被配置为在所述信号线上的电荷达到预设数值时，控制所述信号控制端发出控制信号。
  7. 根据权利要求6所述的放电电路，其中，所述信号控制模块包括电荷检测模块和脉冲信号发生器，所述电荷检测模块与所述信号线电连接，所述电荷检测模块检测所述信号线上的电荷量是否达到预设数值；
    所述脉冲信号发生器的输入端与所述电荷检测模块电连接，所述脉冲信号发生器的输出端与所述放电晶体管的栅极连接；
    所述电荷检测模块被配置为在所述信号线上的电荷超过所述预设数值时，通过所述脉冲信号发生器发出脉冲信号，控制所述放电晶体管的第一电极和第二电极导通。
  8. 根据权利要求1所述的放电电路，其中，所述信号线为栅线或数据线。
  9. 根据权利要求1所述的放电电路，其中，所述放电晶体管为薄膜晶体管。
  10. 根据权利要求9所述的放电电路，其中，所述放电晶体管为N型薄膜晶体管或P型薄膜晶体管。
  11. 一种阵列基板，包括权利要求1-10任一项所述的放电电路。
  12. 根据权利要求11所述的一种阵列基板，其中，所述放电电路的静电放电防护模块设置在所述阵列基板的外围。
  13. 一种液晶显示面板，包括权利要求11或12所述的阵列基板。
  14. 一种显示装置，包括权利要求13所述的液晶显示面板。
PCT/CN2016/102957 2016-01-29 2016-10-21 放电电路、阵列基板、液晶显示面板及显示装置 WO2017128780A1 (zh)

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