WO2017128554A1 - Tft阵列基板及其制造方法 - Google Patents

Tft阵列基板及其制造方法 Download PDF

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WO2017128554A1
WO2017128554A1 PCT/CN2016/081782 CN2016081782W WO2017128554A1 WO 2017128554 A1 WO2017128554 A1 WO 2017128554A1 CN 2016081782 W CN2016081782 W CN 2016081782W WO 2017128554 A1 WO2017128554 A1 WO 2017128554A1
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layer
insulating layer
electrode
semiconductor layer
interlayer insulating
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李金明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
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Definitions

  • the invention belongs to the field of wafer fabrication and flat panel display technology. In particular, it relates to a TFT array substrate and a method of fabricating the same.
  • a semiconductor layer in a thin film transistor is composed of a metal oxide film, and a metal oxide film is very sensitive to an acid, and even a weak acid can quickly etch the oxide semiconductor layer to etch on the oxide semiconductor layer.
  • the oxide semiconductor layer itself is easily destroyed when the metal source electrode and the drain electrode are used.
  • the oxide semiconductor layer is thin (generally between 30 nm and 50 nm), even in hydrofluoric acid (HF) diluted at a concentration of 500:1, the oxide semiconductor layer can be etched in only a few seconds. However, most metals need to be etched under strong acid and at a slower rate. Therefore, how to etch the metal source electrode and the drain electrode on the oxide semiconductor layer becomes an urgent problem to be solved.
  • HF hydrofluoric acid
  • the present invention provides a TFT array substrate capable of avoiding etching of a metal oxide by a metal etching solution and reducing the mask process, and a method of manufacturing the same.
  • a TFT array substrate including: a substrate; a semiconductor layer formed on the substrate; a pixel electrode formed on the substrate to be on the same layer as the semiconductor layer; and a gate insulating layer a layer formed on the semiconductor layer; a gate electrode formed on the gate insulating layer; an interlayer insulating layer formed on the substrate to cover the gate insulating layer, the gate electrode and the pixel electrode; and a source electrode disposed on the interlayer insulating layer And electrically connected to the semiconductor layer; the drain electrode is disposed on the interlayer insulating layer and electrically connects the semiconductor layer and the pixel electrode.
  • the interlayer insulating layer may include a silicon nitride layer, or a composite layer including a silicon oxide layer and a silicon nitride layer formed in order from bottom to top.
  • the TFT array substrate may further include: a passivation layer, a shape The insulating layer is formed on the interlayer insulating layer to cover the source electrode and the drain electrode; and the common electrode is formed on the passivation layer.
  • a method of fabricating a TFT array substrate comprising: forming a semiconductor layer on a substrate; forming a gate insulating layer on the semiconductor layer, the gate insulating layer covering a portion of the semiconductor layer; Forming a gate electrode on the gate insulating layer; forming an interlayer insulating layer on the semiconductor layer to cover the gate insulating layer and the gate electrode, wherein the interlayer insulating layer comprises a silicon nitride layer; and performing an annealing process on the interlayer insulating layer Dispersing hydrogen in the interlayer insulating layer into the semiconductor layer to form a pixel electrode at a portion of the semiconductor layer not covered by the gate insulating layer; forming a semiconductor layer on the interlayer insulating layer and the gate insulating layer a contact hole, and an opening for exposing the pixel electrode is formed on the interlayer insulating layer; a source electrode and a drain electrode are formed on the interlayer insulating layer, wherein
  • the forming of the semiconductor layer may include depositing a metal oxide on the substrate, activating the metal oxide by an annealing process, and then performing a yellow light process and an etching process to form a semiconductor having a predetermined pattern Floor.
  • the step of forming a gate insulating layer may include depositing an insulating layer on the semiconductor layer, and then performing a yellow light process and an etching process to form a gate insulating layer having a predetermined pattern, wherein the insulating layer
  • the layer includes a single layer of a silicon nitride layer or a composite layer including a silicon oxide layer and a silicon nitride layer deposited in this order from bottom to top.
  • the forming of the gate electrode may include depositing a metal layer on the gate insulating layer, and performing a yellow light process and an etching process on the metal layer to form a gate electrode having a predetermined pattern.
  • the interlayer insulating layer may further include a silicon oxide layer in which a silicon nitride layer and a silicon oxide layer are sequentially deposited in order from bottom to top.
  • the method may further include: forming a passivation layer on the interlayer insulating layer to cover the source electrode and the drain electrode; and forming a common electrode on the passivation layer.
  • the forming of the common electrode may include depositing an electrode layer on the passivation layer, followed by performing a yellow light process and an etching process to obtain a common electrode having a predetermined pattern.
  • the TFT array substrate of the present invention and the method of manufacturing the same, etching of the metal oxide by the metal etching solution can be avoided.
  • the array substrate of the TFT including the top gate structure of the present invention saves two photomask processes compared to the conventional top gate structure TFT, thereby reducing the production cost.
  • 1 to 8 are schematic flow charts showing the manufacture of a TFT array substrate according to an exemplary embodiment of the present invention.
  • 1 to 8 are schematic flow charts showing the manufacture of a TFT array substrate according to an exemplary embodiment of the present invention.
  • a semiconductor layer 110 is formed on the substrate 100.
  • the substrate 100 may be formed of a transparent glass material containing SiO 2 as a main component, but is not limited thereto.
  • the semiconductor layer 110 is formed by a physical vapor deposition (PVD) method. Specifically, a metal oxide is deposited on the substrate 100 using PVD, and then the metal oxide is annealed (for example, at 200 ° C to 400 ° C) to activate the metal oxide, followed by a yellow light process and etching. The process is to form a semiconductor layer 110 having a predetermined pattern.
  • PVD physical vapor deposition
  • the metal oxide forming the semiconductor layer 110 may be indium gallium zinc oxide (IGZO), however, the present invention is not limited thereto, and any suitable metal oxide may be selected.
  • the semiconductor layer 110 may have a thickness of 300 angstroms to 1000 angstroms; however, the invention is not limited thereto.
  • a gate insulating layer 120 is formed on the semiconductor layer 110, the gate insulating layer 120 covers a portion of the semiconductor layer 110, and a portion of the semiconductor layer 110 covered by the gate insulating layer 120 may be a gate electrode.
  • a portion of the semiconductor layer 110 that is not covered by the gate insulating layer 120 may provide a position for forming a pixel electrode.
  • an insulating layer is deposited on a portion of the semiconductor layer 110 by plasma enhanced chemical vapor deposition, and then a yellow light process and an etching process are performed to obtain a gate insulating layer 120 having a predetermined pattern.
  • the insulating layer may be formed as a single layer or as a plurality of layers including an inorganic insulating layer of a silicon nitride (SiN x ) layer including, for example, a silicon oxide (SiO x ) layer, silicon nitride (SiN) x) layer, an inorganic insulating layer and the like.
  • the plurality of layers may be a composite layer of a silicon oxide (SiO x ) layer and a silicon nitride (SiN x ) layer deposited in order from bottom to top.
  • a gate electrode 130 is formed on the gate insulating layer 120.
  • a metal layer such as Mo may be deposited on the gate insulating layer 120 by a PVD method, and then a yellow light process and an etching process are performed to obtain a gate electrode 130 having a predetermined pattern.
  • the material of the metal layer is not limited to Mo.
  • the material of the metal layer may further include materials such as Al, Cu, or the like.
  • the thickness of the gate electrode 130 may be 1500 angstroms to 6500 angstroms, however, the invention is not limited thereto.
  • an interlayer insulating layer 140 is formed on the semiconductor layer 110 to cover the gate electrode 130 and the gate insulating layer 120, and a portion of the semiconductor layer 110 not covered by the gate insulating layer 120 is formed as The pixel electrode 150.
  • a metal layer is deposited on the semiconductor layer 110 by plasma enhanced chemical vapor deposition, and the metal layer may be formed as a single layer including silicon oxide or as a silicon nitride layer and silicon oxide deposited in order from bottom to top.
  • a composite layer of layers then, an annealing process is performed on the metal layer to diffuse hydrogen in the silicon nitride to the semiconductor layer 110 to effect hydrogen doping of the semiconductor layer 110, thereby preventing the gate insulating layer of the semiconductor layer 110 a pixel electrode 150 is formed at a portion covered by 120; then, a yellow light process and an etching process are performed to simultaneously form a contact hole H1 for electrically connecting the source electrode to the semiconductor layer 110 and for electrically connecting the drain electrode to the semiconductor layer 110 and a contact hole H2 and an opening H3 on the pixel electrode 150.
  • the TFT in the TFT array substrate according to the present invention can effectively avoid etching of the metal oxide by the metal etching solution by using the top gate structure.
  • the source electrode S and the drain electrode D are formed on the interlayer insulating layer 140. Specifically, an Al/Mo material is first deposited on the interlayer insulating layer 140, followed by a yellow light process and an etching process to obtain a source electrode S/drain electrode D having a predetermined pattern.
  • the material forming the source electrode S/drain electrode D is not limited thereto, and for example, any other suitable material may be used.
  • the source electrode S and the drain electrode D may have a thickness of 200 angstroms to 6000 angstroms, however, the invention is not limited thereto.
  • a passivation layer 160 is formed on the interlayer insulating layer 140 to cover the source electrode S and the drain electrode D.
  • the passivation layer 160 is deposited by plasma-increasing chemical vapor deposition to protect the source electrode S and the drain electrode D.
  • the passivation layer 160 may be formed as a single layer structure including a silicon oxide layer or as a composite layer structure including a silicon oxide layer and a silicon nitride layer.
  • the passivation layer 160 may have a thickness of 1500 angstroms to 4000 angstroms, however, the invention is not limited thereto.
  • a common electrode 170 is formed on the passivation layer 160.
  • the electrode layer is deposited by a PVD method, followed by performing a yellow light process and an etching process to obtain a common electrode 170 having a predetermined pattern.
  • the common electrode 170 can be an ITO layer or can be a layer formed from other suitable transparent conductors.
  • the passivation layer 170 may have a thickness of 300 angstroms to 1000 angstroms, however, the invention is not limited thereto.
  • the mask process performed for forming the contact hole in the passivation layer and the mask process for forming the pixel electrode can be reduced, thereby Reduced production costs and simplified processes.
  • the present invention employs a top gate structure, etching of the metal oxide by the metal etching solution can be avoided.
  • TFT array substrate and the method of fabricating the same according to an exemplary embodiment of the present invention have been described above, but the scope of protection of the present invention is not limited to the specific embodiment described above.

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Abstract

一种TFT阵列基板，包括：基底(100)；半导体层(110)，形成在基底(100)上；像素电极(150)，形成在基底(100)上以与半导体层(110)位于同一层上；栅极绝缘层(120)，形成在半导体层(110)上；栅电极(130)，形成在栅极绝缘层(120)上；层间绝缘层(140)，形成在基底(100)上以覆盖栅极绝缘层(120)、栅电极(130)和像素电极(150)；源电极(S)，设置在层间绝缘层(140)上并电连接到半导体层(110)；漏电极(D)，设置在层间绝缘层(140)上并电连接半导体层(110)和像素电极(150)。还提供了一种TFT阵列基板的制造方法，包括顶栅结构的TFT的阵列基板比传统的顶栅结构的TFT阵列基板节省两道光罩工艺，从而降低了生产成本。

Description

TFT阵列基板及其制造方法 技术领域
本发明属于晶圆制造和平板显示技术领域。具体地讲，涉及一种TFT阵列基板以及制造方法。
背景技术
通常，薄膜晶体管(TFT)中的半导体层由金属氧化物薄膜构成，而金属氧化物薄膜对酸非常敏感，即便是弱酸也能够快速地腐蚀氧化物半导体层，从而在氧化物半导体层上刻蚀金属源电极和漏电极时很容易破坏氧化物半导体层本身。
此外，由于氧化物半导体层较薄(通常在30nm至50nm之间)，即使采用浓度在500:1稀释的氢氟酸(HF)中，只需几秒钟就能够刻蚀氧化物半导体层。然而，大多数金属需要在强酸下刻蚀，并且速率较慢。因此如何在氧化物半导体层上刻蚀金属源电极和漏电极成为急需解决的难题。
发明内容
为了解决上述现有技术的不足，本发明提供一种既能够避免金属刻蚀液对金属氧化物的刻蚀又能够减少光罩工艺的TFT阵列基板及其制造方法。
根据本发明的一方面，提供一种TFT阵列基板，所述TFT阵列基板包括：基底；半导体层，形成在基底上；像素电极，形成在基底上以与半导体层位于同一层上；栅极绝缘层，形成在半导体层上；栅电极，形成在栅极绝缘层上；层间绝缘层，形成在基底上以覆盖栅极绝缘层、栅电极和像素电极；源电极，设置在层间绝缘层上并电连接到半导体层；漏电极，设置在层间绝缘层上并电连接半导体层和像素电极。
根据本发明的示例性实施例，层间绝缘层可以包括氮化硅层，或者包括以从下到上依次形成的氧化硅层和氮化硅层的复合层。
根据本发明的示例性实施例，所述TFT阵列基板还可以包括：钝化层，形 成在层间绝缘层上以覆盖源电极和漏电极；共电极，形成在钝化层上。
根据本发明的另一方面，提供一种制造TFT阵列基板的方法，所述方法包括：在基底上形成半导体层；在半导体层上形成栅极绝缘层，栅极绝缘层覆盖半导体层的一部分；在栅极绝缘层上形成栅电极；在半导体层上形成层间绝缘层以覆盖栅极绝缘层和栅电极，其中，层间绝缘层包括氮化硅层；对层间绝缘层执行退火工艺以使层间绝缘层中的氢扩散到半导体层中，以在半导体层的未被栅极绝缘层覆盖的部分处形成像素电极；在层间绝缘层和栅极绝缘层上形成用于暴露半导体层的接触孔，并且在层间绝缘层上形成用于暴露像素电极的开口；在层间绝缘层上形成源电极和漏电极，其中，源电极经接触孔电连接到半导体层，漏电极经接触孔和开口电连接半导体层和像素电极。
根据本发明的示例性实施例，形成半导体层的步骤可以包括：在基底上沉积金属氧化物，利用退火工艺对金属氧化物活化，之后执行黄光工艺和刻蚀工艺来形成具有预定图案的半导体层。
根据本发明的示例性实施例，形成栅极绝缘层的步骤可以包括：在半导体层上沉积绝缘层，之后执行黄光工艺和刻蚀工艺来形成具有预定图案的栅极绝缘层，其中，绝缘层包括氮化硅层的单层或者包括以从下到上依次沉积的氧化硅层和氮化硅层的复合层。
根据本发明的示例性实施例，形成栅电极的步骤可以包括：在栅极绝缘层上沉积金属层，并对金属层执行黄光工艺和刻蚀工艺以形成具有预定图案的栅电极。
根据本发明的示例性实施例，层间绝缘层还可以包括氧化硅层，其中，以从下到上的顺序依次沉积氮化硅层和氧化硅层。
根据本发明的示例性实施例，所述方法还可以包括：在层间绝缘层上形成钝化层以覆盖源电极和漏电极；在钝化层上形成共电极。
根据本发明的示例性实施例，形成共电极的步骤可以包括：在钝化层上沉积电极层，之后执行黄光工艺和刻蚀工艺来得到具有预定图案的共电极。
根据本发明的TFT阵列基板及其制造方法，能够避免金属刻蚀液对金属氧化物的刻蚀。此外，本发明的包括顶栅结构的TFT的阵列基板比传统的顶栅结构的TFT节省两道光罩工艺，从而降低了生产成本。
附图说明
图1至图8示出了根据本发明的示例性实施例的制造TFT阵列基板的流程示意图。
具体实施方式
下面将参照附图详细地描述本发明的示例性实施例。
以下将结合附图来详细描述本发明的示例性实施例，然而，附图只是示意性地示出了本发明的具体示例，且不具有限制作用。然而，本领域技术人员应理解的是，在不脱离本发明的权利要求所限定的保护范围的情况下，可以对其进行各种修改和变形。
在下文中，将通过参照附图解释本发明的示例性实施例来详细描述本发明。
图1至图8示出了根据本发明的示例性实施例的制造TFT阵列基板的流程示意图。
如图1中所示，在基底100上形成半导体层110。基底100可以由含有SiO2作为主要成分的透明玻璃材料形成，但是不限于此。
通常，通过物理气相沉积(PVD)法形成半导体层110。具体地讲，采用PVD在基底100上沉积金属氧化物，之后对金属氧化物进行退火(例如，在200℃～400℃下)处理以对金属氧化物进行活化，接着执行黄光工艺和刻蚀工艺来形成具有预定图案的半导体层110。
形成半导体层110的金属氧化物可以是氧化铟镓锌(IGZO)，然而，本发明不限于此，可以选用任何适合的金属氧化物。在本发明的一个示例性实施例中，半导体层110的厚度可以为300埃至1000埃；然而，本发明不限于此。
接着，如图2中所示，在半导体层110上形成栅极绝缘层120，栅极绝缘层120覆盖半导体层110的一部分，半导体层110的被栅极绝缘层120覆盖的部分可以为栅电极提供支撑，半导体层110的未被栅极绝缘层120覆盖的部分可以为形成像素电极提供位置。具体地讲，通过等离子增强化学气相沉积法在半导体层110的一部分上沉积绝缘层，之后执行黄光工艺和刻蚀工艺来得到具有预定图案的栅极绝缘层120。
绝缘层可以形成为单层或形成为多层，所述单层包括氮化硅(SiNx)层的无 机绝缘层，所述多层包括诸如氧化硅(SiOx)层、氮化硅(SiNx)层等的无机绝缘层。当绝缘层形成为多层时，多层可以是按从下到上的顺序沉积的氧化硅(SiOx)层和氮化硅(SiNx)层的复合层。
然后，参照图3中所示，在栅极绝缘层120上形成栅电极130。具体地讲，可以通过PVD法在栅极绝缘层120上沉积诸如Mo的金属层，之后执行黄光工艺和刻蚀工艺来得到具有预定图案的栅电极130。在本发明的非限制性实施例中，金属层的材质不限于Mo，例如金属层的材质还可以包括Al、Cu等材料或其组合。栅电极130的厚度可以为1500埃至6500埃，然而，本发明不限于此。
接着，参照图4和图5，在半导体层110上形成层间绝缘层140以覆盖栅电极130和栅极绝缘层120，并且使半导体层110的未被栅极绝缘层120覆盖的部分形成为像素电极150。具体地讲，通过等离子增强化学气相沉积法在半导体层110上沉积金属层，金属层可以形成为包括氧化硅的单层或者形成为以从下到上的顺序沉积的氮化硅层和氧化硅层的复合层；然后，对金属层执行退火工艺，使氮化硅中的氢扩散到半导体层110，以实现对半导体层110的氢掺杂，从而在半导体层110的未被栅极绝缘层120覆盖的部分处形成像素电极150；接着，执行黄光工艺和刻蚀工艺来同时形成用于将源电极电连接到半导体层110上的接触孔H1以及用于将漏电极电连接到半导体层110和像素电极150上的接触孔H2和开口H3。
根据本发明的TFT阵列基板中的TFT采用顶栅结构能够有效地避免金属刻蚀液对金属氧化物的刻蚀。
然后，参照图6，在层间绝缘层140上形成源电极S和漏电极D。具体地讲，首先在层间绝缘层140上沉积Al/Mo材料，接着执行黄光工艺和刻蚀工艺来得到具有预定图案的源电极S/漏电极D。在本发明中，形成源电极S/漏电极D的材料不限于此，例如可以使用任何其它适合的材料。在本发明的一个实施例中，源电极S和漏电极D的厚度可以为200埃至6000埃，然而，本发明不限于此。
接着，参照图7，在层间绝缘层140上形成钝化层160以覆盖源电极S和漏电极D。具体地讲，通过等离子增加化学气相沉积法沉积钝化层160，以保护源电极S和漏电极D。在本发明的示例性实施例中，钝化层160可以形成为包括氧化硅层的单层结构或者形成为包括氧化硅层和氮化硅层的复合层结构。在本发明的一个实施例中，钝化层160的厚度可以为1500埃至4000埃，然而，本发明不限于此。
然后，参照图8，在钝化层160上形成共电极170。具体地讲，通过PVD法沉积电极层，接着执行黄光工艺和刻蚀工艺来得到具有预定图案的共电极170。在本发明的非限制性实施例中，共电极170可以是ITO层或者可以是由其它适合的透明导体形成的层。在本发明的一个实施例中，钝化层170的厚度可以为300埃至1000埃，然而，本发明不限于此。
根据本发明的TFT阵列基板，由于半导体层和像素电极形成在同一层中，因此能够减少为了在钝化层中形成接触孔而执行的光罩工艺以及用于形成像素电极的光罩工艺，从而降低了生产成本，简化了工艺。
此外，由于本发明采用顶栅结构，因此能够避免金属刻蚀液对金属氧化物的刻蚀。
以上描述了根据本发明的示例性实施例的TFT阵列基板及其制造方法，但本发明的保护范围并不限制于上述特定实施例。

Claims (10)

  1. 一种TFT阵列基板，其中，所述TFT阵列基板包括：
    基底；
    半导体层，形成在基底上；
    像素电极，形成在基底上以与半导体层位于同一层上；
    栅极绝缘层，形成在半导体层上；
    栅电极，形成在栅极绝缘层上；
    层间绝缘层，形成在基底上以覆盖栅极绝缘层、栅电极和像素电极；
    源电极，设置在层间绝缘层上并电连接到半导体层；
    漏电极，设置在层间绝缘层上并电连接半导体层和像素电极。
  2. 根据权利要求1所述的TFT阵列基板，其中，层间绝缘层包括氮化硅层，或者包括以从下到上依次形成的氧化硅层和氮化硅层的复合层。
  3. 根据权利要求1所述的TFT阵列基板，其中，所述TFT阵列基板还包括：
    钝化层，形成在层间绝缘层上以覆盖源电极和漏电极；
    共电极，形成在钝化层上。
  4. 一种制造TFT阵列基板的方法，其中，所述方法包括：
    在基底上形成半导体层；
    在半导体层上形成栅极绝缘层，栅极绝缘层覆盖半导体层的一部分；
    在栅极绝缘层上形成栅电极；
    在半导体层上形成层间绝缘层以覆盖栅极绝缘层和栅电极，其中，层间绝缘层包括氮化硅层；
    对层间绝缘层执行退火工艺以使层间绝缘层中的氢扩散到半导体层中，以在半导体层的未被栅极绝缘层覆盖的部分处形成像素电极；
    在层间绝缘层和栅极绝缘层上形成用于暴露半导体层的接触孔，并且在层间绝缘层上形成用于暴露像素电极的开口；
    在层间绝缘层上形成源电极和漏电极，其中，源电极经接触孔电连接到半导体层，漏电极经接触孔和开口电连接半导体层和像素电极。
  5. 根据权利要求4所述的方法，其中，形成半导体层的步骤包括：在基底 上沉积金属氧化物，利用退火工艺对金属氧化物活化，之后执行黄光工艺和刻蚀工艺来形成具有预定图案的半导体层。
  6. 根据权利要求4所述的方法，其中，形成栅极绝缘层的步骤包括：在半导体层上沉积绝缘层，之后执行黄光工艺和刻蚀工艺来形成具有预定图案的栅极绝缘层，其中，绝缘层包括氮化硅层的单层或者包括以从下到上依次沉积的氧化硅层和氮化硅层的复合层。
  7. 根据权利要求4所述的方法，其中，形成栅电极的步骤包括：在栅极绝缘层上沉积金属层，并对金属层执行黄光工艺和刻蚀工艺以形成具有预定图案的栅电极。
  8. 根据权利要求4所述的方法，其中，层间绝缘层还包括氧化硅层，其中，以从下到上的顺序依次沉积氮化硅层和氧化硅层。
  9. 根据权利要求4所述的方法，其中，所述方法还包括：
    在层间绝缘层上形成钝化层以覆盖源电极和漏电极；
    在钝化层上形成共电极。
  10. 根据权利要求9所述的方法，其中，形成共电极的步骤包括：在钝化层上沉积电极层，之后执行黄光工艺和刻蚀工艺来得到具有预定图案的共电极。
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