WO2017121136A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2017121136A1
WO2017121136A1 PCT/CN2016/098352 CN2016098352W WO2017121136A1 WO 2017121136 A1 WO2017121136 A1 WO 2017121136A1 CN 2016098352 W CN2016098352 W CN 2016098352W WO 2017121136 A1 WO2017121136 A1 WO 2017121136A1
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Prior art keywords
substrate
layer
matte
signal line
film layer
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PCT/CN2016/098352
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English (en)
French (fr)
Inventor
王守坤
郭会斌
冯玉春
李梁梁
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/521,079 priority Critical patent/US10147643B2/en
Publication of WO2017121136A1 publication Critical patent/WO2017121136A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, and a display device.
  • a Thin Film Transistor (TFT) array substrate is located on the lower layer, and a color film substrate is located on the upper layer.
  • TFT Thin Film Transistor
  • the TFT array substrate is disposed on the upper layer of the display panel, and the color filter substrate is disposed on the lower layer of the display panel, thereby substantially narrowing the conductive end of the PCB circuit board. Borders, even without borders.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display device.
  • an array substrate including:
  • the matting layer being configured to reduce ambient ambient light entering the signal line if the array substrate is located on a light exiting side, the signal line is
  • the orthographic projection in the plane of the substrate substrate coincides with the orthographic projection of the matte layer in the plane of the substrate.
  • the matte layer comprises an amorphous silicon element or a semiconductor mixture doped with amorphous silicon.
  • the thickness of the matte layer satisfies the interference extinction formula:
  • d is the thickness of the matte layer
  • ⁇ is the wavelength of visible light in air
  • N is the refractive index of the matte layer
  • n is a natural number.
  • the thickness of the matte layer is the thickness of the matte layer.
  • At least one surface of the matte layer is provided with a plurality of convex structures.
  • both surfaces of the matte layer are provided with a plurality of convex structures.
  • the signal line is a gate line or a common electrode line.
  • a display device including the array substrate, The array substrate is located on a light emitting surface of the display device.
  • a method for preparing the array substrate including:
  • the method further includes:
  • the matte film layer is etched by the pattern of the signal lines to form a matte layer having the same pattern as the signal lines.
  • the method further includes: before sequentially depositing a matte film layer and a metal film layer on a surface of the base substrate,
  • the substrate is placed in a vacuum chamber, and a surface of the substrate is roughened by a plasma gas so that a surface of the subsequently formed mat layer adjacent to the substrate has a plurality of protrusions Structure.
  • the method further includes:
  • a metal film layer is deposited on the matte film layer after the roughening treatment.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • 2(a) to 2(c) are schematic structural views of three types of matting layers, respectively;
  • FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 4 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • Example 6 is a flow chart of a method for fabricating an array substrate provided in Example 1;
  • Example 7 is a flow chart of a method for fabricating an array substrate provided in Example 2.
  • FIG. 8 is a flow chart of a method for fabricating an array substrate provided in Example 3.
  • the inventors have noticed that for a narrow bezel or a frameless design, it is equivalent to inverting the existing display panel such that the TFT array substrate is close to the light exiting side.
  • the metal signal lines in the TFT array substrate especially the grid lines, will reflect the ambient light entering the environment, especially when the ambient light is strong, the reflection degree of the light-emitting surface is more serious, thereby causing The contrast of the display panel is poor, which affects the display.
  • FIG. 1 it is a schematic structural diagram of an array substrate according to the present disclosure.
  • the array substrate mainly includes a base substrate 11 and a signal line 12 located above the base substrate 11 .
  • the array substrate further includes: a matting layer 13 between the substrate substrate 11 and the signal line 12, and the matting layer 13 is configured to reduce external ambient light entering the signal line 12 when the array substrate is located on the light exiting side.
  • the orthographic projection of the signal line 12 in the plane of the substrate substrate coincides with the orthographic projection of the matte layer 13 in the plane of the substrate substrate.
  • the matting layer in this embodiment can reduce part of the ambient light, thereby reducing the ambient light entering the signal line, and correspondingly, the light reflected by the signal line is reduced, thereby improving the display due to the signal line reflecting the ambient light.
  • the problem of reduced contrast can reduce part of the ambient light, thereby reducing the ambient light entering the signal line, and correspondingly, the light reflected by the signal line is reduced, thereby improving the display due to the signal line reflecting the ambient light. The problem of reduced contrast.
  • the array substrate further includes: a TFT device, a data line, and a via, a pixel electrode, and the like.
  • the display contrast is lowered, and between the base substrate and the signal line, a
  • the extinction layer of the ambient light entering the signal line is reduced to eliminate the reflection and visual exposure caused by the signal line approaching the light exiting side.
  • the scheme reduces the ambient light entering the signal line by reducing the ambient light by the extinction layer, reduces the ambient light reflected by the signal line, improves the display contrast of the display panel, and the matting layer is in the plane of the substrate.
  • the orthographic projection inside the signal line coincides with the orthographic projection of the signal line in the plane of the substrate, that is, the pattern of the extinction layer is the same as the pattern of the signal line, so as not to affect the transmission of the display panel.
  • the rate while improving the display contrast, ensures the transmittance of the display panel and improves the display quality of the screen.
  • the material of the matte layer may be selected from a dark-colored amorphous silicon element or a semiconductor mixture doped with amorphous silicon.
  • the present disclosure The embodiment is not limited to this.
  • the matte layer of such a material can effectively improve the problem that the display contrast is lowered due to the reflection of the ambient light by the signal line.
  • the matting layer can achieve the reduction of ambient light by:
  • the thickness of the matte layer satisfies the following interference extinction formula:
  • d is the thickness of the matte layer
  • ⁇ is the wavelength of visible light in air
  • N is the refractive index of the matte layer
  • n is a natural number.
  • the matting layer conforming to the thickness defined by the interference extinction principle can reduce the ambient light, and effectively improve the display contrast caused by the signal line reflecting external ambient light.
  • the wavelength ⁇ of visible light ranges from 350 nm to 770 nm; the value of n is an arbitrary natural number.
  • the wavelength can be taken as the average value of the visible light wavelength, for example, about 550 nm.
  • the value of n is, for example, zero.
  • the thickness of the mat is about That is, the matte layer of the thickness satisfies the interference extinction condition, and when the ambient light enters the array substrate, the interference extinction phenomenon can be generated in the matte layer, and the ambient light entering the signal line can be reduced or even avoided, and the signal line is also reflected to be reduced to The light of the human eye, thereby increasing the display contrast of the display panel, and the pattern of the matte layer is the same as the pattern of the signal line, and does not affect the transmittance of the region other than the region where the signal line is located, thereby improving the overall display effect.
  • the matting layer in this embodiment can reduce part of the ambient light, thereby reducing the ambient light entering the signal line, and correspondingly, the light reflected by the signal line is reduced, thereby improving the display due to the signal line reflecting the ambient light.
  • the problem of reduced contrast can reduce part of the ambient light, thereby reducing the ambient light entering the signal line, and correspondingly, the light reflected by the signal line is reduced, thereby improving the display due to the signal line reflecting the ambient light. The problem of reduced contrast.
  • an embodiment of the present disclosure provides a matte layer between the signal line 22 and the substrate 21, and at least one surface of the matte layer 23 is provided with a plurality of surfaces.
  • the shape of the convex structure 231 may be a triangle, a trapezoid or an irregular figure, and the shapes of the plurality of convex structures may be the same or different, but embodiments of the present disclosure are not limited thereto.
  • the structure of the matte layer can include the following types:
  • Type 1 the surface of the matting layer 23 adjacent to the signal line 22 is provided with a plurality of convex structures 231, see FIG. 2(a);
  • Type 2 a surface of the extinction layer 23 remote from the signal line 22 is provided with a plurality of convex structures 231, see FIG. 2(b);
  • Type 3 Both surfaces of the matte layer 23 are provided with a plurality of convex structures 231, see Fig. 2(c).
  • the presence of a plurality of raised structures makes the surface of the matte layer rough, and it is easy to diffusely reflect the ambient light entering the matting layer, thereby reducing the light entering the signal line and reducing the
  • the signal line reflects the light of the human eye, thereby increasing the display contrast of the display panel, and the pattern of the extinction layer is the same as the pattern of the signal line, and does not affect the transmittance of the area other than the area where the signal line is located, and thus The overall display is improved.
  • a type III matte layer is used.
  • the signal lines involved in the embodiments of the present disclosure are gate lines or common electrode lines. Further, similar arrangement of the gate lines and the common electrode lines may be performed at the same time.
  • the embodiment of the present disclosure further provides a display device, for example, a frameless display device.
  • the display device includes the array substrate 31 according to the above embodiment, and a color film substrate disposed opposite to each other. 32.
  • the array substrate 31 is located on the light emitting surface of the display device. Since the matte layer is disposed in the array substrate of the display device, the ambient light that enters the signal line can be reduced by reducing the ambient light while achieving the borderless environment, thereby reducing the ambient light reflected from the signal line. Improve display contrast and improve display quality of display devices.
  • the matting layer in this embodiment can reduce part of the ambient light, thereby reducing the ambient light entering the signal line, and correspondingly, the light reflected by the signal line is reduced, thereby improving the display due to the signal line reflecting the ambient light.
  • the problem of reduced contrast can reduce part of the ambient light, thereby reducing the ambient light entering the signal line, and correspondingly, the light reflected by the signal line is reduced, thereby improving the display due to the signal line reflecting the ambient light. The problem of reduced contrast.
  • the embodiment of the present disclosure further provides a method for fabricating the array substrate, which is described below by way of a detailed embodiment.
  • FIG. 4 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure, the method includes:
  • Step 41 Providing a substrate.
  • Step 42 Forming a patterned matte layer and signal lines on the substrate by using a patterning process.
  • a patterned matting layer and signal lines are formed over the substrate substrate using a patterning process. Therefore, in this embodiment, the matting layer and the signal line can be formed by one patterning process, which saves the process flow and simplifies the process complexity. At the same time, the structure of the fabricated array substrate can improve the display contrast degradation caused by the signal line reflecting external ambient light.
  • a process of forming a TFT device, an insulating layer, and a process of a pixel electrode may be included, and these fabrication processes may be performed in accordance with the prior art.
  • step 42 includes:
  • a matte film layer and a metal film layer are sequentially deposited on one surface of the base substrate.
  • the matte film layer 52 and the metal film layer 53 are sequentially deposited on one surface of the base substrate 51 by a physical vapor deposition or chemical vapor deposition process, as shown in FIG. 5( a ); the matte film layer 52 is made of a dark color.
  • the amorphous silicon is a simple substance or a semiconductor mixture doped with an amorphous silicon element
  • the metal film layer is made of a metal element or a metal mixture such as copper, silver, nickel, etc., but embodiments of the present disclosure are not limited thereto.
  • a photoresist P of a predetermined thickness is applied onto the metal film layer 53 (for example, using a positive photoresist), and then, a reticle is used.
  • the metal film layer 53 is exposed and developed, and then the developed photoresist is peeled off.
  • FIG. 5(d) the region of the metal film layer 53 from which the photoresist is stripped is etched, and retained. A portion of the patterned signal line 54 is formed.
  • the matting process is not required for the matting layer and the signal line, and the matting layer and the signal line can be formed by only one patterning process, thereby saving significant
  • the process flow simplifies the process complexity.
  • a matting layer capable of reducing external ambient light is formed, ambient light entering the signal line is reduced, and light reflected from the signal line is further reduced, and the contrast of the subsequently formed display device is improved.
  • FIG. 6 is a flow chart of a method for fabricating an array substrate provided in Example 1, which mainly includes:
  • Step 61 Providing a substrate.
  • Step 62 The substrate is placed in a vacuum chamber, and a surface of the substrate is roughened by a plasma gas so that a surface of the subsequently formed mat layer adjacent to the substrate has a plurality of convex structures.
  • the surface of the substrate is bombarded with these plasma gases such as SF 6 , O 2 , etc., thereby roughening the surface.
  • Step 63 sequentially depositing a matte film layer and a metal film layer on one surface of the base substrate.
  • Step 64 performing a photolithography process on the metal film layer using a mask to form a patterned signal line.
  • Step 65 etching the matte film layer by using a pattern of signal lines to form a matte layer having the same pattern as the signal lines.
  • the technical solution can form a plurality of convex structures in the surface of the matting layer close to the substrate substrate when the matte film layer is deposited by means of the surface roughened by the substrate.
  • a flow chart of a method for fabricating an array substrate provided in Example 2 mainly includes:
  • Step 71 Providing a substrate.
  • Step 72 depositing a matte film layer on a surface of the base substrate.
  • Step 73 The substrate substrate on which the matte film layer is deposited is placed in a vacuum chamber, and the matte film layer is roughened by a plasma gas so that the matte film layer has a plurality of convex structures.
  • Step 74 depositing a metal film layer on the matte film layer after the roughening treatment.
  • Step 75 performing a photolithography process on the metal film layer using a reticle to form a patterned signal line.
  • Step 76 etching the matte film layer by using a pattern of signal lines to form a matte layer having the same pattern as the signal line.
  • the surface away from the substrate substrate in the matting film layer is roughened, that is, a plurality of convex structures are formed.
  • a flow chart of a method for fabricating an array substrate provided in Example 3 mainly includes the following steps:
  • Step 81 Providing a substrate.
  • Step 82 The substrate is placed in a vacuum chamber, and a surface of the substrate is roughened by a plasma gas so that a surface of the subsequently formed mat layer adjacent to the substrate has a plurality of convex structures.
  • Step 83 depositing a matte film layer on the surface of the base substrate after the roughening treatment.
  • Step 84 The substrate substrate on which the matte film layer is deposited is placed in a vacuum chamber, and the matte film layer is roughened by a plasma gas so that the matte film layer has a plurality of convex structures.
  • Step 85 depositing a metal film layer on the matte film layer after the roughening treatment.
  • Step 86 performing a photolithography process on the metal film layer using a reticle to form a patterned signal line.
  • Step 87 etching the matte film layer by using a pattern of signal lines to form a matte layer having the same pattern as the signal line.

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Abstract

公开一种阵列基板及其制作方法、显示装置。阵列基板包括：衬底基板(11)，位于衬底基板(11)之上的信号线(12)，位于衬底基板(11)与信号线(12)之间的消光层(13)，该消光层(13)配置来在阵列基板位于出光侧时消减外界环境光。信号线(12)在衬底基板(11)所在平面内的正投影与消光层(13)在衬底基板(11)所在平面内的正投影重合。

Description

阵列基板及其制作方法、显示装置 技术领域
本公开的实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
常见的显示面板中，薄膜晶体管(Thin Film Transistor，TFT)阵列基板位于下层，彩膜基板位于上层。为了实现窄边框甚至是无边框设计，会将TFT阵列基板设置在显示面板的上层，而将彩膜基板设置在显示面板的下层，从而，可大幅度窄化与PCB电路板贴合的导电端的边框，甚至实现无边框。
公开内容
本公开实施例提供一种阵列基板及其制作方法、显示装置。
根据本公开的至少一个实施例，提供一种阵列基板，包括：
衬底基板，
位于所述衬底基板之上的信号线，
位于所述衬底基板与所述信号线之间的消光层，所述消光层配置来在所述阵列基板位于出光侧的情况下消减进入所述信号线的外界环境光，所述信号线在所述衬底基板所在平面内的正投影与所述消光层在所述衬底基板所在平面内的正投影重合。
例如，所述消光层包括非晶硅单质或掺杂有非晶硅单质的半导体混合物。
例如，所述消光层的厚度满足干涉消光公式：
d＝(2n+1)λ/4N            (1)
其中，所述d为消光层的厚度，所述λ为可见光在空气中的波长，所述N为消光层的折射率，所述n为自然数。
例如，所述消光层的厚度为
Figure PCTCN2016098352-appb-000001
例如，所述消光层中至少一表面设置有多个凸起结构。
例如，所述消光层中两个表面均设置有多个凸起结构。
例如，所述信号线为栅线或公共电极线。
根据本公开的实施例，还提供一种显示装置，包括所述的阵列基板，所 述阵列基板位于该显示装置的出光面。
根据本公开的实施例，还提供一种制备所述的阵列基板的方法，包括：
提供一衬底基板；以及
例如，该方法还包括：
在所述衬底基板的一表面依次沉积消光膜层和金属膜层；
利用掩模版对所述金属膜层进行光刻工艺，形成图案化的信号线；以及
利用所述信号线的图案，对所述消光膜层进行刻蚀，形成与所述信号线相同图案的消光层。
例如，所述方法还包括：在所述衬底基板的一表面依次沉积消光膜层和金属膜层之前，
将所述衬底基板置于真空腔室中，利用等离子气体对所述衬底基板的一表面进行粗糙化处理，以使得后续形成的消光层中靠近所述衬底基板的表面具有多个凸起结构。
例如，所述方法还包括：
在所述衬底基板的一表面沉积消光膜层；
将沉积有消光膜层的衬底基板置于真空腔室中，利用等离子气体对所述消光膜层进行粗糙化处理，以使得所述消光膜层具有多个凸起结构；以及
在粗糙化处理后的消光膜层之上沉积金属膜层。
附图说明
以下将结合附图对本公开的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本公开的实施例，其中：
图1为本公开实施例提供的一种阵列基板的结构示意图；
图2(a)-图2(c)分别为消光层的三种类型的结构示意图；
图3为本公开实施例提供的一种显示装置的结构示意图；
图4为本公开实施例提供的一种阵列基板的制作方法流程图；
图5(a)-图5(e)为本公开实施例步骤42的工艺流程图；
图6为实例1提供的一种阵列基板的制作方法流程图；
图7为实例2提供的一种阵列基板的制作方法流程图；
图8为实例3提供的一种阵列基板的制作方法流程图。
具体实施方式
下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在无需做出创造性劳动前提下所获得的所有其它实施例，都应属于本公开保护的范围。
发明人注意到，对于窄边框或无边框设计，相当于是将现有的显示面板倒置，使得TFT阵列基板靠近出光侧。但是这样设置，TFT阵列基板中的金属信号线，尤其是栅线会对进入的外界环境光造成反射，特别是外界环境光较强时，出光面的反射程度更为严重，从而，就会导致显示面板的对比度较差，影响显示效果。
下面通过示例实施例对本公开实施例所涉及的技术方案进行详细描述，本公开的实施例包括但并不限于以下实施例。
如图1所示，为本公开所涉及的一种阵列基板的结构示意图，该阵列基板主要包括：衬底基板11，位于衬底基板11之上的信号线12。此外，阵列基板还包括：位于衬底基板11与信号线12之间的消光层13，消光层13用于在阵列基板位于出光侧的情况下消减进入信号线12的外界环境光。信号线12在衬底基板所在平面内的正投影与消光层13在衬底基板所在平面内的正投影重合。
该实施例中的消光层能够消减部分外界环境光，从而减少进入信号线的外界环境光，相应的，信号线反射出的光线随之减少，从而改善了由于信号线反射外界环境光而导致显示对比度下降的问题。
此外，该阵列基板还包括：TFT器件、数据线以及过孔、像素电极等结构。本公开的实施例未在图中示出，因而，并不在此进行赘述。
在本公开实施例的上述阵列基板的方案中，为了改善无边框显示面板存在的信号线反射外界环境光而导致显示对比度下降的问题，在衬底基板与信号线之间，设置一用于在阵列基板位于出光侧时消减进入信号线的外界环境光的消光层，以消除信号线靠近出光侧而造成的反光和视觉暴露。该方案通过消光层消减外界环境光的方式减少了进入信号线的外界环境光，减少了信号线反射的外界环境光，提升了显示面板的显示对比度，而且，该消光层在衬底基板所在平面内的正投影与信号线在衬底基板所在平面内的正投影重合，即该消光层的图案与信号线的图案相同，从而不会影响显示面板的透过 率，在提升显示对比度的同时，保证了显示面板的透过率，改善了画面显示质量。
例如，为了能够更好的实现对进入显示面板的外界环境光的消减，消光层的材质可选择颜色较深的非晶硅单质或掺杂有非晶硅单质的半导体混合物，但是，本公开的实施例并不限于此。
在本发明实施例中，此类材质的消光层能够有效改善由于信号线反射外界环境光而导致显示对比度下降的问题。
例如，在本公开实施例中，消光层可通过以下方式实现对外界环境光的消减：
方式一：干涉消光原理
由于各种波长的光都可以在一定的干涉消光条件下消光，在本公开的实施例中，消光层的厚度满足以下干涉消光公式：
d＝(2n+1)λ/4N       (1)
其中，d为消光层的厚度，λ为可见光在空气中的波长，N为消光层的折射率，n为自然数。
在本发明实施例中，符合该干涉消光原理所限定的厚度的消光层能够实现对外界环境光的消减，有效改善由于信号线反射外界环境光而导致显示对比度下降的问题。
例如，可见光的波长λ的取值范围为：350nm～770nm；n的取值为任意自然数。对于外界环境光，其波长可取值为可见光波长的平均值，例如：550nm左右。考虑到显示面板的厚度的限制，即为了适应现有的轻薄需求，n的取值例如为0。因而，当波长λ取值为550nm，n取值为0，当消光层的折射率为4时，消光层的厚度约为
Figure PCTCN2016098352-appb-000002
即该厚度的消光层满足干涉消光条件，在外界环境光进入阵列基板时，可在消光层产生干涉消光现象，减少甚至避免进入信号线的环境光线，进而，也会减小被信号线反射至人眼的光线，从而，提升显示面板的显示对比度，而且，该消光层的图案与信号线的图案相同，不会影响信号线所在区域以外的区域的透过率，因而，从整体上改善了显示效果。
该实施例中的消光层能够消减部分外界环境光，从而减少进入信号线的外界环境光，相应的，信号线反射出的光线随之减少，从而改善了由于信号线反射外界环境光而导致显示对比度下降的问题。
方式二：漫反射原理
考虑到现有的无边框设计中，对比度下降的主要原因在于：信号线大多为金属材质且表面光滑，很容易对进入的光线产生镜面反射。如图2(a)所示，而本公开的实施例为了改善这一问题，设置了位于信号线22与衬底基板21之间的消光层，该消光层23中至少一表面设置有多个凸起结构231。凸起结构231的形状可以为三角形、梯形或不规则图形，而且，多个凸起结构的形状可以相同，也可以不同，但是本公开的实施例并不限于此。例如，消光层的结构可以包括以下几种类型：
类型一：消光层23中靠近信号线22的表面设置有多个凸起结构231，参见图2(a)；
类型二：消光层23中远离信号线22的表面设置有多个凸起结构231，参见图2(b)；
类型三：消光层23的两个表面均设置有多个凸起结构231，参见图2(c)。
但是，本公开的实施例并不限于上述方式和类型。
无论以上哪种类型，多个凸起结构的存在使得消光层的表面粗糙，很容易对进入该消光层的外界环境光产生漫反射，进而，导致进入信号线的光线减少，也会减小被信号线反射至人眼的光线，从而，提升显示面板的显示对比度，而且，该消光层的图案与信号线的图案相同，不会影响信号线所在区域以外的区域的透过率，因而，从整体上改善了显示效果。
在本公开的实施例中，为了增加漫反射效果，例如使用类型三的消光层。
例如，本公开实施例中所涉及的信号线为栅线或公共电极线，此外，也可以同时对栅线以及公共电极线进行类似设置。
同时，本公开实施例还提供了一种显示装置，例如，一种无边框显示装置，如图3所示，该显示装置包括上述实施例所涉及的阵列基板31，以及相对设置的彩膜基板32。阵列基板31位于该显示装置的出光面。由于该显示装置的阵列基板中设置有消光层，因此，在实现无边框的同时，可以通过消减外界环境光的方式减少进入信号线的外界环境光，进而，减少信号线反射出的外界环境光，提升显示对比度，改善显示装置的显示质量。
该实施例中的消光层能够消减部分外界环境光，从而减少进入信号线的外界环境光，相应的，信号线反射出的光线随之减少，从而改善了由于信号线反射外界环境光而导致显示对比度下降的问题。
与本公开实施例提供的阵列基板的构思相同，本公开实施例还提供了一种制作所述的阵列基板的方法，下面通过详细的实施例介绍。
如图4所示，为本公开实施例提供的一种阵列基板的制作方法流程图，该方法包括：
步骤41：提供一衬底基板。
步骤42：利用一次构图工艺，在所述衬底基板之上形成图案化的消光层和信号线。
利用一次构图工艺，在所述衬底基板之上形成图案化的消光层和信号线。因此，该实施例中通过一次构图工艺即可形成消光层和信号线，节省了工艺流程，简化了工艺复杂度。同时，制作而成的阵列基板的结构能够改善由于信号线反射外界环境光而导致显示对比度下降的问题。
此外，还可以包括形成TFT器件的过程，绝缘层以及像素电极的过程，这些制作工艺流程均可按照现有技术执行。
例如，步骤42包括：
421：在衬底基板的一表面依次沉积消光膜层和金属膜层。
例如，利用物理气相沉积或化学气相沉积工艺在衬底基板51的一表面依次沉积消光膜层52和金属膜层53，如图5(a)所示；消光膜层52的材质为颜色较深的非晶硅单质或掺杂有非晶硅单质的半导体混合物，金属膜层的材质为金属单质或金属混合物，例如：铜、银、镍等，但是，本公开的实施例并不限于此。
422：利用掩模版对金属膜层进行光刻工艺，形成图案化的信号线。
例如，首先，如图5(b)、5(c)所示，在金属膜层53上涂布设定厚度的光刻胶P(例如使用正性光刻胶)，然后，利用掩模版S对金属膜层53进行曝光、显影，然后将显影溶解掉的光刻胶剥离，最后，如图5(d)所示，对剥离光刻胶的金属膜层53的区域进行刻蚀，保留的部分形成图案化的信号线54。
423：利用所述信号线的图案，对所述消光膜层进行刻蚀，形成与所述信号线相同图案的消光层。
在该步中，由于信号线54已经图案化，且消光层55的图案与信号线54的图案相同，因此，不需要对消光层进行额外的构图工艺，只需利用已形成的信号线的图案，对消光膜层进行掩模阻挡，以便于对消光膜层的暴露出的 区域进行刻蚀，最终形成与信号线的图案相同的消光层55，如图5(e)所示。
本公开的实施例中，由于消光层与信号线的图案相同，因此，不需要对消光层和信号线分别进行构图工艺，只需一次构图工艺即可形成消光层和信号线，从而，显著节省了工艺流程，简化了工艺复杂度。而且，形成了能够消减外界环境光的消光层，减少了进入信号线的环境光，进一步，减少了信号线反射出的光线，提升了后续形成的显示装置的对比度。
在本公开的实施例中，基于以上制作方案，提供了以下示例实例。
实例1：
如图6所示，为实例1提供的一种阵列基板的制作方法流程图，主要包括：
步骤61：提供一衬底基板。
步骤62：将衬底基板置于真空腔室中，利用等离子气体对衬底基板的一表面进行粗糙化处理，以使得后续形成的消光层中靠近衬底基板的表面具有多个凸起结构。
例如，在本公开实施例中，将衬底基板置于真空腔室后，利用SF6、O2等这些等离子气体，对衬底基板表面进行轰击，从而，对表面进行粗糙化处理。
步骤63：在衬底基板的一表面依次沉积消光膜层和金属膜层。
步骤64：利用掩模版对金属膜层进行光刻工艺，形成图案化的信号线。
步骤65：利用信号线的图案，对消光膜层进行刻蚀，形成与信号线相同图案的消光层。
该技术方案可以借助衬底基板粗糙化的表面，在沉积消光膜层时，使得消光层中靠近衬底基板的表面形成多个凸起结构。
实例2：
如图7所示，为实例2提供的一种阵列基板的制作方法流程图，主要包括：
步骤71：提供一衬底基板。
步骤72：在衬底基板的一表面沉积消光膜层。
步骤73：将沉积有消光膜层的衬底基板置于真空腔室中，利用等离子气体对消光膜层进行粗糙化处理，以使得消光膜层具有多个凸起结构。
步骤74：在粗糙化处理后的消光膜层之上沉积金属膜层。
步骤75：利用掩模版对金属膜层进行光刻工艺，形成图案化的信号线。
步骤76：利用信号线的图案，对消光膜层进行刻蚀，形成与信号线相同图案的消光层。
在该技术方案中，是在沉积了消光膜层之后，在消光膜层中远离衬底基板的表面作粗糙化处理，即形成多个凸起结构。
实例3：
如图8所示，为实例3提供的一种阵列基板的制作方法流程图，主要包括以下步骤：
步骤81：提供一衬底基板。
步骤82：将衬底基板置于真空腔室中，利用等离子气体对衬底基板的一表面进行粗糙化处理，以使得后续形成的消光层中靠近衬底基板的表面具有多个凸起结构。
步骤83：在衬底基板的进行粗糙化处理后的表面沉积消光膜层。
步骤84：将沉积有消光膜层的衬底基板置于真空腔室中，利用等离子气体对消光膜层进行粗糙化处理，以使得消光膜层具有多个凸起结构。
步骤85：在粗糙化处理后的消光膜层之上沉积金属膜层。
步骤86：利用掩模版对金属膜层进行光刻工艺，形成图案化的信号线。
步骤87：利用信号线的图案，对消光膜层进行刻蚀，形成与信号线相同图案的消光层。
该实例3的技术方案中，一方面，借助衬底基板粗糙化的表面，在沉积消光膜层时使得消光层中靠近衬底基板的表面形成多个凸起结构，另一方面，在消光膜层中远离衬底基板的表面作粗糙化处理，形成多个凸起结构。但是，本公开的实施例并不限于此。
以上所述，仅为本公开的示例性实施例，但本公开的保护范围并不局限于此，任何熟悉本技术领域的普通技术人员在本公开的实施例揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。
本申请要求于2016年1月11日提交的名称为“一种阵列基板及其制作方法、显示装置”的中国专利申请No.201610015755.8的优先权，其全文通过引用合并于本文。

Claims (12)

  1. 一种阵列基板，包括：
    衬底基板；
    位于所述衬底基板之上的信号线；以及
    位于所述衬底基板与所述信号线之间的消光层，所述消光层配置来在所述阵列基板位于出光侧的情况下消减进入所述信号线的外界环境光，
    其中，所述信号线在所述衬底基板所在平面内的正投影与所述消光层在所述衬底基板所在平面内的正投影重合。
  2. 如权利要求1所述的阵列基板，其中，所述消光层的材质包括非晶硅单质或掺杂有非晶硅单质的半导体混合物。
  3. 如权利要求1或2所述的阵列基板，其中，所述消光层的厚度满足干涉消光公式：
    d＝(2n+1)λ/4N  (1)其中，d为消光层的厚度，λ为可见光在空气中的波长，N为消光层的折射率，n为自然数。
  4. 如权利要求1-3任一项所述的阵列基板，其中，所述消光层的厚度为
    Figure PCTCN2016098352-appb-100001
  5. 如权利要求1-4任一项所述的阵列基板，其中，所述消光层中至少一表面设置有多个凸起结构。
  6. 如权利要求1-5任一项所述的阵列基板，其中，所述消光层中两个表面均设置有多个凸起结构。
  7. 如权利要求1-6任一项所述的阵列基板，其中，所述信号线为栅线或公共电极线。
  8. 一种显示装置，包括权利要求1-7任一项所述的阵列基板，所述阵列基板位于该显示装置的出光面。
  9. 一种阵列基板的制作方法，包括：
    提供一衬底基板；以及
    利用一次构图工艺，在所述衬底基板之上形成图案化的消光层和信号线。
  10. 如权利要求9所述的方法，还包括：
    在所述衬底基板的一表面依次沉积消光膜层和金属膜层；
    利用掩模版对所述金属膜层进行光刻工艺，形成图案化的信号线；以及
    利用所述信号线的图案，对所述消光膜层进行刻蚀，形成与所述信号线相同图案的消光层。
  11. 如权利要求10所述的方法，还包括：
    将所述衬底基板置于真空腔室中，利用等离子气体对所述衬底基板的一表面进行粗糙化处理，以使得后续形成的消光层中靠近所述衬底基板的表面具有多个凸起结构。
  12. 如权利要求10或11所述的方法，还包括：
    在所述衬底基板的一表面沉积消光膜层；
    将沉积有消光膜层的衬底基板置于真空腔室中，利用等离子气体对所述消光膜层进行粗糙化处理，以使得所述消光膜层具有多个凸起结构；以及
    在粗糙化处理后的消光膜层之上沉积金属膜层。
PCT/CN2016/098352 2016-01-11 2016-09-07 阵列基板及其制作方法、显示装置 WO2017121136A1 (zh)

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CN105470268A (zh) * 2016-01-11 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN109407431A (zh) * 2017-08-17 2019-03-01 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN109378345A (zh) * 2018-10-11 2019-02-22 深圳市华星光电技术有限公司 薄膜晶体管及其制造方法
CN110993622A (zh) * 2019-12-13 2020-04-10 Tcl华星光电技术有限公司 阵列基板及其制备方法、显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1858911A (zh) * 2005-05-02 2006-11-08 三星电子株式会社 Tft阵列面板、包含它的液晶显示器及tft阵列面板制造方法
CN101330106A (zh) * 2008-07-28 2008-12-24 友达光电股份有限公司 显示面板的薄膜晶体管基板与薄膜晶体管及其制作方法
US20150198853A1 (en) * 2014-01-10 2015-07-16 Samsung Display Co., Ltd. Display apparatus and method of manufacturing the same
CN105470268A (zh) * 2016-01-11 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103185978B (zh) * 2011-12-28 2016-02-24 上海中航光电子有限公司 液晶面板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1858911A (zh) * 2005-05-02 2006-11-08 三星电子株式会社 Tft阵列面板、包含它的液晶显示器及tft阵列面板制造方法
CN101330106A (zh) * 2008-07-28 2008-12-24 友达光电股份有限公司 显示面板的薄膜晶体管基板与薄膜晶体管及其制作方法
US20150198853A1 (en) * 2014-01-10 2015-07-16 Samsung Display Co., Ltd. Display apparatus and method of manufacturing the same
CN105470268A (zh) * 2016-01-11 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

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