WO2017121093A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2017121093A1
WO2017121093A1 PCT/CN2016/092057 CN2016092057W WO2017121093A1 WO 2017121093 A1 WO2017121093 A1 WO 2017121093A1 CN 2016092057 W CN2016092057 W CN 2016092057W WO 2017121093 A1 WO2017121093 A1 WO 2017121093A1
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Prior art keywords
voltage
transistor
unit
pixel circuit
pole
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PCT/CN2016/092057
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English (en)
French (fr)
Inventor
谭文
陈佳
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/513,983 priority Critical patent/US10223990B2/en
Publication of WO2017121093A1 publication Critical patent/WO2017121093A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3651—Control of matrices with row and column drivers using an active matrix using multistable liquid crystals, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
    • G09G2300/0482—Use of memory effects in nematic liquid crystals
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display panel.
  • MIP Memory in Pixel
  • the pixel driving circuit includes: a switching transistor TFT, an analog voltage storage unit (Analog Memory Uint), a storage capacitor Cst, and a liquid crystal capacitor Clc.
  • the display panel including the pixel driving circuit is in a standby state or displays a static screen. (ie, the static display mode), the analog voltage storage unit provides a stable data voltage for the liquid crystal capacitor Clc.
  • the analog voltage storage unit provides a stable data voltage for the liquid crystal capacitor Clc.
  • it is no longer necessary to update the display screen by the gate drive thereby reducing the update frequency when the display panel displays the static picture. This can reduce the power consumption of the integrated circuit, that is, the overall power consumption of the display panel is reduced.
  • one of the objects of the present invention is to provide a pixel circuit and a driving method thereof, and a display panel including the pixel circuit, which is capable of storing an analog data voltage, thereby enabling static of a color picture display.
  • the present invention provides a pixel circuit including a data writing unit, a voltage following unit, a voltage storage unit, and a liquid crystal capacitor;
  • the data writing unit is connected to the voltage storage unit, an input end of the voltage following unit is connected to the data writing unit and the voltage storage unit, and an output end of the voltage following unit and the liquid crystal capacitor
  • the first end is connected, the voltage storage unit is connected to the first power end, and the second end of the liquid crystal capacitor is connected to the second power end;
  • the data writing unit is configured to transmit a data voltage on the data line to the voltage storage unit and the voltage following unit when the pixel circuit is in a normal display mode;
  • the voltage storage unit is configured to store the data voltage when the pixel circuit is in a normal display mode, and to transmit the data voltage or an adjustment voltage to the pixel circuit when in a static display mode
  • the input of the voltage following unit, the adjustment voltage satisfies:
  • Vdata' 2Vref-Vdata
  • Vdata' is the adjustment voltage
  • Vref is a voltage outputted by the first power terminal
  • Vdata is the data voltage
  • the voltage following unit is configured to output a corresponding data output voltage according to the data voltage or the adjustment voltage, so that the liquid crystal capacitor generates a corresponding liquid crystal deflection electric field;
  • the voltage output by the second power terminal meets:
  • Vcom Vref- ⁇ V
  • Vcom is a voltage output by the second power terminal
  • ⁇ V is a voltage difference between an input end and an output end of the voltage follower unit.
  • the voltage storage unit includes a storage capacitor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
  • a control electrode of the fifth transistor is connected to the first control line, the fifth transistor a first pole is connected to the first power terminal, and a second pole of the fifth transistor is connected to the first end of the storage capacitor;
  • a control electrode of the sixth transistor is connected to the second control line, a first pole of the sixth transistor is connected to the first power terminal, a second pole of the fifth transistor is second with the second storage capacitor End connection
  • a control electrode of the seventh transistor is connected to the second control line, a first pole of the seventh transistor is connected to a first end of the storage capacitor, and a second pole of the seventh transistor is opposite to the voltage
  • An input end of the following unit is connected to the data writing unit;
  • a control electrode of the eighth transistor is connected to the first control line, a first pole of the eighth transistor is connected to a second end of the storage capacitor, and a second pole of the eighth transistor is opposite to the voltage
  • An input end of the following unit is connected to the data writing unit;
  • the voltage storage unit further includes a first voltage compensation unit and a second voltage compensation unit;
  • the first voltage compensation unit is disposed between the second pole of the fifth transistor and the first end of the storage capacitor, and the second voltage compensation unit is disposed at the second pole of the sixth transistor Between the second ends of the storage capacitors;
  • the first voltage compensation unit is configured to prevent leakage between the first end of the storage capacitor and the first power terminal when the pixel circuit is in a static display mode and the fifth transistor is in an off state Current
  • the second voltage compensation unit is configured to prevent leakage between the second end of the storage capacitor and the first power terminal when the pixel circuit is in a static display mode and the sixth transistor is in an off state Current.
  • the first voltage compensation unit includes a ninth transistor and an eleventh transistor
  • a control electrode of the ninth transistor is connected to the first control line, and a first pole of the ninth transistor is connected to a second pole of the fifth transistor and a second pole of the eleventh transistor, a second pole of the ninth transistor is connected to the first end of the storage capacitor;
  • a control electrode of the eleventh transistor is connected to the second control line, a first pole of the eleventh transistor is connected to a third power terminal, and a second pole of the eleventh transistor is opposite to the fifth a second pole connection of the transistor;
  • the second voltage compensation unit includes a tenth transistor and a twelfth transistor
  • a control electrode of the tenth transistor is connected to the second control line, and a first pole of the tenth transistor is connected to a second pole of the sixth transistor and a second pole of the twelfth transistor, a second pole of the tenth transistor is connected to the second end of the storage capacitor;
  • a control electrode of the twelfth transistor is connected to the first control line, a first pole of the twelfth transistor is connected to a third power terminal, and a second pole of the twelfth transistor is opposite to the sixth The second pole of the transistor is connected.
  • the data writing unit includes a third transistor
  • a control electrode of the third transistor is coupled to a third control line, a first pole of the third transistor is coupled to a data line, a second pole of the third transistor is coupled to an input of the voltage follower unit, and The voltage storage unit is connected.
  • the pixel circuit further includes a third voltage compensation unit
  • the third voltage compensation unit is disposed between the voltage storage unit and the second pole of the third transistor;
  • the third voltage compensation unit is configured to prevent leakage current from being generated between the voltage storage unit and the data line when the third transistor is in an off state.
  • the third voltage compensation unit includes a second transistor and a fourth transistor
  • a control electrode of the second transistor is connected to a third control line, a first pole of the second transistor is connected to a second pole of the fourth transistor and the data writing unit, and the second transistor is a diode connected to the voltage storage unit and the voltage follower unit;
  • the control electrode of the fourth transistor is connected to the fourth control line, and the first pole of the fourth transistor is connected to the fourth power terminal.
  • the voltage following unit includes a first transistor, and the first transistor is a common drain amplifying transistor;
  • a gate of the first transistor is connected to the data writing unit and the voltage storage unit, a source of the first transistor is connected to a fifth power terminal, a drain of the first transistor and the liquid crystal The first end of the capacitor is connected.
  • the static display mode includes an alternate first polarity display phase and a second polarity display phase;
  • the voltage storage unit transmits the data voltage to an input end of the voltage following unit during the first polarity display phase
  • the voltage storage unit transmits the adjustment voltage to an input of the voltage follower unit during the second polarity display phase.
  • each transistor in the pixel circuit is an N-type transistor.
  • the present invention further provides a driving method of a pixel circuit, wherein the pixel circuit is any one of the above pixel circuits, and the driving method of the pixel circuit includes:
  • the data writing unit transmits a data voltage on the data line to the voltage storage unit and an input end of the voltage following unit, and the voltage following unit outputs corresponding data according to the data voltage. Outputting a voltage for the liquid crystal capacitor to generate a corresponding liquid crystal deflection electric field;
  • the voltage storage unit sends the data voltage or the adjustment voltage to an input end of the voltage following unit, and the voltage following unit outputs a corresponding according to the data voltage or the adjusted voltage
  • the data output voltage is such that the liquid crystal capacitor generates a corresponding liquid crystal deflection electric field.
  • the voltage storage unit alternately transmits the data voltage and the adjustment voltage to the voltage following unit.
  • the present invention also provides a display panel comprising any of the above pixel circuits.
  • the present invention has the following advantageous effects.
  • the present invention provides a pixel circuit and a driving method thereof, and a display panel including the pixel circuit, the pixel circuit including a data writing unit, a voltage storage unit, a voltage following unit, and a liquid crystal capacitor, wherein the data writing unit and the voltage
  • the storage unit is connected to the voltage following unit, and the data writing unit is configured to send the data voltage on the data line to the voltage storage unit and the voltage following unit when the pixel circuit is in the normal display mode; the voltage storage unit and the first power terminal and the voltage Connected to the input terminal of the unit, the voltage storage unit is configured to store the data voltage when the pixel circuit is in the normal display mode, and to send the data voltage or the adjustment voltage to the voltage follower unit when the pixel circuit is in the static display mode
  • the input end of the voltage follower unit is connected to the first end of the liquid crystal capacitor, the second end of the liquid crystal capacitor is connected to the second power end, and the voltage follower unit is configured to output the corresponding data voltage or the adjusted voltage according to the voltage storage unit
  • the data output voltage is used for the liquid crystal capacitor to generate a corresponding liquid crystal deflection electric field.
  • the technical solution of the present invention stores the analog data voltage in the data line in the normal display mode by the voltage storage unit, and outputs the data voltage and/or the analog voltage in the static display mode, so that the liquid crystal capacitor generates a corresponding liquid crystal deflection electric field. , in turn, achieve a static display.
  • the voltage storage unit can store the data voltage corresponding to each display gray scale, static display of the color screen by the display panel can be realized for the entire display panel.
  • FIG. 1 is a circuit diagram of a pixel driving circuit in the prior art.
  • FIG. 2 is a schematic circuit diagram of a pixel circuit according to a first embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of a pixel circuit according to a second embodiment of the present invention.
  • FIG. 4 is a timing chart showing the operation of the pixel circuit shown in FIG.
  • FIG. 5 is a schematic circuit diagram of a pixel circuit according to a third embodiment of the present invention.
  • FIG. 6 is a timing chart showing the operation of the pixel circuit shown in FIG. 5.
  • FIG. 7 is a flowchart of a driving method of a pixel circuit according to a fourth embodiment of the present invention.
  • FIG. 2 is a schematic circuit diagram of a pixel circuit according to a first embodiment of the present invention. As shown in FIG. 2, the pixel circuit includes two working modes: a normal display mode and a static display mode.
  • the pixel circuit includes a data writing unit 1, a voltage storage unit 2, a voltage following unit 3, and a liquid crystal capacitor Clc.
  • the data writing unit 1 and the voltage storage unit 2 and the voltage follower list The element 3 is connected, and the data writing unit 1 is for transmitting the data voltage on the data line to the voltage storage unit 2 and the voltage following unit 3 when the pixel circuit is in the normal display mode.
  • the voltage storage unit 2 is connected to the first power terminal 4 and the input terminal of the voltage follower unit 3, and the voltage storage unit 2 is configured to store the data voltage when the pixel circuit is in the normal display mode, and when the pixel circuit is in the static display mode, The data voltage or the adjustment voltage is sent to the input end of the voltage follower unit 3, wherein the adjustment voltage is a voltage output by the voltage storage unit 2 based on the data voltage and the voltage output by the first power terminal 4, and the adjustment voltage is satisfied. :
  • Vdata' 2Vref-Vdata
  • Vdata' is the adjustment voltage
  • Vref is the voltage output by the first power supply terminal 4
  • Vdata is the data voltage
  • the output end of the voltage follower unit 3 is connected to the first end of the liquid crystal capacitor Clc, the second end of the liquid crystal capacitor Clc is connected to the second power terminal 5, and the voltage follower unit 3 is used for the data voltage or the voltage adjustment according to the voltage storage unit 2.
  • the corresponding data output voltage is outputted for the liquid crystal capacitor Clc to generate a corresponding liquid crystal deflection electric field.
  • the voltage output by the second power terminal 5 satisfies:
  • Vcom Vref- ⁇ V
  • Vcom is the voltage output by the second power terminal 5
  • ⁇ V is the voltage difference between the input terminal and the output terminal of the voltage follower unit 3.
  • the voltage following unit 3 in this embodiment is an electronic device that implements an output voltage following an input voltage change.
  • the voltage amplification factor of the voltage follower unit 3 is always less than and close to 1, ie the voltage at the output of the voltage follower unit 3 is less than and close to the voltage at its input.
  • the voltage difference ⁇ V between the input and output of the voltage follower unit 3 is generally a small fixed value.
  • the data voltage on the data line is written to the voltage follower unit 3 and the voltage storage unit 2 through the data writing unit 1, that is, the voltage at the Q point is Vdata.
  • the voltage storage unit 2 stores the data voltage, and the voltage follower unit 3 outputs corresponding data output power according to the data voltage.
  • the voltage output voltage is equal to Vdata- ⁇ V, that is, the voltage at point P is Vdata- ⁇ V.
  • the voltage difference between both ends of the liquid crystal capacitor Clc (also referred to as liquid crystal deflection voltage) is equal to Vdata - ⁇ V - Vcom.
  • the data writing unit 1 stops data writing, and the voltage storage unit 2 outputs a data voltage or an adjustment voltage to the input terminal of the voltage following unit 3.
  • Vclc_1+Vclc_2 Vdata- ⁇ V-Vcom+Vdata'- ⁇ V-Vcom
  • Vclc_1 and Vclc_2 are equal in magnitude but opposite in polarity, and both correspond to the same display gray scale (brightness). Therefore, regardless of whether the voltage storage unit 2 outputs the data voltage or the adjustment voltage to the voltage follower unit 3, the display gray scale corresponding to the voltage difference between the two ends of the liquid crystal capacitor Clc does not change, and the pixel circuit can maintain the static display.
  • the voltage storage unit 2 can store the data voltage corresponding to each display gray scale, thereby enabling static display of the color picture.
  • the static display mode of the pixel circuit includes an alternate first polarity display phase and a second polarity display phase.
  • the voltage storage unit 2 transmits the data voltage to the input of the voltage follower unit 3.
  • the voltage storage unit 2 sends the adjustment voltage to the input of the voltage follower unit 3.
  • the data voltage and the adjustment voltage are alternately outputted to the voltage follower unit 3 through the voltage storage unit 2.
  • the polarity reversal of the voltage difference between the two ends of the liquid crystal capacitor Clc can be realized, thereby effectively preventing the problem of liquid crystal fatigue during static display.
  • FIG. 3 is a schematic circuit diagram of a pixel circuit according to a second embodiment of the present invention. As shown in FIG. 3, the pixel circuit shown in FIG. 3 is a specific scheme based on the pixel circuit shown in FIG. 2.
  • the data writing unit 1 includes a third transistor T3.
  • the control electrode of the third transistor T3 is connected to the third control line S3, the first electrode of the third transistor T3 is connected to the data line, and the second electrode of the third transistor T3 is connected to the input terminal of the voltage follower unit 3 and the voltage storage unit 2. .
  • the voltage follower unit 3 comprises a first transistor T1.
  • the first transistor T1 is a common drain amplifying transistor, the gate of the first transistor T1 is connected to the data writing unit 1 and the voltage storage unit 2, and the source of the first transistor T1 is connected to the fifth power terminal 6, first
  • the drain of the transistor T1 is connected to the first end of the liquid crystal capacitor Clc.
  • the voltage storage unit 2 includes a storage capacitor Cst, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.
  • the control electrode of the fifth transistor T5 is connected to the first control line S1
  • the first electrode of the fifth transistor T5 is connected to the first power supply terminal 4
  • the second electrode of the fifth transistor T5 is connected to the first end of the storage capacitor Cst.
  • the control electrode of the sixth transistor T6 is connected to the second control line S2, the first electrode of the sixth transistor T6 is connected to the first power supply terminal 4, and the second electrode of the fifth transistor T5 is connected to the second terminal of the storage capacitor Cst.
  • the control electrode of the seventh transistor T7 is connected to the second control line S2, the first electrode of the seventh transistor T7 is connected to the first end of the storage capacitor Cst, and the second electrode of the seventh transistor T7 is connected to the input end of the voltage follower unit 3
  • the data writing unit 1 is connected.
  • the control electrode of the eighth transistor T8 is connected to the first control line S1
  • the first electrode of the eighth transistor T8 is connected to the second end of the storage capacitor Cst
  • the second electrode of the eighth transistor T8 is connected to the input terminal of the voltage follower unit 3
  • the data writing unit 1 is connected.
  • the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors, and the first power terminal 4 supplies the reference voltage Vref.
  • the working process of the pixel circuit may include three stages from the first stage to the third stage.
  • the pixel circuit In the first stage, the pixel circuit is in the normal display mode. At this time, the first control line S1 outputs a high level, the second control line S2 outputs a low level, and the third control line S3 outputs a high level. At this time, the third transistor T3, the fifth transistor T5, and the eighth transistor T8 are turned on, and the sixth transistor T6 and the seventh transistor T7 are turned off.
  • the sixth transistor T6 is turned off and the eighth transistor T8 is turned on, the voltage at the Q point is written to the second end of the storage capacitor Cst, and the voltage at the point M is Vdata.
  • the pixel circuit is in a static display mode and corresponds to a first polarity display phase.
  • the first control line S1 outputs a high level
  • the second control line S2 outputs a low level
  • the third control line S3 outputs a low level.
  • the fifth transistor T5 and the eighth transistor T8 are turned on
  • the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned off.
  • the second end of the storage capacitor Cst outputs a voltage to the Q point because the second of the storage capacitor Cst
  • the liquid crystal capacitor Clc has the same voltage difference Vclc_1 between the two ends in the second stage and the voltage difference Vclc between the two ends in the first stage, and the polarity is the same, so the liquid crystal capacitor Clc The display gray level corresponding to the voltage difference between the two ends does not change.
  • the pixel circuit is in the static display mode and corresponds to the second polarity display phase.
  • the first control line S1 outputs a low level
  • the second control line S2 outputs a high level
  • the third control line S3 outputs a low level.
  • the sixth transistor T6 and the seventh transistor T7 are turned on
  • the third transistor T3, the fifth transistor T5, and the eighth transistor T8 are turned off.
  • the first power terminal 4 charges the second end of the storage capacitor Cst, and the voltage of the second terminal of the storage capacitor Cst becomes Vref, that is, The voltage at point M is Vref.
  • the voltage of the first end of the storage capacitor Cst is bootstrapped, and the voltage of the first end of the storage capacitor Cst jumps to 2Vref-Vdata, that is, the voltage at the N point is 2Vref-Vdata.
  • Vclc_2 2Vref-Vdata-Vth-Vcom
  • the liquid crystal capacitor Clc has the same voltage difference Vclc_2 between the two ends in the third stage and the voltage difference Vclc_1 between the two ends in the second stage, but the polarity is opposite, so the liquid crystal capacitor Clc The voltage difference between the two ends is in polarity reversal At the same time, it can also ensure that the gray scale corresponding to the polarity is reversed.
  • the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors, which is only the embodiment.
  • the above-mentioned transistors can be simultaneously prepared by the same production process, thereby reducing the production process and shortening the production cycle. It should be understood by those skilled in the art that the technical solutions for realizing the processes of the above stages by varying the types of transistors and correspondingly changing the output signals of the control lines are all within the scope of protection of the present invention.
  • a third embodiment of the present invention provides a pixel circuit which is a modification based on the pixel circuit shown in FIG.
  • the pixel circuit cannot maintain static display for a long time.
  • the principle of the pixel circuit shown in FIG. 2 that cannot maintain static display for a long time will be described in detail below with reference to an example. It is assumed that the data voltage Vdata on the data line is larger than the voltage Vref of the first power terminal 4.
  • the sixth transistor T6 When the pixel circuit shown in FIG. 3 is in the second stage, although the sixth transistor T6 is in the off state, since the first pole of the sixth transistor T6 is connected to the first power terminal 4, the first power terminal 4 and the storage capacitor Cst are Leakage current (small current flowing through the sixth transistor T6) is easily generated between the second ends. Specifically, since the voltage of the second end of the storage capacitor Cst is Vdata in the second phase, that is, the voltage of the second end of the storage capacitor Cst is greater than the voltage of the first power terminal 4, the second end of the storage capacitor Cst passes the The six-transistor T6 discharges, and the leakage current flows from the second end of the storage capacitor Cst to the first power supply terminal 4.
  • the voltage of the second terminal of the storage capacitor Cst decreases correspondingly, and the voltage of the first end of the storage capacitor Cst (equal to Vref) remains unchanged, so the voltage difference between the two ends of the storage capacitor Cst continues to increase in the second phase.
  • the voltage of the first end of the storage capacitor Cst is 2Vref-Vdata in the third stage, and 2Vref-Vdata ⁇ Vref, that is, the voltage of the first end of the storage capacitor Cst is lower than the voltage of the first power terminal 4,
  • the first power terminal 4 charges the first end of the storage capacitor Cst through the fifth transistor T5, and the leakage current flows from the first power terminal 4 to the first end of the storage capacitor Cst, and the voltage at the first end of the storage capacitor Cst Corresponding rise, and since the voltage at the second end of the storage capacitor Cst (equal to Vref) remains unchanged, the voltage difference between the two ends of the storage capacitor Cst continues to increase in the third phase.
  • the voltage difference between the two ends of the storage capacitor Cst may be over time during the static display of the pixel circuit shown in FIG. As the gradual decrease, the voltage actually discharged by the voltage storage unit 2 is far from the data voltage or the adjustment voltage, thereby causing the static display to fail.
  • one data line often corresponds to a plurality of pixel circuits.
  • the pixel circuit in which the data voltage is written enters In the static display mode, the data line will write the corresponding data voltage to the next pixel circuit, that is, the pixel voltage in the data line will change.
  • the pixel circuit that has entered the static display mode since the voltages of the first pole and the second pole of the third transistor T3 are different, a leakage current is generated between the data line and the voltage storage unit 2, and then the Q point is generated. The voltage has an effect. When the voltage at the Q point deviates far from the data voltage or the regulated voltage, the static display fails.
  • FIG. 5 is a schematic circuit diagram of a pixel circuit according to a third embodiment of the present invention, and the pixel circuit shown in FIG. 5 is a modified scheme based on the pixel circuit shown in FIG. 2, FIG.
  • the illustrated pixel circuit includes not only the data writing unit 1, the voltage storage unit 2, the voltage following unit 3, and the liquid crystal capacitor Clc in the pixel circuit shown in FIG. 2, but also the first voltage compensation unit 21 and the second voltage compensation unit 22.
  • a third voltage compensation unit 9 For the specific structure of the data writing unit 1, the voltage storage unit 2, and the voltage following unit 3 in this embodiment, refer to the description in the second embodiment above, and details are not described herein again.
  • the first voltage compensation unit 21 is disposed between the second electrode of the fifth transistor T5 and the first end of the storage capacitor Cst for when the pixel circuit is in the static display mode and the fifth transistor T5 is in the off state. Preventing leakage current from being generated between the first end of the storage capacitor Cst and the first power supply terminal 4.
  • the second voltage compensation unit 22 is disposed between the second pole of the sixth transistor T6 and the second end of the storage capacitor Cst for preventing the storage capacitor when the pixel circuit is in the static display mode and the sixth transistor T6 is in the off state. A leakage current is generated between the second end of the Cst and the first power terminal 4.
  • a third voltage compensation unit 9 is disposed between the voltage storage unit 2 and the second electrode of the third transistor T3 for preventing the voltage storage unit 2 and the data line when the third transistor T3 is in an off state. A leakage current is generated between them.
  • the leakage current between the data line and the voltage storage unit 2 can be effectively avoided, and the voltage output from the voltage storage unit 2 is far from the data voltage or the adjustment voltage.
  • the first voltage compensation unit 21 includes a ninth transistor T9 and an eleventh transistor T11.
  • control electrode of the ninth transistor T9 is connected to the first control line S1
  • first electrode of the ninth transistor T9 is connected to the second electrode of the fifth transistor T5 and the second electrode of the eleventh transistor T11.
  • the second pole of the nine transistor T9 is connected to the first end of the storage capacitor Cst.
  • the control electrode of the eleventh transistor T11 is connected to the second control line S2, the first pole of the eleventh transistor T11 is connected to the third power terminal 7, and the second pole of the eleventh transistor T11 is The second pole of the fifth transistor T5 is connected.
  • the second voltage compensation unit 22 includes a tenth transistor T10 and a twelfth transistor T12.
  • the control electrode of the tenth transistor T10 is connected to the second control line S2, the first pole of the tenth transistor T10 is connected to the second pole of the sixth transistor T6 and the second pole of the twelfth transistor T12, and the tenth transistor is tenth
  • the diode is connected to the second end of the storage capacitor Cst.
  • the control electrode of the twelfth transistor T12 is connected to the first control line S1, the first electrode of the twelfth transistor T12 is connected to the third power terminal 7, the second electrode of the twelfth transistor T12 and the second of the sixth transistor T6 Extremely connected.
  • the third voltage compensation unit 9 includes a second transistor T2 and a fourth transistor T4.
  • control electrode of the second transistor T2 is connected to the third control line S3
  • first electrode of the second transistor T2 is connected to the second electrode of the fourth transistor T4 and the data writing unit 1
  • the second transistor T2 is The second pole is connected to the voltage storage unit 2 and the voltage follower unit 3.
  • the control electrode of the fourth transistor T4 is connected to the fourth control line S4, and the first electrode of the fourth transistor T4 is connected to the fourth power supply terminal 8.
  • the working process corresponding to the pixel circuit shown in FIG. 5 in the normal display mode and the static display mode will be described in detail below with reference to the accompanying drawings, wherein the first transistor T1 to the twelfth transistor T12 are assumed to be N-type transistors,
  • the first power terminal 4 provides a reference voltage Vref
  • the five power terminals 6 provide an operating voltage Vdd, and the operating voltage Vdd is greater than twice the reference voltage Vref and greater than the maximum data voltage that can be loaded on the data line.
  • FIG. 6 is a timing chart showing the operation of the pixel circuit shown in FIG. 5. As shown in FIG. 6, the operation of the pixel circuit also includes three stages from the first stage to the third stage described in the second embodiment.
  • the pixel circuit is in the normal display mode.
  • the first control line S1 outputs a high level
  • the second control line S2 outputs a low level
  • the third control line S3 outputs a high level
  • the fourth control line S4 outputs a low level.
  • the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 are turned on
  • the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on.
  • Tenth transistor T10 and the eleventh transistor T11 are turned off.
  • the data line writes the data voltage Vdata to the second end of the storage capacitor Cst through the second transistor T2, the third transistor T3, and the eighth transistor T8, and the voltages of the Q point and the M point are both Vdata.
  • the first power terminal 4 writes the reference voltage Vref to the first end of the storage capacitor Cst through the fifth transistor T5 and the ninth transistor T9, and the voltage at the point N is Vref.
  • the voltage difference between both ends of the storage capacitor Cst is Vref-Vdata.
  • the voltage at the Q point is Vdata
  • the voltage at the point P is Vdata-Vth
  • the voltage difference between both ends of the liquid crystal capacitor Clc is Vdata-Vth-Vcom.
  • the pixel circuit is in a static display mode and corresponds to a first polarity display phase.
  • the first control line S1 outputs a high level
  • the second control line S2 outputs a low level
  • the third control line S3 outputs a low level
  • the fourth control line S4 outputs a high level.
  • the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 are turned on
  • the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned on.
  • the tenth transistor T10 and the eleventh transistor T11 are turned off.
  • the sixth transistor T6 Although the sixth transistor T6 is in an off state, since the voltage at the point R is higher than the reference voltage Vref output from the first power terminal 4, there is a flow in the sixth transistor T6 from the third power terminal 7 The leakage current of the first power terminal 4 effectively avoids leakage current between the second terminal of the storage capacitor Cst and the first power terminal 4.
  • the tenth transistor T10 Although the tenth transistor T10 is in the off state, since the voltage of the R point is higher than the voltage of the second terminal of the storage capacitor Cst, there is a flow of the third power supply terminal 7 in the tenth transistor T10. The leakage current at the second end of the storage capacitor Cst, at which time the voltage at the second end of the storage capacitor Cst rises.
  • the fourth transistor T4 since the fourth transistor T4 is turned on, the voltage at point D becomes Vdd.
  • the third transistor T3 since the voltage at the point D is higher than the maximum voltage loaded in the data line, the third transistor T3 exists.
  • the leakage current flowing from the fourth power supply terminal 8 to the data line effectively avoids leakage current between the data line and the voltage storage unit 2.
  • the second transistor T2 Although the second transistor T2 is in the off state, since the voltage at the point D is higher than the voltage at the Q point, there is a leakage current flowing from the fourth power terminal 8 to the Q point in the second transistor T2. At this time, the voltage at the second end of the storage capacitor Cst rises.
  • the leakage current of the second transistor T2 and the tenth transistor T10 causes the voltage of the second terminal of the storage capacitor Cst to rise by ⁇ Vm, and after the end of the second phase, the voltage at the M point For Vdata+ ⁇ Vm, the voltage difference between both ends of the storage capacitor Cst is Vref ⁇ Vdata ⁇ Vm. Compared with the first stage, the voltage difference between the two ends of the storage capacitor Cst is reduced in the second stage.
  • the voltage at the point M is Vdata+ ⁇ Vm
  • the voltage at the Q point is Vdata+ ⁇ Vm
  • the voltage at the point P is Vdata+ ⁇ Vm ⁇ Vth
  • the voltage difference between both ends of the liquid crystal capacitor Clc is Vdata+ ⁇ Vm ⁇ Vth ⁇ Vcom.
  • the pixel circuit is in the static display mode and corresponds to the second polarity display phase.
  • the first control line S1 outputs a low level
  • the second control line S2 outputs a high level
  • the third control line S3 outputs a low level
  • the fourth control line S4 outputs a high level.
  • the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 are turned on
  • the second transistor T2, the third transistor T3, the fifth transistor T5, and the eighth transistor T8 are turned on.
  • the ninth transistor T9 and the twelfth transistor T12 are turned off.
  • the second end of the storage capacitor Cst is connected to the first power terminal 4, and the voltage of the second end of the storage capacitor Cst becomes Vref. That is, the voltage at point M becomes Vref.
  • the voltage of the first end of the storage capacitor Cst is bootstrapped, and the voltage of the first end of the storage capacitor Cst jumps. Change to 2Vref-Vdata- ⁇ Vm, that is, the voltage at the N point is 2Vref-Vdata- ⁇ Vm.
  • the fifth transistor T5 Since the fifth transistor T5 is turned off and the eleventh transistor T11 is turned on, the voltage at the point S is Vdd.
  • the fifth transistor T5 Although the fifth transistor T5 is in an off state, since the voltage at the point S is higher than the reference voltage Vref output from the first power terminal 4, there is a flow in the fifth transistor T5 from the third power terminal 7 Leakage current of the first power terminal 4, Therefore, leakage current is generated between the first end of the storage capacitor Cst and the first power terminal 4.
  • the ninth transistor T9 Although the ninth transistor T9 is in an off state, since the voltage at the point S is higher than the voltage at the first end of the storage capacitor Cst (ie, the N point voltage 2Vref-Vdata- ⁇ Vm), then at this time There is a leakage current flowing from the third power supply terminal 7 to the first end of the storage capacitor Cst in the nine-transistor T9, and the voltage at the first end of the storage capacitor Cst is raised.
  • a leakage current flowing from the fourth power supply terminal 8 to the data line exists in the third transistor T3, thereby effectively preventing leakage current from being generated between the data line and the voltage storage unit 2, and the fourth power supply terminal is present in the second transistor T2.
  • the leakage current of the second transistor T2 and the ninth transistor T9 causes the first terminal voltage of the storage capacitor Cst to rise by ⁇ Vn, and after the end of the third phase, the voltage at the N point 2Vref ⁇ Vdata ⁇ Vm+ ⁇ Vn, the voltage difference between both ends of the storage capacitor Cst is Vref ⁇ Vdata ⁇ Vm+ ⁇ Vn.
  • the voltage difference between the two ends of the storage capacitor Cst increases in the third stage.
  • the voltages output by the third power terminal 7 and the fourth power terminal 8 are equal, and the first polarity display phase is equal to the duration of the second polarity display phase, and the second voltage can be made at this time.
  • the boosting amount ⁇ Vm of the voltage of the second end of the storage capacitor Cst in the first polarity display phase and the first voltage compensating unit and the third voltage compensating unit in the second polarity display phase to the storage capacitor The amount of increase ⁇ Vn of the voltage at the first end of Cst is equal.
  • the boosting amount ⁇ Vm of the voltage of the second terminal of the storage capacitor Cst in the first polarity display phase is a small value, and the storage capacitor Cst is the first.
  • the voltage at the terminal is in the second polarity display phase
  • the lifting amount ⁇ Vn is also a small value, which does not significantly affect the data voltage or the adjustment voltage outputted by the voltage storage unit 2, that is, the display gray level corresponding to the voltage difference between the two ends of the liquid crystal capacitor Clc
  • the pixel circuit provided by the third embodiment of the present invention can not only realize polarity inversion of the voltage difference between both ends of the liquid crystal capacitor, but also realize static display for a long time.
  • the gate of the transistor specifically refers to the gate of the transistor
  • the first and second poles of the transistor refer to the source and the drain of the transistor, respectively.
  • the source of the first extreme transistor is the drain of the second transistor
  • the drain of the first transistor is the source of the first transistor.
  • FIG. 7 is a flowchart of a driving method of a pixel circuit according to a fourth embodiment of the present invention.
  • the pixel circuit is the pixel circuit provided in the first embodiment, the second embodiment, or the third embodiment.
  • the driving method of the pixel circuit includes steps 101 to 102.
  • Step 101 In the normal display mode, the data writing unit sends the data voltage on the data line to the voltage storage unit and the input end of the voltage following unit, and the voltage following unit outputs a corresponding data output voltage according to the data voltage for the liquid crystal capacitor. A corresponding liquid crystal deflection electric field is generated.
  • Step 102 In the static display mode, the voltage storage unit sends the data voltage or the adjustment voltage to the input end of the voltage follower unit, and the voltage follower unit outputs a corresponding data output voltage according to the data voltage or the adjusted voltage, so that the liquid crystal capacitor generates corresponding The liquid crystal deflects the electric field.
  • step 102 the voltage storage unit alternately transmits the data voltage and the adjustment voltage to the voltage follower unit to achieve polarity inversion for the voltage difference between the two ends of the liquid crystal capacitor.
  • step 101 and the step 102 in this embodiment refer to the corresponding content in the foregoing first to third embodiments, and details are not described herein again.
  • a fifth embodiment of the present invention provides a display panel including a plurality of pixel circuits, each of which is a pixel circuit provided by any one of the first to third embodiments described above, the display panel Can achieve static display of color pictures.

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Abstract

提供了一种像素电路及其驱动方法、和包含该像素电路的显示面板。该像素电路包括：数据写入单元（1）、电压存储单元（2）、电压跟随单元（3）和液晶电容(Clc)，其中，数据写入单元（1）用于在像素电路处于正常显示模式时，将数据线上的数据电压发送至电压存储单元（2）和电压跟随单元（3）；电压存储单（2）用于在像素电路处于正常显示模式时将数据电压进行存储，以及在像素电路处于静态显示模式时，将数据电压或调整电压发送至电压跟随单元（3）的输入端；电压跟随单元（3）用于根据电压存储单元（2）提供的数据电压或调整电压输出相应的数据输出电压，以供液晶电容(Clc)产生相应的液晶偏转电场，从而可实现显示面板对彩色画面的静态显示。

Description

像素电路及其驱动方法、显示面板 技术领域
本发明涉及显示技术领域，特别涉及像素电路及其驱动方法、显示面板。
背景技术
随着智能穿戴、移动应用等技术的发展，对超低功耗LCD显示技术的发展提出了要求。像素存储(Memory in Pixel，简称MIP)显示技术作为一种新型低功耗LCD显示技术，由于具有无需改变LCD的制备工艺、无需新型材料开发、结构简单、成本低等特点，具有广阔的发展前景。
图1为现有技术中像素驱动电路的电路示意图。如图1所示，该像素驱动电路包括：开关晶体管TFT、模拟电压存储单元(Analog Memory Uint)、存储电容Cst和液晶电容Clc，在包含该像素驱动电路的显示面板处于待机状态或显示静态画面(即静态显示模式)时，模拟电压存储单元为液晶电容Clc提供稳定的数据电压，此时不再需要通过栅极驱动对显示画面进行更新，从而降低了显示面板显示静态画面时的更新频率，如此可以降低集成电路的电力消耗，即显示面板的整体电力消耗降低。
然而，由于现有的模拟电压存储单元的电路结构较复杂，很难将其集成到像素电路中。因此，现有技术中大都使用集成的一位数字存储器作为模拟电压存储单元，该数字存储器只能存储LCD像素的黑白电压，即只能实现黑白显示，从而大大限制了MIP显示技术的应用范围。
由此可见，如何将MIP显示技术应用于彩色显示是本领域亟需解决的技术问题。
发明内容
鉴于上述技术问题，本发明的目的之一提供一种像素电路及其驱动方法、和一种包含该像素电路的显示面板，该像素电路能够对模拟数据电压进行存储，从而能够实现彩色画面的静态显示。
为实现上述目的，本发明提供了一种像素电路，包括数据写入单元、电压跟随单元、电压存储单元和液晶电容；
所述数据写入单元与所述电压存储单元连接，所述电压跟随单元的输入端与所述数据写入单元和所述电压存储单元连接，所述电压跟随单元的输出端与所述液晶电容的第一端连接，所述电压存储单元与第一电源端连接，所述液晶电容的第二端与第二电源端连接；
所述数据写入单元构造为在所述像素电路处于正常显示模式时，将数据线上的数据电压发送至所述电压存储单元和所述电压跟随单元；
所述电压存储单元构造为在所述像素电路处于正常显示模式时将所述数据电压进行存储，以及，在所述像素电路处于静态显示模式时，将所述数据电压或调整电压发送至所述电压跟随单元的输入端，所述调整电压满足：
Vdata′＝2Vref-Vdata
其中，Vdata’为所述调整电压，Vref为所述第一电源端输出的电压，Vdata为所述数据电压；
所述电压跟随单元构造为根据所述数据电压或所述调整电压输出相应的数据输出电压，以供所述液晶电容产生相应的液晶偏转电场；
所述第二电源端输出的电压满足：
Vcom＝Vref-ΔV
其中，Vcom为所述第二电源端输出的电压，ΔV为所述电压跟随单元的输入端与输出端之间的电压差。
可选地，所述电压存储单元包括存储电容、第五晶体管、第六晶体管、第七晶体管和第八晶体管；
所述第五晶体管的控制极与第一控制线连接，所述第五晶体管 的第一极与所述第一电源端连接，所述第五晶体管的第二极与所述存储电容的第一端连接；
所述第六晶体管的控制极与第二控制线连接，所述第六晶体管的第一极与所述第一电源端连接，所述第五晶体管的第二极与所述存储电容的第二端连接；
所述第七晶体管的控制极与所述第二控制线连接，所述第七晶体管的第一极与所述存储电容的第一端连接，所述第七晶体管的第二极与所述电压跟随单元的输入端和所述数据写入单元连接；
所述第八晶体管的控制极与所述第一控制线连接，所述第八晶体管的第一极与所述存储电容的第二端连接，所述第八晶体管的第二极与所述电压跟随单元的输入端和所述数据写入单元连接；
可选地，所述电压存储单元还包括第一电压补偿单元和第二电压补偿单元；
所述第一电压补偿单元设置于所述第五晶体管的第二极与所述存储电容的第一端之间，所述第二电压补偿单元设置于所述第六晶体管的第二极与所述存储电容的第二端之间；
所述第一电压补偿单元用于在所述像素电路处于静态显示模式且所述第五晶体管处于截止状态时，防止在所述存储电容的第一端与所述第一电源端之间产生漏电流；
所述第二电压补偿单元用于在所述像素电路处于静态显示模式且所述第六晶体管处于截止状态时，防止在所述存储电容的第二端与所述第一电源端之间产生漏电流。
可选地，所述第一电压补偿单元包括第九晶体管和第十一晶体管；
所述第九晶体管的控制极与所述第一控制线连接，所述第九晶体管的第一极与所述第五晶体管的第二极和所述第十一晶体管的第二极连接，所述第九晶体管的第二极与所述存储电容的第一端连接；
所述第十一晶体管的控制极与所述第二控制线连接，所述第十一晶体管的第一极与第三电源端连接，所述第十一晶体管的第二极与所述第五晶体管的第二极连接；
可选地，所述第二电压补偿单元包括第十晶体管和第十二晶体管；
所述第十晶体管的控制极与所述第二控制线连接，所述第十晶体管的第一极与所述第六晶体管的第二极和所述第十二晶体管的第二极连接，所述第十晶体管的第二极与所述存储电容的第二端连接；
所述第十二晶体管的控制极与所述第一控制线连接，所述第十二晶体管的第一极与第三电源端连接，所述第十二晶体管的第二极与所述第六晶体管的第二极连接。
可选地，所述数据写入单元包括第三晶体管；
所述第三晶体管的控制极与第三控制线连接，所述第三晶体管的第一极与数据线连接，所述第三晶体管的第二极与所述电压跟随单元的输入端和所述电压存储单元连接。
可选地，所述像素电路还包括第三电压补偿单元；
所述第三电压补偿单元设置于所述电压存储单元与所述第三晶体管的第二极之间；
所述第三电压补偿单元用于在所述第三晶体管处于截止状态时，防止在所述电压存储单元与所述数据线之间产生漏电流。
可选地，所述第三电压补偿单元包括第二晶体管和第四晶体管；
所述第二晶体管的控制极与第三控制线连接，所述第二晶体管的第一极与所述第四晶体管的第二极和所述数据写入单元连接，所述第二晶体管的第二极与所述电压存储单元和所述电压跟随单元连接；
所述第四晶体管的控制极与第四控制线连接，所述第四晶体管的第一极与第四电源端连接。
可选地，所述电压跟随单元包括第一晶体管，所述第一晶体管为共漏极放大晶体管；
所述第一晶体管的栅极与所述数据写入单元和所述电压存储单元连接，所述第一晶体管的源极与第五电源端连接，所述第一晶体管的漏极与所述液晶电容的第一端连接。
可选地，所述静态显示模式包括交替进行的第一极性显示阶段和第二极性显示阶段；
在所述第一极性显示阶段时，所述电压存储单元将所述数据电压发送至所述电压跟随单元的输入端；
在所述第二极性显示阶段时，所述电压存储单元将所述调整电压发送至所述电压跟随单元的输入端。
可选地，所述像素电路中的各晶体管均为N型晶体管。
为实现上述目的，本发明还提供了一种像素电路的驱动方法，所述像素电路为上述的任一像素电路，所述像素电路的驱动方法包括：
在正常显示模式时，所述数据写入单元将数据线上的数据电压发送至所述电压存储单元以及所述电压跟随单元的输入端，所述电压跟随单元根据所述数据电压输出相应的数据输出电压，以供所述液晶电容产生相应的液晶偏转电场；
在静态显示模式时，所述电压存储单元将所述数据电压或所述调整电压发送至所述电压跟随单元的输入端，所述电压跟随单元根据所述数据电压或所述调整电压输出相应的数据输出电压，以供所述液晶电容产生相应的液晶偏转电场。
可选地，在所述静态显示模式时，所述电压存储单元将所述数据电压和所述调整电压交替发送至所述电压跟随单元。
为实现上述目的，本发明还提供了一种显示面板，包括上述的任一像素电路。
本发明具有以下有益效果。
本发明提供了一种像素电路及其驱动方法、和包括该像素电路的显示面板，该像素电路包括数据写入单元、电压存储单元、电压跟随单元和液晶电容，其中，数据写入单元与电压存储单元和电压跟随单元连接，数据写入单元用于在像素电路处于正常显示模式时，将数据线上的数据电压发送至电压存储单元和电压跟随单元；电压存储单元与第一电源端以及电压跟随单元的输入端连接，电压存储单元用于在像素电路处于正常显示模式时将数据电压进行存储，以及在像素电路处于静态显示模式时，将数据电压或调整电压发送至电压跟随单元 的输入端；电压跟随单元的输出端与液晶电容的第一端连接，液晶电容的第二端与第二电源端连接，电压跟随单元用于根据电压存储单元提供的数据电压或调整电压输出相应的数据输出电压，以供液晶电容产生相应的液晶偏转电场。本发明的技术方案通过电压存储单元在正常显示模式时将数据线中的模拟数据电压进行存储，并在静态显示模式时输出数据电压和/或模拟电压，以供液晶电容产生相应的液晶偏转电场，进而实现了静态显示。与此同时，由于电压存储单元可存储对应各显示灰阶的数据电压，因此对于整个显示面板而言，可实现显示面板对彩色画面的静态显示。
附图说明
图1为现有技术中像素驱动电路的电路示意图。
图2为本发明的第一实施例提供的一种像素电路的电路示意图。
图3为本发明的第二实施例提供的一种像素电路的电路示意图。
图4为图3所示像素电路的工作时序图。
图5为本发明的第三实施例提供的一种像素电路的电路示意图。
图6为图5所示像素电路的工作时序图。
图7为本发明的第四实施例提供的一种像素电路的驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的像素电路及其驱动方法、显示面板进行详细描述。
第一实施例
图2为本发明的第一实施例提供的一种像素电路的电路示意图。如图2所示，该像素电路包含正常显示模式和静态显示模式两种工作模式，该像素电路包括数据写入单元1、电压存储单元2、电压跟随单元3和液晶电容Clc。
该实施例中，数据写入单元1与电压存储单元2和电压跟随单 元3连接，数据写入单元1用于在像素电路处于正常显示模式时，将数据线上的数据电压发送至电压存储单元2和电压跟随单元3。
电压存储单元2与第一电源端4和电压跟随单元3的输入端连接，电压存储单元2用于在像素电路处于正常显示模式时将数据电压进行存储，以及在像素电路处于静态显示模式时，将数据电压或调整电压发送至电压跟随单元3的输入端，其中，该调整电压为电压存储单元2基于数据电压和第一电源端4输出的电压进行调整后所输出的电压，该调整电压满足：
Vdata′＝2Vref-Vdata
其中，Vdata’为调整电压，Vref为第一电源端4输出的电压，Vdata为数据电压。
电压跟随单元3的输出端与液晶电容Clc的第一端连接，液晶电容Clc的第二端与第二电源端5连接，电压跟随单元3用于根据电压存储单元2提供的数据电压或调整电压输出相应的数据输出电压，以供液晶电容Clc产生相应的液晶偏转电场。
在本实施例中，第二电源端5输出的电压满足：
Vcom＝Vref-ΔV
其中，Vcom为第二电源端5输出的电压，ΔV为电压跟随单元3的输入端与输出端之间的电压差。
需要说明的是，本实施例中的电压跟随单元3为实现输出电压跟随输入电压变化的一种电子器件。该电压跟随单元3的电压放大倍数恒小于且接近于1，即电压跟随单元3的输出端的电压小于且接近于其输入端的电压。此外，该电压跟随单元3的输入端与输出端之间的电压差ΔV一般为一个较小的固定值。
下面将对本实施例提供的像素电路在正常显示模式和静态显示模式时对应的工作过程进行详细的描述。
当本实施例提供的像素电路处于正常显示模式时，数据线上的数据电压通过数据写入单元1写入至电压跟随单元3和电压存储单元2，即Q点电压为Vdata。与此同时，电压存储单元2对该数据电压进行存储，电压跟随单元3根据该数据电压输出相应的数据输出电 压，该数据输出电压大小等于Vdata-ΔV，即P点电压为Vdata-ΔV。此时，液晶电容Clc的两端之间的电压差(又称为液晶偏转电压)等于Vdata-ΔV-Vcom。
当本实施例提供的像素电路处于静态显示模式时，数据写入单元1停止数据写入，电压存储单元2向电压跟随单元3的输入端输出数据电压或调整电压。
当电压存储单元2向电压跟随单元3的输入端输出数据电压时，则Q点电压为Vdata，P点电压为Vdata-ΔV。此时，液晶电容Clc的两端之间的电压差Vclc_1＝Vdata-ΔV-Vcom。
当电压存储单元2向电压跟随单元3的输入端输出调整电压时，则Q点电压为Vdata’，P点电压为Vdata′-ΔV。此时，液晶电容Clc的两端之间的电压差Vclc_2＝Vdata′-ΔV-Vcom。
其中，
Vclc_1+Vclc_2＝Vdata-ΔV-Vcom+Vdata′-ΔV-Vcom
             ＝Vdata-ΔV-Vcom+2Vref-Vdata-ΔV-Vcom
             ＝2Vref-2ΔV-2Vcom
             ＝2Vref-2ΔV-2(Vref-ΔV)
             ＝0
由上式可见，Vclc_1与Vclc_2的大小相等但极性相反，两者对应于相同的显示灰阶(亮度)。因此，无论电压存储单元2向电压跟随单元3输出的是数据电压还是调整电压，此时液晶电容Clc的两端之间的电压差所对应的显示灰阶不变，像素电路可维持静态显示。此外，本实施例中对数据电压的大小没有限制，因而该电压存储单元2可存储对应于各显示灰阶的数据电压，进而能支持彩色画面的静态显示。
作为本实施例中的一种优选方案，该像素电路的静态显示模式包括交替进行的第一极性显示阶段和第二极性显示阶段。在第一极性显示阶段时，电压存储单元2将数据电压发送至电压跟随单元3的输入端。在第二极性显示阶段时，电压存储单元2将调整电压发送至电压跟随单元3的输入端。本实施例中，在静态显示模式时，通过电压存储单元2交替地将数据电压和调整电压输出至电压跟随单元3的输 入端，可实现液晶电容Clc的两端之间的电压差的极性反转，从而可有效防止静态显示过程中出现液晶疲劳的问题。
第二实施例
图3为本发明的第二实施例提供的一种像素电路的电路示意图。如图3所示，图3所示的像素电路为基于图2所示像素电路的一种具体方案。
可选地，数据写入单元1包括第三晶体管T3。第三晶体管T3的控制极与第三控制线S3连接，第三晶体管T3的第一极与数据线连接，第三晶体管T3的第二极与电压跟随单元3的输入端和电压存储单元2连接。
可选地，电压跟随单元3包括第一晶体管T1。该第一晶体管T1为共漏极放大晶体管，该第一晶体管T1的栅极与数据写入单元1和电压存储单元2连接，第一晶体管T1的源极与第五电源端6连接，第一晶体管T1的漏极与液晶电容Clc的第一端连接。此时，电压存储单元2的输入端与输出端之间的电压差ΔV等于第一晶体管T1的阈值电压Vth(Vth为定值)。
电压存储单元2包括存储电容Cst、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8。
第五晶体管T5的控制极与第一控制线S1连接，第五晶体管T5的第一极与第一电源端4连接，第五晶体管T5的第二极与存储电容Cst的第一端连接。
第六晶体管T6的控制极与第二控制线S2连接，第六晶体管T6的第一极与第一电源端4连接，第五晶体管T5的第二极与存储电容Cst的第二端连接。
第七晶体管T7的控制极与第二控制线S2连接，第七晶体管T7的第一极与存储电容Cst的第一端连接，第七晶体管T7的第二极与电压跟随单元3的输入端和数据写入单元1连接。
第八晶体管T8的控制极与第一控制线S1连接，第八晶体管T8的第一极与存储电容Cst的第二端连接，第八晶体管T8的第二极与电压跟随单元3的输入端和数据写入单元1连接。
下面将结合附图来对图3所示像素电路在正常显示模式和静态显示模式时对应的工作过程进行详细的描述。该实施例中，假定第一晶体管T1、第三晶体管T3、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8均为N型晶体管，第一电源端4提供参考电压Vref，第二电源端5提供公共电压Vcom，其中Vcom＝Vref-Vth，第五电源端6提供工作电压Vdd。
图4为图3所示像素电路的工作时序图。如图4所示，该像素电路的工作过程可包括第一阶段至第三阶段三个阶段。
第一阶段，像素电路处于正常显示模式。此时，第一控制线S1输出高电平，第二控制线S2输出低电平，第三控制线S3输出高电平。此时，第三晶体管T3、第五晶体管T5和第八晶体管T8导通，第六晶体管T6和第七晶体管T7截止。
在第一阶段中，由于第三晶体管T3导通，则数据电压可通过第三晶体管T3写入至Q点，此时Q点电压为Vdata。由于Q点电压为Vdata，即第一晶体管T1的栅极电压为Vdata，此时第一晶体管T1的漏极对应输出的数据输出电压为Vdata-Vth，即P点电压为Vdata-Vth。相应地，液晶电容Clc的两端之间电压差(即液晶电容Clc的第一端与第二端之间的电压差)Vclc＝Vdata-Vth-Vcom。
与此同时，由于第六晶体管T6截止，第八晶体管T8导通，则Q点电压被写入至存储电容Cst的第二端，此时M点电压为Vdata。与此同时，由于第五晶体管T5导通，第七晶体管T7截止，则第一电源端4通过第五晶体管T5向存储电容Cst的第一端充电，此时N点电压为Vref。相应地，存储电容Cst的两端之间的电压差(即存储电容Cst的第一端与第二端之间的电压差)为Vcst＝Vref-Vdata。
第二阶段，像素电路处于静态显示模式且对应第一极性显示阶段。此时，第一控制线S1输出高电平，第二控制线S2输出低电平，第三控制线S3输出低电平。此时，第五晶体管T5和第八晶体管T8导通，第三晶体管T3、第六晶体管T6和第七晶体管T7截止。
在第二阶段中，由于第三晶体管T3和第七晶体管T7均截止，则存储电容Cst的第二端向Q点输出电压，因为存储电容Cst的第二 端的电压为Vdata，则Q点电压会维持在Vdata，相应地，P点电压为Vdata-Vth，液晶电容Clc的两端之间的电压差Vclc_1＝Vdata-Vth-Vcom。
由上述内容可见，液晶电容Clc在第二阶段中两端之间的电压差Vclc_1与在第一阶段中两端之间的电压差Vclc两者大小相等且极性相同，因此该液晶电容Clc的两端之间的电压差所对应的显示灰阶不变。
第三阶段，像素电路处于静态显示模式且对应第二极性显示阶段。此时，第一控制线S1输出低电平，第二控制线S2输出高电平，第三控制线S3输出低电平。此时，第六晶体管T6和第七晶体管T7导通，第三晶体管T3、第五晶体管T5和第八晶体管T8截止。
在第三阶段中，由于第六晶体管T6导通，第八晶体管T8截止，则第一电源端4向存储电容Cst的第二端进行充电，存储电容Cst的第二端的电压变为Vref，即M点电压为Vref。此时，存储电容Cst为了维持其自身两端之间的电压差Vref-Vdata不变，则存储电容Cst的第一端的电压会进行自举，存储电容Cst的第一端的电压跳变至2Vref-Vdata，即N点电压为2Vref-Vdata。
此外，由于第五晶体管T5截止，第七晶体管T7导通，则存储电容Cst的第一端对Q点充电，此时Q点电压变为2Vref-Vdata(电压存储单元2输出调整电压)。由于Q点电压为2Vref-Vdata，即第一晶体管T1的栅极电压为2Vref-Vdata，此时第一晶体管T1的漏极对应输出的数据输出电压为2Vref-Vdata-Vth，即P点电压为2Vref-Vdata-Vth。相应地，液晶电容Clc的两端之间的电压差Vclc_2＝2Vref-Vdata-Vth-Vcom。
因为Vcom＝Vref-Vth，则Vref＝Vcom+Vth，此时
Vclc_2＝2Vref-Vdata-Vth-Vcom
      ＝2(Vcom+Vth)-Vdata-Vth-Vcom
      ＝Vcom+Vth-Vdata
由上述内容可见，液晶电容Clc在第三阶段中两端之间的电压差Vclc_2与在第二阶段中两端之间的电压差Vclc_1两者大小相等但极性相反，因此该液晶电容Clc的两端之间的电压差在实现极性反转 的同时，还能保证极性反转后所对应的显示灰阶不变。
在后续过程中，通过重复上述第二阶段和第三阶段，可在保证实现静态显示的前提下，同时实现液晶电容Clc的两端之间的电压差的极性反转。
需要说明的是，本实施例中第一晶体管T1、第三晶体管T3、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8均为N型晶体管的情况仅为本实施例中的一种优选方式，此时可采用同一生产工序同时制备出上述各晶体管，从而可减少生产工序，缩短生产周期。本领域技术人员应该知晓的是，通过对晶体管的类型进行变化以及对控制线的输出信号进行相应变化以实现上述各阶段的过程的技术方案均应属于本发明保护的范围。
第三实施例
本发明的第三实施例提供了一种像素电路，该像素电路为基于图2所示像素电路的一种改进方案。
在图2所示像素电路的实际工作过程中，该像素电路无法长时间维持静态显示，下面将结合实例来对该图2所示的像素电路无法长时间维持静态显示的原理进行详细说明，其中，假定数据线上的数据电压Vdata大于第一电源端4的电压Vref。
当图3所示像素电路处于第二阶段时，虽然第六晶体管T6处于截止状态，但是由于第六晶体管T6的第一极连接第一电源端4，因此在第一电源端4与存储电容Cst的第二端之间容易产生漏电流(流过第六晶体管T6的微小电流)。具体地，由于存储电容Cst的第二端在第二阶段时的电压为Vdata，即存储电容Cst的第二端的电压大于第一电源端4的电压，则存储电容Cst的第二端会通过第六晶体管T6进行放电，漏电流由存储电容Cst的第二端流向第一电源端4，此时存储电容Cst的第二端的电压会相应下降，又由于存储电容Cst的第一端的电压(等于Vref)保持不变，因此在第二阶段中存储电容Cst的两端之间的电压差会持续增大。
当图3所示像素电路处于第三阶段时，虽然第五晶体管T5处于截止状态，但是由于第五晶体管T5的第一极连接第一电源端4，因 此在第一电源端4与存储电容Cst的第一端之间容易产生漏电流(流过第五晶体管T5的微小电流)。具体地，由于存储电容Cst的第一端在第三阶段时的电压为2Vref-Vdata，且2Vref-Vdata＜Vref，即存储电容Cst的第一端的电压小于第一电源端4的电压，则第一电源端4会通过第五晶体管T5向存储电容Cst的第一端充电，漏电流由第一电源端4流向存储电容Cst的第一端，此时存储电容Cst的第一端的电压会相应上升，又由于存储电容Cst的第二端的电压(等于Vref)保持不变，因此在第三阶段中存储电容Cst的两端之间的电压差会持续增大。
由上述内容可见，当在数据电压Vdata大于第一电源端4的电压Vref时，图3所示的像素电路在进行静态显示的过程中，存储电容Cst的两端之间的电压差会随着时间的推移而不断增大，并最终导致电压存储单元2实际输出的电压远远偏离数据电压或调整电压，进而造成静态显示失败。
同理，当在数据电压Vdata小于第一电源端4的电压Vref时，则图3所示的像素电路在进行静态显示的过程中，存储电容Cst的两端之间的电压差会随着时间的推移而不断减小，并最终导致电压存储单元2实际输出的电压远远偏离数据电压或调整电压，进而造成静态显示失败。
此外，对于显示面板而言，一条数据线往往对应多个像素电路，在一帧画面中，当数据线成功将数据电压写入至某个像素电路后，该写入了数据电压的像素电路进入静态显示模式，此时该数据线会向下一个像素电路写入对应的数据电压，即，数据线中的像素电压会发生变化。对于已经进入静态显示模式的像素电路而言，由于第三晶体管T3的第一极与第二极的电压不同，因此在数据线和电压存储单元2之间会产生漏电流，进而会对Q点电压产生影响，当Q点电压远远偏离数据电压或调整电压时，则静态显示失败。
为克服上述技术问题，本发明的第三实施例提供了一种像素电路。图5为本发明的第三实施例提供的一种像素电路的电路示意图，图5所示像素电路为基于图2所示像素电路的一种改进方案，图5 所示的像素电路不但包括图2所示像素电路中的数据写入单元1、电压存储单元2、电压跟随单元3和液晶电容Clc，还包括第一电压补偿单元21、第二电压补偿单元22和第三电压补偿单元9。本实施例中的数据写入单元1、电压存储单元2和电压跟随单元3的具体结构，可参见上述第二实施例中的描述，此处不再赘述。
在图5中，第一电压补偿单元21设置于第五晶体管T5的第二极与存储电容Cst的第一端之间，用于在像素电路处于静态显示模式且第五晶体管T5处于截止状态时，防止在存储电容Cst的第一端与第一电源端4之间产生漏电流。第二电压补偿单元22设置于第六晶体管T6的第二极与存储电容Cst的第二端之间，用于在像素电路处于静态显示模式且第六晶体管T6处于截止状态时，防止在存储电容Cst的第二端与第一电源端4之间产生漏电流。
本实施例中，通过设置第一电压补偿单元21和第二电压补偿单元22，可有效地避免第一电源端4与存储电容Cst的两端之间产生漏电流而导致存储电容Cst的两端之间的电压差持续增大或持续减小的问题。
在图5中，第三电压补偿单元9设置于电压存储单元2与第三晶体管T3的第二极之间，用于在第三晶体管T3处于截止状态时，防止在电压存储单元2与数据线之间产生漏电流。
本实施例中，通过设置第三电压补偿单元9，可有效地避免数据线与电压存储单元2之间产生漏电流而导致电压存储单元2输出的电压远远偏离数据电压或调整电压的问题。
进一步可选地，第一电压补偿单元21包括第九晶体管T9和第十一晶体管T11。
该实施例中，第九晶体管T9的控制极与第一控制线S1连接，第九晶体管T9的第一极与第五晶体管T5的第二极和第十一晶体管T11的第二极连接，第九晶体管T9的第二极与存储电容Cst的第一端连接。
第十一晶体管T11的控制极与第二控制线S2连接，第十一晶体管T11的第一极与第三电源端7连接，第十一晶体管T11的第二极与 第五晶体管T5的第二极连接。
第二电压补偿单元22包括第十晶体管T10和第十二晶体管T12。
第十晶体管T10的控制极与第二控制线S2连接，第十晶体管T10的第一极与第六晶体管T6的第二极和第十二晶体管T12的第二极连接，第十晶体管T10的第二极与存储电容Cst的第二端连接。
第十二晶体管T12的控制极与第一控制线S1连接，第十二晶体管T12的第一极与第三电源端7连接，第十二晶体管T12的第二极与第六晶体管T6的第二极连接。
第三电压补偿单元9包括第二晶体管T2和第四晶体管T4。
该实施例中，第二晶体管T2的控制极与第三控制线S3连接，第二晶体管T2的第一极与第四晶体管T4的第二极和数据写入单元1连接，第二晶体管T2的第二极与电压存储单元2和电压跟随单元3连接。
第四晶体管T4的控制极与第四控制线S4连接，第四晶体管T4的第一极与第四电源端8连接。
下面将结合附图来对图5所示像素电路在正常显示模式和静态显示模式时对应的工作过程进行详细的描述，其中，假定第一晶体管T1至第十二晶体管T12均为N型晶体管，第一电源端4提供参考电压Vref，第二电源端5提供公共电压Vcom，其中Vcom＝Vref-Vth，Vth为第一晶体管T1的阈值电压，第三电源端7、第四电源端8和第五电源端6提供工作电压Vdd，工作电压Vdd大于参考电压Vref的2倍，且大于数据线上能够加载的最大数据电压。
图6为图5所示像素电路的工作时序图，如图6所示，该像素电路的工作过程同样包括上述第二实施例中描述的第一阶段至第三阶段三个阶段。
第一阶段，像素电路处于正常显示模式。此时，第一控制线S1输出高电平，第二控制线S2输出低电平，第三控制线S3输出高电平，第四控制线S4输出低电平。此时，第二晶体管T2、第三晶体管T3、第五晶体管T5、第八晶体管T8、第九晶体管T9和第十二晶体管T12导通，第四晶体管T4、第六晶体管T6、第七晶体管T7、第十晶体管 T10和第十一晶体管T11截止。
在第一阶段中，数据线通过第二晶体管T2、第三晶体管T3和第八晶体管T8将数据电压Vdata写入至存储电容Cst的第二端，此时Q点和M点的电压均为Vdata。第一电源端4通过第五晶体管T5和第九晶体管T9将参考电压Vref写入至存储电容Cst的第一端，此时N点的电压为Vref。存储电容Cst的两端之间的电压差为Vref-Vdata。
此外，由于Q点电压为Vdata，则P点电压为Vdata-Vth，液晶电容Clc的两端之间的电压差为Vdata-Vth-Vcom。
第二阶段，像素电路处于静态显示模式且对应第一极性显示阶段。此时，第一控制线S1输出高电平，第二控制线S2输出低电平，第三控制线S3输出低电平，第四控制线S4输出高电平。此时，第四晶体管T4、第五晶体管T5、第八晶体管T8、第九晶体管T9和第十二晶体管T12导通，第二晶体管T2、第三晶体管T3、第六晶体管T6、第七晶体管T7、第十晶体管T10和第十一晶体管T11截止。
在第二阶段中，由于第五晶体管T5和第九晶体管T9导通，因此在第一电源端4的作用下，存储电容Cst的第一端的电压维持在Vref，即N点电压为Vref。此外，由于第十二晶体管T12导通，则R点电压为Vdd。
对于第六晶体管T6而言，虽然第六晶体管T6处于截止状态，但是由于R点的电压高于第一电源端4输出的参考电压Vref，则第六晶体管T6中存在由第三电源端7流向第一电源端4的漏电流，从而有效避免了在存储电容Cst的第二端与第一电源端4之间产生漏电流。
对于第十晶体管T10而言，虽然第十晶体管T10处于截止状态，但是由于R点的电压高于存储电容Cst的第二端的电压，则此时第十晶体管T10中存在由第三电源端7流向存储电容Cst的第二端的漏电流，此时存储电容Cst的第二端的电压会升高。
与此同时，由于第四晶体管T4导通，则D点电压变为Vdd。对于第三晶体管T3而言，虽然第三晶体管T3处于截止状态，但是由于D点的电压高于数据线中加载的最大电压，则第三晶体管T3中存在 由第四电源端8流向数据线的漏电流，从而有效避免了在数据线与电压存储单元2之间产生漏电流。
对于第二晶体管T2而言，虽然第二晶体管T2处于截止状态，但是由于D点的电压高于Q点电压，则此时第二晶体管T2中存在由第四电源端8流向Q点的漏电流，此时存储电容Cst的第二端的电压会升高。
在本实施例中，假定在第二阶段中，通过第二晶体管T2和第十晶体管T10的漏电流使得存储电容Cst的第二端的电压升高了ΔVm，则第二阶段结束后，M点电压为Vdata+ΔVm，存储电容Cst的两端之间的电压差为Vref-Vdata-ΔVm。相较于第一阶段，存储电容Cst的两端之间的电压差在第二阶段会减小。
由于，M点电压为Vdata+ΔVm，则Q点电压为Vdata+ΔVm，P点电压为Vdata+ΔVm-Vth，液晶电容Clc的两端之间的电压差为Vdata+ΔVm-Vth-Vcom。
第三阶段，像素电路处于静态显示模式且对应第二极性显示阶段。此时，第一控制线S1输出低电平，第二控制线S2输出高电平，第三控制线S3输出低电平，第四控制线S4输出高电平。此时，第四晶体管T4、第六晶体管T6、第七晶体管T7、第十晶体管T10和第十一晶体管T11导通，第二晶体管T2、第三晶体管T3、第五晶体管T5、第八晶体管T8、第九晶体管T9和第十二晶体管T12截止。
在第三阶段中，由于第六晶体管T6和第十晶体管T10导通，则使得存储电容Cst的第二端与第一电源端4连接，此时存储电容Cst的第二端的电压变为Vref，即M点电压变为Vref。此时，存储电容Cst为了维持其自身两端之间的电压差Vref-Vdata-ΔVm不变，则存储电容Cst的第一端的电压会进行自举，存储电容Cst的第一端的电压跳变至2Vref-Vdata-ΔVm，即N点电压为2Vref-Vdata-ΔVm。
由于第五晶体管T5截止，且第十一晶体管T11导通，则S点的电压为Vdd。对于第五晶体管T5而言，虽然第五晶体管T5处于截止状态，但是由于S点的电压高于第一电源端4输出的参考电压Vref，则第五晶体管T5中存在由第三电源端7流向第一电源端4的漏电流， 从而有效避免了在存储电容Cst的第一端与第一电源端4之间产生漏电流。
对于第九晶体管T9而言，虽然第九晶体管T9处于截止状态，但是由于S点的电压高于存储电容Cst的第一端的电压(即N点电压2Vref-Vdata-ΔVm)，则此时第九晶体管T9中存在由第三电源端7流向存储电容Cst的第一端的漏电流，此时存储电容Cst的第一端的电压会升高。
此外，第三晶体管T3中存在由第四电源端8流向数据线的漏电流，从而有效避免了在数据线与电压存储单元2之间产生漏电流，第二晶体管T2中存在由第四电源端8流向Q点的漏电流，此时存储电容Cst的第一端的电压会升高。具体原理可参见上述对第二阶段的描述，此处不再赘述。
在本实施例中，假定在第三阶段中，通过第二晶体管T2和第九晶体管T9的漏电流使得存储电容Cst的第一端电压升高了ΔVn，则第三阶段结束后，N点电压为2Vref-Vdata-ΔVm+ΔVn，存储电容Cst的两端之间的电压差为Vref-Vdata-ΔVm+ΔVn。相较于第二阶段，存储电容Cst的两端之间的电压差在第三阶段会增加。
本实施例中，优选地，第三电源端7和第四电源端8输出的电压相等，且第一极性显示阶段与第二极性显示阶段的持续时间相等，此时可使得第二电压补偿单元和第三电压补偿单元在第一极性显示阶段对存储电容Cst的第二端的电压的提升量ΔVm与第一电压补偿单元和第三电压补偿单元在第二极性显示阶段对存储电容Cst的第一端的电压的提升量ΔVn相等。因此，每执行一次第一极性显示阶段和第二极性显示阶段之后，存储电容Cst的两端之间的电压差会恢复至Vref-Vdata，从而可有效地防止存储电容Cst的两端之间的电压差持续增大或持续减小的问题，进而保证了该像素电路能够长时间地进行静态显示。
需要说明的是，在实际应用中，由于漏电流为微小电流，因此存储电容Cst的第二端的电压在第一极性显示阶段时的提升量ΔVm为一个较小值，存储电容Cst的第一端的电压在第二极性显示阶段时 的提升量ΔVn也为一个较小值，其不会对电压存储单元2所输出的数据电压或调整电压产生明显影响，即液晶电容Clc的两端之间的电压差所对应的显示灰阶也不会存在明显变化。对于用户而言，该像素电路在静态显示过程中的显示灰阶基本没有发生变化。
本发明的第三实施例提供的像素电路不仅能够实现液晶电容的两端之间的电压差的极性反转，还能实现长时间的静态显示。
需要说明的是，在上述各实施例中，晶体管的控制极具体是指晶体管的栅极，晶体管的第一极和第二极分别是指晶体管的源极和漏极。当第一极为晶体管的源极时，则第二极为晶体管的漏极；当第一极为晶体管的漏极时，则第一极为晶体管的源极。
第四实施例
图7为本发明的第四实施例提供的一种像素电路的驱动方法的流程图。如图7所示，该像素电路为上述第一实施例、第二实施例或第三实施例中提供的像素电路，具体结构可参见上述第一实施例、第二实施例和第三实施例中的内容。该像素电路的驱动方法包括步骤101至102。
步骤101、在正常显示模式时，数据写入单元将数据线上的数据电压发送至电压存储单元以及电压跟随单元的输入端，电压跟随单元根据数据电压输出相应的数据输出电压，以供液晶电容产生相应的液晶偏转电场。
步骤102、在静态显示模式时，电压存储单元将数据电压或调整电压发送至电压跟随单元的输入端，电压跟随单元根据数据电压或调整电压输出相应的数据输出电压，以供液晶电容产生相应的液晶偏转电场。
可选地，在步骤102中，电压存储单元将数据电压和调整电压交替发送至电压跟随单元，以供液晶电容的两端之间的电压差实现极性反转。
对于本实施例中步骤101和步骤102的具体描述，可参见上述第一实施例至第三实施例中的相应内容，此处不再赘述。
第五实施例
本发明的第五实施例提供了一种显示面板，该显示面板包括多个像素电路，每个像素电路为上述第一实施例至第三实施例中任一个所提供的像素电路，该显示面板能够实现彩色画面的静态显示。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种像素电路，包括：数据写入单元、电压跟随单元、电压存储单元和液晶电容，其中
    所述数据写入单元与所述电压存储单元连接，所述电压跟随单元的输入端与所述数据写入单元和所述电压存储单元连接，所述电压跟随单元的输出端与所述液晶电容的第一端连接，所述电压存储单元与第一电源端连接，所述液晶电容的第二端与第二电源端连接；
    所述数据写入单元构造为在所述像素电路处于正常显示模式时，将数据线上的数据电压发送至所述电压存储单元和所述电压跟随单元；
    所述电压存储单元构造为在所述像素电路处于正常显示模式时将所述数据电压进行存储，以及在所述像素电路处于静态显示模式时，将所述数据电压或调整电压发送至所述电压跟随单元的输入端，所述调整电压满足：
    Vdata′＝2Vref-Vdata
    其中，Vdata’为所述调整电压，Vref为所述第一电源端输出的电压，Vdata为所述数据电压；
    所述电压跟随单元构造为根据所述数据电压或所述调整电压输出相应的数据输出电压，以供所述液晶电容产生相应的液晶偏转电场；
    所述第二电源端输出的电压满足：
    Vcom＝Vref-ΔV
    其中，Vcom为所述第二电源端输出的电压，ΔV为所述电压跟随单元的输入端与输出端之间的电压差。
  2. 根据权利要求1所述的像素电路，其中，所述电压存储单元包括存储电容、第五晶体管、第六晶体管、第七晶体管和第八晶体管；
    所述第五晶体管的控制极与第一控制线连接，所述第五晶体管的第一极与所述第一电源端连接，所述第五晶体管的第二极与所述存 储电容的第一端连接；
    所述第六晶体管的控制极与第二控制线连接，所述第六晶体管的第一极与所述第一电源端连接，所述第五晶体管的第二极与所述存储电容的第二端连接；
    所述第七晶体管的控制极与所述第二控制线连接，所述第七晶体管的第一极与所述存储电容的第一端连接，所述第七晶体管的第二极与所述电压跟随单元的输入端和所述数据写入单元连接；
    所述第八晶体管的控制极与所述第一控制线连接，所述第八晶体管的第一极与所述存储电容的第二端连接，所述第八晶体管的第二极与所述电压跟随单元的输入端和所述数据写入单元连接。
  3. 根据权利要求2所述像素电路，其中，所述电压存储单元还包括第一电压补偿单元和第二电压补偿单元；
    所述第一电压补偿单元设置于所述第五晶体管的第二极与所述存储电容的第一端之间，所述第二电压补偿单元设置于所述第六晶体管的第二极与所述存储电容的第二端之间；
    所述第一电压补偿单元用于在所述像素电路处于静态显示模式且所述第五晶体管处于截止状态时，防止在所述存储电容的第一端与所述第一电源端之间产生漏电流；
    所述第二电压补偿单元用于在所述像素电路处于静态显示模式且所述第六晶体管处于截止状态时，防止在所述存储电容的第二端与所述第一电源端之间产生漏电流。
  4. 根据权利要求3所述的像素电路，其中，所述第一电压补偿单元包括第九晶体管和第十一晶体管；
    所述第九晶体管的控制极与所述第一控制线连接，所述第九晶体管的第一极与所述第五晶体管的第二极和所述第十一晶体管的第二极连接，所述第九晶体管的第二极与所述存储电容的第一端连接；
    所述第十一晶体管的控制极与所述第二控制线连接，所述第十一晶体管的第一极与第三电源端连接，所述第十一晶体管的第二极与 所述第五晶体管的第二极连接。
  5. 根据权利要求3所述的像素电路，其中，所述第二电压补偿单元包括第十晶体管和第十二晶体管；
    所述第十晶体管的控制极与所述第二控制线连接，所述第十晶体管的第一极与所述第六晶体管的第二极和所述第十二晶体管的第二极连接，所述第十晶体管的第二极与所述存储电容的第二端连接；
    所述第十二晶体管的控制极与所述第一控制线连接，所述第十二晶体管的第一极与第三电源端连接，所述第十二晶体管的第二极与所述第六晶体管的第二极连接。
  6. 根据权利要求1所述的像素电路，其中，所述数据写入单元包括第三晶体管；
    所述第三晶体管的控制极与第三控制线连接，所述第三晶体管的第一极与数据线连接，所述第三晶体管的第二极与所述电压跟随单元的输入端和所述电压存储单元连接。
  7. 根据权利要求6所述的像素电路，还包括第三电压补偿单元；
    所述第三电压补偿单元设置于所述电压存储单元与所述第三晶体管的第二极之间；
    所述第三电压补偿单元用于在所述第三晶体管处于截止状态时，防止在所述电压存储单元与所述数据线之间产生漏电流。
  8. 根据权利要求7所述的像素电路，其中，所述第三电压补偿单元包括第二晶体管和第四晶体管；
    所述第二晶体管的控制极与第三控制线连接，所述第二晶体管的第一极与所述第四晶体管的第二极和所述数据写入单元连接，所述第二晶体管的第二极与所述电压存储单元和所述电压跟随单元连接；
    所述第四晶体管的控制极与第四控制线连接，所述第四晶体管的第一极与第四电源端连接。
  9. 根据权利要求1所述的像素电路，其中，所述电压跟随单元包括第一晶体管，所述第一晶体管为共漏极放大晶体管；
    所述第一晶体管的栅极与所述数据写入单元和所述电压存储单元连接，所述第一晶体管的源极与第五电源端连接，所述第一晶体管的漏极与所述液晶电容的第一端连接。
  10. 根据权利要求1所述的像素电路，其中，所述静态显示模式包括交替进行的第一极性显示阶段和第二极性显示阶段；
    在所述第一极性显示阶段时，所述电压存储单元将所述数据电压发送至所述电压跟随单元的输入端；
    在所述第二极性显示阶段时，所述电压存储单元将所述调整电压发送至所述电压跟随单元的输入端。
  11. 根据权利要求1-10中任一项所述的像素电路，其中，各晶体管均为N型晶体管。
  12. 一种像素电路的驱动方法，其中，所述像素电路为上述权利要求1-11中任一项所述的像素电路，所述像素电路的驱动方法包括：
    在正常显示模式时，所述数据写入单元将数据线上的数据电压发送至所述电压存储单元以及所述电压跟随单元的输入端，所述电压跟随单元根据所述数据电压输出相应的数据输出电压，以供所述液晶电容产生相应的液晶偏转电场；
    在静态显示模式时，所述电压存储单元将所述数据电压或所述调整电压发送至所述电压跟随单元的输入端，所述电压跟随单元根据所述数据电压或所述调整电压输出相应的数据输出电压，以供所述液晶电容产生相应的液晶偏转电场。
  13. 根据权利要求12所述的像素电路的驱动方法，其中，在所 述静态显示模式时，所述电压存储单元将所述数据电压和所述调整电压交替发送至所述电压跟随单元。
  14. 一种显示面板，包括：如上述权利要求1-11中任一项所述的像素电路。
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US10636373B2 (en) * 2017-09-20 2020-04-28 Boe Technology Group Co., Ltd. Pixel circuit, memory circuit, display panel and driving method

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