WO2017118096A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2017118096A1
WO2017118096A1 PCT/CN2016/099429 CN2016099429W WO2017118096A1 WO 2017118096 A1 WO2017118096 A1 WO 2017118096A1 CN 2016099429 W CN2016099429 W CN 2016099429W WO 2017118096 A1 WO2017118096 A1 WO 2017118096A1
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Prior art keywords
transparent electrode
insulating layer
layer
disposed
drain
Prior art date
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Ceased
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PCT/CN2016/099429
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English (en)
French (fr)
Inventor
蔡振飞
王文杰
郝静
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/532,470 priority Critical patent/US10411044B2/en
Publication of WO2017118096A1 publication Critical patent/WO2017118096A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display substrate, a display device, and a method of fabricating the display substrate.
  • the passivation layer when the passivation layer is formed, the passivation layer is located in the data line.
  • the first particles on the upper surface may cause a short circuit between the data line and the common electrode to form a poor signal transmission; the second particles falling in the pixel region may cause a short circuit between the pixel electrode and the common electrode to form a dot defect.
  • the incidence of these two kinds of defects is very high, and can not be effectively solved by means of equipment cleaning and the like.
  • the present disclosure provides a display substrate including a substrate; a data line disposed over the substrate; a first insulating layer disposed over the data line; and one or more second insulating layers disposed over the first insulating layer a first transparent electrode disposed over the one or more second insulating layers.
  • the display substrate further includes a gate electrode and a second transparent electrode disposed on the substrate, the second transparent electrode corresponding to the first transparent electrode; one or more third insulating layers disposed on the gate and Above the second transparent electrode.
  • the data lines are disposed over one or more third insulating layers.
  • the first insulating layer, the one or more second insulating layers, and the one or more third insulating layers are made of at least one of the following materials: a silicon nitride compound, a silicon oxide compound.
  • the display substrate further includes an active layer disposed over the one or more third insulating layers; a source and a drain disposed over the active layer.
  • a first via that communicates with the second transparent electrode and the drain is disposed in the first insulating layer, the one or more second insulating layers, and the one or more third insulating layers.
  • a first connection layer is disposed in the first via for electrically connecting the second transparent electrode and the drain.
  • a portion of the upper surface of the drain is exposed in the first via, and A connection layer is in contact with the side of the drain and the exposed upper surface and the side of the second transparent electrode.
  • the display substrate further includes a first transparent electrode line disposed over the substrate.
  • a second via hole is disposed at a position corresponding to the first transparent electrode line in the first insulating layer, the one or more second insulating layers, and the one or more third insulating layers.
  • the display substrate further includes a second connection layer disposed in the second via for electrically connecting the first transparent electrode line and the first transparent electrode.
  • a portion of the first tie layer, a portion of the second tie layer, and the first transparent electrode are disposed in the same layer.
  • the first transparent electrode line, the second transparent electrode, and the gate are disposed in the same layer.
  • the data lines, sources, and drains are arranged in the same layer.
  • the first transparent electrode is a common electrode and the second transparent electrode is a pixel electrode.
  • the present disclosure also proposes a display device including the above display substrate.
  • the present disclosure also provides a method of fabricating a display substrate.
  • the method includes forming a gate electrode and a second transparent electrode on a substrate; forming a third insulating layer over the gate electrode and the second transparent electrode; forming an active layer over the third insulating layer, and above the active layer Forming a source, a drain, and a data line; forming a first insulating layer over the source, the drain, and the data line; forming a second insulating layer over the first insulating layer; and forming a second over the second insulating layer A transparent electrode.
  • the above fabrication method further includes forming a first via that communicates with the second transparent electrode and the drain in the first insulating layer, the second insulating layer, and the third insulating layer before forming the first transparent electrode, and A first connection layer is formed in the first via to electrically connect the second transparent electrode and the drain.
  • the step of forming the gate and the second transparent electrode on the substrate further comprises forming a first transparent electrode line on the substrate.
  • the step of forming a first via connecting the second transparent electrode and the drain in the first insulating layer, the second insulating layer, and the third insulating layer further includes: a first insulating layer and a second insulating layer And forming a second via hole at a position corresponding to the first transparent electrode line in the third insulating layer, and forming a second connection layer in the second via hole to electrically connect the first transparent electrode line and the first transparent electrode.
  • the first via is formed by dry etching.
  • the data line and the first transparent electrode may be separated by a plurality of insulating layers, and conductive particles are present in one of the insulating layers.
  • the data line and the first transparent electrode are not turned on.
  • the second transparent electrode By disposing the second transparent electrode on the substrate such that at least three insulating layers are separated between the first transparent electrode and the second transparent electrode, and in the case where conductive particles are present in one or both of the insulating layers, The first transparent electrode and the second transparent electrode are electrically connected. Therefore, the technical solution of the present disclosure reduces the short circuit between the data line and the first transparent electrode layer, the first transparent electrode layer and the second transparent electrode layer.
  • FIG. 1 is a schematic structural view of a display substrate in the prior art
  • FIG. 2 shows a schematic structural view of a display substrate in accordance with an embodiment of the present disclosure
  • FIG. 3 illustrates a schematic flow chart of a method of fabricating a display substrate in accordance with an embodiment of the present disclosure
  • FIG. 4 through 10 schematically illustrate schematic views of various steps of a method of fabricating a display substrate in accordance with an embodiment of the present disclosure.
  • FIG. 2 illustrates a schematic diagram of a display substrate in accordance with an embodiment of the present disclosure.
  • the display substrate includes a substrate 1; a data line 2 disposed on the substrate 1; and is disposed on the data line 2 a first insulating layer 3; a second insulating layer 4 disposed over the first insulating layer 3; and a first transparent electrode 5 disposed over the second insulating layer 4.
  • the data line 2 and the first transparent electrode 5 can be separated by a plurality of insulating layers, and an insulating layer therein (for example, the first insulating layer) In the case where the conductive particles 17 are present in the layer 3), the data line 2 and the first transparent electrode 5 are also not turned on.
  • the probability of the conductive particles in the plurality of insulating layers being connected is extremely small, so that the probability of conducting the data line 2 and the first transparent electrode 5 is extremely small, thereby ensuring the data line 2 And the first transparent electrode 5 is not electrically connected by the conductive particles in the insulating layer and thus causes a short circuit.
  • the display substrate further includes a gate electrode 6 and a second transparent electrode 7 disposed on the substrate 1, the second transparent electrode 7 corresponding to the first transparent electrode 5;
  • the third insulating layer 8 over the pole 6 and the second transparent electrode 7, wherein the data line 2 is disposed above the third insulating layer 8.
  • the second transparent electrode 7 by disposing the second transparent electrode 7 on the substrate 1, at least three insulating layers are separated between the first transparent electrode 5 and the second transparent electrode 7 (for example, the pixel electrode) (in FIG.
  • the first transparent electrode 5 and the second transparent electrode 7 It will not turn on. Even if conductive particles are present in at least three insulating layers, the probability that the conductive particles are connected in at least three insulating layers is extremely small, so that the probability of the first transparent electrode 5 and the second transparent electrode 7 being turned on is extremely small, thereby ensuring the first A transparent electrode 5 and a second transparent electrode 7 are not electrically connected by conductive particles in the insulating layer to cause a short circuit.
  • the first insulating layer 3, the second insulating layer 4, and the third insulating layer 8 are made of at least one of the following materials: a silicon nitride compound, a silicon oxide compound. Silicon nitride compounds (such as silicon nitride) and silicon oxide compounds (such as silicon oxide) are commonly used as insulation materials in the prior art, and the fabrication process is relatively mature and easy to set.
  • the display substrate further includes an active layer 9 disposed over the third insulating layer 8; a source 10 and a drain 11 disposed over the active layer 9.
  • a first via hole 12 communicating the second transparent electrode 7 and the drain electrode 10 is disposed in the first insulating layer 3, the second insulating layer 4, and the third insulating layer 8, and the first via hole 12 is disposed in the first via hole 12
  • the connection layer 13 is for electrically connecting the second transparent electrode 7 and the drain electrode 11.
  • the drain 11 and the second transparent electrode 7 can be electrically connected through the first via 12 and the first connection layer 13, thereby ensuring that the data signal can be transmitted from the data line 2 when the thin film transistor is turned on.
  • the source 10 is transferred from the source 10 to the drain 11 and further to the second transparent electrode 7.
  • a portion of the upper surface of the drain electrode 11 may be exposed in the first via hole 12 such that the first connection layer 13 is in contact with the side surface of the drain electrode 11 and the exposed portion upper surface and the side surface of the second transparent electrode 7.
  • the first via 12 can be formed by dry etching. Since the dry etching has a faster etching speed for the first insulating layer 3, the second insulating layer 4, the third insulating layer 8, and the like made of a semiconductor material, the etching speed of the drain 11 made of a metal material is slow, so When the first via hole 12 is formed, the via hole formed in the first insulating layer 3 and the second insulating layer 4 may be made larger, and the third insulating layer 8 is formed to have a smaller via hole due to the blocking of the drain electrode 11. Thereby, a portion of the upper surface of the drain electrode 11 is exposed in the formed first via hole 12.
  • the side area of the drain is generally small, it is difficult to ensure good electrical connection between the first connection layer and the drain only by contact with the side faces of the drain.
  • the first connection layer 13 and the upper surface of the drain 11 have a certain contact area, thereby ensuring that the second transparent electrode 7 and the drain 11 have a good electrical connection relationship, thereby ensuring that the data signal can be transmitted well to The second transparent electrode 7.
  • the display substrate further includes a first transparent electrode line 14 disposed over the substrate 1.
  • a second via hole 15 is provided at a position corresponding to the first transparent electrode line 14 in the first insulating layer 3, the second insulating layer 4, and the third insulating layer 8.
  • the second connection layer 16 is disposed in the second via 15 for electrically connecting the first transparent electrode line 14 and the first transparent electrode 5.
  • the signal in the first transparent electrode line 14 can be transmitted to the first transparent electrode 5 through the second via 15 and the second connection layer 16.
  • the portion of the first connection layer 13, the portion of the second connection layer 16, and the first transparent electrode 5 may be disposed in the same layer, thereby simplifying the fabrication process.
  • the first transparent electrode line 14, the second transparent electrode 7, and the gate electrode 6 may be disposed in the same layer, thereby simplifying the fabrication process.
  • the data line 2, the source 10, and the drain 11 can be disposed in the same layer, thereby simplifying the fabrication process.
  • the first transparent electrode 5 is a common electrode and the second transparent electrode 7 is a pixel electrode.
  • the present disclosure also proposes a display device including the above display substrate.
  • the display device in this embodiment may be: electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, etc. Functional product or part.
  • the present disclosure also proposes a method of fabricating a display substrate. As shown in FIG. 3, the manufacturing method of the display substrate includes the following steps:
  • step S1 a gate electrode 6 and a second transparent electrode 7 are formed on the substrate 1, as shown in FIG. 4;
  • step S2 a third insulating layer 8 is formed over the gate 11 and the second transparent electrode 7, as shown in FIG. 5;
  • step S3 an active layer 9 is formed over the third insulating layer 8, and a source 10, a drain 11 and a data line 2 are formed over the active layer 9, as shown in FIG. 6;
  • step S4 a first insulating layer 3 is formed over the source 10, the drain 11 and the data line 2, as shown in FIG. 7;
  • step S5 a second insulating layer 4 is formed over the first insulating layer 3, as shown in FIG. 8;
  • step S8 a first transparent electrode 5 is formed over the second insulating layer 4 as shown in FIG.
  • the method for manufacturing the display substrate may further include: before step S8:
  • step S6 a first via 12 communicating with the second transparent electrode 7 and the drain 11 is formed in the first insulating layer 3, the second insulating layer 4, and the third insulating layer 8, as shown in FIG.
  • step S7 a first connection layer 13 is formed in the first via hole 12 to electrically connect the second transparent electrode 7 and the drain electrode 11, as shown in FIG.
  • step S1 further includes forming a first transparent electrode line 14 on the substrate 1.
  • step S6 may further include forming a second via 15 at a position corresponding to the first transparent electrode line 14 in the first insulating layer 3, the second insulating layer 4, and the third insulating layer 8, as shown in FIG. 9 is shown.
  • step S7 may further include forming a second connection layer 16 in the second via hole 12 to electrically connect the first transparent electrode line 14 and the first transparent electrode 5, as shown in FIG.
  • the forming process employed in the above process may include, for example, a deposition process such as deposition, sputtering, and the like, and a patterning process such as etching.
  • the technical solutions of the present disclosure have been described in detail above with reference to the accompanying drawings.
  • the conductive particles therein may cause short-circuiting of the conductive structures on both sides of the insulating layer.
  • the technical solution of the present disclosure by providing the first insulating layer and the one or more second insulating layers, the data line and the first transparent electrode may be separated by a plurality of insulating layers, and conductive layers are present in one of the insulating layers. In the case of particles, the data line and the first transparent electrode are not turned on.
  • the second transparent electrode By disposing the second transparent electrode on the substrate, the first transparent electrode and the second transparent electrode are separated by at least three insulating layers, and one or two insulating layers are stored therein. In the case of conductive particles, the first transparent electrode and the second transparent electrode are not turned on. Therefore, the technical solution of the present disclosure reduces the short circuit between the data line and the first transparent electrode layer, the first transparent electrode layer and the second transparent electrode layer.
  • the second insulating layer and one layer of the third insulating layer are schematically illustrated in the drawings, those skilled in the art may provide a plurality of second insulating layers and according to the teachings of the present disclosure. / or a multilayered third insulating layer.
  • the material and thickness of the plurality of second insulating layers may be the same or different, and the materials and thicknesses of the plurality of third insulating layers may be the same or different.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种显示基板，包括：基底（1）；数据线（2），设置在基底（1）之上；第一绝缘层（3），设置在数据线（2）之上；第二绝缘层（4），设置在第一绝缘层（3）之上；第一透明电极（5），设置在第二绝缘层（4）之上。通过第二绝缘层，减少了数据线与第一透明电极层、第一透明电极层与第二透明电极层之间的短路情况。还涉及显示基板的制作方法和显示装置。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示基板、一种显示装置以及显示基板的制作方法。
背景技术
在目前的TFT-LCD生产线生产过程中，由于设备腔室的空间较大，因此其中可能存在着较多的颗粒等异物，这种颗粒等异物容易随着反应气体一起沉积到基板上。
尤其在ADS(Advanced Super Dimension Switch高级超维场)或HADS(高开口率ADS)型TFT-LCD的生产工艺中，如图1所示，在形成钝化层时，钝化层中位于数据线上的第一颗粒可能造成数据线与公共电极短路，形成信号传输不良；落在像素区域的第二颗粒可能导致像素电极和公共电极的短路，形成点不良。目前这两种不良的发生率很高，并且通过设备清洁等手段均无法有效解决。
发明内容
本公开提出了一种显示基板，包括基底；数据线，设置在基底之上；第一绝缘层，设置在数据线之上；一个或多个第二绝缘层，设置在第一绝缘层之上；第一透明电极，设置在一个或多个第二绝缘层之上。
在一些实施例中，显示基板还包括栅极和第二透明电极，设置在基底之上，第二透明电极与第一透明电极相对应；一个或多个第三绝缘层，设置在栅极和第二透明电极之上。数据线设置在一个或多个第三绝缘层之上。
在一些实施例中，第一绝缘层、一个或多个第二绝缘层和一个或多个第三绝缘层由以下至少一种材料制成：硅氮化合物、硅氧化合物。
在一些实施例中，显示基板还包括有源层，设置在一个或多个第三绝缘层之上；源极和漏极，设置在有源层之上。在第一绝缘层、一个或多个第二绝缘层和一个或多个第三绝缘层中设置有连通第二透明电极和漏极的第一过孔。在第一过孔中设置有第一连接层，用于将第二透明电极和漏极电连接。
在一些实施例中，在第一过孔中露出漏极的部分上表面，并且第 一连接层与漏极的侧面和露出的部分上表面以及第二透明电极的侧面相接触。
在一些实施例中，显示基板还包括第一透明电极线，设置在基底之上。在第一绝缘层、一个或多个第二绝缘层和一个或多个第三绝缘层中与第一透明电极线对应的位置设置有第二过孔。显示基板还包括第二连接层，设置在第二过孔中，用于将第一透明电极线和第一透明电极电连接。
在一些实施例中，第一连接层的部分、第二连接层的部分和第一透明电极同层设置。
在一些实施例中，第一透明电极线、第二透明电极和栅极同层设置。
在一些实施例中，数据线、源极和漏极同层设置。
在一些实施例中，第一透明电极为公共电极，第二透明电极为像素电极。
本公开还提出了一种显示装置，包括上述显示基板。
本公开还提供了一种显示基板的制作方法。该方法包括在基底上形成栅极和第二透明电极；在栅极和第二透明电极之上形成第三绝缘层；在第三绝缘层之上形成有源层，并且在有源层之上形成源极、漏极和数据线；在源极、漏极和数据线之上形成第一绝缘层；在第一绝缘层之上形成第二绝缘层；以及在第二绝缘层之上形成第一透明电极。
在一些实施例中，上述制作方法还在形成第一透明电极之前包括在第一绝缘层、第二绝缘层和第三绝缘层中形成连通第二透明电极和漏极的第一过孔，并且在第一过孔中形成第一连接层，以将第二透明电极和漏极电连接。
在一些实施例中，在基底上形成栅极和第二透明电极的步骤还包括在基底上形成第一透明电极线。
在一些实施例中，在第一绝缘层、第二绝缘层和第三绝缘层中形成连通第二透明电极和漏极的第一过孔的步骤还包括在第一绝缘层、第二绝缘层和第三绝缘层中与第一透明电极线对应的位置形成第二过孔，并且在第二过孔中形成第二连接层，以将第一透明电极线和第一透明电极电连接。
在一些实施例中，第一过孔通过干法蚀刻形成。
根据上述技术方案，通过设置第一绝缘层和一个或多个第二绝缘层，可以使得数据线和第一透明电极之间相隔多层绝缘层，在其中的一层绝缘层中存在导电颗粒的情况下，不会将数据线和第一透明电极导通。通过将第二透明电极设置在基底上，使得第一透明电极与第二透明电极之间至少相隔三层绝缘层，在其中的一层或两层绝缘层中存在导电颗粒的情况下，不会将第一透明电极与第二透明电极导通。因此，本公开的技术方案减少了数据线与第一透明电极层、第一透明电极层与第二透明电极层之间的短路情况。
附图说明
通过参考附图会更加清楚的理解本公开的特征和优点，附图是示意性的而不应理解为对本公开进行任何限制，在附图中：
图1示出了现有技术中显示基板的结构示意图；
图2示出了根据本公开的实施例的显示基板的结构示意图；
图3示出了根据本公开的实施例的显示基板制作方法的示意流程图；
图4至图10示意性地示出了根据本公开的实施例的显示基板制作方法的各步骤的示意图。
附图标号说明：
1-基底；2-数据线；3-第一绝缘层；4-第二绝缘层；5-第一透明电极；6-栅极；7-第二透明电极；8-第三绝缘层；9-有源层；10-源极；11-漏极；12-第一过孔；13-第一连接层；14-第一透明电极线；15-第二过孔；16-第二连接层；17-导电颗粒。
具体实施方式
为了能够更清楚地理解本公开的上述目的、特征和优点，下面结合附图和具体实施方式对本公开进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本公开，但是，本公开还可以采用其他不同于在此描述的其他方式来实施，因此，本公开的保护范围并不受下面公开的具体实施例的限制。
图2图示了根据本公开的实施例的显示基板的示意图。如图2所示，显示基板包括基底1；设置在基底1之上的数据线2；设置在数据线2之 上的第一绝缘层3；设置在第一绝缘层3之上的第二绝缘层4；以及设置在第二绝缘层4之上的第一透明电极5。通过设置第一绝缘层3和第二绝缘层4，可以使得数据线2和第一透明电极5(例如公共电极)之间相隔多层绝缘层，在其中的一层绝缘层(例如第一绝缘层3)中存在导电颗粒17的情况下，数据线2和第一透明电极5也不会被导通。即使在多层绝缘层中都存在导电颗粒，多层绝缘层中的导电颗粒相连的概率也极小，因此将数据线2和第一透明电极5导通的概率极小，因而保证数据线2和第一透明电极5不会因绝缘层中的导电颗粒而电连通并且进而造成短路。
在一些实施例中，如图2所示，显示基板还包括设置在基底1之上的栅极6和第二透明电极7，第二透明电极7与第一透明电极5相对应；设置在栅极6和第二透明电极7之上的第三绝缘层8，其中数据线2设置在第三绝缘层8之上。在这样的实施例中，通过将第二透明电极7设置在基底1上，使得第一透明电极5与第二透明电极7(例如像素电极)之间至少相隔三层绝缘层(在图2中分别为第一绝缘层3、第二绝缘层4和第三绝缘层8)，在其中的一层或两层绝缘层中存在导电颗粒的情况下，第一透明电极5与第二透明电极7也不会导通。即使在至少三层绝缘层中都存在导电颗粒，至少三层绝缘层中导电颗粒相连的概率也极小，所以第一透明电极5与第二透明电极7导通的概率极小，因而保证第一透明电极5和第二透明电极7不会因绝缘层中的导电颗粒而电连通进而造成短路。
第一绝缘层3、第二绝缘层4和第三绝缘层8由以下至少一种材料制成：硅氮化合物、硅氧化合物。硅氮化合物(例如氮化硅)和硅氧化合物(例如氧化硅)均为现有技术中常用的绝缘层材料，制作工艺较为成熟，易于设置。
在一些实施例中，如图2所示，显示基板还包括设置在第三绝缘层8之上的有源层9；设置在有源层9之上的源极10和漏极11。在第一绝缘层3、第二绝缘层4和第三绝缘层8中设置有连通第二透明电极7和漏极10的第一过孔12，并且在第一过孔12中设置有第一连接层13，用于将第二透明电极7和漏极11电连接。
通过第一过孔12和第一连接层13可以将漏极11和第二透明电极7电连接，从而保证薄膜晶体管在导通时，数据信号能够从数据线2传输 至源极10，并从源极10传输至漏极11，进而传输至第二透明电极7。
在第一过孔12中可以露出漏极11的部分上表面，使得第一连接层13与漏极11的侧面和露出的部分上表面以及第二透明电极7的侧面相接触。
第一过孔12可以通过干法蚀刻形成。由于干法蚀刻对于半导体材料制成的第一绝缘层3、第二绝缘层4和第三绝缘层8等的蚀刻速度较快，对于金属材料制成的漏极11的蚀刻速度较慢，因此在形成第一过孔12时，可以使得在第一绝缘层3和第二绝缘层4形成的过孔较大，而第三绝缘层8由于漏极11的遮挡，因此形成的过孔较小，从而在形成的第一过孔12中露出漏极11的部分上表面。
由于漏极的侧面积通常较小，因此仅与漏极的侧面相接触难以保证第一连接层与漏极之间的良好的电连接。本实施例可以使得第一连接层13与漏极11的上表面存在一定的接触面积，因而保证第二透明电极7和漏极11具有良好的电连接关系，从而保证数据信号能够良好地传输至第二透明电极7。
在一些实施例中，如图2所示，显示基板还包括设置在基底1之上的第一透明电极线14。在第一绝缘层3、第二绝缘层4和第三绝缘层8中与第一透明电极线14对应的位置设置有第二过孔15。第二连接层16设置在第二过孔15中，用于将第一透明电极线14和第一透明电极5电连接。
通过第二过孔15和第二连接层16可以保证第一透明电极线14中的信号能够传输至第一透明电极5。
如图2所示，第一连接层13的部分、第二连接层16的部分和第一透明电极5可以同层设置，从而简化制作工艺。
第一透明电极线14、第二透明电极7和栅极6可以同层设置，从而简化制作工艺。
另外，数据线2、源极10和漏极11可以同层设置，从而简化制作工艺。
在一些实施例中，第一透明电极5为公共电极，并且第二透明电极7为像素电极。
本公开还提出了一种显示装置，包括上述显示基板。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示 功能的产品或部件。
本公开还提出了一种显示基板的制作方法。如图3所示，显示基板的制作方法包括以下步骤：
在步骤S1中，在基底1上形成栅极6和第二透明电极7，如图4所示；
在步骤S2中，在栅极11和第二透明电极7之上形成第三绝缘层8，如图5所示；
在步骤S3中，在第三绝缘层8之上形成有源层9，并且在有源层9之上形成源极10、漏极11和数据线2，如图6所示；
在步骤S4中，在源极10、漏极11和数据线2之上形成第一绝缘层3，如图7所示；
在步骤S5中，在第一绝缘层3之上形成第二绝缘层4，如图8所示；
在步骤S8中，在第二绝缘层4之上形成第一透明电极5，如图10所示。
可选地，显示基板的制作方法还可以在步骤S8之前包括：
在步骤S6中，在第一绝缘层3、第二绝缘层4和第三绝缘层8中形成连通第二透明电极7和漏极11的第一过孔12，如图9所示；
在步骤S7中，在第一过孔12中形成第一连接层13，以将第二透明电极7和漏极11电连接，如图10所示。
可选地，步骤S1还包括在基底1上形成第一透明电极线14。
在这样的实施例中，步骤S6还可以包括在第一绝缘层3、第二绝缘层4和第三绝缘层8中与第一透明电极线14对应的位置形成第二过孔15，如图9所示。并且步骤S7还可以包括在第二过孔12中形成第二连接层16，以将第一透明电极线14和第一透明电极5电连接，如图10所示。
在上述流程所采用的形成工艺例如可包括：沉积、溅射等成膜工艺和刻蚀等构图工艺。
以上结合附图详细说明了本公开的技术方案。在现有技术中，在形成绝缘层时，其中的导电颗粒可能导致绝缘层两侧的导电结构短路。根据本公开的技术方案，通过设置第一绝缘层和一个或多个第二绝缘层，可以使得数据线和第一透明电极之间相隔多层绝缘层，在其中的一层绝缘层中存在导电颗粒的情况下，不会将数据线和第一透明电极导通。通过将第二透明电极设置在基底上，使得第一透明电极与第二透明电极之间至少相隔三层绝缘层，在其中的一层或两层绝缘层中存 在导电颗粒的情况下，不会将第一透明电极与第二透明电极导通。因此，本公开的技术方案减少了数据线与第一透明电极层、第一透明电极层与第二透明电极层之间的短路情况。
应当指出的是，尽管在附图中仅示意性地图示了一层第二绝缘层和一层第三绝缘层，但是本领域技术人员可以根据本公开的教导而设置多层第二绝缘层和/或多层第三绝缘层。多层第二绝缘层的材料和厚度等可以相同或不同，并且多层第三绝缘层的材料和厚度也可以相同或不同。当显示基板包括多层第二绝缘层或多层第三绝缘层时，数据线与第一透明电极层、第一透明电极层与第二透明电极层之间的短路情况可以进一步减少。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本公开中，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种显示基板，包括：
    基底；
    数据线，设置在所述基底之上；
    第一绝缘层，设置在所述数据线之上；
    一个或多个第二绝缘层，设置在所述第一绝缘层之上；
    第一透明电极，设置在所述一个或多个第二绝缘层之上。
  2. 根据权利要求1所述的显示基板，还包括：
    栅极和第二透明电极，设置在所述基底之上，所述第二透明电极与所述第一透明电极相对应；
    一个或多个第三绝缘层，设置在所述栅极和第二透明电极之上，
    其中，所述数据线设置在所述一个或多个第三绝缘层之上。
  3. 根据权利要求2所述的显示基板，其中所述第一绝缘层、一个或多个第二绝缘层和一个或多个第三绝缘层由以下至少一种材料制成：硅氮化合物、硅氧化合物。
  4. 根据权利要求2或3所述的显示基板，还包括：
    有源层，设置在所述一个或多个第三绝缘层之上；
    源极和漏极，设置在所述有源层之上；
    其中，在所述第一绝缘层、一个或多个第二绝缘层和一个或多个第三绝缘层中设置有连通所述第二透明电极和所述漏极的第一过孔，
    在所述第一过孔中设置有第一连接层，用于将所述第二透明电极和所述漏极电连接。
  5. 根据权利要求4所述的显示基板，其中在所述第一过孔中露出漏极的部分上表面，
    所述第一连接层与所述漏极的侧面和露出的部分上表面以及所述第二透明电极的侧面相接触。
  6. 根据权利要求4所述的显示基板，还包括：
    第一透明电极线，设置在所述基底之上，
    其中，在所述第一绝缘层、一个或多个第二绝缘层和一个或多个第三绝缘层中与所述第一透明电极线对应的位置设置有第二过孔；
    第二连接层，设置在所述第二过孔中，用于将所述第一透明电极 线和所述第一透明电极电连接。
  7. 根据权利要求6所述的显示基板，其中所述第一连接层的部分、第二连接层的部分和所述第一透明电极同层设置。
  8. 根据权利要求6所述的显示基板，其中所述第一透明电极线、所述第二透明电极和所述栅极同层设置。
  9. 根据权利要求4所述的显示基板，其中所述数据线、源极和漏极同层设置。
  10. 根据权利要求2至9中任一项所述的显示基板，其中所述第一透明电极为公共电极，所述第二透明电极为像素电极。
  11. 一种显示装置，包括权利要求1至10中任一项所述的显示基板。
  12. 一种显示基板的制作方法，包括：
    在基底上形成栅极和第二透明电极；
    在栅极和第二透明电极之上形成第三绝缘层；
    在第三绝缘层之上形成有源层，并且在有源层之上形成源极、漏极和数据线；
    在源极、漏极和数据线之上形成第一绝缘层；
    在第一绝缘层之上形成第二绝缘层；以及
    在第二绝缘层之上形成第一透明电极。
  13. 根据权利要求12所述的制作方法，还包括在形成第一透明电极之前在第一绝缘层、第二绝缘层和第三绝缘层中形成连通第二透明电极和漏极的第一过孔，并且在第一过孔中形成第一连接层，以将第二透明电极和漏极电连接。
  14. 根据权利要求13所述的制作方法，其中在基底上形成栅极和第二透明电极的步骤还包括在基底上形成第一透明电极线。
  15. 根据权利要求14所述的制作方法，其中在第一绝缘层、第二绝缘层和第三绝缘层中形成连通第二透明电极和漏极的第一过孔，并且在第一过孔中形成第一连接层，以将第二透明电极和漏极电连接的步骤还包括在第一绝缘层、第二绝缘层和第三绝缘层中与第一透明电极线对应的位置形成第二过孔，并且在第二过孔中形成第二连接层，以将第一透明电极线和第一透明电极电连接。
  16. 根据权利要求13所述的制作方法，其中所述第一过孔通过干法蚀刻形成。
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