WO2017117986A1 - 电压转换电路、电压转换方法、栅极驱动电路、显示面板及显示装置 - Google Patents

电压转换电路、电压转换方法、栅极驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2017117986A1
WO2017117986A1 PCT/CN2016/092202 CN2016092202W WO2017117986A1 WO 2017117986 A1 WO2017117986 A1 WO 2017117986A1 CN 2016092202 W CN2016092202 W CN 2016092202W WO 2017117986 A1 WO2017117986 A1 WO 2017117986A1
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Prior art keywords
circuit
switching transistor
signal
voltage
control
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PCT/CN2016/092202
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English (en)
French (fr)
Inventor
苏国火
孙志华
汪建明
张志豪
张旭
张银龙
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/518,362 priority Critical patent/US20180218687A1/en
Publication of WO2017117986A1 publication Critical patent/WO2017117986A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a voltage conversion circuit, a voltage conversion method, a gate driving circuit, a display panel, and a display device.
  • LED Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • PDP Plasma Display Panel
  • LCD Liquid Crystal Display
  • a gate driving circuit loads a gate scan signal to each gate line in the display panel, and the data driving circuit loads a data signal to each data line in the display panel.
  • the voltage conversion circuit converts the input small-amplitude voltage signal into a voltage signal that can be used to drive a large value of the pixel.
  • the voltage signal input by the voltage conversion circuit is the operating voltage VDD (typically 3.3V) and the working ground GND (0V).
  • the converted voltage signal is a high voltage signal VGH (about 30V) and a low voltage signal VGL ( About -8V).
  • At least two-stage conversion circuit is required to realize voltage conversion.
  • a two-stage conversion circuit is used to implement voltage conversion, and the first-stage conversion circuit only raises VDD to VGH.
  • the second-stage conversion circuit only reduces GND to VGL, and there are many circuit components, and the circuit structure is complicated.
  • the embodiments of the present invention provide a voltage conversion circuit, a voltage conversion method, a gate driving circuit, a display panel, and a display device, wherein the structure of the voltage conversion circuit is optimized.
  • an embodiment of the present invention provides a voltage conversion circuit including: a control sub-circuit and an output sub-circuit, wherein an input end of the control sub-circuit is connected to a signal input end of the voltage conversion circuit, and the output sub- An output of the circuit is coupled to a signal output of the voltage conversion circuit, the control sub-circuit being configured to output a first conversion control signal to the output sub-circuit when the input thereof receives the first voltage signal, and a second conversion control signal is output to the output sub-circuit when the input terminal receives the second voltage signal; and the output sub-circuit is configured to be from the control The sub-circuit outputs a third voltage signal upon receiving the first conversion control signal, and outputs a fourth voltage signal upon receiving the second conversion control signal from the control sub-circuit.
  • the control sub-circuit includes: a first control sub-circuit and a second control sub-circuit, the first control sub-circuit being configured to receive the first voltage signal at an input thereof
  • the second control sub-circuit outputs a first control signal, and outputs a second control signal to the second control sub-circuit when the input terminal receives the second voltage signal
  • the second control sub-circuit is configured Outputting the first conversion control signal to the output sub-circuit when the first control signal is received at an input thereof, and outputting to the output sub-circuit when the second control signal is received at an input thereof The second conversion control signal.
  • an output end of the first control sub-circuit is connected to a control end of the second control sub-circuit; a first input end of the second control sub-circuit is configured to input a first reference voltage signal a first reference voltage terminal connected to the second reference voltage terminal for inputting a second reference voltage signal, the first output terminal being connected to the first control terminal of the output sub-circuit, the second output terminal Connected to a third reference voltage terminal for inputting a third voltage signal and a first input terminal of the output sub-circuit, respectively, the third output terminal is connected to the second control terminal of the output sub-circuit, and the fourth output terminal is respectively And connected to a fourth reference voltage terminal for inputting the fourth voltage signal and a second input terminal of the output sub-circuit.
  • the first control sub-circuit comprises an inverter; an input of the inverter is connected to the signal input, and an output is connected to a control end of the second control sub-circuit.
  • the second control sub-circuit includes: a first switching transistor, a second switching transistor, a first resistor and a second resistor; wherein a gate of the first switching transistor and the second switch a gate of the transistor is connected to an output of the inverter, a source of the first switching transistor is connected to a first reference voltage terminal for inputting a first reference voltage signal, and a drain of the first switching transistor And respectively connected to the first end of the first resistor and the first control end of the output sub-circuit; the second end of the first resistor and the third reference voltage end for inputting the third voltage signal respectively a first input end of the output sub-circuit is connected; a source of the second switching transistor is connected to a second reference voltage terminal for inputting a second reference voltage signal, and a drain of the second switching transistor is respectively associated with the a first end of the second resistor is coupled to the second control terminal of the output subcircuit; a second end of the second resistor is coupled to a fourth reference voltage terminal for inputting
  • the output sub-circuit comprises: a third switching transistor and a fourth switch a transistor; wherein a gate of the third switching transistor is connected to a drain of the first switching transistor, and a source of the third switching transistor is connected to a third reference voltage terminal for inputting a third voltage signal, a gate and a source of the third switching transistor are respectively connected to a first end and a second end of the first resistor, a drain of the third switching transistor and a drain of the fourth switching transistor a signal output terminal is connected; a gate of the fourth switching transistor is connected to a drain of the second switching transistor, a source of the fourth switching transistor and a fourth reference voltage terminal for inputting a fourth voltage signal Connected, the gate and the source of the fourth switching transistor are respectively connected to the first end and the second end of the second resistor.
  • the first input of the control subcircuit is connected to a first reference voltage terminal for inputting a first reference voltage signal
  • the second input is coupled to a second reference for inputting a second reference voltage signal
  • the voltage terminals are connected, the first output terminal is connected to the first control terminal of the output sub-circuit, and the second output terminal is respectively connected to the third reference voltage terminal for inputting the third voltage signal and the first input of the output sub-circuit Connected to the terminal, the third output terminal is connected to the second control terminal of the output sub-circuit, and the fourth output terminal is respectively connected with a fourth reference voltage terminal for inputting the fourth voltage signal and a second input terminal of the output sub-circuit Connected.
  • the control sub-circuit includes: a first switching transistor, a second switching transistor, a first resistor and a second resistor; wherein a gate of the first switching transistor and a second switching transistor a gate is connected to an input end of the control sub-circuit, a source of the first switching transistor is connected to a first reference voltage terminal for inputting a first reference voltage signal, and a drain of the first switching transistor is respectively a first end of the first resistor is coupled to a first control terminal of the output subcircuit; a second end of the first resistor is coupled to a third reference voltage terminal for inputting a third voltage signal and the output a first input end of the sub-circuit is connected; a source of the second switching transistor is connected to a second reference voltage terminal for inputting a second reference voltage signal, and a drain of the second switching transistor is respectively associated with the second a first end of the resistor is coupled to the second control terminal of the output subcircuit; a second end of the second resistor is coupled to
  • the output sub-circuit includes: a third switching transistor and a fourth switching transistor; wherein a gate of the third switching transistor is connected to a drain of the second switching transistor, the third a source of the switching transistor is connected to a third reference voltage terminal for inputting a third voltage signal, and a gate and a source of the third switching transistor are respectively connected to the first end and the second end of the second resistor, a drain of the third switching transistor and a drain of the fourth switching transistor and the a signal output terminal is connected; a gate of the fourth switching transistor is connected to a drain of the first switching transistor, and a source of the fourth switching transistor is connected to a fourth reference voltage terminal for inputting a fourth voltage signal The gate and the source of the fourth switching transistor are respectively connected to the first end and the second end of the first resistor.
  • a voltage value of the third voltage signal is greater than a voltage value of the first voltage signal; a voltage value of the first voltage signal is greater than a voltage value of the second voltage signal; The voltage value of the voltage signal is greater than the voltage value of the fourth voltage signal.
  • a voltage value of the first reference voltage signal is less than or equal to a voltage value of the first voltage signal; and the second reference voltage signal is The voltage value is greater than or equal to the voltage value of the second voltage signal and less than the voltage value of the first reference voltage signal.
  • the first switching transistor and the third switching transistor are P-type transistors; the second switching transistor and the first The four switching transistor is an N-type transistor.
  • the embodiment of the present invention further provides a voltage conversion method, including: when a first voltage signal is input to a signal input end of the voltage conversion circuit, the control sub-circuit outputs a first conversion control signal to the output sub-circuit, The output sub-circuit outputs a third voltage signal under control of the first conversion control signal; and when the second voltage signal is received at a signal input end of the voltage conversion circuit, the control sub-circuit is output to the output The sub-circuit outputs a second conversion control signal, and the output sub-circuit outputs a fourth voltage signal under the control of the second conversion control signal.
  • a voltage value of the third voltage signal is greater than a voltage value of the first voltage signal; a voltage of the first voltage signal The value is greater than the voltage value of the second voltage signal; the voltage value of the second voltage signal is greater than the voltage value of the fourth voltage signal.
  • the embodiment of the invention further provides a gate driving circuit, comprising: the voltage conversion circuit provided by the embodiment of the invention.
  • the embodiment of the invention further provides a display panel, comprising: the above-mentioned gate driving circuit provided by the embodiment of the invention.
  • the embodiment of the invention further provides a display device, comprising: the display panel provided by the embodiment of the invention.
  • the first control sub-circuit outputs a first control signal to the second control sub-circuit when the first voltage signal is input, and the second control sub-circuit outputs the output to the output sub-circuit under the control of the first control signal.
  • the output sub-circuit outputs a first voltage signal under the control of the third control signal;
  • the first control sub-circuit outputs a second control to the second control sub-circuit when the second voltage signal is input a signal, the second control sub-circuit outputs a fourth control signal (second conversion control signal) to the output sub-circuit under the control of the second control signal, and the output sub-circuit outputs a fourth voltage signal under the control of the fourth control signal;
  • the voltage conversion circuit can convert the first voltage signal into the third voltage signal and the second voltage signal into the fourth voltage signal, and the voltage boosting and lowering are implemented by the voltage conversion circuit, and only used The voltage conversion can be realized by the first-stage circuit, and the structure of the voltage conversion circuit is simplified.
  • 1 is a schematic structural view of a conventional voltage conversion circuit
  • FIG. 2 is a schematic structural diagram of a voltage conversion circuit according to an embodiment of the present invention.
  • FIG. 3 is a second schematic structural diagram of a voltage conversion circuit according to an embodiment of the present invention.
  • FIG. 4 is a timing diagram of input signals and output signals of a voltage conversion circuit according to an embodiment of the present invention.
  • FIG. 5 is a third schematic structural diagram of a voltage conversion circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of a voltage conversion method according to an embodiment of the present disclosure.
  • FIG. 7 is a second schematic flowchart of a voltage conversion method according to an embodiment of the present invention.
  • a voltage conversion circuit includes: a first control sub-circuit 1, a second control sub-circuit 2, and an output sub-circuit 3.
  • the input terminal A of the first control sub-circuit 1 serves as the signal input terminal A of the voltage conversion circuit
  • the output terminal of the output sub-circuit 3 serves as the signal output terminal B of the voltage conversion circuit.
  • the output of the first control sub-circuit 1 When the first voltage signal is received at the input end of the first control sub-circuit 1, the output of the first control sub-circuit 1 outputs a first control signal to the second control sub-circuit 2; When the input end of a control sub-circuit 1 receives the second voltage signal, the output of the first control sub-circuit 1 outputs a second control signal to the second control sub-circuit 2.
  • the output of the second control sub-circuit 2 When the second control sub-circuit 2 receives the first control signal from the first control sub-circuit 1, the output of the second control sub-circuit 2 outputs a third control to the output sub-circuit 3 a signal; when the second control sub-circuit 2 receives the second control signal from the first control sub-circuit 1, the output of the second control sub-circuit 2 outputs the output to the output sub-circuit 3 Four control signals.
  • the output sub-circuit 3 When the output sub-circuit 3 receives the third control signal from the second control sub-circuit 2, the output end of the output sub-circuit 3 outputs a third voltage signal; at the output sub-circuit 3 When the second control sub-circuit 2 receives the fourth control signal, the output terminal of the output sub-circuit 3 outputs a fourth voltage signal.
  • the first control sub-circuit outputs a first control signal to the second control sub-circuit when the first voltage signal is input, and the second control sub-circuit outputs the output under the control of the first control signal.
  • the sub-circuit outputs a third control signal, and the output sub-circuit outputs a third voltage signal under the control of the third control signal;
  • the first control sub-circuit outputs a second control signal to the second control sub-circuit when the second voltage signal is input,
  • the second control sub-circuit outputs a fourth control signal to the output sub-circuit under the control of the second control signal, and the output sub-circuit outputs the fourth voltage signal under the control of the fourth control signal.
  • the voltage conversion circuit can convert the first input signal into the first voltage signal and the second input signal into the second voltage signal, and the increase and decrease of the input voltage are implemented by the voltage conversion circuit,
  • the voltage conversion can be realized by using a primary circuit, and the structure of the voltage conversion circuit is simplified.
  • the voltage conversion circuit provided by the embodiment of the present invention may be used to increase the voltage value of the first voltage signal to the voltage value of the third voltage signal, and reduce the voltage value of the second voltage signal to the voltage value of the fourth voltage signal. . That is, in the embodiment of the invention, the voltage value of the third voltage signal is greater than the voltage value of the first voltage signal, the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal, and the voltage value of the second voltage signal is greater than The voltage value of the fourth voltage signal.
  • the voltage conversion circuit provided by the embodiment of the present invention may reduce the voltage value of the first voltage signal to the voltage value of the third voltage signal, and increase the voltage value of the second voltage signal to the first value.
  • the voltage value of the four voltage signals that is, in the embodiment of the present invention, The voltage value of the third voltage signal is smaller than the voltage value of the first voltage signal, the voltage value of the first voltage signal is smaller than the voltage value of the second voltage signal, and the voltage value of the second voltage signal is smaller than the voltage value of the fourth voltage signal.
  • the embodiment given in the following is an example of increasing the voltage value of the first voltage signal to the voltage value of the third voltage signal and reducing the voltage value of the second voltage signal to the voltage value of the fourth voltage signal, that is, The voltage value of the third voltage signal is greater than the voltage value of the first voltage signal, the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal, and the voltage value of the second voltage signal is greater than the voltage value of the fourth voltage signal.
  • the first voltage signal may be a VDD signal, the voltage value is generally 3.3V, the second voltage signal may be a GND signal, the voltage value is 0V, and the third voltage signal may be a VGH signal, and the voltage value is about 30V, and the fourth The voltage signal can be a VGL signal with a voltage value of approximately -8V.
  • the voltage values of the first voltage signal, the second voltage signal, the third voltage signal, and the fourth voltage signal may be other values, which are not limited herein.
  • the input terminal 1a of the first control sub-circuit 1 is connected to the signal input terminal A of the voltage conversion circuit, and the first controller is connected.
  • the output 1b of the circuit 1 is connected to the control terminal 2a of the second control sub-circuit 2.
  • the first input terminal 2b of the second control sub-circuit 2 is connected to the first reference voltage terminal Ref1 for inputting the first reference voltage signal
  • the second input terminal 2c is connected to the second reference voltage terminal for inputting the second reference voltage signal.
  • Ref2 is connected
  • the first output terminal 2d is connected to the first control terminal 3a of the output sub-circuit 3
  • the second output terminal 2e is connected to the third reference voltage terminal Ref3 for inputting the third voltage signal and the first input of the output sub-circuit 3.
  • the terminal 3b is connected, the third output terminal 2f is connected to the second control terminal 3c of the output sub-circuit 3, the fourth output terminal 2g is connected to the fourth reference voltage terminal Ref4 for inputting the fourth voltage signal and the second output terminal circuit 3
  • the input terminal 3d is connected.
  • the output 3e of the output sub-circuit 3 is connected to the signal output B of the voltage conversion circuit.
  • the voltage value of the first reference voltage signal may be less than, equal to, or greater than the voltage value of the first voltage signal, which is not limited herein;
  • the voltage value of the second reference voltage signal may be less than, equal to, or greater than the voltage value of the second voltage signal, which is not limited herein; as long as the voltage value of the second reference voltage signal is less than the voltage of the first reference voltage signal The value is such that the output sub-circuit 3 can operate normally.
  • the voltage value of the first reference voltage signal is equal to the first voltage
  • the voltage value of the signal, and the voltage value of the second reference voltage signal is equal to the voltage value of the second voltage signal.
  • the first reference voltage signal and the first voltage signal are both VDD signals
  • the voltage value is generally 3.3V
  • the second reference voltage signal and the second voltage signal are both GND signals
  • the voltage value is 0V.
  • the first control sub-circuit 1 may specifically include: an inverter U; an input terminal u1 of the inverter U (ie, the first The input terminal 1a) of the control subcircuit is connected to the signal input terminal A, and the output terminal u2 (i.e., the output terminal 1b of the first control subcircuit) is connected to the control terminal 2a of the second control subcircuit 2.
  • the working principle is: when the inverter U receives the VDD signal sent by the signal input terminal A, The inverter U outputs a GND signal to the control terminal 2a of the second control sub-circuit 2; when the inverter U receives the GND signal transmitted from the signal input terminal A, the inverter U is directed to the control terminal of the second control sub-circuit 2 2a outputs the VDD signal.
  • the second control sub-circuit 2 may specifically include: a first switching transistor T1, a second switching transistor T2, a first resistor R1, and a second resistor R2; wherein a gate of the first switching transistor T1 and a gate of the second switching transistor T2 are connected to an output terminal u2 of the inverter U1, a source of the first switching transistor T1 and a first reference for inputting The first reference voltage terminal Ref1 of the voltage signal is connected, and the drain of the first switching transistor T1 is respectively connected to the first end of the first resistor R1 and the first control terminal 3a of the output sub-circuit 3; the second end of the first resistor R1 Connected to a third reference voltage terminal Ref3 for inputting a third voltage signal and a first input terminal 3b of the output sub-circuit 3, respectively; a source of the second switching transistor T2 and a second reference for inputting a second reference voltage signal
  • the voltage terminal Ref3 a third reference voltage terminal Ref3 for inputting a third voltage signal and
  • One switching transistor is a P-type transistor, and the second switching transistor is an N-type transistor.
  • the second control sub-circuit 2 specifically adopts the P-type first switching transistor T1, the N-type second switching transistor T2, the first resistor R1, and the second power.
  • the resistor R2 is a specific structure
  • the working principle is: when the gate of the first switching transistor T1 and the gate of the second switching transistor T2 receive the GND signal sent by the inverter U, due to the gate of the first switching transistor T1
  • the voltage value (0V) of the GND signal of the pole input is smaller than the voltage value (3.3V) of the VDD signal of the source input of the first switching transistor T1
  • the first switching transistor T1 is a P-type transistor, and therefore, the first switching transistor T1 is at Turning on, the first reference voltage terminal Ref1 for inputting the first reference voltage signal outputs a VDD signal to the first control terminal 3a of the output sub-circuit 3 through the first switching transistor T1, and on the other hand, due to the second switching transistor The voltage value (0V) of the GND signal input
  • the first switching transistor T1 is a P-type transistor, therefore, the first switching transistor T1 is turned off, and the third reference voltage terminal Ref3 for inputting the third voltage signal is directed to the first control terminal 3a of the output module 3
  • the VGH signal is output.
  • the second The switching transistor T2 is an N-type transistor, and therefore, the second switching transistor T2 is in an on state, such that the second reference voltage terminal Ref2 for inputting the second reference voltage signal passes through the second switching transistor T2 to the second of the output sub-circuit 3.
  • the control terminal 3c outputs a GND signal.
  • the output sub-circuit 3, as shown in FIG. 3, may specifically include: a third switching transistor T3 and a fourth switching transistor T4; wherein, the third switch The gate of the transistor T3 is connected to the drain of the first switching transistor T1, the source of the third switching transistor T3 is connected to the third reference voltage terminal Ref3 for inputting the third voltage signal, and the gate of the third switching transistor T3 is The source is connected to the first end and the second end of the first resistor R1, respectively, and the drain of the third switching transistor T3 is respectively connected to the signal output terminal B and the drain of the fourth switching transistor T4; the gate of the fourth switching transistor T4 The pole is connected to the drain of the second switching transistor T2, the source of the fourth switching transistor T4 is connected to the fourth reference voltage terminal Ref4 for inputting the fourth voltage signal, and the gate and the source of the fourth switching transistor T4 are respectively The first end and the second end of the second resistor R2 are connected.
  • the first voltage signal and the first reference voltage signal are both VDD signals, and the second voltage signal and the second reference voltage signal are both GND signals,
  • One switching transistor is a P-type transistor, the second switching transistor is an N-type transistor, the third voltage signal is a VGH signal, and when the fourth voltage signal is a VGL signal, the third switching transistor is a P-type transistor, and the fourth switching transistor is an N-type transistor. Transistor.
  • the working principle is: in the third switching transistor T3
  • the gate receives the VDD signal sent by the first reference voltage terminal Ref1 for inputting the first reference voltage signal
  • the gate of the fourth switching transistor T4 receives the fourth reference voltage terminal Ref4 for inputting the fourth voltage signal
  • the voltage value (3.3 V) of the VDD signal input to the gate of the third switching transistor T3 is smaller than the voltage value (30 V) of the VGH signal input from the source of the third switching transistor T3, and the third switching transistor T3 is a P-type transistor, and therefore, the third switching transistor T3 is in an on state, so that the third reference voltage terminal Ref3 for inputting the third voltage signal outputs a VGH signal to the signal output terminal B through the third switching transistor T3, and the other On the other hand, since the voltage value (-8 V)
  • the switching transistor mentioned in the above embodiment of the present invention may be a Thin Film Transistor (TFT) or a Metal Oxide Semiconductor (MOS), which is not limited herein. .
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the sources and drains of these transistors can be interchanged without specific distinction.
  • the switching transistors are A thin film transistor is taken as an example for description.
  • FIG. 4 is a timing chart of an input signal of the signal input terminal A of the voltage conversion circuit shown in FIG. 3 and an output signal of the signal output terminal B.
  • the inverter U receives the VDD signal sent by the signal input terminal A, the inverter U outputs the GND signal to the control terminal 2a of the second control sub-circuit; the first switching transistor T1 in the second control sub-circuit When the gate of the gate and the second switching transistor T2 receives the GND signal sent by the inverter U, the first switching transistor T1 is in an on state, and the second switching transistor T2 is turned off, for inputting the first reference voltage signal.
  • the first reference voltage terminal Ref1 outputs a VDD signal to the first control terminal 3a of the output sub-circuit 3 through the first switching transistor T1, and the fourth reference voltage terminal Ref4 for inputting the fourth voltage signal passes through the second resistor R2 to the output sub-circuit
  • the second control terminal 3c of 3 outputs a VGL signal; the gate of the third switching transistor T3 receives the VDD signal sent by the first reference voltage terminal Ref1 for inputting the first reference voltage signal, and the gate of the fourth switching transistor T4 receives When the VGL signal sent by the fourth reference voltage terminal Ref4 for inputting the fourth voltage signal is turned on, the third switching transistor T3 is in an on state, and the fourth switching transistor T4 is turned off, and is used to input a third voltage signal.
  • a reference voltage terminal Ref3 B VGH output signal terminal to the signal output by the third switching transistor T3.
  • the inverter U receives the GND signal sent by the signal input terminal A, the inverter U outputs the VDD signal to the control terminal 2a of the second control sub-circuit; the first switching transistor T1 in the second control sub-circuit When the gate of the gate and the second switching transistor T2 receives the VDD signal sent by the inverter U, the first switching transistor T1 is turned off, and the second switching transistor T2 is in an on state for inputting the third voltage signal.
  • the third reference voltage terminal Ref3 outputs a VGH signal to the first control terminal 3a of the output sub-circuit 3 through the first resistor R1, and the second reference voltage terminal Ref2 for inputting the second reference voltage signal passes through the second switching transistor T2 to the output sub-circuit
  • the second control terminal 3c of 3 outputs a GND signal; the gate of the third switching transistor T3 receives the VGH signal sent by the third reference voltage terminal Ref3 for inputting the third voltage signal, and the gate of the fourth switching transistor T4 is received.
  • the GND signal sent by the second reference voltage terminal Ref2 of the second reference voltage signal is input, the third switching transistor T3 is turned off, and the fourth switching transistor T4 is in an on state for inputting the fourth voltage signal.
  • Ref4 B reference voltage terminal VGL output signal to a signal output terminal through the fourth switching transistor T4.
  • the circuit structure can also omit the reverser U1 and the third switching transistor T3 in the output sub-circuit 3 and the third reference voltage terminal Ref3 for inputting the third voltage signal and the fourth switching transistor
  • the position of T4 and the fourth reference voltage terminal Ref4 for inputting the fourth voltage signal are interchanged, that is, the circuit structure as shown in FIG. 5, and the signal can also be input when the first voltage signal (VDD signal) is input to the signal input terminal A.
  • the output terminal B outputs a third voltage signal (VGH signal), and the signal output terminal B outputs a fourth voltage signal (VGL signal) when the signal input terminal A inputs the second voltage signal (GND signal).
  • the working principle of the voltage conversion circuit shown in FIG. 5 is similar to that of the voltage conversion circuit shown in FIG. 3, and will not be described herein.
  • the embodiment of the present invention further provides a voltage conversion method.
  • the first voltage signal is input at the signal input end, that is, in the first time period, as shown in FIG. 6, the following operations are performed.
  • step S601 the first control sub-circuit outputs a first control signal to the second control sub-circuit.
  • step S602 the second control sub-circuit outputs a third control signal to the output sub-circuit under the control of the first control signal.
  • step S603 the output sub-circuit outputs a third voltage signal under the control of the third control signal.
  • step S701 the first control sub-circuit outputs a second control signal to the second control sub-circuit.
  • step S702 the second control sub-circuit outputs a fourth control signal to the output sub-circuit under the control of the second control signal.
  • step S703 the output sub-circuit outputs a fourth voltage signal under the control of the fourth control signal.
  • the voltage conversion method of the first voltage signal can be raised to the voltage value of the third voltage signal by using the voltage conversion method provided by the embodiment of the present invention, and the voltage value of the second voltage signal is reduced to the fourth voltage signal.
  • the voltage value that is, the voltage value of the third voltage signal is greater than the voltage value of the first voltage signal, the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal, and the voltage value of the second voltage signal is greater than the fourth voltage The voltage value of the signal.
  • the first voltage signal may be a VDD signal, the voltage value is generally 3.3V, the second voltage signal may be a GND signal, the voltage value is 0V, and the third voltage signal may be a VGH signal, and the voltage value is about 30V, and the fourth The voltage signal can be a VGL signal with a voltage value of approximately -8V.
  • the first control sub-circuit outputs a first control signal to the second control sub-circuit when receiving the VDD signal of the signal input terminal; the second control sub-circuit is at the first control signal Controlling, outputting a third control signal to the output sub-circuit; the output sub-circuit outputs a VGH signal under the control of the third control signal; and the first control sub-circuit outputs to the second control sub-circuit when receiving the GND signal of the signal input end a second control signal; the second control sub-circuit outputs a fourth control signal to the output sub-circuit under the control of the second control signal; and the output sub-circuit outputs the VGL signal under the control of the fourth control signal.
  • the voltage conversion method of the first voltage signal is reduced to the voltage value of the third voltage signal, and the voltage value of the second voltage signal is raised to the fourth voltage.
  • the voltage value of the signal that is, the voltage value of the third voltage signal is less than the voltage value of the first voltage signal, the voltage value of the first voltage signal is less than the voltage value of the second voltage signal, and the voltage value of the second voltage signal is less than the The voltage value of the four voltage signals is not limited herein.
  • an embodiment of the present invention further provides a gate driving circuit, including: the voltage conversion circuit provided by the embodiment of the present invention.
  • a gate driving circuit including: the voltage conversion circuit provided by the embodiment of the present invention.
  • the gate driving circuit reference may be made to the embodiment of the voltage conversion circuit described above, and the repeated description is omitted.
  • an embodiment of the present invention further provides a display panel, including the above-mentioned gate driving circuit provided by the embodiment of the present invention.
  • a display panel including the above-mentioned gate driving circuit provided by the embodiment of the present invention.
  • the display panel refer to the embodiment of the above-mentioned gate driving circuit, and the repeated description is omitted.
  • the above display panel provided by the embodiment of the present invention can be applied to a flat panel display panel such as an OLED or an LCD, which is not limited herein.
  • the gate driving circuit may be directly integrated on the array substrate in the display panel, or the gate driving circuit may be bound to the array substrate in the display panel, which is not limited herein.
  • an embodiment of the present invention further provides a display device, which is provided by the embodiment of the present invention.
  • the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or component that has a display function, such as a navigator or a wearable device.
  • a display function such as a navigator or a wearable device.
  • the embodiment provides a voltage conversion circuit, a voltage conversion method, a gate driving circuit and a display device.
  • the first control sub-circuit outputs to the second control sub-circuit when the first voltage signal is input. a first control signal, the second control sub-circuit outputs a third control signal to the output sub-circuit under the control of the first control signal, and the output sub-circuit outputs a third voltage signal under the control of the third control signal;
  • the first control sub-circuit And outputting a second control signal to the second control sub-circuit when the second voltage signal is input, the second control sub-circuit outputs a fourth control signal to the output sub-circuit under the control of the second control signal, and the output sub-circuit is at the fourth control signal
  • the fourth voltage signal is output under the control; thus, the voltage conversion circuit can convert the first voltage signal into the third voltage signal and the second voltage signal into the fourth voltage signal, and the voltage is raised and lowered.
  • Voltage conversion The circuit realizes that the voltage conversion can be realized only

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Abstract

一种电压转换电路、电压转换方法、栅极驱动电路、显示面板及显示装置。所述电压转换电路包括控制子电路（1，2）和输出子电路（3），所述控制子电路（1，2）被配置为在其输入端（A）接收到第一电压信号时向所述输出子电路（3）输出第一转换控制信号，并且在其输入端（A）接收到第二电压信号时向所述输出子电路（3）输出第二转换控制信号；以及所述输出子电路（3）被配置为在从所述控制子电路（1，2）接收到第一转换控制信号时输出第三电压信号，并且在从所述控制子电路（1，2）接收到第二转换控制信号时输出第四电压信号。这样，该电压转换电路既能将第一电压信号转换为第三电压信号，又能将第二电压信号转换为第四电压信号，电压的提升和降低都是该电压转换电路实现的，该电压转换电路的结构精简。

Description

电压转换电路、电压转换方法、栅极驱动电路、显示面板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种电压转换电路、电压转换方法、栅极驱动电路、显示面板及显示装置。
背景技术
随着显示技术的不断发展，发光二极管(Light Emitting Diode，LED)、有机发光二极管(Organic Light Emitting Diode，OLED)、等离子显示器(Plasma Display Panel,PDP)及液晶显示器(Liquid Crystal Display,LCD)等平板显示器发展迅速。
在平板显示器中，栅极驱动电路向显示面板中的各栅线加载栅极扫描信号，数据驱动电路向显示面板中的各数据线加载数据信号。在栅极驱动电路中，电压转换电路将输入的小幅值的电压信号转换成能用于驱动像素点的大幅值的电压信号。通常情况下，电压转换电路输入的电压信号为工作电压VDD(一般为3.3V)和工作地GND(0V)，转换后输出的电压信号为高电压信号VGH(约30V)和低电压信号VGL(约-8V)。
在现有的电压转换电路中，至少需要两级转换电路来实现电压的转换，如图1所示，采用了两级转换电路来实现电压转换，第一级转换电路只将VDD提升至VGH，第二级转换电路只将GND降低至VGL，电路器件多，电路结构较为复杂。
发明内容
有鉴于此，本发明实施例提供了一种电压转换电路、电压转换方法、栅极驱动电路、显示面板及显示装置，其中，优化了电压转换电路的结构。
因此，本发明实施例提供了一种电压转换电路，包括：控制子电路和输出子电路，其中，所述控制子电路的输入端与所述电压转换电路的信号输入端连接，所述输出子电路的输出端与所述电压转换电路的信号输出端连接，所述控制子电路被配置为在其输入端接收到第一电压信号时向所述输出子电路输出第一转换控制信号，并且在其输入端接收到第二电压信号时向所述输出子电路输出第二转换控制信号；以及所述输出子电路被配置为在从所述控 制子电路接收到第一转换控制信号时输出第三电压信号，并且在从所述控制子电路接收到第二转换控制信号时输出第四电压信号。
根据本发明实施例，所述控制子电路包括：第一控制子电路和第二控制子电路，所述第一控制子电路被配置为在其输入端接收到所述第一电压信号时向所述第二控制子电路输出第一控制信号，并且在其输入端接收到所述第二电压信号时向所述第二控制子电路输出第二控制信号；以及所述第二控制子电路被配置为在其输入端接收到所述第一控制信号时向所述输出子电路输出所述第一转换控制信号，并且在其输入端接收到所述第二控制信号时向所述输出子电路输出所述第二转换控制信号。
根据本发明实施例，所述第一控制子电路的输出端与所述第二控制子电路的控制端相连；所述第二控制子电路的第一输入端与用于输入第一参考电压信号的第一参考电压端相连，第二输入端与用于输入第二参考电压信号的第二参考电压端相连，第一输出端与所述输出子电路的第一控制端相连，第二输出端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连，第三输出端与所述输出子电路的第二控制端相连，第四输出端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连。
根据本发明实施例，所述第一控制子电路包括反向器；所述反向器的输入端与所述信号输入端相连，输出端与所述第二控制子电路的控制端相连。
根据本发明实施例，所述第二控制子电路包括：第一开关晶体管、第二开关晶体管、第一电阻和第二电阻；其中，所述第一开关晶体管的栅极和所述第二开关晶体管的栅极与所述反向器的输出端相连，所述第一开关晶体管的源极与用于输入第一参考电压信号的第一参考电压端相连，所述第一开关晶体管的漏极分别与所述第一电阻的第一端和所述输出子电路的第一控制端相连；所述第一电阻的第二端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连；所述第二开关晶体管的源极与用于输入第二参考电压信号的第二参考电压端相连，所述第二开关晶体管的漏极分别与所述第二电阻的第一端和所述输出子电路的第二控制端相连；所述第二电阻的第二端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连。
根据本发明实施例，所述输出子电路包括：第三开关晶体管和第四开关 晶体管；其中，所述第三开关晶体管的栅极与所述第一开关晶体管的漏极相连，所述第三开关晶体管的源极与用于输入第三电压信号的第三参考电压端相连，所述第三开关晶体管的栅极和源极分别与所述第一电阻的第一端和第二端相连，所述第三开关晶体管的漏极和所述第四开关晶体管的漏极与所述信号输出端相连；所述第四开关晶体管的栅极与所述第二开关晶体管的漏极相连，所述第四开关晶体管的源极与用于输入第四电压信号的第四参考电压端相连，所述第四开关晶体管的栅极和源极分别与所述第二电阻的第一端和第二端端相连。
根据本发明实施例，所述控制子电路的第一输入端与用于输入第一参考电压信号的第一参考电压端相连，第二输入端与用于输入第二参考电压信号的第二参考电压端相连，第一输出端与所述输出子电路的第一控制端相连，第二输出端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连，第三输出端与所述输出子电路的第二控制端相连，第四输出端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连。
根据本发明实施例，所述控制子电路包括：第一开关晶体管、第二开关晶体管、第一电阻和第二电阻；其中，所述第一开关晶体管的栅极和所述第二开关晶体管的栅极与所述控制子电路的输入端相连，所述第一开关晶体管的源极与用于输入第一参考电压信号的第一参考电压端相连，所述第一开关晶体管的漏极分别与所述第一电阻的第一端和所述输出子电路的第一控制端相连；所述第一电阻的第二端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连；所述第二开关晶体管的源极与用于输入第二参考电压信号的第二参考电压端相连，所述第二开关晶体管的漏极分别与所述第二电阻的第一端和所述输出子电路的第二控制端相连；所述第二电阻的第二端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连。
根据本发明实施例，所述输出子电路包括：第三开关晶体管和第四开关晶体管；其中，所述第三开关晶体管的栅极与所述第二开关晶体管的漏极相连，所述第三开关晶体管的源极与用于输入第三电压信号的第三参考电压端相连，所述第三开关晶体管的栅极和源极分别与所述第二电阻的第一端和第二端相连，所述第三开关晶体管的漏极和所述第四开关晶体管的漏极与所述 信号输出端相连；所述第四开关晶体管的栅极与所述第一开关晶体管的漏极相连，所述第四开关晶体管的源极与用于输入第四电压信号的第四参考电压端相连，所述第四开关晶体管的栅极和源极分别与所述第一电阻的第一端和第二端端相连。
根据本发明实施例，所述第三电压信号的电压值大于所述第一电压信号的电压值；所述第一电压信号的电压值大于所述第二电压信号的电压值；所述第二电压信号的电压值大于所述第四电压信号的电压值。
根据本发明实施例，在本发明实施例提供的上述电压转换电路中，所述第一参考电压信号的电压值小于或等于所述第一电压信号的电压值；所述第二参考电压信号的电压值大于或等于所述第二电压信号的电压值，且小于所述第一参考电压信号的电压值。
在一种可能的实现方式中，在本发明实施例提供的上述电压转换电路中，所述第一开关晶体管和所述第三开关晶体管为P型晶体管；所述第二开关晶体管和所述第四开关晶体管为N型晶体管。
本发明实施例还提供了一种电压转换方法，包括：在所述电压转换电路的信号输入端输入第一电压信号时，所述控制子电路向所述输出子电路输出第一转换控制信号，所述输出子电路在所述第一转换控制信号的控制下输出第三电压信号；以及在所述电压转换电路的信号输入端接收到第二电压信号时，所述控制子电路向所述输出子电路输出第二转换控制信号，所述输出子电路在所述第二转换控制信号的控制下输出第四电压信号。
在一种可能的实现方式中，在本发明实施例提供的上述电压转换方法中，所述第三电压信号的电压值大于所述第一电压信号的电压值；所述第一电压信号的电压值大于所述第二电压信号的电压值；所述第二电压信号的电压值大于所述第四电压信号的电压值。
本发明实施例还提供了一种栅极驱动电路，包括：本发明实施例提供的上述电压转换电路。
本发明实施例还提供了一种显示面板，包括：本发明实施例提供的上述栅极驱动电路。
本发明实施例还提供了一种显示装置，包括：本发明实施例提供的上述显示面板。
本发明实施例提供的上述电压转换电路、其电压转换方法及相关装置， 在该电压转换电路中，第一控制子电路在输入第一电压信号时向第二控制子电路输出第一控制信号，第二控制子电路在第一控制信号的控制下向输出子电路输出第三控制信号(第一转换控制信号)，输出子电路在第三控制信号的控制下输出第一电压信号；第一控制子电路在输入第二电压信号时向第二控制子电路输出第二控制信号，第二控制子电路在第二控制信号的控制下向输出子电路输出第四控制信号(第二转换控制信号)，输出子电路在第四控制信号的控制下输出第四电压信号；这样，该电压转换电路既能将第一电压信号转换为第三电压信号，又能将第二电压信号转换为第四电压信号，电压的提升和降低都是该电压转换电路实现的，只用了一级电路便可实现电压的转换，该电压转换电路的结构精简。
附图说明
图1为现有的电压转换电路的结构示意图；
图2为本发明实施例提供的电压转换电路的结构示意图之一；
图3为本发明实施例提供的电压转换电路的结构示意图之二；
图4为本发明实施例提供的电压转换电路的输入信号和输出信号的时序图；
图5为本发明实施例提供的电压转换电路的结构示意图之三；
图6为本发明实施例提供的电压转换方法的示意流程图之一；
图7为本发明实施例提供的电压转换方法的示意流程图之二。
具体实施方式
下面结合附图，对本发明实施例提供的电压转换电路、电压转换方法及相关装置的具体实施方式进行详细地说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例提供的一种电压转换电路，如图2所示，包括：第一控制子电路1、第二控制子电路2和输出子电路3。
第一控制子电路1的输入端A作为所述电压转换电路的信号输入端A，所述输出子电路3的输出端作为所述电压转换电路的信号输出端B。
在所述第一控制子电路1的输入端接收到第一电压信号时，所述第一控制子电路1的输出端向所述第二控制子电路2输出第一控制信号；在所述第一控制子电路1的输入端接收到第二电压信号时，所述第一控制子电路1的输出端向所述第二控制子电路2输出第二控制信号。
在所述第二控制子电路2从所述第一控制子电路1接收到所述第一控制信号时，所述第二控制子电路2的输出端向所述输出子电路3输出第三控制信号；在所述第二控制子电路2从所述第一控制子电路1接收到所述第二控制信号时，所述第二控制子电路2的输出端向所述输出子电路3输出第四控制信号。
在所述输出子电路3从所述第二控制子电路2接收到所述第三控制信号时，所述输出子电路3的输出端输出第三电压信号；在所述输出子电路3从所述第二控制子电路2接收到所述第四控制信号时，所述输出子电路3的输出端输出第四电压信号。
本发明实施例提供的上述电压转换电路，第一控制子电路在输入第一电压信号时向第二控制子电路输出第一控制信号，第二控制子电路在第一控制信号的控制下向输出子电路输出第三控制信号，输出子电路在第三控制信号的控制下输出第三电压信号；第一控制子电路在输入第二电压信号时向第二控制子电路输出第二控制信号，第二控制子电路在第二控制信号的控制下向输出子电路输出第四控制信号，输出子电路在第四控制信号的控制下输出第四电压信号。这样，该电压转换电路既能将第一输入信号转换为第一电压信号，又能将第二输入信号转换为第二电压信号，输入电压的提升和降低都是该电压转换电路实现的，只用了一级电路便可实现电压的转换，该电压转换电路的结构精简。
作为示例，可以利用本发明实施例提供的上述电压转换电路将第一电压信号的电压值提升为第三电压信号的电压值，将第二电压信号的电压值降低为第四电压信号的电压值。也就是说，在发明实施例中，第三电压信号的电压值大于第一电压信号的电压值，第一电压信号的电压值大于第二电压信号的电压值，第二电压信号的电压值大于第四电压信号的电压值。
可替代地，作为另一示例，可以利用本发明实施例提供的上述电压转换电路将第一电压信号的电压值降低为第三电压信号的电压值，将第二电压信号的电压值提升为第四电压信号的电压值。也就是说，在本发明实施例中， 第三电压信号的电压值小于第一电压信号的电压值，第一电压信号的电压值小于第二电压信号的电压值，第二电压信号的电压值小于第四电压信号的电压值。
本发明以下给出的实施例以将第一电压信号的电压值提升为第三电压信号的电压值，将第二电压信号的电压值降低为第四电压信号的电压值为例进行说明，即第三电压信号的电压值大于第一电压信号的电压值，第一电压信号的电压值大于第二电压信号的电压值，第二电压信号的电压值大于第四电压信号的电压值。具体地，第一电压信号可以为VDD信号，电压值一般为3.3V，第二电压信号可以为GND信号，电压值为0V，第三电压信号可以为VGH信号，电压值约为30V，第四电压信号可以为VGL信号，电压值约为-8V。
当然，在本发明实施例提供的上述电压转换电路中，第一电压信号、第二电压信号、第三电压信号和第四电压信号的电压值也可以为其他数值，在此不做限定。
根据本发明实施例，在本发明实施例提供的上述电压转换电路中，如图3所示，第一控制子电路1的输入端1a与电压转换电路的信号输入端A相连，第一控制子电路1的输出端1b与第二控制子电路2的控制端2a相连。
第二控制子电路2的第一输入端2b与用于输入第一参考电压信号的第一参考电压端Ref1相连，第二输入端2c与用于输入第二参考电压信号的第二参考电压端Ref2相连，第一输出端2d与输出子电路3的第一控制端3a相连，第二输出端2e与用于输入第三电压信号的第三参考电压端Ref3和输出子电路3的第一输入端3b相连，第三输出端2f与输出子电路3的第二控制端3c相连，第四输出端2g与用于输入第四电压信号的第四参考电压端Ref4和输出子电路3的第二输入端3d相连。
输出子电路3的输出端3e与电压转换电路的信号输出端B相连。
在具体实施时，在本发明实施例提供的上述电压转换电路中，所述第一参考电压信号的电压值可以小于、等于或大于第一电压信号的电压值，在此不做限定；所述第二参考电压信号的电压值可以小于、等于或大于第二电压信号的电压值，在此不做限定；只要保证所述第二参考电压信号的电压值小于所述第一参考电压信号的电压值，使得所述输出子电路3能够正常工作即可。在下面的描述中，以所述第一参考电压信号的电压值等于所述第一电压 信号的电压值，所述第二参考电压信号的电压值等于所述第二电压信号的电压值为例进行说明。例如，所述第一参考电压信号和所述第一电压信号均为VDD信号，电压值一般为3.3V，所述第二参考电压信号和所述第二电压信号均为GND信号，电压值为0V。
作为示例，在本发明实施例提供的上述电压转换电路中，第一控制子电路1，如图3所示，具体可以包括：反向器U；反向器U的输入端u1(即第一控制子电路的输入端1a)与信号输入端A相连，输出端u2(即第一控制子电路的输出端1b)与第二控制子电路2的控制端2a相连。
本发明实施例提供的电压转换电路中第一控制子电路1具体采用上述反向器U作为具体结构时，其工作原理为：在反向器U接收到信号输入端A发送的VDD信号时，反向器U向第二控制子电路2的控制端2a输出GND信号；在反向器U接收到信号输入端A发送的GND信号时，反向器U向第二控制子电路2的控制端2a输出VDD信号。
作为示例，在本发明实施例提供的上述电压转换电路中，第二控制子电路2，如图3所示，具体可以包括：第一开关晶体管T1、第二开关晶体管T2、第一电阻R1和第二电阻R2；其中，第一开关晶体管T1的栅极和第二开关晶体管T2的栅极与反向器U的输出端u2相连，第一开关晶体管T1的源极与用于输入第一参考电压信号的第一参考电压端Ref1相连，第一开关晶体管T1的漏极分别与第一电阻R1的第一端和输出子电路3的第一控制端3a相连；第一电阻R1的第二端分别与用于输入第三电压信号的第三参考电压端Ref3和输出子电路3的第一输入端3b相连；第二开关晶体管T2的源极与用于输入第二参考电压信号的第二参考电压端Ref2相连，第二开关晶体管T2的漏极分别与第二电阻R2的第一端和输出子电路3的第二控制端3c相连；第二电阻R2的第二端分别与用于输入第四电压信号的第四参考电压端Ref4和输出子电路3的第二输入端3d相连。
在具体实施时，在本发明实施例提供的上述电压转换电路中，第一电压信号和第一参考电压信号均为VDD信号，第二电压信号和第二参考电压信号均为GND信号时，第一开关晶体管为P型晶体管，第二开关晶体管为N型晶体管。
本发明实施例提供的电压转换电路中第二控制子电路2具体采用上述P型的第一开关晶体管T1、N型的第二开关晶体管T2、第一电阻R1和第二电 阻R2作为具体结构时，其工作原理为：在第一开关晶体管T1的栅极和第二开关晶体管T2的栅极接收到反向器U发送的GND信号时，由于第一开关晶体管T1的栅极输入的GND信号的电压值(0V)小于第一开关晶体管T1的源极输入的VDD信号的电压值(3.3V)，第一开关晶体管T1为P型晶体管，因此，第一开关晶体管T1处于导通状态，使得用于输入第一参考电压信号的第一参考电压端Ref1通过第一开关晶体管T1向输出子电路3的第一控制端3a输出VDD信号，另一方面，由于第二开关晶体管T2的栅极输入的GND信号的电压值(0V)等于第二开关晶体管T2的源极输入的GND信号的电压值(0V)，第二开关晶体管T2为N型晶体管，因此，第二开关晶体管T2截止，用于输入第四电压信号的第四参考电压端Ref4通过第二电阻R2向输出模块3的第二控制端3c输出VGL信号；在第一开关晶体管T1的栅极和第二开关晶体管T2的栅极接收到反向器U发送的VDD信号时，由于第一开关晶体管T1的栅极输入的VDD信号的电压值(3.3V)等于第一开关晶体管T1的源极输入的VDD信号的电压值(3.3V)，第一开关晶体管T1为P型晶体管，因此，第一开关晶体管T1截止，用于输入第三电压信号的第三参考电压端Ref3向输出模块3的第一控制端3a输出VGH信号，另一方面，由于第二开关晶体管T2的栅极输入的VDD信号的电压值(3.3V)大于第二开关晶体管T2的源极输入的GND信号的电压值(0V)，第二开关晶体管T2为N型晶体管，因此，第二开关晶体管T2处于导通状态，使得用于输入第二参考电压信号的第二参考电压端Ref2通过第二开关晶体管T2向输出子电路3的第二控制端3c输出GND信号。
在具体实施时，在本发明实施例提供的上述电压转换电路中，输出子电路3，如图3所示，具体可以包括：第三开关晶体管T3和第四开关晶体管T4；其中，第三开关晶体管T3的栅极与第一开关晶体管T1的漏极相连，第三开关晶体管T3的源极与用于输入第三电压信号的第三参考电压端Ref3相连，第三开关晶体管T3的栅极和源极分别与第一电阻R1的第一端和第二端相连，第三开关晶体管T3的漏极分别与信号输出端B和第四开关晶体管T4的漏极相连；第四开关晶体管T4的栅极与第二开关晶体管T2的漏极相连，第四开关晶体管T4的源极与用于输入第四电压信号的第四参考电压端Ref4相连，第四开关晶体管T4的栅极和源极分别与第二电阻R2的第一端和第二端相连。
在具体实施时，在本发明实施例提供的上述电压转换电路中，在第一电压信号和第一参考电压信号均为VDD信号，第二电压信号和第二参考电压信号均为GND信号，第一开关晶体管为P型晶体管，第二开关晶体管为N型晶体管，第三电压信号为VGH信号，第四电压信号为VGL信号时，第三开关晶体管为P型晶体管，第四开关晶体管为N型晶体管。
本发明实施例提供的电压转换电路中输出子电路3具体采用上述P型的第三开关晶体管T3、N型的第四开关晶体管T4作为具体结构时，其工作原理为：在第三开关晶体管T3的栅极接收到用于输入第一参考电压信号的第一参考电压端Ref1发送的VDD信号、且第四开关晶体管T4的栅极接收到用于输入第四电压信号的第四参考电压端Ref4发送的VGL信号时，由于第三开关晶体管T3的栅极输入的VDD信号的电压值(3.3V)小于第三开关晶体管T3的源极输入的VGH信号的电压值(30V)，第三开关晶体管T3为P型晶体管，因此，第三开关晶体管T3处于导通状态，使得用于输入第三电压信号的第三参考电压端Ref3通过第三开关晶体管T3向信号输出端B输出VGH信号，另一方面，由于第四开关晶体管T4的栅极输入的VGL信号的电压值(-8V)等于第四开关晶体管T4的源极输入的VGL信号的电压值(-8V)，第四开关晶体管T4为N型晶体管，因此，第四开关晶体管T4截止；在第三开关晶体管T3的栅极接收到用于输入第三电压信号的第三参考电压端Ref3发送的VGH信号、且第四开关晶体管T4的栅极接收到用于输入第二参考电压信号的第二参考电压端Ref2发送的GND信号时，由于第三开关晶体管T3的栅极输入的VGH信号的电压值(30V)等于第三开关晶体管T3的源极输入的VGH信号的电压值(30V)，第三开关晶体管T3为P型晶体管，因此，第三开关晶体管T3截止，另一方面，由于第四开关晶体管T4的栅极输入的GND信号的电压值(0V)大于第四开关晶体管T4的源极输入的VGL信号的电压值(-8V)，第四开关晶体管T4为N型晶体管，因此，第四开关晶体管T4处于导通状态，使得用于输入第四电压信号的第四参考电压端Ref4通过第四开关晶体管T4向信号输出端B输出VGL信号。
需要说明的是本发明上述实施例中提到的开关晶体管可以是薄膜晶体管(Thin Film Transistor,TFT)，也可以是金属氧化物半导体场效应管(Metal Oxide Semiconductor,MOS)，在此不做限定。在具体实施中，这些晶体管的源极和漏极可以互换，不做具体区分。在描述具体实施例时以开关晶体管都 为薄膜晶体管为例进行说明的。
下面以如图3所示的具体示例对电压转换电路的工作原理进行详细的说明。图4为如图3所示的电压转换电路的信号输入端A的输入信号和信号输出端B的输出信号的时序图。
在第一时段，反向器U接收到信号输入端A发送的VDD信号，反向器U向第二控制子电路的控制端2a输出GND信号；第二控制子电路中的第一开关晶体管T1的栅极和第二开关晶体管T2的栅极接收到反向器U发送的GND信号时，第一开关晶体管T1处于导通状态，第二开关晶体管T2截止，用于输入第一参考电压信号的第一参考电压端Ref1通过第一开关晶体管T1向输出子电路3的第一控制端3a输出VDD信号，用于输入第四电压信号的第四参考电压端Ref4通过第二电阻R2向输出子电路3的第二控制端3c输出VGL信号；第三开关晶体管T3的栅极接收到用于输入第一参考电压信号的第一参考电压端Ref1发送的VDD信号，第四开关晶体管T4的栅极接收到用于输入第四电压信号的第四参考电压端Ref4发送的VGL信号时，第三开关晶体管T3处于导通状态，第四开关晶体管T4截止，用于输入第三电压信号的第三参考电压端Ref3通过第三开关晶体管T3向信号输出端B输出VGH信号。
在第二时段，反向器U接收到信号输入端A发送的GND信号，反向器U向第二控制子电路的控制端2a输出VDD信号；第二控制子电路中的第一开关晶体管T1的栅极和第二开关晶体管T2的栅极接收到反向器U发送的VDD信号时，第一开关晶体管T1截止，第二开关晶体管T2处于导通状态，用于输入第三电压信号的第三参考电压端Ref3通过第一电阻R1向输出子电路3的第一控制端3a输出VGH信号，用于输入第二参考电压信号的第二参考电压端Ref2通过第二开关晶体管T2向输出子电路3的第二控制端3c输出GND信号；第三开关晶体管T3的栅极接收到用于输入第三电压信号的第三参考电压端Ref3发送的VGH信号，第四开关晶体管T4的栅极接收到用于输入第二参考电压信号的第二参考电压端Ref2发送的GND信号时，第三开关晶体管T3截止，第四开关晶体管T4处于导通状态，用于输入第四电压信号的第四参考电压端Ref4通过第四开关晶体管T4向信号输出端B输出VGL信号。
需要说明的是，本发明实施例提供的上述电压转换电路并非局限于如图 3所示的电路结构，还可以省去反向器U1并将输出子电路3中的第三开关晶体管T3和用于输入第三电压信号的第三参考电压端Ref3的位置与第四开关晶体管T4和用于输入第四电压信号的第四参考电压端Ref4的位置互换，即如图5所示的电路结构，同样能够实现在信号输入端A输入第一电压信号(VDD信号)时信号输出端B输出第三电压信号(VGH信号)，在信号输入端A输入第二电压信号(GND信号)时信号输出端B输出第四电压信号(VGL信号)。图5所示的电压转换电路的工作原理与图3所示的电压转换电路的工作原理类似，在此不做赘述。
基于同一发明构思，本发明实施例还提供了一种电压转换方法，在信号输入端输入第一电压信号时，即在第一时段时，如图6所示，执行以下操作。
在步骤S601、第一控制子电路向第二控制子电路输出第一控制信号。
在步骤S602、第二控制子电路在第一控制信号的控制下向输出子电路输出第三控制信号。
在步骤S603、输出子电路在第三控制信号的控制下输出第三电压信号。
在信号输入端输入第二电压信号时，如图7所示，执行以下操作。
在步骤S701、第一控制子电路向第二控制子电路输出第二控制信号。
在步骤S702、第二控制子电路在第二控制信号的控制下向输出子电路输出第四控制信号。
在步骤S703、输出子电路在第四控制信号的控制下输出第四电压信号。
在具体实施时，可以利用本发明实施例提供的上述电压转换方法将第一电压信号的电压值提升为第三电压信号的电压值，将第二电压信号的电压值降低为第四电压信号的电压值，也就是说，第三电压信号的电压值大于第一电压信号的电压值，第一电压信号的电压值大于第二电压信号的电压值，第二电压信号的电压值大于第四电压信号的电压值。具体地，第一电压信号可以为VDD信号，电压值一般为3.3V，第二电压信号可以为GND信号，电压值为0V，第三电压信号可以为VGH信号，电压值约为30V，第四电压信号可以为VGL信号，电压值约为-8V。则在本发明实例提供的上述电压转换方法中，第一控制子电路在接收到信号输入端的VDD信号时，向第二控制子电路输出第一控制信号；第二控制子电路在第一控制信号的控制下向输出子电路输出第三控制信号；输出子电路在第三控制信号的控制下输出VGH信号；第一控制子电路在接收到信号输入端的GND信号时，向第二控制子电路输出 第二控制信号；第二控制子电路在第二控制信号的控制下向输出子电路输出第四控制信号；输出子电路在第四控制信号的控制下输出VGL信号。
当然，可替换地，也可以利用本发明实施例提供的上述电压转换方法将第一电压信号的电压值降低为第三电压信号的电压值，将第二电压信号的电压值提升为第四电压信号的电压值，也就是说，第三电压信号的电压值小于第一电压信号的电压值，第一电压信号的电压值小于第二电压信号的电压值，第二电压信号的电压值小于第四电压信号的电压值，在此不做限定。
基于同一发明构思，本发明实施例还提供了一种栅极驱动电路，包括：本发明实施例提供的上述电压转换电路。该栅极驱动电路的实施可以参见上述电压转换电路的实施例，重复之处不再赘述。
基于同一发明构思，本发明实施例还提供了一种显示面板，包括：本发明实施例提供的上述栅极驱动电路。该显示面板的实施可以参见上述栅极驱动电路的实施例，重复之处不再赘述。
在具体实施时，本发明实施例提供的上述显示面板可以适用于OLED或LCD等平板显示面板，在此不做限定。具体地，栅极驱动电路可以直接集成于显示面板中的阵列基板上，或者，栅极驱动电路也可以与显示面板中的阵列基板绑定，在此不做限定。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、可穿戴装置等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本发明实施例提供的一种电压转换电路、电压转换方法、栅极驱动电路及显示装置，在该电压转换电路中，第一控制子电路在输入第一电压信号时向第二控制子电路输出第一控制信号，第二控制子电路在第一控制信号的控制下向输出子电路输出第三控制信号，输出子电路在第三控制信号的控制下输出第三电压信号；第一控制子电路在输入第二电压信号时向第二控制子电路输出第二控制信号，第二控制子电路在第二控制信号的控制下向输出子电路输出第四控制信号，输出子电路在第四控制信号的控制下输出第四电压信号；这样，该电压转换电路既能将第一电压信号转换为第三电压信号，又能将第二电压信号转换为第四电压信号，电压的提升和降低都是该电压转换电 路实现的，只用了一级转换电路便可实现电压的转换，该电压转换电路的结构精简。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
本申请要求2016年01月04日提交的申请号为“201610005886.8”且发明名称为“一种电平转换电路、电平转换方法及相关装置”的中国优先申请的优先权，通过引用将其全部内容并入于此。

Claims (20)

  1. 一种电压转换电路，包括：控制子电路和输出子电路，其中，所述控制子电路的输入端与所述电压转换电路的信号输入端连接，所述输出子电路的输出端与所述电压转换电路的信号输出端连接，
    所述控制子电路被配置为在其输入端接收到第一电压信号时向所述输出子电路输出第一转换控制信号，并且在其输入端接收到第二电压信号时向所述输出子电路输出第二转换控制信号；以及
    所述输出子电路被配置为在从所述控制子电路接收到第一转换控制信号时输出第三电压信号，并且在从所述控制子电路接收到第二转换控制信号时输出第四电压信号。
  2. 如权利要求1所述的电压转换电路，其中，所述控制子电路包括：第一控制子电路和第二控制子电路，
    所述第一控制子电路被配置为在其输入端接收到所述第一电压信号时向所述第二控制子电路输出第一控制信号，并且在其输入端接收到所述第二电压信号时向所述第二控制子电路输出第二控制信号；以及
    所述第二控制子电路被配置为在其输入端接收到所述第一控制信号时向所述输出子电路输出所述第一转换控制信号，并且在其输入端接收到所述第二控制信号时向所述输出子电路输出所述第二转换控制信号。
  3. 如权利要求2所述的电压转换电路，其中，所述第一控制子电路的输出端与所述第二控制子电路的控制端相连；
    所述第二控制子电路的第一输入端与用于输入第一参考电压信号的第一参考电压端相连，第二输入端与用于输入第二参考电压信号的第二参考电压端相连，第一输出端与所述输出子电路的第一控制端相连，第二输出端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连，第三输出端与所述输出子电路的第二控制端相连，第四输出端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连。
  4. 如权利要求3所述的电压转换电路，其中，所述第一控制子电路，包括：反向器；
    所述反向器的输入端与所述信号输入端相连，输出端与所述第二控制子 电路的控制端相连。
  5. 如权利要求3所述的电压转换电路，其中，所述第二控制子电路包括：第一开关晶体管、第二开关晶体管、第一电阻和第二电阻；其中，
    所述第一开关晶体管的栅极和所述第二开关晶体管的栅极与所述反向器的输出端相连，
    所述第一开关晶体管的源极与用于输入第一参考电压信号的第一参考电压端相连，所述第一开关晶体管的漏极分别与所述第一电阻的第一端和所述输出子电路的第一控制端相连；
    所述第一电阻的第二端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连；
    所述第二开关晶体管的源极与用于输入第二参考电压信号的第二参考电压端相连，所述第二开关晶体管的漏极分别与所述第二电阻的第一端和所述输出子电路的第二控制端相连；
    所述第二电阻的第二端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连。
  6. 如权利要求3所述的电压转换电路，其中，所述输出子电路包括：第三开关晶体管和第四开关晶体管；其中，
    所述第三开关晶体管的栅极与所述第一开关晶体管的漏极相连，所述第三开关晶体管的源极与用于输入第三电压信号的第三参考电压端相连，所述第三开关晶体管的栅极和源极分别与所述第一电阻的第一端和第二端相连，所述第三开关晶体管的漏极和所述第四开关晶体管的漏极与所述信号输出端相连；
    所述第四开关晶体管的栅极与所述第二开关晶体管的漏极相连，所述第四开关晶体管的源极与用于输入第四电压信号的第四参考电压端相连，所述第四开关晶体管的栅极和源极分别与所述第二电阻的第一端和第二端端相连。
  7. 如权利要求1所述的电压转换电路，其中，所述控制子电路的第一输入端与用于输入第一参考电压信号的第一参考电压端相连，第二输入端与用于输入第二参考电压信号的第二参考电压端相连，第一输出端与所述输出子电路的第一控制端相连，第二输出端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连，第三输出端与所述输出子电 路的第二控制端相连，第四输出端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连。
  8. 如权利要求7所述的电压转换电路，其中，所述控制子电路包括：第一开关晶体管、第二开关晶体管、第一电阻和第二电阻；其中，
    所述第一开关晶体管的栅极和所述第二开关晶体管的栅极与所述控制子电路的输入端相连，
    所述第一开关晶体管的源极与用于输入第一参考电压信号的第一参考电压端相连，所述第一开关晶体管的漏极分别与所述第一电阻的第一端和所述输出子电路的第一控制端相连；
    所述第一电阻的第二端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连；
    所述第二开关晶体管的源极与用于输入第二参考电压信号的第二参考电压端相连，所述第二开关晶体管的漏极分别与所述第二电阻的第一端和所述输出子电路的第二控制端相连；
    所述第二电阻的第二端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连。
  9. 如权利要求7所述的电压转换电路，其中，所述输出子电路包括：第三开关晶体管和第四开关晶体管；其中，
    所述第三开关晶体管的栅极与所述第二开关晶体管的漏极相连，所述第三开关晶体管的源极与用于输入第三电压信号的第三参考电压端相连，所述第三开关晶体管的栅极和源极分别与所述第二电阻的第一端和第二端相连，所述第三开关晶体管的漏极和所述第四开关晶体管的漏极与所述信号输出端相连；
    所述第四开关晶体管的栅极与所述第一开关晶体管的漏极相连，所述第四开关晶体管的源极与用于输入第四电压信号的第四参考电压端相连，所述第四开关晶体管的栅极和源极分别与所述第一电阻的第一端和第二端端相连。
  10. 如权利要求1-9任一项所述的电压转换电路，其中，所述第三电压信号的电压值大于所述第一电压信号的电压值；
    所述第一电压信号的电压值大于所述第二电压信号的电压值；
    所述第二电压信号的电压值大于所述第四电压信号的电压值。
  11. 如权利要求10所述的电压转换电路，其中，所述第一参考电压信号的电压值小于或等于所述第一电压信号的电压值；
    所述第二参考电压信号的电压值大于或等于所述第二信号的电压值，且小于所述第一参考电压信号的电压值。
  12. 如权利要求11所述的电压转换电路，其特征在于，所述第一开关晶体管和所述第三开关晶体管为P型晶体管；
    所述第二开关晶体管和所述第四开关晶体管为N型晶体管。
  13. 一种如权利要求1所述的电压转换电路的电压转换方法，包括：
    在所述电压转换电路的信号输入端输入第一电压信号时，所述控制子电路向所述输出子电路输出第一转换控制信号，所述输出子电路在所述第一转换控制信号的控制下输出第三电压信号；以及
    在所述电压转换电路的信号输入端接收到第二电压信号时，所述控制子电路向所述输出子电路输出第二转换控制信号，所述输出子电路在所述第二转换控制信号的控制下输出第四电压信号。
  14. 如权利要求13所述的电压转换方法，其中，所述控制子电路包括：第一控制子电路和第二控制子电路，
    在所述电压转换电路的信号输入端输入第一电压信号时，所述第一控制子电路向所述第二控制子电路输出第一控制信号，所述第二控制子电路在所述第一控制信号的控制下向所述输出子电路输出第一转换控制信号；以及
    在所述电压转换电路的信号输入端输入第二电压信号时，所述第一控制子电路向所述第二控制子电路输出第二控制信号，所述第二控制子电路在所述第二控制信号的控制下向所述输出子电路输出第二转换控制信号。
  15. 如权利要求13所述的电压转换方法，其中，
    所述第一控制子电路包括反向器；所述反向器的输入端与所述信号输入端相连，输出端与所述第二控制子电路的控制端相连；
    所述第二控制子电路包括：第一开关晶体管、第二开关晶体管、第一电阻和第二电阻；其中，
    所述第一开关晶体管的栅极和所述第二开关晶体管的栅极与所述反向器的输出端相连，
    所述第一开关晶体管的源极与用于输入第一参考电压信号的第一参考电压端相连，所述第一开关晶体管的漏极分别与所述第一电阻的第 一端和所述输出子电路的第一控制端相连；
    所述第一电阻的第二端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连；
    所述第二开关晶体管的源极与用于输入第二参考电压信号的第二参考电压端相连，所述第二开关晶体管的漏极分别与所述第二电阻的第一端和所述输出子电路的第二控制端相连；
    所述第二电阻的第二端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连；
    所述输出子电路包括：第三开关晶体管和第四开关晶体管；其中，
    所述第三开关晶体管的栅极与所述第一开关晶体管的漏极相连，所述第三开关晶体管的源极与用于输入第三电压信号的第三参考电压端相连，所述第三开关晶体管的栅极和源极分别与所述第一电阻的第一端和第二端相连，所述第三开关晶体管的漏极和所述第四开关晶体管的漏极与所述信号输出端相连；
    所述第四开关晶体管的栅极与所述第二开关晶体管的漏极相连，所述第四开关晶体管的源极与用于输入第四电压信号的第四参考电压端相连，所述第四开关晶体管的栅极和源极分别与所述第二电阻的第一端和第二端端相连。
  16. 如权利要求13所述的电压转换方法，其中，
    所述控制子电路包括：第一开关晶体管、第二开关晶体管、第一电阻和第二电阻；其中，
    所述第一开关晶体管的栅极和所述第二开关晶体管的栅极与所述控制子电路的输入端相连，
    所述第一开关晶体管的源极与用于输入第一参考电压信号的第一参考电压端相连，所述第一开关晶体管的漏极分别与所述第一电阻的第一端和所述输出子电路的第一控制端相连；
    所述第一电阻的第二端分别与用于输入第三电压信号的第三参考电压端和所述输出子电路的第一输入端相连；
    所述第二开关晶体管的源极与用于输入第二参考电压信号的第二参考电压端相连，所述第二开关晶体管的漏极分别与所述第二电阻的第一端和所述输出子电路的第二控制端相连；
    所述第二电阻的第二端分别与用于输入第四电压信号的第四参考电压端和所述输出子电路的第二输入端相连，
    其中，所述输出子电路包括：第三开关晶体管和第四开关晶体管；其中，
    所述第三开关晶体管的栅极与所述第二开关晶体管的漏极相连，所述第三开关晶体管的源极与用于输入第三电压信号的第三参考电压端相连，所述第三开关晶体管的栅极和源极分别与所述第二电阻的第一端和第二端相连，所述第三开关晶体管的漏极和所述第四开关晶体管的漏极与所述信号输出端相连；
    所述第四开关晶体管的栅极与所述第一开关晶体管的漏极相连，所述第四开关晶体管的源极与用于输入第四电压信号的第四参考电压端相连，所述第四开关晶体管的栅极和源极分别与所述第一电阻的第一端和第二端端相连。
  17. 如权利要求13所述的电压转换方法，其中，
    所述第三电压信号的电压值大于所述第一电压信号的电压值；
    所述第一电压信号的电压值大于所述第二电压信号的电压值；
    所述第二电压信号的电压值大于所述第四电压信号的电压值。
  18. 一种栅极驱动电路，包括：如权利要求1-12任一项所述的电压转换电路。
  19. 一种显示面板，包括：如权利要求18所述的栅极驱动电路。
  20. 一种显示装置，包括：如权利要求19所述的显示面板。
PCT/CN2016/092202 2016-01-04 2016-07-29 电压转换电路、电压转换方法、栅极驱动电路、显示面板及显示装置 WO2017117986A1 (zh)

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