WO2017113441A1 - 液晶显示器 - Google Patents

液晶显示器 Download PDF

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Publication number
WO2017113441A1
WO2017113441A1 PCT/CN2016/070813 CN2016070813W WO2017113441A1 WO 2017113441 A1 WO2017113441 A1 WO 2017113441A1 CN 2016070813 W CN2016070813 W CN 2016070813W WO 2017113441 A1 WO2017113441 A1 WO 2017113441A1
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WO
WIPO (PCT)
Prior art keywords
electrically connected
signal
liquid crystal
crystal display
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/070813
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English (en)
French (fr)
Inventor
郭平昇
张先明
朱立伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/908,250 priority Critical patent/US10102818B2/en
Publication of WO2017113441A1 publication Critical patent/WO2017113441A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the invention relates to a liquid crystal display, in particular to a gate driver on array (GOA).
  • the liquid crystal display of the circuit is a gate driver on array (GOA).
  • LCD monitors have gradually become widely used in various electronic devices such as televisions, mobile phones, digital cameras, computer screens or notebook screens with high-resolution color screens. monitor.
  • a conventional liquid crystal display includes a source driver and a plurality of gate drivers (gate Driver) and LCD panel.
  • the gate driver is equivalent to a shift register (shift Register), the purpose of which is to output a scan signal to the liquid crystal display panel at regular intervals.
  • the source driver charges and discharges the pixel cells to the required voltage during the 21.7 ⁇ s period to display the corresponding gray scale.
  • a technique of fabricating a gate driving circuit on a liquid crystal display panel has been developed.
  • a gate driving circuit and a pixel matrix region are formed directly on the substrate.
  • the gate driving circuit When the clock signal generated by the controller and the start signal are transmitted to the gate driving circuit, the gate driving circuit generates a scanning signal to the pixel unit of the pixel matrix area, and at the same time, the source driver outputs the gray scale voltage to the pixel.
  • the pixel unit of the matrix area is a technique of fabricating a gate driving circuit on a liquid crystal display panel.
  • the substrate may be infiltrated due to inadvertent assembly, causing a short circuit of the controller, thereby causing the substrate to burn.
  • the present invention provides a liquid crystal display including a substrate including a pixel matrix region and a circuit placement region on a first side and a second side of the pixel matrix region.
  • the liquid crystal display further includes: a plurality of GOA circuit units disposed on the circuit placement area, wherein the plurality of GOA circuit units are serially connected for outputting according to a plurality of clock signals and a potential value of the start signal And scanning a signal to the pixel matrix area; a controller, configured to generate a plurality of the clock signal and the start signal; a level adjuster electrically connected to the controller, configured to adjust a plurality of the clocks a signal and a level of the start signal; and an overcurrent protection circuit electrically connected to the level adjuster for outputting an adjustment signal to the one of the plurality of clock signals when the one of the plurality of clock signals is greater than a predetermined value
  • the controller is configured to turn off the liquid crystal display.
  • the plurality of clock signals comprise a first clock signal, a second clock signal and a third clock signal
  • each GOA circuit unit is configured to use the scan signal output by the GOA circuit unit of the previous stage, and the latter
  • the scan signal, the first fixed voltage, the second fixed voltage, the first clock signal, the second clock signal, and the third clock signal output by the stage GOA circuit unit output a scan signal at the output end.
  • the controller when the controller receives the adjustment signal, first switching a plurality of the clock signals and the start signal to the first fixed voltage or the second fixed voltage And then turn off the liquid crystal display.
  • the controller when the controller receives the adjustment signal, first switching a plurality of the clock signals and the start signal to a floating state, and then turning off the liquid crystal display.
  • each GOA circuit unit includes: an input control module, configured to output a control signal at a control node according to the first clock signal and the third clock signal; and output a control module electrically connected to The control node is configured to output the scan signal at the output end according to the control signal and the second clock signal; and a pull-down module electrically connected to the output control module for using the scan The signal is pulled low.
  • the pull-down module includes: a first transistor having a gate electrically connected to the control node, a drain electrically connected to the pull-down driving node, and a source electrically connected to the first fixed voltage; a second transistor having a gate electrically connected to the pull-down driving node, a drain electrically connected to the output terminal, a source electrically connected to the first fixed voltage, and a third transistor having a gate electrically connected thereto
  • the pull-down driving node has a source electrically connected to the first fixed voltage, and a resistor electrically connected to the second fixed voltage and the pull-down driving node respectively.
  • the input control module includes: a fourth transistor having a gate electrically connected to the first clock signal, and a drain electrically connected to the scan signal output by the previous stage GOA circuit unit, The source is electrically connected to the control node; the fifth transistor has a gate electrically connected to the third clock signal, a drain electrically connected to the control node, and a source electrically connected to the second stage The scan signal output by the GOA circuit unit.
  • the output control module includes: a sixth transistor having a gate electrically connected to the second fixed voltage, a drain electrically connected to the control node, and a source electrically connected to the a drain of the third transistor; a seventh transistor having a gate electrically connected to a source of the sixth transistor, a drain electrically connected to the second clock signal, a source electrically connected to the output terminal, and a capacitor having two ends respectively A source and a gate of the seventh transistor are connected.
  • the overcurrent protection circuit is integrated within the level adjuster.
  • the liquid crystal display of the present invention further includes an overcurrent protection circuit.
  • the overcurrent protection circuit is configured to output an adjustment signal to the controller to turn off the liquid crystal display when one of the plurality of clock signals is greater than a predetermined value. In this way, the liquid crystal display is temporarily turned off and presents a black screen, so that the substrate can be prevented from burning.
  • FIG. 1 is a schematic view of a liquid crystal display of the present invention.
  • FIG. 2 is a circuit diagram of a GOA circuit unit SR(n).
  • FIG. 3 is a schematic diagram of an overcurrent protection circuit for determining whether the currents of the clock signals CK1 and CK2 are normal during operation.
  • FIG. 1 is a schematic diagram of a liquid crystal display 10 of the present invention.
  • the liquid crystal display 10 includes a controller 14 and a source driver (source) Driver)16, multiple GOA circuit units (gate driving unit) SR(1) to SR(n), overcurrent protection circuit 30, level adjuster 40, and substrate 20.
  • the substrate 20 has a first side 2031, a second side 2032, and a third side 2033, the first side 2031 and the second side 2032 being parallel to each other, the third side 2033 being perpendicular to the first side 2031 and the second side 2032.
  • the substrate 20 includes a pixel matrix region 203 and circuit placement regions 201 on both sides of the pixel matrix region 203.
  • a plurality of GOA circuit units SR(1) to SR(n) are placed in the circuit placement area 201.
  • the source driver 16 is located on the third side 2033 of the substrate 20 and is electrically connected to the pixel unit of the pixel matrix region 203 through the flexible circuit board 24.
  • the GOA circuit units SR(1) to SR(n) generate scan signals to the pixels.
  • the pixel driver of the matrix region 203 outputs the gray scale voltage to the pixel unit of the pixel matrix region 203.
  • the plurality of GOA circuit units SR(1) to SR(n) shown in FIG. 1 are serial connections.
  • the plurality of GOA circuit units SR(1) to SR(n) are a one-to-one multi-line pixel unit connected to the pixel matrix region 203.
  • a 1024 ⁇ The 768 resolution liquid crystal display panel has 768 GOA circuit units SR, and each of the GOA circuit units SR(1) to SR(n) is connected to one row of pixel units, n is 768.
  • the GOA circuit unit SR(n) is configured to output a scan signal from the output terminal G(n) to the GOA circuit corresponding to the nth row of the pixel matrix region 203 according to the potential values of the clock signal CK(n) and the start signal STV(n).
  • the level adjuster 40 is electrically connected to the controller 14 for adjusting the levels of the plurality of clock signals CK1-CKn and the start signal STV.
  • the overcurrent protection circuit 30 is electrically connected to the level adjuster 40 for outputting the adjustment signal AD to the controller 14 to turn off the liquid crystal display 10 when one of the plurality of clock signals CK1-CKn is greater than a predetermined value.
  • FIG. 2 is a circuit diagram of the GOA circuit unit SR(n). Since the circuit structure of each GOA circuit unit SR is the same, the following only uses the circuit structure of the GOA circuit unit SR(n) as an explanation.
  • the GOA circuit unit SR(n) of the present embodiment is driven by three clock signals CK1-CK3, but the GOA circuit unit SR(n) driven using other numbers of clock signals is also within the scope of the present invention.
  • each stage of the GOA circuit unit SR(n) is used for the scan signal G(n-1) outputted by the previous stage GOA circuit unit SR(n-1), and the subsequent stage GOA circuit unit SR(n).
  • Each level of the GOA circuit unit SR(n) includes an input control module 100, an output control module 200, and a pull down module 300.
  • the input control module 100 is configured to output a control signal Q(n) at the control node Q according to the first clock signal CK1 and the third clock signal CK3.
  • the output control module 200 is electrically connected to the control node Q for outputting the scan signal G(n) at the output terminal OUT according to the control signal Q(n) and the second clock signal CK2.
  • the pull-down module 300 is electrically connected to the output control module 200 for pulling the scan signal G(n) to a low level.
  • the pull-down module 300 includes a first transistor T1, a second transistor T2, a third transistor T3, and a resistor R1.
  • the gate of the first transistor T1 is electrically connected to the control node Q, and the drain thereof is electrically connected to the pull-down driving node P, and the source thereof is electrically connected to the first fixed voltage VGL.
  • the gate of the second transistor T2 is electrically connected to the pull-down driving node P, the drain thereof is electrically connected to the output terminal OUT, and the source thereof is electrically connected to the first fixed voltage VGL.
  • the gate of the third transistor T3 is electrically connected to the pull-down driving node P, and the source thereof is electrically connected to the first fixed voltage VGL. Both ends of the resistor R1 are electrically connected to the second fixed voltage VGH and the pull-down drive node P, respectively.
  • the input control module 100 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is electrically connected to the first clock signal CK1, and the drain thereof is electrically connected to the scan signal G(n-1) outputted by the previous stage GOA circuit unit SR(n-1), and its source is electrically Connect to control node Q.
  • the gate of the fifth transistor T5 is electrically connected to the third clock signal CK3, the drain thereof is electrically connected to the control node Q, and the source thereof is electrically connected to the scan signal G output by the first-stage GOA circuit unit SR(n+1) ( n+1).
  • the output control module 200 includes a sixth transistor T6, a seventh transistor T7, and a capacitor C1.
  • the gate of the sixth transistor T6 is electrically connected to the second fixed voltage VGH, and the drain thereof is electrically connected to the control node Q, and the source thereof is electrically connected to the drain of the third transistor T3.
  • the gate of the seventh transistor T7 is electrically connected to the source of the sixth transistor T6, the drain thereof is electrically connected to the second clock signal CK2, and the source thereof is electrically connected to the output terminal OUT. Both ends of the capacitor C1 are respectively connected to the source and the gate of the seventh transistor T7.
  • the present invention is not limited to the circuit configuration of the GOA circuit unit SR(n) shown in Fig. 2.
  • Other GOA circuit units SR(n) operating using a plurality of clock signals CK1-CKn are also within the scope of the present invention.
  • FIG. 3 is a schematic diagram of the overcurrent protection circuit for determining whether the currents of the clock signals CK1 and CK2 are normal during operation.
  • the overcurrent protection circuit 30 is electrically connected to the level adjuster 40.
  • FIG. 3 illustrates the current variation during operation of the clock signal CK1.
  • the current value of time period is about 10 ⁇ 40mA.
  • the normal and short-circuited clock signal CK2 is during its operation (normal time)
  • the current value of period is approximately 0 mA.
  • the overcurrent protection circuit 30 of the present embodiment can set the predetermined value Ith to 30 mA, and when the current value of one of the clock signals CK1 CKCKn during operation exceeds the predetermined value Ith, the output adjustment signal AD is output to the controller. 14.
  • the controller 14 receives the adjustment signal AD, the plurality of clock signals CK1-CKn and the start signal STV are first switched to the first fixed voltage VGH or the second fixed VGL voltage, and then the liquid crystal display 10 is turned off, or the controller 14 When receiving the adjustment signal AD, first switching the plurality of clock signals CK1-CKn and the start signal STV to a floating state (floating) State), then turn off the liquid crystal display 10.
  • the predetermined value Ith of the embodiment is 30 mA
  • the person skilled in the art can adjust the predetermined value Ith according to actual needs, for example, 10 mA, 20 mA, 40 mA.
  • the liquid crystal display of the present invention is not limited to the above embodiments.
  • the overcurrent protection circuit 30 can also be integrated into the level adjuster 40, and the operation principle is the same.
  • the liquid crystal display of the present invention further includes an overcurrent protection circuit.
  • the overcurrent protection circuit is configured to output an adjustment signal to the controller to turn off the liquid crystal display when one of the plurality of clock signals is greater than a predetermined value. In this way, the liquid crystal display is temporarily turned off and presents a black screen, so that the substrate can be prevented from burning.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶显示器（10），其包括基板（20），所述基板（20）包含像素矩阵区（203）以及位于所述像素矩阵区（203）第一侧（2031）和第二侧（2032）的电路放置区（201）。所述液晶显示器（10）另包含：多个GOA电路单元（SR(1) -SR(n)），设于所述电路放置区（201）上，多个所述GOA电路单元（SR(1) -SR(n)）是串连连接，用来依据多个时钟信号（CK1-CKn）和起始信号（STV）的电位值，输出扫描信号予所述像素矩阵区（203）；控制器（14），用于产生多个所述时钟信号（CK1-CKn）和所述起始信号（STV）；位准调整器（40），电性连接于所述控制器（14），用于调整多个所述时钟信号（CK1-CKn）和所述起始信号（STV）的电平；及过电流保护电路（30），电性连接于所述位准调整器（40），用来于多个所述时钟信号（CK1-CKn）其中之一大于预定值时，输出调整信号（AD）至所述控制器（14）以使所述液晶显示器（10）关闭。如此一来，所述液晶显示器（10）会暂时关闭，而呈现黑画面，因此能避免基板（20）烧毁。

Description

液晶显示器 技术领域
本发明是有关于一种液晶显示器，尤指一种使用栅极驱动 (Gate driver on array，GOA) 电路的液晶显示器。
 背景技术
功能先进的显示器渐成为现今消费电子产品的重要特色，其中液晶显示器已经逐渐成为各种电子设备如电视、行动电话、数字相机、计算机屏幕或笔记型计算机屏幕所广泛应用具有高分辨率彩色屏幕的显示器。
传统的液晶显示器包含源极驱动器、多个栅极驱动器(gate driver)以及液晶显示面板。在目前的液晶显示面板设计中，栅极驱动器等效上为移位寄存器(shift register)，其目的即每隔一固定间隔输出扫描讯号至液晶显示面板。液晶显示面板是以红色、绿色、蓝色像素的顺序横向排列。以一个1024 × 768分辨率的液晶显示面板以及60Hz的更新频率为例，每一个画面的显示时间约为1/60=16.67ms。所以每一个扫描信号的脉波约为16.67ms/768=21.7μs。而源极驱动器则在这21.7μs的时间内，将像素单元充放电到所需的电压，以显示出相对应的灰阶。
为了制造窄边框的液晶显示器，目前已开发一种将栅极驱动电路制作在液晶显示面板上的技术。栅极驱动电路和像素矩阵区直接形成于该基板上。当控制器产生的时钟信号以及起始信号传送至栅极驱动电路时，栅极驱动电路会产生扫描信号至像素矩阵区的像素单元，在此同时，源极驱动器就会输出灰阶电压至像素矩阵区的像素单元。
由于控制器安装于基板的位置是对应于胶框，因此基板会因为组装不慎使得水气渗入，导致控制器发生短路，进而让基板烧毁。
 技术问题
为了解决现有技术基板会烧毁的技术问题，有必要提供一种避免基板烧毁的液晶显示器。
 技术解决方案
本发明提供一种液晶显示器，其包括基板，所述基板包含像素矩阵区以及位于所述像素矩阵区第一侧和第二侧的电路放置区。所述液晶显示器另包含：多个GOA电路单元，设于所述电路放置区上，多个所述GOA电路单元是串连连接，用来依据多个时钟信号和起始信号的电位值，输出扫描信号予所述像素矩阵区；控制器，用于产生多个所述时钟信号和所述起始信号；位准调整器，电性连接于所述控制器，用于调整多个所述时钟信号和所述起始信号的电平；及过电流保护电路，电性连接于所述位准调整器，用来于多个所述时钟信号其中之一大于预定值时，输出调整信号至所述控制器以使所述液晶显示器关闭。
依据本发明的实施例，多个所述时钟信号包含第一时钟信号、第二时钟信号及第三时钟信号，每一GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一固定电压、第二固定电压、所述第一时钟信号、所述第二时钟信号及所述第三时钟信号，在输出端输出扫描信号。
依据本发明的实施例，当所述控制器接收到所述调整信号时，先将多个所述时钟信号和所述起始信号切换至所述第一固定电压或是所述第二固定电压，再关闭所述液晶显示器。
依据本发明的实施例，当所述控制器接收到所述调整信号时，先将多个所述时钟信号和所述起始信号切换至浮动状态，再关闭所述液晶显示器。
依据本发明的实施例，每一GOA电路单元包含：输入控制模块，用来依据所述第一时钟信号和所述第三时钟信号，在控制节点输出控制信号；输出控制模块，电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号；及下拉模块，电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平。
依据本发明的实施例，所述下拉模块包含：第一晶体管，其栅极电性连接所述控制节点，其漏极电性连接下拉驱动节点，其源极电性连接第一固定电压；第二晶体管，其栅极电性连接所述下拉驱动节点，其漏极电性连接所述输出端，其源极电性连接所述第一固定电压；第三晶体管，其栅极电性连接所述下拉驱动节点，其源极电性连接所述第一固定电压；及电阻，其两端分别电性连接第二固定电压和所述下拉驱动节点。
依据本发明的实施例，所述输入控制模块包含：第四晶体管，其栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号，其源极电性连接所述控制节点；第五晶体管，其栅极电性连接所述第三时钟信号，其漏极电性连接所述控制节点，其源极电性连接所述后一级GOA电路单元输出的扫描信号。
依据本发明的实施例，所述输出控制模块包含：第六晶体管，其栅极电性连接所述第二固定电压，其漏极电性连接所述控制节点，其源极电性连接所述第三晶体管的漏极； 第七晶体管，其栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端；及电容，其两端分别连接所述第七晶体管的源极和栅极。
依据本发明的实施例，所述过电流保护电路集成于所述位准调整器之内。
 有益效果
相较于现有技术，本发明液晶显示器进一步包括一过电流保护电路。所述过电流保护电路用于多个所述时钟信号其中之一大于预定值时，输出调整信号至所述控制器以使所述液晶显示器关闭。如此一来，所述液晶显示器会暂时关闭，而呈现黑画面，因此能避免基板烧毁。
 附图说明
图1是本发明液晶显示器的示意图。
图2是GOA电路单元SR(n)的电路图。
图3是过电流保护电路用于判断时钟信号CK1和CK2在工作期间电流是否正常的示意图。
 本发明的最佳实施方式
请参阅图1，图1是本发明液晶显示器10的示意图。液晶显示器10包含控制器14、源极驱动器(source driver)16、多个GOA电路单元(gate driving unit) SR(1)~SR(n)、过电流保护电路30、位准调整器40以及基板20。基板20具有第一侧2031、第二侧2032和第三侧2033，第一侧2031和第二侧2032彼此平行，第三侧2033垂直于第一侧2031和第二侧2032。基板20包含像素矩阵区203以及位于像素矩阵区203的两侧的电路放置区201。多个GOA电路单元SR(1)~SR(n)放置在电路放置区201。源极驱动器16位于基板20的第三侧2033，通过软性电路板24电性连接到像素矩阵区203的像素单元。当控制器14产生的时钟信号CK1-CKn以及起始信号STV传送至GOA电路单元SR(1)~SR(n)时，GOA电路单元SR(1)~SR(n)会产生扫描信号至像素矩阵区203的像素单元，在此同时，源极驱动器16就会输出灰阶电压至像素矩阵区203的像素单元。
图1所示的多个GOA电路单元SR(1)~SR(n)是串连连接。多个GOA电路单元SR(1)~SR(n)是一对一的连接到像素矩阵区203的多行像素单元。举例来说，一个1024 × 768分辨率的液晶显示面板具有768个GOA电路单元SR，每一个GOA电路单元SR(1)~SR(n)连接到一行像素单元，n为768。GOA电路单元SR(n)用来依据时钟信号CK(n)和起始信号STV(n)的电位值，从输出端G(n)输出扫描信号予像素矩阵区203对应第n行的GOA电路单元SR(n)。位准调整器40电性连接于控制器14，用于调整多个时钟信号CK1-CKn和起始信号STV的电平。过电流保护电路30电性连接于位准调整器40，用来于多个时钟信号CK1-CKn其中之一大于预定值时，输出调整信号AD至控制器14以使液晶显示器10关闭。
请参阅图2，图2是GOA电路单元SR(n)的电路图。由于每一GOA电路单元SR的电路结构相同，因此以下仅采用GOA电路单元SR(n)的电路结构做为说明。本实施例GOA电路单元SR(n)是采用三个时钟信号CK1-CK3来驱动，但使用其它数量的时钟信号来驱动的GOA电路单元SR(n)亦属于本发明的范畴。依据本实施例，每一级GOA电路单元SR(n)用来依据前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)、后一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)、第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3，在输出端OUT输出扫描信号G(n)。每一级GOA电路单元SR(n)包含输入控制模块100、输出控制模块200和下拉模块300。输入控制模块100用来依据第一时钟信号CK1和第三时钟信号CK3，在控制节点Q输出控制信号Q(n)。输出控制模块200电性连接于控制节点Q，用来依据控制信号Q(n)和第二时钟信号CK2，在输出端OUT输出扫描信号G(n)。下拉模块300电性连接输出控制模块200，用来将扫描信号G(n)下拉至低电平。
下拉模块300包含第一晶体管T1、第二晶体管T2、第三晶体管T3和电阻R1。第一晶体管T1的栅极电性连接控制节点Q，其漏极电性连接下拉驱动节点P，其源极电性连接第一固定电压VGL。第二晶体管T2的栅极电性连接下拉驱动节点P，其漏极电性连接输出端OUT，其源极电性连接第一固定电压VGL。第三晶体管T3的栅极电性连接下拉驱动节点P，其源极电性连接第一固定电压VGL。电阻R1的两端分别电性连接第二固定电压VGH和下拉驱动节点P。
输入控制模块100包含第四晶体管T4和第五晶体管T5。第四晶体管T4的栅极电性连接第一时钟信号CK1，其漏极电性连接前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)，其源极电性连接控制节点Q。第五晶体管T5的栅极电性连接第三时钟信号CK3，其漏极电性连接控制节点Q，其源极电性连接后一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)。
输出控制模块200包含第六晶体管T6、第七晶体管T7和电容C1。第六晶体管T6的栅极电性连接第二固定电压VGH，其漏极电性连接控制节点Q，其源极电性连接第三晶体管T3的漏极。第七晶体管T7的栅极电性连接第六晶体管T6的源极，其漏极电性连接第二时钟信号CK2，其源极电性连接输出端OUT。电容C1的两端分别连接第七晶体管T7的源极和栅极。
本发明并不以图2所示的GOA电路单元SR(n)的电路结构为限，其它使用多个时钟信号CK1-CKn运作的GOA电路单元SR(n)亦属于本发明的范畴。
请参阅图3，图3是过电流保护电路用于判断时钟信号CK1和CK2在工作期间电流是否正常的示意图。过电流保护电路30电性连接于位准调整器40。图3所绘示的是时钟信号CK1的工作期间的电流变化。当时钟信号CK1发生短路导致输出电流不正常时，不正常的时钟信号CK1在其工作期间(normal time period)的电流值大约为10~40mA。相比之下，而正常而没有短路的时钟信号CK2在其工作期间(normal time period)的电流值大约为0mA。因此本实施例过电流保护电路30可以设定预定值Ith为30mA时，当侦测到时钟信号CK1~CKn其中之一在工作期间的电流值超过预定值Ith时，输出调整信号AD给控制器14。当控制器14接收到调整信号AD时，先将多个时钟信号CK1-CKn和起始信号STV切换至第一固定电压VGH或是第二固定VGL电压，再关闭液晶显示器10，或者控制器14接收到调整信号AD时，先将多个时钟信号CK1-CKn和起始信号STV切换至浮动状态(floating state)，再关闭液晶显示器10。
请注意，虽然本实施例的预定值Ith是30mA，但是本领域技术人员可依据实际需求调整该预定值Ith，例如10mA、20mA、40mA。本发明液晶显示器并不限于以上实施方式所述，例如：过电流保护电路30也可以集成于位准调整器40之内，其运作原理相同。
综合以上，本发明液晶显示器进一步包括一过电流保护电路。所述过电流保护电路用于多个所述时钟信号其中之一大于预定值时，输出调整信号至所述控制器以使所述液晶显示器关闭。如此一来，所述液晶显示器会暂时关闭，而呈现黑画面，因此能避免基板烧毁。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种液晶显示器，其包括：
    基板，包含像素矩阵区以及位于所述像素矩阵区第一侧和第二侧的电路放置区；
    多个GOA电路单元，设于所述电路放置区上，多个所述GOA电路单元是串连连接，用来依据多个时钟信号和起始信号的电位值，输出扫描信号予所述像素矩阵区；
    控制器，用于产生多个所述时钟信号和所述起始信号；
    位准调整器，电性连接于所述控制器，用于调整多个所述时钟信号和所述起始信号的电平；及
    过电流保护电路，电性连接于所述位准调整器，用来于多个所述时钟信号其中之一大于预定值时，输出调整信号至所述控制器以使所述液晶显示器关闭；
    其中多个所述时钟信号包含第一时钟信号、第二时钟信号及第三时钟信号，每一GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一固定电压、第二固定电压、所述第一时钟信号、所述第二时钟信号及所述第三时钟信号，在输出端输出扫描信号，当所述控制器接收到所述调整信号时，先将多个所述时钟信号和所述起始信号切换至浮动状态，再关闭所述液晶显示器。
  2. 根据权利要求1所述的液晶显示器，其中当所述控制器接收到所述调整信号时，先将多个所述时钟信号和所述起始信号切换至所述第一固定电压或是所述第二固定电压，再关闭所述液晶显示器。
  3. 据权利要求1所述的液晶显示器，其中每一GOA电路单元包含：
    输入控制模块，用来依据所述第一时钟信号和所述第三时钟信号，在控制节点输出控制信号；
    输出控制模块，电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号；及
    下拉模块，电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平。
  4. 根据权利要求3所述的液晶显示器，其中所述下拉模块包含：
    第一晶体管，其栅极电性连接所述控制节点，其漏极电性连接下拉驱动节点，其源极电性连接第一固定电压；
    第二晶体管，其栅极电性连接所述下拉驱动节点，其漏极电性连接所述输出端，其源极电性连接所述第一固定电压；
    第三晶体管，其栅极电性连接所述下拉驱动节点，其源极电性连接所述第一固定电压；及
    电阻，其两端分别电性连接第二固定电压和所述下拉驱动节点。
  5. 如权利要求4所述的液晶显示器，其中所述输入控制模块包含：
    第四晶体管，其栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号，其源极电性连接所述控制节点；
    第五晶体管，其栅极电性连接所述第三时钟信号，其漏极电性连接所述控制节点，其源极电性连接所述后一级GOA电路单元输出的扫描信号。
  6. 如权利要求5所述的液晶显示器，其中所述输出控制模块包含：
    第六晶体管，其栅极电性连接所述第二固定电压，其漏极电性连接所述控制节点，其源极电性连接所述第三晶体管的漏极；
    第七晶体管，其栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端；及
    电容，其两端分别连接所述第七晶体管的源极和栅极。
  7. 根据权利要求1所述的液晶显示器，其中所述过电流保护电路集成于所述位准调整器之内。
  8. 一种液晶显示器，其包括基板，所述基板包含像素矩阵区以及位于所述像素矩阵区第一侧和第二侧的电路放置区，其中所述液晶显示器另包含：
    多个GOA电路单元，设于所述电路放置区上，多个所述GOA电路单元是串连连接，用来依据多个时钟信号和起始信号的电位值，输出扫描信号予所述像素矩阵区；
    控制器，用于产生多个所述时钟信号和所述起始信号；
    位准调整器，电性连接于所述控制器，用于调整多个所述时钟信号和所述起始信号的电平；及
    过电流保护电路，电性连接于所述位准调整器，用来于多个所述时钟信号其中之一大于预定值时，输出调整信号至所述控制器以使所述液晶显示器关闭。
  9. 根据权利要求8所述的液晶显示器，其中 多个所述时钟信号包含第一时钟信号、第二时钟信号及第三时钟信号，每一GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、后一级GOA电路单元输出的扫描信号、第一固定电压、第二固定电压、所述第一时钟信号、所述第二时钟信号及所述第三时钟信号，在输出端输出扫描信号。
  10. 根据权利要求9所述的液晶显示器，其中当所述控制器接收到所述调整信号时，先将多个所述时钟信号和所述起始信号切换至所述第一固定电压或是所述第二固定电压，再关闭所述液晶显示器。
  11. 根据权利要求9所述的液晶显示器，其中当所述控制器接收到所述调整信号时，先将多个所述时钟信号和所述起始信号切换至浮动状态，再关闭所述液晶显示器。
  12. 根据权利要求9所述的液晶显示器，其中每一GOA电路单元包含：
    输入控制模块，用来依据所述第一时钟信号和所述第三时钟信号，在控制节点输出控制信号；
    输出控制模块，电性连接于所述控制节点，用来依据所述控制信号和所述第二时钟信号，在所述输出端输出所述扫描信号；及
    下拉模块，电性连接所述输出控制模块，用来将所述扫描信号下拉至低电平。
  13. 根据权利要求12所述的液晶显示器，其中所述下拉模块包含：
    第一晶体管，其栅极电性连接所述控制节点，其漏极电性连接下拉驱动节点，其源极电性连接第一固定电压；
    第二晶体管，其栅极电性连接所述下拉驱动节点，其漏极电性连接所述输出端，其源极电性连接所述第一固定电压；
    第三晶体管，其栅极电性连接所述下拉驱动节点，其源极电性连接所述第一固定电压；及
    电阻，其两端分别电性连接第二固定电压和所述下拉驱动节点。
  14. 如权利要求13所述的液晶显示器，其中所述输入控制模块包含：
    第四晶体管，其栅极电性连接所述第一时钟信号，其漏极电性连接所述前一级GOA电路单元输出的扫描信号，其源极电性连接所述控制节点；
    第五晶体管，其栅极电性连接所述第三时钟信号，其漏极电性连接所述控制节点，其源极电性连接所述后一级GOA电路单元输出的扫描信号。
  15. 如权利要求13所述的液晶显示器，其中所述输出控制模块包含：
    第六晶体管，其栅极电性连接所述第二固定电压，其漏极电性连接所述控制节点，其源极电性连接所述第三晶体管的漏极；
    第七晶体管，其栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第二时钟信号，其源极电性连接所述输出端；及
    电容，其两端分别连接所述第七晶体管的源极和栅极。
  16. 根据权利要求8所述的液晶显示器，其中所述过电流保护电路集成于所述位准调整器之内。
PCT/CN2016/070813 2015-12-31 2016-01-13 液晶显示器 Ceased WO2017113441A1 (zh)

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