WO2017024651A1 - 避免goa基板烧毁的液晶显示器 - Google Patents

避免goa基板烧毁的液晶显示器 Download PDF

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Publication number
WO2017024651A1
WO2017024651A1 PCT/CN2015/089154 CN2015089154W WO2017024651A1 WO 2017024651 A1 WO2017024651 A1 WO 2017024651A1 CN 2015089154 W CN2015089154 W CN 2015089154W WO 2017024651 A1 WO2017024651 A1 WO 2017024651A1
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Prior art keywords
electrically connected
gate driving
gate
liquid crystal
signal
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PCT/CN2015/089154
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English (en)
French (fr)
Inventor
郭平昇
朱立伟
陈明暐
曹丹
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深圳市华星光电技术有限公司
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Priority to US14/891,191 priority Critical patent/US20170213513A1/en
Publication of WO2017024651A1 publication Critical patent/WO2017024651A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/046—Dealing with screen burn-in prevention or compensation of the effects thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the invention relates to a liquid crystal display, in particular to a gate driving substrate (Gate driver on Array, GOA) LCD display.
  • GOA gate driving substrate
  • LCD monitors have become widely used in a variety of electronic devices such as televisions, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens.
  • PDAs personal digital assistants
  • a display with a high resolution color screen is a display with a high resolution color screen.
  • a conventional liquid crystal display includes a source driver and a gate driver (gate Driver) and LCD panel.
  • the gate driver is equivalent to a shift register, logic circuit (logic Circuit), electric shifter (Level shifter), and digital buffer amplifier (Digital Buffer), the purpose of the shift register is to output the scan signal to the liquid crystal display panel at regular intervals.
  • the pixels are arranged in RGB horizontal arrangement.
  • the source driver charges and discharges the pixel cells to the required voltage during the 21.7 ⁇ s period to display the corresponding gray scale.
  • the liquid crystal display includes a controller, a source driver, and a gate driving unit (gate driving Unit) and GOA substrate.
  • the GOA substrate includes a pixel array region.
  • the transmission line of the GOA control signal is on both sides of the panel, It is just the location where the sealant is coated.
  • the sealant may cause moisture infiltration due to problems such as aging, poor quality, poor coating, etc., causing the control signals of the GOA circuit to be short-circuited with each other, thereby causing the panel to burn out.
  • the invention provides a liquid crystal display comprising a gate drive (Gate driver on An array of GOA substrates, the GOA substrate comprising a pixel array region and a circuit placement region on a first side and a second side of the pixel array region, the first side and the second side being parallel to each other, the liquid crystal
  • the display further includes: a plurality of gate driving units disposed on the circuit placement area, wherein the plurality of gate driving units are serially connected, and are configured to output a scanning signal according to a potential value of a clock signal and a control signal.
  • a detecting circuit electrically connected to the gate driving unit of the last stage for using the gate driving unit of the last stage or the gate driving unit of the last second stage Or when the scan signal output by the gate driving unit of the third stage is less than a predetermined value, outputting an adjustment signal; and a level adjuster electrically connected to the plurality of the gate driving unit and the The detecting circuit is configured to output a plurality of clock signals of a low level and a control signal of a low level to the plurality of gate driving units when receiving the adjusting signal.
  • the liquid crystal display further includes a source driver
  • the GOA substrate further includes a third side, the third side is perpendicular to the first side and the second side, and the plurality of A source driver is located on the third side.
  • each gate driving unit includes: a first transistor having a drain electrically connected to the clock signal, a source electrically connected to the output terminal for outputting the scan signal, and a gate thereof Electrically connected to a trigger node; a second transistor having a drain electrically connected to the clock signal, a source electrically connected to the control terminal to output the control signal, and a gate electrically connected to the trigger a third transistor having a drain electrically connected to the output terminal, a source electrically connected to a power supply voltage, and a fourth transistor having a drain electrically connected to the trigger node and having a source The connection is electrically connected to the power supply voltage, and the gate thereof is electrically connected to the gate of the third transistor.
  • the level adjuster when the level adjuster outputs a plurality of clock signals of a low level and a control signal of a low level to a plurality of the gate driving units, the plurality of the gate driving units are stopped.
  • the scan signal is output.
  • a plurality of clock signals of a high level and a control signal of a high level are output to a plurality of the gate driving units, so that The plurality of gate driving units output the scan signal to the pixel array region.
  • the invention provides a liquid crystal display comprising a gate drive (Gate driver on An array of GOA substrates, the GOA substrate comprising a pixel array region and a circuit placement region on a first side and a second side of the pixel array region, the first side and the second side being parallel to each other, the liquid crystal
  • the display further includes: a plurality of gate driving units disposed on the circuit placement area, wherein the plurality of gate driving units are serially connected, and are configured to output a scanning signal according to a potential value of a clock signal and a control signal.
  • a pixel array area a detecting circuit electrically connected to the gate driving unit of the last stage, for outputting an adjustment signal when an output signal of the gate driving unit of the last stage is less than a predetermined value
  • a level adjuster electrically connected to the plurality of the gate driving unit and the detecting circuit, configured to output a plurality of clock signals of a low level and a low level when receiving the adjusting signal The control signal is applied to a plurality of the gate drive units.
  • the liquid crystal display further includes a source driver
  • the GOA substrate further includes a third side, the third side is perpendicular to the first side and the second side, and the plurality of A source driver is located on the third side.
  • the liquid crystal display further includes a flexible circuit board for electrically connecting the plurality of the source drivers and the pixel array region.
  • each gate driving unit includes: a first transistor having a drain electrically connected to the clock signal, a source electrically connected to the output terminal for outputting the scan signal, and a gate thereof Electrically connected to a trigger node; a second transistor having a drain electrically connected to the clock signal, a source electrically connected to the control terminal to output the control signal, and a gate electrically connected to the trigger a third transistor having a drain electrically connected to the output terminal, a source electrically connected to a power supply voltage, and a fourth transistor having a drain electrically connected to the trigger node and having a source The connection is electrically connected to the power supply voltage, and the gate thereof is electrically connected to the gate of the third transistor.
  • the output signal is output by the gate driving unit of the last stage or the gate driving unit of the last second stage or the gate driving unit of the last third stage Control signal.
  • the output signal is triggered by the gate driving unit of the last stage or the gate driving unit of the last second stage or the gate driving unit of the last third stage The signal of the node.
  • the level adjuster when the level adjuster outputs a plurality of clock signals of a low level and a control signal of a low level to a plurality of the gate driving units, the plurality of the gate driving units are stopped.
  • the scan signal is output.
  • a plurality of clock signals of a high level and a control signal of a high level are output to a plurality of the gate driving units, so that The plurality of gate driving units output the scan signal to the pixel array region.
  • the detection circuit is integrated within the level adjuster.
  • the liquid crystal display of the present invention further includes a detecting circuit.
  • the detecting circuit is configured to output an adjustment signal when an output signal of the gate driving unit of the last stage is less than a predetermined value.
  • the level adjuster After receiving the adjustment signal, the level adjuster outputs a plurality of low-level clock signals and a low-level control signal to the plurality of gate driving units, so that the plurality of the gate driving units Stop outputting the scan signal, At the same time, the data transmission is turned off. In this way, the liquid crystal display is temporarily turned off and presents a black screen, so that the GOA substrate can be prevented from being burnt.
  • FIG. 1 is a schematic view of a liquid crystal display using a gate drive substrate of the present invention.
  • FIG. 2 is a partial circuit diagram of a gate driving unit.
  • FIG. 3 is a schematic diagram of the detection circuit and the level adjuster of FIG. 1.
  • FIG. 4 is a schematic diagram of a detection circuit for determining an output signal of a gate drive unit of a final stage.
  • FIG. 1 is a gate driver (Gate driver on) according to the present invention.
  • Array, GOA Schematic of a liquid crystal display 10 of a substrate.
  • the liquid crystal display 10 includes a controller 14, a source driver 16, and a plurality of gate driving units (gate Driving unit) 18(1) to 18(n), detection circuit 30, and GOA substrate 20.
  • the GOA substrate 20 has a first side 2031, a second side 2032, and a third side 2033, the first side 2031 and the second side 2032 being parallel to each other, the third side 2033 being perpendicular to the first side 2031 and the second side 2032.
  • the GOA substrate 20 includes a pixel array region 203 and circuit placement regions 201 on both sides of the pixel array region 203.
  • Multiple gate drive units 18(1) ⁇ 18(n) (also known as GOA The circuit unit) is placed in the circuit placement area 201.
  • the source driver 16 is located on the third side 2033 of the GOA substrate 20, and is electrically connected to the pixel unit of the pixel array region 203 through the flexible circuit board 24.
  • the gate driving units 18(1) to 18(n) When the clock signal generated by the controller 14 and the GOA control signal are transmitted to the gate driving units 18(1) to 18(n), the gate driving units 18(1) to 18(n) generate a scanning signal to the pixel array region.
  • the source driver 16 outputs a gray scale voltage to the pixel unit of the pixel array region 203.
  • the plurality of gate drive units 18(1) to 18(n) shown in FIG. 1 are connected in series. Further, the plurality of gate driving units 18(1) to 18(n) are a plurality of rows of pixel units connected to the pixel array region 203 one-to-one. For example, a 1024 ⁇
  • the 768 resolution liquid crystal display panel has 768 gate drive units 18, and each gate drive unit 18(1) ⁇ 18(n) is connected to a row of pixel units, n is 768.
  • the gate driving unit 18(n) is configured to output a scan signal from the output terminal G(n) to the gate of the nth row corresponding to the pixel array region 203 according to the potential values of the clock signal CK(n) and the control signal STV(n). Drive unit 18(n).
  • FIG. 2 is a partial circuit diagram of the gate driving unit 18(n). Since the circuit structure of each of the gate driving units 18 is the same, only the circuit structure of the gate driving unit 18(n) will be described below.
  • the gate driving unit 18(n) includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the drain of the first transistor T1 is electrically connected to the clock signal CK(n), the source thereof is electrically connected to the output terminal G(n) to output a scan signal, and the gate thereof is electrically connected to the trigger node Q(n).
  • the drain of the second transistor T2 is electrically connected to the clock signal CK(n), the source thereof is electrically connected to the control terminal STV(n) to output a control signal, and the gate thereof is electrically connected to the trigger node Q(n).
  • the drain of the third transistor T3 is electrically connected to the output terminal G(n), and the source thereof is electrically connected to the power supply voltage Vss.
  • the drain of the fourth transistor T4 is electrically connected to the trigger node Q(n), the source thereof is electrically connected to the power supply voltage Vss, and the gate thereof is electrically connected to the gate of the third transistor T3.
  • the first transistor T1 and the second transistor T2 are both turned on, so that the high-level clock signal CK(n) is turned on to the output terminal G(n) and the control End STV(n).
  • the scan signal outputted by the output terminal G(n) and the control signal outputted by the control terminal STV(n) are both at a high level.
  • both the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 and the fourth transistor T4 are both turned on and the power supply voltage Vss is turned on. .
  • the scan signal output from the output terminal G(n) is at a low level.
  • FIG. 3 is a schematic diagram of the detection circuit and the level adjuster of FIG. 1.
  • 4 is a schematic diagram of a detection circuit for determining an output signal GOA_FB of a gate drive unit of a final stage.
  • the detecting circuit 30 is electrically connected to the gate driving unit 18(n) of the last stage for outputting the GOA_FB_L (or GOA_FB_R) of the gate driving unit 18(n) of the last stage to be smaller than a predetermined value Vth.
  • GOA_FB_L or GOA_FB_R
  • the output signal GOA_FB_L (or GOA_FB_R) is the scan signal G(n) of the gate drive unit 18(n) of the last stage, or the control signal STV of the gate drive unit 18(n) of the last stage ( n), or the signal of the trigger node Q(n) of the gate drive unit 18(n) of the last stage.
  • the level adjuster 40 is electrically connected to the plurality of gate driving units 18(1) ⁇ 18(n) and the detecting circuit 30, and outputs a plurality of clock signals CK of a low level when receiving the adjusting signal. (1) ⁇ CK(n) and the low level control signals STV(1) to STV(n) are supplied to the plurality of gate driving units 18(1) to 18(n).
  • the level adjuster 40 When the level adjuster 40 outputs a plurality of low-level clock signals CK(1) to CK(n) and low-level control signals STV(1) to STV(n) to the plurality of gate driving units 18 (1) When ⁇ 18(n), the plurality of gate driving units 18(1) to 18(n) stop outputting the scanning signals. When the level adjuster 40 does not receive the adjustment signal, it outputs a plurality of high level clock signals CK(1) ⁇ CK(n) and a high level control signal STV(1) ⁇ STV(n) to The plurality of gate driving units 18(1) to 18(n) cause the plurality of gate driving units 18(1) to 18(n) to output the scanning signals to the pixel array region 203.
  • the detecting circuit 30 of the embodiment is electrically connected to the gate driving unit 18(n) of the last stage, and the output signal of the gate driving unit 18(n) used for the last stage is smaller than The adjustment signal is output when the predetermined value is described.
  • the detecting circuit 30 can also be electrically connected to the gate driving unit 18 (n-1) and used for the scanning signal G(n-1) of the gate driving unit 18 (n-1). Whether the control signal STV(n-1) or the signal of the trigger node Q(n-1) is smaller than the predetermined value, the adjustment signal is output.
  • the detecting circuit 30 can also be electrically connected to the gate driving unit 18 (n-2) and used for the scanning signal G(n-2) of the gate driving unit 18 (n-2). Whether the control signal STV(n-2) or the signal of the trigger node Q(n-2) is smaller than the predetermined value, the adjustment signal is output.
  • the liquid crystal display of the present invention is not limited to the above embodiments.
  • the detecting circuit 30 can also be integrated in the source driver 16, and the operation principle is the same.
  • the liquid crystal display of the present invention further includes a detecting circuit.
  • the detecting circuit is configured to output an adjustment signal when an output signal of the gate driving unit of the last stage is less than a predetermined value.
  • the level adjuster After receiving the adjustment signal, the level adjuster outputs a plurality of low-level clock signals and a low-level control signal to the plurality of gate driving units, so that the plurality of the gate driving units Stop outputting the scan signal, Also close the data transfer. In this way, the liquid crystal display is temporarily turned off and presents a black screen, so that the GOA substrate can be prevented from being burnt.

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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Multimedia (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶显示器（10），其包括GOA基板（20），所述GOA基板（20）包含像素阵列区（203）及电路放置区（201）。所述液晶显示器（10）包含：多个栅极驱动单元（18（1）~18（n）），设于所述电路放置区（201）上，用来依据时钟信号（CK（1）~CK（n））和控制信号（STV（1）~STV（n））的电位值，输出扫描信号（G（1）~G（n））予所述像素阵列区（203）；侦测电路（30）用来当最后一级的所述栅极驱动单元（18（n））的输出信号（GOA_FB_L，GOA_FB_R）小于预定值（Vth）时，输出调整信号。位准调整器（40）接收到所述调整信号后，会输出低电平的多个时钟信号（CK（1）~CK（n））和低电平的控制信号（STV（1）~STV（n））予多个所述栅极驱动单元（18（1）~18（n）），使得多个所述栅极驱动单元（18（1）~18（n））停止输出所述扫描信号（G（1）~G（n））。如此一来，所述液晶显示器（10）会暂时关闭，而呈现黑画面，因此能避免GOA基板（20）烧毁。

Description

避免GOA基板烧毁的液晶显示器 技术领域
本发明是有关于一种液晶显示器，尤指一种使用栅极驱动基板(Gate driver on array，GOA)的液晶显示器。
 背景技术
功能先进的显示器渐成为现今消费电子产品的重要特色，其中液晶显示器已经逐渐成为各种电子设备如电视、行动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记型计算机屏幕所广泛应用具有高分辨率彩色屏幕的显示器。
传统的液晶显示器包含源极驱动器、栅极驱动器(gate driver)以及液晶显示面板。在目前的液晶显示面板设计中，栅极驱动器等效上为移位寄存器(shift register), 逻辑电路(logic circuit), 电位移转器(Level shifter), 还有数字缓冲放大器(Digital buffer)，移位暂存器的目的即每隔一固定间隔输出扫描讯号至液晶显示面板。以一个1024 × 768分辨率的液晶显示面板, 其像素排列为RGB横向排列, 以及60Hz的更新频率为例，每一个画面的显示时间约为1/60=16.67ms。所以每一个扫描信号的脉波约为16.67ms/768=21.7μs。而源极驱动器则在这21.7μs的时间内，将像素单元充放电到所需的电压，以显示出相对应的灰阶。
为了制造窄边框的液晶显示器，目前已开发一种将栅极驱动器制作在液晶显示面板上的技术，也就是栅极驱动基板(Gate driver on array，GOA)。液晶显示器包含控制器、源极驱动器(source driver)、栅极驱动单元(gate driving unit)以及GOA基板。GOA基板包含像素阵列区。当控制器产生的时钟信号以及GOA控制信号传送至栅极驱动单元时，栅极驱动单元会产生扫描信号至像素阵列区的像素单元，在此同时，源极驱动器会输出灰阶电压至像素阵列区的像素单元。
由于传输GOA控制讯号的走线位在面板的两侧, 正好是框胶涂布的位置。框胶可能由于老化、品质不好、涂布不佳等问题造成水气渗入, 使得GOA 电路的控制讯号彼此间短路, 进而让面板烧毁。
 技术问题
为了解决现有技术GOA基板会烧毁的技术问题，有必要提供一种避免GOA基板烧毁的液晶显示器。
 技术解决方案
本发明提供一种液晶显示器，其包括栅极驱动(Gate driver on array，GOA)基板，所述GOA基板包含像素阵列区以及位于所述像素阵列区第一侧和第二侧的电路放置区，所述第一侧和所述第二侧彼此平行，所述液晶显示器另包含：多个栅极驱动单元，设于所述电路放置区上，多个所述栅极驱动单元是串连连接，用来依据时钟信号和控制信号的电位值，输出扫描信号予所述像素阵列区；侦测电路，电性连接于最后一级的所述栅极驱动单元，用来当最后一级的所述栅极驱动单元或是最后第二级的所述栅极驱动单元或是最后第三级的所述栅极驱动单元所输出的的扫描信号小于一预定值时，输出一调整信号；及位准调整器，电性连接于多个所述栅极驱动单元和所述侦测电路，用于收到所述调整信号时，输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元。
依据本发明的实施例，所述液晶显示器另包含源极驱动器，所述GOA基板另包含第三侧，所述第三侧垂直于所述第一侧和所述第二侧，多个所述源极驱动器位于所述第三侧。
依据本发明的实施例，每一栅极驱动单元包含：第一晶体管，其漏极电性连接于所述时钟信号，其源极电性连接于输出端以输出所述扫描信号，其栅极电性连接于一触发节点；第二晶体管，其漏极电性连接于所述时钟信号，其源极电性连接于控制端以输出所述控制信号，其栅极电性连接于所述触发节点；第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于一电源电压；以及第四晶体管，其漏极电性连接于所述触发节点，其源极电性连接于所述电源电压，其栅极电性连接于所述第三晶体管的栅极。
依据本发明的实施例，当所述位准调整器输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元时，多个所述栅极驱动单元停止输出所述扫描信号。
依据本发明的实施例，当所述位准调整器未收到所述调整信号时，输出高电平的多个时钟信号和高电平的控制信号予多个所述栅极驱动单元，使得所述多个栅极驱动单元输出所述扫描信号予所述像素阵列区。
本发明提供一种液晶显示器，其包括栅极驱动(Gate driver on array，GOA)基板，所述GOA基板包含像素阵列区以及位于所述像素阵列区第一侧和第二侧的电路放置区，所述第一侧和所述第二侧彼此平行，所述液晶显示器另包含：多个栅极驱动单元，设于所述电路放置区上，多个所述栅极驱动单元是串连连接，用来依据时钟信号和控制信号的电位值，输出扫描信号予所述像素阵列区；侦测电路，电性连接于最后一级的所述栅极驱动单元，用来当最后一级的所述栅极驱动单元的输出信号小于一预定值时，输出一调整信号；及位准调整器，电性连接于多个所述栅极驱动单元和所述侦测电路，用于收到所述调整信号时，输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元。
依据本发明的实施例，所述液晶显示器另包含源极驱动器，所述GOA基板另包含第三侧，所述第三侧垂直于所述第一侧和所述第二侧，多个所述源极驱动器位于所述第三侧。
依据本发明的实施例，所述液晶显示器另包含软性电路板，用来电性连接多个所述源极驱动器和所述像素阵列区。
依据本发明的实施例，每一栅极驱动单元包含：第一晶体管，其漏极电性连接于所述时钟信号，其源极电性连接于输出端以输出所述扫描信号，其栅极电性连接于一触发节点；第二晶体管，其漏极电性连接于所述时钟信号，其源极电性连接于控制端以输出所述控制信号，其栅极电性连接于所述触发节点；第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于一电源电压；以及第四晶体管，其漏极电性连接于所述触发节点，其源极电性连接于所述电源电压，其栅极电性连接于所述第三晶体管的栅极。
依据本发明的实施例，所述输出信号是最后一级的所述栅极驱动单元或是最后第二级的所述栅极驱动单元或是最后第三级的所述栅极驱动单元所输出的控制信号。
依据本发明的实施例，所述输出信号是最后一级的所述栅极驱动单元或是最后第二级的所述栅极驱动单元或是最后第三级的所述栅极驱动单元的触发节点的信号。
依据本发明的实施例，当所述位准调整器输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元时，多个所述栅极驱动单元停止输出所述扫描信号。
依据本发明的实施例，当所述位准调整器未收到所述调整信号时，输出高电平的多个时钟信号和高电平的控制信号予多个所述栅极驱动单元，使得所述多个栅极驱动单元输出所述扫描信号予所述像素阵列区。
依据本发明的实施例，所述侦测电路集成于所述位准调整器之内。
 有益效果
相较于现有技术，本发明液晶显示器进一步包括一侦测电路。所述侦测电路用来当最后一级的所述栅极驱动单元的输出信号小于一预定值时，输出调整信号。所述位准调整器接收到所述调整信号后，会输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元，使得多个所述栅极驱动单元停止输出所述扫描信号, 同时关闭掉资料传输。如此一来，所述液晶显示器会暂时关闭，而呈现黑画面，因此能避免GOA基板烧毁。
 附图说明
图1是本发明使用栅极驱动基板的液晶显示器的示意图。
图2是栅极驱动单元的局部电路图。
图3是图1的侦测电路和位准调整器的示意图。
图4是侦测电路用于判断最后一级的栅极驱动单元的输出信号的示意图。
 本发明的最佳实施方式
请参阅图1，图1是本发明使用栅极驱动(Gate driver on array，GOA)基板的液晶显示器10的示意图。液晶显示器10包含控制器14、源极驱动器(source driver)16、多个栅极驱动单元(gate driving unit) 18(1)~18(n)、侦测电路30以及GOA基板20。GOA基板20具有第一侧2031、第二侧2032和第三侧2033，第一侧2031和第二侧2032彼此平行，第三侧2033垂直于第一侧2031和第二侧2032。GOA基板20包含像素阵列区203以及位于像素阵列区203的两侧的电路放置区201。多个栅极驱动单元18(1)~18(n) (亦即GOA 电路单元)放置在电路放置区201。源极驱动器16位于GOA基板20的第三侧2033，通过软性电路板24电性连接到像素阵列区203的像素单元。当控制器14产生的时钟信号以及GOA控制信号传送至栅极驱动单元18(1)~18(n)时，栅极驱动单元18(1)~18(n)会产生扫描信号至像素阵列区203的像素单元，在此同时，源极驱动器16会输出灰阶电压至像素阵列区203的像素单元。
图1所示的多个栅极驱动单元18(1)~18(n)是串连连接。而且多个栅极驱动单元18(1)~18(n)是一对一的连接到像素阵列区203的多行像素单元。举例来说，一个1024 × 768分辨率的液晶显示面板具有768个栅极驱动单元18，每一个栅极驱动单元18(1)~18(n)连接到一行像素单元，n为768。栅极驱动单元18(n)用来依据时钟信号CK(n)和控制信号STV(n)的电位值，从输出端G(n)输出扫描信号予像素阵列区203对应第n行的栅极驱动单元18(n)。
请参阅图2，图2是栅极驱动单元18(n)的局部电路图。由于每一栅极驱动单元18的电路结构相同，因此以下仅采用栅极驱动单元18(n)的电路结构做为说明。栅极驱动单元18(n)包含第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。第一晶体管T1的漏极电性连接于时钟信号CK(n)，其源极电性连接于输出端G(n)以输出扫描信号，其栅极电性连接于触发节点Q(n)。第二晶体管T2的漏极电性连接于时钟信号CK(n)，其源极电性连接于控制端STV(n)以输出控制信号，其栅极电性连接于触发节点Q(n)。第三晶体管T3的漏极电性连接于输出端G(n)，其源极电性连接于电源电压Vss。第四晶体管T4漏极电性连接于触发节点Q(n)，其源极电性连接于电源电压Vss，其栅极电性连接于第三晶体管T3的栅极。当触发节点Q(n)的信号电平为高电平时，第一晶体管T1和第二晶体管T2都会开启，使得高电平的时钟信号CK(n)导通至输出端G(n)和控制端STV(n)。此时，输出端G(n)输出的扫描信号和控制端STV(n)输出的控制信号皆为高电平。相对地，当触发节点Q(n)的信号电平为低电平时，第一晶体管T1和第二晶体管T2都会关闭，而第三晶体管T3和第四晶体管T4皆会开启并导通电源电压Vss。此时，输出端G(n)输出的扫描信号为低电平。
请参阅图3和图4，图3是图1的侦测电路和位准调整器的示意图。图4是侦测电路用于判断最后一级的栅极驱动单元的输出信号GOA_FB的示意图。侦测电路30电性连接于最后一级的栅极驱动单元18(n)，用来当最后一级的栅极驱动单元18(n)的输出信号GOA_FB_L(或是GOA_FB_R)小于一预定值Vth时，输出一调整信号。所述输出信号GOA_FB_L(或是GOA_FB_R)是最后一级的栅极驱动单元18(n)的扫描信号G(n)，或是最后一级的栅极驱动单元18(n)的控制信号STV(n)，或是最后一级的栅极驱动单元18(n)的触发节点Q(n)的信号。位准调整器40电性连接于多个栅极驱动单元18(1)~18(n)和侦测电路30，用于收到所述调整信号时，输出低电平的多个时钟信号CK(1)~CK(n)和低电平的控制信号STV(1)~STV(n)予多个栅极驱动单元18(1)~18(n)。当位准调整器40输出低电平的多个时钟信号CK(1)~CK(n)和低电平的控制信号STV(1)~STV(n)予多个栅极驱动单元18(1)~18(n)时，多个栅极驱动单元18(1)~18(n)停止输出所述扫描信号。当位准调整器40未收到所述调整信号时，输出高电平的多个时钟信号CK(1)~CK(n)和高电平的控制信号STV(1)~STV(n)予多个栅极驱动单元18(1)~18(n)，使得多个栅极驱动单元18(1)~18(n)输出所述扫描信号予像素阵列区203。
请注意，虽然本实施例的侦测电路30是电性连接于最后一级的栅极驱动单元18(n)，并用来于最后一级的栅极驱动单元18(n)的输出信号小于所述预定值时输出调整信号。但于其它实施例中，侦测电路30也可以电性连接于栅极驱动单元18(n-1)，并用来于栅极驱动单元18(n-1)的扫描信号G(n-1)，或是控制信号STV(n-1)，或是触发节点Q(n-1)的信号小于所述预定值时输出调整信号。在又一实施例中，侦测电路30也可以电性连接于栅极驱动单元18(n-2)，并用来于栅极驱动单元18(n-2)的扫描信号G(n-2)，或是控制信号STV(n-2)，或是触发节点Q(n-2)的信号小于所述预定值时输出调整信号。
本发明液晶显示器并不限于以上实施方式所述，例如：侦测电路30也可以集成在源极驱动器16中，其运作原理相同。
综合以上，本发明液晶显示器进一步包括一侦测电路。所述侦测电路用来当最后一级的所述栅极驱动单元的输出信号小于一预定值时，输出调整信号。所述位准调整器接收到所述调整信号后，会输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元，使得多个所述栅极驱动单元停止输出所述扫描信号, 同时关闭资料传输。如此一来，所述液晶显示器会暂时关闭，而呈现黑画面，因此能避免GOA基板烧毁。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种液晶显示器，其包括栅极驱动(Gate driver on array，GOA)基板，所述GOA基板包含像素阵列区以及位于所述像素阵列区第一侧和第二侧的电路放置区，所述第一侧和所述第二侧彼此平行，所述液晶显示器另包含：
    多个栅极驱动单元，设于所述电路放置区上，多个所述栅极驱动单元是串连连接，用来依据时钟信号和控制信号的电位值，输出扫描信号予所述像素阵列区；
    侦测电路，电性连接于最后一级的所述栅极驱动单元，用来当最后一级的所述栅极驱动单元或是最后第二级的所述栅极驱动单元或是最后第三级的所述栅极驱动单元所输出的的扫描信号小于一预定值时，输出一调整信号；及
    位准调整器，电性连接于多个所述栅极驱动单元和所述侦测电路，用于收到所述调整信号时，输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元。
  2. 根据权利要求1所述的液晶显示器，其中所述液晶显示器另包含源极驱动器，所述GOA基板另包含第三侧，所述第三侧垂直于所述第一侧和所述第二侧，多个所述源极驱动器位于所述第三侧。
  3. 根据权利要求1所述的液晶显示器，其中每一栅极驱动单元包含：
    第一晶体管，其漏极电性连接于所述时钟信号，其源极电性连接于输出端以输出所述扫描信号，其栅极电性连接于一触发节点；
    第二晶体管，其漏极电性连接于所述时钟信号，其源极电性连接于控制端以输出所述控制信号，其栅极电性连接于所述触发节点；
    第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于一电源电压；以及
    第四晶体管，其漏极电性连接于所述触发节点，其源极电性连接于所述电源电压，其栅极电性连接于所述第三晶体管的栅极。
  4. 根据权利要求1所述的液晶显示器，其中当所述位准调整器输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元时，多个所述栅极驱动单元停止输出所述扫描信号。
  5. 根据权利要求4所述的液晶显示器，其中当所述位准调整器未收到所述调整信号时，输出高电平的多个时钟信号和高电平的控制信号予多个所述栅极驱动单元，使得所述多个栅极驱动单元输出所述扫描信号予所述像素阵列区。
  6. 一种液晶显示器，其包括栅极驱动(Gate driver on array，GOA)基板，所述GOA基板包含像素阵列区以及位于所述像素阵列区第一侧和第二侧的电路放置区，所述第一侧和所述第二侧彼此平行，所述液晶显示器另包含：
    多个栅极驱动单元，设于所述电路放置区上，多个所述栅极驱动单元是串连连接，用来依据时钟信号和控制信号的电位值，输出扫描信号予所述像素阵列区；
    侦测电路，电性连接于最后一级的所述栅极驱动单元，用来当最后一级的所述栅极驱动单元或是最后第二级的所述栅极驱动单元或是最后第三级的所述栅极驱动单元所输出的输出信号小于一预定值时，输出一调整信号；及
    位准调整器，电性连接于多个所述栅极驱动单元和所述侦测电路，用于收到所述调整信号时，输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元。
  7. 根据权利要求6所述的液晶显示器，其中所述液晶显示器另包含源极驱动器，所述GOA基板另包含第三侧，所述第三侧垂直于所述第一侧和所述第二侧，多个所述源极驱动器位于所述第三侧。
  8. 根据权利要求7所述的液晶显示器，其中所述液晶显示器另包含软性电路板，用来电性连接多个所述源极驱动器和所述像素阵列区。
  9. 根据权利要求6所述的液晶显示器，其中每一栅极驱动单元包含：
    第一晶体管，其漏极电性连接于所述时钟信号，其源极电性连接于输出端以输出所述扫描信号，其栅极电性连接于一触发节点；
    第二晶体管，其漏极电性连接于所述时钟信号，其源极电性连接于控制端以输出所述控制信号，其栅极电性连接于所述触发节点；
    第三晶体管，其漏极电性连接于所述输出端，其源极电性连接于一电源电压；以及
    第四晶体管，其漏极电性连接于所述触发节点，其源极电性连接于所述电源电压，其栅极电性连接于所述第三晶体管的栅极。
  10. 根据权利要求9所述的液晶显示器，其中所述输出信号是最后一级的所述栅极驱动单元或是最后第二级的所述栅极驱动单元或是最后第三级的所述栅极驱动单元所输出的控制信号。
  11. 根据权利要求9所述的液晶显示器，其中所述输出信号是最后一级的所述栅极驱动单元或是最后第二级的所述栅极驱动单元或是最后第三级的所述栅极驱动单元的触发节点的信号。
  12. 根据权利要求6所述的液晶显示器，其中当所述位准调整器输出低电平的多个时钟信号和低电平的控制信号予多个所述栅极驱动单元时，多个所述栅极驱动单元停止输出所述扫描信号。
  13. 根据权利要求12所述的液晶显示器，其中当所述位准调整器未收到所述调整信号时，输出高电平的多个时钟信号和高电平的控制信号予多个所述栅极驱动单元，使得所述多个栅极驱动单元输出所述扫描信号予所述像素阵列区。
  14. 根据权利要求6所述的液晶显示器，其中所述侦测电路集成于所述位准调整器之内。
PCT/CN2015/089154 2015-08-13 2015-09-08 避免goa基板烧毁的液晶显示器 WO2017024651A1 (zh)

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