WO2017107238A1 - 阵列基板及其制造方法、液晶显示面板 - Google Patents

阵列基板及其制造方法、液晶显示面板 Download PDF

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WO2017107238A1
WO2017107238A1 PCT/CN2015/099737 CN2015099737W WO2017107238A1 WO 2017107238 A1 WO2017107238 A1 WO 2017107238A1 CN 2015099737 W CN2015099737 W CN 2015099737W WO 2017107238 A1 WO2017107238 A1 WO 2017107238A1
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layer
metal layer
substrate
array substrate
metal
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French (fr)
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王威
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G02F1/133516—Methods for their manufacture, e.g. printing, electro-deposition or photolithography
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an array substrate, a method of manufacturing the same, and a liquid crystal display panel having the array substrate.
  • IGZO Indium Gallium Zinc Oxide
  • AOS amorphous Oxide semiconductor layers
  • IGZO is a kind of For materials that are extremely sensitive to water and oxygen, water molecules and oxygen molecules in the LCD working environment can easily affect their electrical properties. Therefore, in order to improve the electrical stability of the TFT channel, a protective layer needs to be formed on the channel.
  • the material of the protective layer in the prior art is generally silicon oxide SiO 2 , silicon nitride Si 3 N 4 , and usually adopts chemical vapor deposition (CVD), atomic layer epitaxy (ALD), and magnetic control. It is produced by sputtering or the like.
  • CVD chemical vapor deposition
  • ALD atomic layer epitaxy
  • magnetic control It is produced by sputtering or the like.
  • the chemical vapor deposition method easily causes impurities such as hydrogen atoms to be doped into the channel, which not only damages the channel but also affects the electrical properties of the channel; the quality of the protective layer obtained by magnetron sputtering is poor, The stability of the protection of the track is poor; the process of atomic layer epitaxy is complicated and takes a long time, which is not conducive to industrialization.
  • the present invention provides an array substrate, a method for fabricating the same, and a liquid crystal display panel, which can prevent impurities such as hydrogen atoms from being doped into the channel, and the obtained protective layer has a high film quality, ensuring electrical properties of the channel, and the process. Simple and easy to implement, it is conducive to industrialization.
  • a method for fabricating an array substrate according to an embodiment of the present invention includes: sequentially forming a first metal layer, an insulating layer, and a semiconductor pattern layer on a substrate substrate; and forming a second metal layer on the insulating layer and the semiconductor pattern layer,
  • the surface of the region corresponding to the second metal layer and the semiconductor pattern layer is an aluminum Al layer, and the Al layer is formed by magnetron sputtering; thermal annealing is performed at a temperature of 300 to 400 ° C in an atmosphere having an oxygen concentration higher than 21%.
  • Processing causing an oxidation reaction of the Al layer to form an Al 2 O 3 layer; etching a second metal layer including the Al 2 O 3 layer to retain a protective layer having a predetermined size on the semiconductor pattern layer; in Al 2 A third metal layer is formed on the O 3 layer, the third metal layer is formed with a recess, and the recess exposes the Al 2 O 3 layer of its corresponding region.
  • the first metal layer is a gate of a thin film transistor of the array substrate
  • the second metal layer includes a source and a drain of the thin film transistor, and the source and the drain are located on both sides of the groove.
  • the method further comprises: forming a passivation layer on the exposed Al 2 O 3 layer and the third metal layer.
  • a passivation layer is formed on the exposed Al 2 O 3 layer and the third metal layer by any combination of chemical vapor deposition, atomic layer epitaxy, coating, sputtering, and evaporation.
  • the material of the passivation layer and the material of the second metal layer are different.
  • the material of the passivation layer is the same as the material of the second metal layer.
  • An array substrate provided by the embodiment of the invention includes: a substrate substrate; a first metal layer, an insulating layer and a semiconductor pattern layer sequentially formed on the substrate substrate; and a protective layer formed on the semiconductor pattern layer to protect
  • the surface of the layer is an Al 2 O 3 layer, and the Al 2 O 3 layer is obtained by thermal annealing of an Al layer formed by magnetron sputtering in an atmosphere having an oxygen concentration higher than 21% at a temperature of 300 to 400 ° C;
  • a third metal layer is formed on the Al 2 O 3 layer, the third metal layer is formed with a recess, and the recess exposes the Al 2 O 3 layer of its corresponding region.
  • the first metal layer is a gate of a thin film transistor of the array substrate
  • the second metal layer includes a source and a drain of the thin film transistor, and the source and the drain are located on both sides of the groove.
  • a liquid crystal display panel includes an array substrate, a color filter substrate disposed at a distance from the array substrate, and a liquid crystal interposed therebetween, the array substrate comprising: a substrate substrate; a first metal layer, an insulating layer and a semiconductor pattern layer formed on the substrate substrate in sequence; a protective layer formed on the semiconductor pattern layer, the surface of the protective layer being an Al 2 O 3 layer, and the Al 2 O 3 layer being made of magnetic
  • the Al layer formed by the controlled sputtering method is obtained by thermal annealing at a temperature of 300 to 400 ° C in an atmosphere having an oxygen concentration higher than 21%; the third metal layer is formed on the Al 2 O 3 layer, and the third metal layer A groove is formed and the groove exposes the Al 2 O 3 layer of its corresponding region.
  • the first metal layer is a gate of a thin film transistor of the array substrate
  • the second metal layer includes a source and a drain of the thin film transistor, and the source and the drain are located on both sides of the groove.
  • the array substrate, the manufacturing method thereof and the liquid crystal display panel of the embodiments of the present invention are thermally annealed at a temperature of 300 to 400 ° C in an atmosphere having an oxygen concentration higher than 21% by magnetron sputtering to obtain a channel.
  • the protective layer, and the material of the protective layer includes Al 2 O 3 , which can avoid impurities such as hydrogen atoms from being doped into the channel compared to the chemical vapor deposition method, thereby avoiding damage to the channel and ensuring electrical properties of the channel;
  • the Al 2 O 3 protective layer prepared by the oxidation reaction has higher film quality and higher density, which can further ensure the electrical properties of the channel.
  • the magnetron sputtering method and the thermal annealing process are simple and beneficial to the industry. Chemical.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 2 is a schematic view showing the first metal layer, the insulating layer and the semiconductor pattern layer sequentially formed on the substrate substrate in the method shown in FIG. 1;
  • FIG. 3 is a schematic view showing the formation of a second metal layer and an Al 2 O 3 layer on the insulating layer and the semiconductor pattern layer in the method shown in FIG. 1;
  • FIG. 4 is a schematic view showing the formation of a third metal layer on the Al 2 O 3 layer in the method shown in FIG. 1;
  • Fig. 5 is a cross-sectional view showing the structure of an embodiment of a liquid crystal display panel of the present invention.
  • Fig. 1 is a flow chart showing an embodiment of a method for fabricating an array substrate of the present invention.
  • the method is used to form a protective layer of an IGZO channel of a TFT, the primary function of which is to prevent water molecules and oxygen molecules from entering and contacting the IGZO channel to ensure electrical properties of the IGZO channel, and thus the protective layer can also be called It is a water oxygen barrier layer or an Etch Stop Layer (ESL) layer.
  • ESL Etch Stop Layer
  • S11 forming a first metal layer, an insulating layer, and a semiconductor pattern layer in this order on the substrate substrate.
  • the substrate substrate 21 is used to form an array substrate, and thus the substrate substrate 21 may be a glass substrate, a transparent plastic substrate, or a flexible substrate.
  • the first metal layer 22 may be formed on the substrate substrate 21 by a method such as chemical vapor deposition, vacuum evaporation, plasma chemical vapor deposition, sputtering or low pressure chemical vapor deposition.
  • a gate electrode of the TFT having a predetermined pattern since the source and the drain of the TFT are subsequently formed, the insulating layer 23, that is, the gate insulating layer (Gate) is further formed on the substrate substrate 21 including the first metal layer 22. Insulation Layer, GI).
  • the semiconductor pattern layer 24 formed on the insulating layer 23 is an amorphous oxide semiconductor layer of the TFT and has a predetermined pattern.
  • the material of the semiconductor pattern layer 24 includes, but is not limited to, IGZO and ITZO (InSnZnO).
  • a whole semiconductor pattern layer 24 formed on the insulating layer 23 may be etched by using an etching solution including, but not limited to, phosphoric acid, nitric acid, acetic acid, and deionized water, thereby obtaining a semiconductor pattern layer having a predetermined pattern. 24, of course, other embodiments may also employ dry etching, but are not limited thereto.
  • the second metal layer 25 is used to obtain a protective layer of the IGZO channel of the embodiment of the present invention, and the second metal layer 25 is preferably formed by magnetron sputtering at a temperature of 300 to 400 ° C. Al layer.
  • the second metal layer 25 of other embodiments may be provided with an Al layer of a predetermined thickness only on the surface, or an Al layer of a predetermined thickness may be provided only on the surface corresponding to the semiconductor pattern layer 24, and formed in a predetermined manner under the Al layer.
  • a substrate, the material of the substrate is not limited in the present invention.
  • the embodiment of the present invention is not only compared with the chemical vapor deposition method or the plasma enhanced chemical vapor deposition (PECVD) method. Damage to the IGZO channel can be reduced, and impurities such as hydrogen atoms can be prevented from being incorporated into the semiconductor pattern layer 24 (IGZO channel), thereby ensuring electrical properties of the IGZO channel.
  • PECVD plasma enhanced chemical vapor deposition
  • the magnetron sputtering method is simple and easy to implement, and is more efficient than chemical vapor deposition or plasma enhanced chemical vapor deposition, which is advantageous for industrialization.
  • the Al atoms in the Al layer are oxidized in an oxygen-rich atmosphere having an oxygen O 2 concentration higher than 21%, and the Al 2 O 3 layer 26 can be formed to the maximum extent.
  • the temperature of 300 to 400 ° C can promote the oxidation reaction so that as many Al atoms as possible in the Al layer are oxidized, thereby ensuring the compactness of the formed Al 2 O 3 layer 26 to the greatest extent, and making the film quality better. High, further ensuring the electrical performance of the IGZO channel.
  • the thermal annealing treatment in the oxygen-rich atmosphere can simultaneously have three functions: first, reducing the defect state density of the IGZO active layer (IGZO channel) (mainly reducing the oxygen vacancy concentration), and obtaining good results.
  • the active layer electrical properties; secondly, to some extent repair the damage caused by the magnetron sputtering process and the etching process on the channel of the active layer during the deposition and patterning of the second metal layer 25;
  • the layer is oxidized to a higher film quality Al 2 O 3 layer 26 to form a channel protective layer.
  • the embodiment of the present invention may etch the Al 2 O 3 layer 26 by using, but not limited to, wet etching, dry etching, or the like.
  • the predetermined size is the size of the IGZO channel of the TFT
  • the protective layer of the predetermined size (shown as the Al 2 O 3 layer 26) is the protective layer of the IGZO channel.
  • the third metal layer 27 is a source/drain electrode layer of the TFT, and includes a source electrode 271 and a drain electrode 272, and the source electrode 271 and the drain electrode 272 are located on both sides of the protective layer.
  • the manufacturing method of the embodiment of the present invention further includes forming a passivation layer 28 on the exposed Al 2 O 3 layer (the predetermined size of the Al 2 O 3 layer 26) and the third metal layer 27.
  • the passivation layer 28 may be formed on the exposed Al 2 O 3 layer 26 and the third metal layer 27 by any combination of chemical vapor deposition, atomic layer epitaxy, coating, sputtering, and evaporation.
  • the materials of the passivation layer 28 and the second metal layer 25 may be the same or different.
  • the embodiment of the present invention further provides an array substrate having the structure shown in FIG. 4 which is obtained by the above method, and a manufacturing method of other structures of the array substrate can be referred to the prior art.
  • the embodiment of the present invention further provides a liquid crystal display panel.
  • the liquid crystal display panel 50 includes the array substrate 10 , a color film substrate 51 disposed opposite to the array substrate 10 , and the array substrate 10 and the color The liquid crystal 52 between the film substrates 51.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
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Abstract

一种阵列基板（10）的制造方法及由该方法制得的阵列基板（10）以及具有该阵列基板（10）的液晶显示面板（50），采用磁控溅射法在氧气浓度高于21%的氛围中以300～400℃的温度进行热退火处理，从而制得沟道的保护层，其中该保护层的材质包括Al2O3。能够避免氢原子等杂质掺入沟道中，制得的保护层膜质较高，从而确保沟道的电学性能，且工艺简单易实现，有利于产业化。

Description

阵列基板及其制造方法、液晶显示面板 【技术领域】
本发明涉及液晶显示技术领域，具体而言涉及一种阵列基板及其制造方法、以及具有该阵列基板的液晶显示面板。
【背景技术】
随着液晶显示器(Liquid Crystal Display，LCD)尺寸和清晰度的增加，具有较大电子迁移率的TFT(Thin Film Transistor，薄膜晶体管)结构已崭露头角并表现出巨大的市场应用前景。当前，业界普遍采用IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)制备TFT的非晶态氧化半导体层(Amorphous Oxide Semiconductor，AOS，又称半导体图案层或IGZO沟道)，由于IGZO是一种对水和氧极其敏感的材料，LCD工作环境中的水分子和氧分子极易对其电学性能产生影响，因此为了提高TFT的沟道的电学稳定性需要在沟道上形成一保护层。
现有技术中保护层的材质一般为氧化硅SiO2、氮化硅Si3N4，且通常采用化学气相沉积(Chemical vapor deposition，CVD)、原子层外延(Atom Layer Deposition，ALD)以及磁控溅射(Sputter)等方式制得。然而，化学气相沉积方式容易使氢原子等杂质掺入到沟道中，不仅会损伤沟道，而且影响沟道的电学性能；采用磁控溅射方式制得的保护层的质量较差，对沟道的保护的稳定性较差；原子层外延方式的工艺复杂，耗时较长，因此不利于产业化。
【发明内容】
有鉴于此，本发明提供一种阵列基板及其制造方法、液晶显示面板，能够避免氢原子等杂质掺入沟道中，制得的保护层膜质较高，确保沟道的电学性能，且工艺简单易实现，有利于产业化。
本发明实施例提供的一种阵列基板的制造方法，包括：在衬底基材上依次形成第一金属层、绝缘层和半导体图案层；在绝缘层和半导体图案层上形成第二金属层，其中第二金属层与半导体图案层对应的区域的表面为 铝Al层，且Al层采用磁控溅射法形成；在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理，使得Al层发生氧化反应形成Al2O3层；对包含所述Al2O3层的第二金属层进行刻蚀，以在半导体图案层上保留具有预定尺寸的保护层；在Al2O3层上形成第三金属层，第三金属层形成有凹槽，且凹槽暴露其对应区域的Al2O3层。
其中，第一金属层为阵列基板的薄膜晶体管的栅极，第二金属层包括薄膜晶体管的源极和漏极，源极和漏极位于凹槽的两侧。
其中，所述方法还包括：在被暴露的Al2O3层和第三金属层上形成钝化层。
其中，采用化学气相沉积、原子层外延、涂覆、溅射以及蒸镀中的任意组合方式在被暴露的Al2O3层和第三金属层上形成钝化层。
其中，钝化层的材质和第二金属层的材质不相同。
其中，钝化层的材质和第二金属层的材质相同。
本发明实施例提供的一种阵列基板，包括：衬底基材；依次形成于衬底基材上的第一金属层、绝缘层和半导体图案层；保护层，形成于半导体图案层上，保护层的表面为Al2O3层，Al2O3层由采用磁控溅射法形成的Al层在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理制得；第三金属层，形成于Al2O3层上，第三金属层形成有凹槽，且凹槽暴露其对应区域的Al2O3层。
其中，第一金属层为阵列基板的薄膜晶体管的栅极，第二金属层包括薄膜晶体管的源极和漏极，源极和漏极位于凹槽的两侧。
本发明实施例提供的一种液晶显示面板，包括阵列基板、与所述阵列基板相对间隔设置的彩膜基板以及夹设于两者之间的液晶，所述阵列基板包括：衬底基材；依次形成于衬底基材上的第一金属层、绝缘层和半导体图案层；保护层，形成于半导体图案层上，保护层的表面为Al2O3层，Al2O3层由采用磁控溅射法形成的Al层在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理制得；第三金属层，形成于Al2O3层上，第三金属层形成有凹槽，且凹槽暴露其对应区域的Al2O3层。
其中，第一金属层为阵列基板的薄膜晶体管的栅极，第二金属层包括薄膜晶体管的源极和漏极，源极和漏极位于凹槽的两侧。
本发明实施例的阵列基板及其制造方法、液晶显示面板，采用磁控溅射方式在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理，以此制得沟道的保护层，且该保护层的材质包括Al2O3，相比较于化学气相沉积方式，能够避免氢原子等杂质掺入沟道中，从而避免损伤沟道，确保沟道的电学性能；并且，氧化反应制得的Al2O3保护层膜质较高，具有较高的致密度，可进一步确保沟道的电学性能；另外，磁控溅射方式和热退火处理的工艺简单，有利于产业化。
【附图说明】
图1是本发明的阵列基板的制造方法一实施例的流程示意图；
图2是图1所示方法中在衬底基材上依次形成第一金属层、绝缘层和半导体图案层的示意图；
图3是图1所示方法中在绝缘层和半导体图案层上形成第二金属层以及Al2O3层的示意图；
图4是图1所示方法中在Al2O3层上形成第三金属层的示意图；
图5是本发明的液晶显示面板一实施例的结构剖视图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图1是本发明的阵列基板的制造方法一实施例的流程示意图。所述方法用于形成TFT的IGZO沟道的保护层，该保护层的首要作用是防止水分子和氧分子进入并接触IGZO沟道以确保IGZO沟道的电学性能，因此该保护层也可称为水氧阻隔层或刻蚀阻挡(Etch Stop Layer，ESL)层。结合图1～图7所示，所述方法包括：
S11：在衬底基材上依次形成第一金属层、绝缘层和半导体图案层。
参阅图2所示，衬底基材21用于形成阵列基板，因此所述衬底基材21可以为玻璃基材、透明塑料基材或可挠式基材。
本实施例可采用例如化学气相沉积、真空蒸镀、等离子化学气相沉积、溅射或低压化学气相沉积等方法在衬底基材21上形成第一金属层22，即形 成具有预定图案的TFT的栅极，由于后续需要形成TFT的源极和漏极，因此进一步在包括第一金属层22的衬底基材21上形成绝缘层23，即栅极绝缘层(Gate Insulation Layer，GI)。
在绝缘层23上形成的半导体图案层24为TFT的非晶态氧化半导体层且具有预定图案。该半导体图案层24的材质包括但不限于IGZO、ITZO(InSnZnO)。本发明实施例可以利用包括但不限于具有磷酸、硝酸、醋酸以及去离子水的蚀刻液对形成于绝缘层23上的一整片半导体图案层24进行蚀刻，从而得到具有预定图案的半导体图案层24，当然其他实施例也可以采用干法蚀刻，但并不限于此。
S12：在绝缘层和半导体图案层上形成第二金属层，第二金属层与半导体图案层对应的区域的表面为Al层，Al层采用磁控溅射法形成。
参阅图3所示，第二金属层25用于制得本发明实施例的IGZO沟道的保护层，该第二金属层25优选为采用磁控溅射法在300～400℃的温度下形成的Al层。当然，其他实施例的第二金属层25可以仅在表面设置预定厚度的Al层，或者仅在对应于半导体图案层24的表面设置预定厚度的Al层，而在Al层的下方采用预定方式形成一层衬底，本发明对于该衬底的材质并不予以限制。
磁控溅射方式形成Al层的过程中，不会产生氢原子等杂质，因此相比较于化学气相沉积方式或者等离子增强化学气相沉积(Plasma Enhanced Chemical vapor deposition，PECVD)方式，本发明实施例不仅能够减少对IGZO沟道的损伤，而且可避免氢原子等杂质掺入半导体图案层24(IGZO沟道)，从而确保IGZO沟道的电学性能。
并且，磁控溅射方式的工艺简单易实现，与化学气相沉积方式以及或者等离子增强化学气相沉积相比效率高，有利于产业化。
S13：在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理，使得Al层发生氧化反应以形成Al2O3层。
继续参阅图3所示，Al层(第二金属层25)中的Al原子在氧气O2浓度高于21％的富氧氛围中发生氧化反应，能够最大程度的生成Al2O3层26，同时300～400℃的温度能够促使所述氧化反应以使Al层中尽可能多的Al原子被氧化，从而最大程度的保证所形成的Al2O3层26的致密性，使其膜 质较高，进一步确保IGZO沟道的电学性能。
在本发明实施例中，在富氧氛围中进行热退火处理可同时具有三个作用：一是，降低IGZO主动层(IGZO沟道)的缺陷态密度(主要是降低氧空位浓度)，获得良好的主动层电学特性；二是，一定程度上修复在第二金属层25沉积和图案化过程中，磁控溅射工艺和刻蚀工艺对主动层的沟道造成的损伤；三是，将Al层氧化为膜质较高的Al2O3层26，形成沟道保护层。
S14：对包含Al2O3层的第二金属层进行刻蚀，以在半导体图案层上保留具有预定尺寸的保护层。
继续参阅图3所示，本发明实施例可以采用包括但不限于湿法刻蚀、干法刻蚀等方式对Al2O3层26进行刻蚀。该预定尺寸为TFT的IGZO沟道的尺寸，该预定尺寸的保护层(图示为Al2O3层26)即为IGZO沟道的保护层。
S15：在Al2O3层上形成第三金属层，第三金属层形成有凹槽，且凹槽暴露其对应区域的Al2O3层。
参阅图4所示，第三金属层27为TFT的源漏电极层，包括源极271和漏极272，源极271和漏极272位于所述保护层的两侧。
进一步地，本发明实施例的制造方法还包括：在被暴露的Al2O3层(预定尺寸的Al2O3层26)和第三金属层27上形成钝化层28。其中，可以采用化学气相沉积、原子层外延、涂覆、溅射以及蒸镀中的任意组合方式在被暴露的Al2O3层26和第三金属层27上形成钝化层28。并且，该钝化层28和第二金属层25的材质可以相同也可以不相同。
本发明实施例还提供一种采用上述方法制得的具有图4所示结构的阵列基板，该阵列基板的其他结构的制造方法可参阅现有技术。
本发明实施例还提供一种液晶显示面板，如图5所示，该液晶显示面板50包括上述阵列基板10、与阵列基板10相对间隔设置的彩膜基板51以及夹设于阵列基板10和彩膜基板51之间的液晶52。
应理解，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种阵列基板的制造方法，其中，所述方法包括：
    在衬底基材上依次形成第一金属层、绝缘层和半导体图案层；
    在所述绝缘层和所述半导体图案层上形成第二金属层，其中所述第二金属层与所述半导体图案层对应的区域的表面为铝Al层，且所述Al层采用磁控溅射法形成；
    在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理，使得所述Al层发生氧化反应形成Al2O3层；
    对包含所述Al2O3层的第二金属层进行刻蚀，以在所述半导体图案层上保留具有预定尺寸的保护层；
    在所述Al2O3层上形成第三金属层，所述第三金属层形成有凹槽，且所述凹槽暴露其对应区域的Al2O3层。
  2. 根据权利要求1所述的方法，其中，所述第一金属层为所述阵列基板的薄膜晶体管的栅极，所述第三金属层包括所述薄膜晶体管的源极和漏极，所述源极和所述漏极位于所述凹槽的两侧。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：
    在被暴露的所述Al2O3层和所述第三金属层上形成钝化层。
  4. 根据权利要求3所述的方法，其中，采用化学气相沉积、原子层外延、涂覆、溅射以及蒸镀中的任意组合方式在被暴露的所述Al2O3层和所述第三金属层上形成所述钝化层。
  5. 根据权利要求4所述的方法，其中，所述钝化层的材质和所述第二金属层的材质不相同。
  6. 根据权利要求6所述的方法，其中，所述钝化层的材质和所述第二金属层的材质相同。
  7. 一种阵列基板，其中，所述阵列基板包括：
    衬底基材；
    依次形成于所述衬底基材上的第一金属层、绝缘层和半导体图案层；
    保护层，形成于所述半导体图案层上，所述保护层的表面为Al2O3层，所述Al2O3层由采用磁控溅射法形成的Al层在氧气浓度高于21％的氛围中 以300～400℃的温度进行热退火处理制得；
    第三金属层，形成于所述Al2O3层上，所述第三金属层形成有凹槽，且所述凹槽暴露其对应区域的Al2O3层。
  8. 根据权利要求7所述的阵列基板，其中，所述第一金属层为所述阵列基板的薄膜晶体管的栅极，所述第二金属层包括所述薄膜晶体管的源极和漏极，所述源极和所述漏极位于所述凹槽的两侧。
  9. 一种液晶显示面板，其中，所述液晶显示面板包括阵列基板、与所述阵列基板相对间隔设置的彩膜基板以及夹设于两者之间的液晶，所述阵列基板包括：
    衬底基材；
    依次形成于所述衬底基材上的第一金属层、绝缘层和半导体图案层；
    保护层，形成于所述半导体图案层上，所述保护层的表面为Al2O3层，所述Al2O3层由采用磁控溅射法形成的Al层在氧气浓度高于21％的氛围中以300～400℃的温度进行热退火处理制得；
    第三金属层，形成于所述Al2O3层上，所述第三金属层形成有凹槽，且所述凹槽暴露其对应区域的Al2O3层。
  10. 根据权利要求7所述的液晶显示面板，其中，所述第一金属层为所述阵列基板的薄膜晶体管的栅极，所述第二金属层包括所述薄膜晶体管的源极和漏极，所述源极和所述漏极位于所述凹槽的两侧。
PCT/CN2015/099737 2015-12-21 2015-12-30 阵列基板及其制造方法、液晶显示面板 Ceased WO2017107238A1 (zh)

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