WO2017101521A1 - 一种氮化物发光二极管及其生长方法 - Google Patents

一种氮化物发光二极管及其生长方法 Download PDF

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WO2017101521A1
WO2017101521A1 PCT/CN2016/097870 CN2016097870W WO2017101521A1 WO 2017101521 A1 WO2017101521 A1 WO 2017101521A1 CN 2016097870 W CN2016097870 W CN 2016097870W WO 2017101521 A1 WO2017101521 A1 WO 2017101521A1
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layer
type
emitting diode
light emitting
nitride light
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PCT/CN2016/097870
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English (en)
French (fr)
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蓝永凌
张家宏
林兓兓
黄文宾
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厦门市三安光电科技有限公司
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Publication of WO2017101521A1 publication Critical patent/WO2017101521A1/zh
Priority to US15/870,899 priority Critical patent/US20180138367A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and in particular, to a nitride light emitting diode and a growth method thereof.
  • Chinese patent document CN201310032282.9 discloses an epitaxial structure of a large-sized chip light effect and a growth method thereof, maintaining the total thickness of the original n-type GaN, changing the heterogeneous manner of Si of the n-type GaN layer, and passing the cycle.
  • Sexually miscellaneous Si and non-discrete Si alternately grow, the disparate Si GaN is low-resistance, and the Si-doped GaN is high-resistance, and the high- and low-resistance n-type GaN is used in the current transport process.
  • the electronic lateral expansion capability is enhanced, on the one hand, the current crowding phenomenon is solved, the driving voltage is lowered, on the other hand, the quantum well current is uniformized, the overall light-emitting area is increased, and the brightness and the light effect are improved.
  • an object of the present invention is to provide a nitride light-emitting diode and a growth method thereof, which have a concentration of 1 ⁇ 10 2 by increasing the complexity of the n-type GaN layer. / cm 3 or more, reduce the series resistance and contact resistance of the LED, and reduce the operating voltage of the chip.
  • the unhealthy A1G is used under high temperature and low pressure conditions.
  • the superlattice structure formed by alternately stacking the aN layer and the n-type GaN layer, and adjusting the first concentration of the undoped AlGaN layer and the n-type GaN layer by adjusting the impurity concentration of the n-type GaN layer
  • the resulting second stresses that are different from the first stress cancel each other out, reducing crystal defects and warpage.
  • the lattice mismatch phenomenon of the layer and the occurrence of cracks and warpage due to excessive first stress are controlled.
  • the n-type layer adopts a superlattice structure formed by alternately forming an undoped AlGaN layer and an n-type miscellaneous GaN layer, which can effectively disperse the electric field and also enhance the antistatic capability.
  • a nitride light emitting diode provided by the present invention includes a substrate, and a buffer layer, an n-type layer, a quantum well light-emitting layer and a p-type layer sequentially formed on the substrate, wherein the n-type layer is a superlattice structure formed by alternately stacking a disparate AlGaN layer and an n-type doped GaN layer, the undoped AlGaN layer generating a first stress, canceling a second stress generated by the n-type GaN layer, thereby reducing n Crystal defects and warpage caused by squalor.
  • the A1 component of the undoped AlGaN layer is controlled such that the first stress generated by the impurity is canceled by the second stress generated by the n-type GaN layer.
  • the impurity concentration of the n-type GaN layer is greater than or equal to 1 ⁇ 10 20 /cm 3 .
  • the n-type GaN layer was badly heteroaryl 1x10 20 / cm 3 ⁇ lxl0 22 / cm 3.
  • the thickness of the n-type GaN layer is greater than the thickness of the unearthed AlGaN layer, for adjusting the surface flatness of the superlattice structure, and improving the crystal quality of the superlattice structure.
  • the thickness ratio of the undoped AlGaN layer to the n-type GaN layer is 1:2 ⁇ 1:4.
  • the n-type GaN layer has a thickness of 5 ⁇ to 150 ⁇ .
  • the aluminum component in the undoped AlGaN layer is 3 ⁇ 3 ⁇ 4 ⁇ 8 ⁇ 3 ⁇ 4.
  • the n-type impurity is Si, Ge, Sn or Pb.
  • the number of cycles of the superlattice structure layer is 60-150.
  • the present invention also provides a method for growing a nitride light emitting diode, comprising the steps of: Sl, providing a substrate; S2, growing a buffer layer on the substrate; S3, growing in the nitride buffer layer Forming a layer; and continuing to grow a quantum well light-emitting layer and a p-type layer on the N-type layer; wherein, in the step S3), the n-type layer is formed by alternately stacking undoped AlGaN and n-type GaN layers a superlattice structure, the first undoped AlGaN layer generates a first stress, canceling a second stress generated by the n-type GaN layer, thereby reducing crystals generated by the n-type layer due to catastrophic enthalpy Defects and warpage.
  • the first stress generated by the undoped AlGaN layer and the second stress generated by the n-type doped GaN layer cancel each other by controlling the A1 composition of the unearthed AlGaN layer.
  • the epitaxial growth chamber temperature is greater than 1050 ° C, and the pressure is lower than 100 torr.
  • the impurity concentration of the n-type GaN layer is greater than or equal to 1 ⁇ 10 2 o/ cm 3 , and further, the impurity concentration ranges from 1 ⁇ 10 2 ( Vcm 3 to l ⁇ 10 22 /cm 3 ) .
  • the thickness of the n-type GaN layer is greater than the thickness of the unearthed AlGaN layer, for adjusting the surface flatness of the superlattice structure, and improving the crystal quality of the superlattice structure, Further, a thickness ratio of the undoped AlGaN layer to the n-type GaN layer is 1:2 to 1:4, wherein the n-type GaN layer has a thickness of 5 ⁇ to 150 ⁇ .
  • the aluminum component in the AlGaN layer is 3 ⁇ 3 ⁇ 4 ⁇ 8 ⁇ 3 ⁇ 4.
  • the n-type impurity is Si, Ge, Sn or Pb.
  • the number of cycles of the superlattice structure layer is 60-150.
  • the present invention has at least the following beneficial effects: 1)
  • the n-type layer adopts a superlattice structure in which an undoped AlGaN layer and an n-type GaN layer are alternately stacked, so that the undoped AlGaN layer in the superlattice structure is generated.
  • the first stress and the second stress generated by the n-type GaN layer cancel each other, and reduce crystal defects and warpage caused by the high concentration of the n-type layer, for example, surface black spots and fogging problems;
  • the impurity concentration of the n-type layer is 1x1 0 20 /cm 3
  • the series resistance of the crystal is lowered, thereby lowering the driving voltage thereof; 3) controlling the thickness of the undoped AlGaN layer and the n-type GaN layer, so that the undistracted AlGaN layer is smaller than the thickness of the n-type GaN layer, Adjusting the surface flatness of the superlattice structure, improving the crystal quality of the superlattice structure, reducing lattice mismatch with the subsequent epitaxial layer, and causing cracks and crystal warpage due to excessive tensile stress; 4
  • the superlattice structure formed by the undoped AlGaN layer and the n-type GaN layer can effectively disperse the electric field, thereby improving the antistatic ability and device stability.
  • FIG. 1 is a schematic structural view of a nitride light emitting diode according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of an N-type layer according to an embodiment of the present invention.
  • FIG. 3 is a flow chart of growth of a nitride light emitting diode according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a nitride light emitting diode formed according to a growth process of a nitride light emitting diode.
  • a nitride light emitting diode includes a substrate 10, and a nitride buffer layer 20, an n-type layer 40, a quantum well light-emitting layer 50, and a p-type layer 60, which are sequentially disposed on the substrate 10.
  • the example further includes a u-GaN layer 30 sandwiched between the nitride buffer layer 20 and the n-type layer 40, wherein the substrate 10 is a sapphire flat substrate, a sapphire patterned substrate, a silicon nitride substrate, and a GaN liner.
  • the nitride buffer layer 20 is a single layer structure or a superlattice structure, and the constituent material of the nitride buffer layer 20 is GaN, AlN, AlGaN or Al xM yGa i- x. — y N (x>0, y ⁇ 0), M is indium, silicon, or metal, and the p-type layer 60 is a GaN layer of Mg.
  • the n-type impurity concentration is generally less than 1 ⁇ 10 ll Vcm 3 because the n-type impurity is greater than lxl0 2 . / cm 3 ⁇ , which causes surface defects and warpage of the crystal, such as black spots and fogging; and as its impurity concentration increases, the series resistance of the n-type layer 40 decreases, thereby lowering the overall light-emitting diode Voltage. Therefore, in view of the adverse effects of the impurity concentration on the crystal quality and the series resistance, how to reduce the surface defects and warpage caused by the crystal under the premise of increasing the series resistance and reducing the series resistance is a key problem solved by the present invention.
  • the n-type layer 40 in the present embodiment adopts an undoped AlGaN layer. 41 and n-type miscellaneous GaN layer 42
  • the superlattice structure formed by alternately stacking causes the first stress generated by the undoped AlGaN layer 41 in the superlattice structure to cancel out the second stress generated by the n-type GaN layer 42 to reduce the n-type layer Miscellaneous crystal defects and warpage.
  • the n-type impurity is Si, Ge, Sn or Pb, and this embodiment is preferably Si.
  • the first stress and the second stress are different in stress direction or different in stress type.
  • the first stress generated by the undissimilar AlGaN layer 41 and the second stress generated by the n-type doped GaN layer 42 are different types.
  • the stress, the first stress is the tensile stress, and the second stress is the compressive stress.
  • the tensile stress generated by the undoped AlGaN layer 41 increases as the A1 composition increases, and the compressive stress generated by the n-type GaN layer 42 varies with the Si impurity concentration and The thickness thereof increases, so that in order to offset the tensile stress generated by the undoped AlGaN layer 41 in the superlattice structure and the compressive stress generated by the n-type GaN layer 42 in the super-lattice structure, the adjustment is not uncomfortable in this embodiment.
  • the Si concentration of the A1 component, the n-type doped GaN layer 42 in the hetero-AlGaN layer 41, and the thickness of the n-type doped GaN layer 42 and the unearthed AlGaN layer 41 achieve stress cancellation.
  • the A1 component in the undoped AlGaN layer 41 is 3 ⁇ 3 ⁇ 4 ⁇ 8 ⁇ 3 ⁇ 4, and the Si impurity concentration is 1x10 2Q /cm 3 ⁇ lxl0 22 /cm 3 .
  • the Si concentration of the n-type doped GaN layer 42 is larger than that of the conventional 1x10 19 /cm 3 , the compressive stress generated by the n-type GaN layer 42 and the tensile stress generated by the undoped AlGaN layer 41 can be completely completed in each period.
  • the n-type GaN layer 42 and the unearthed AlGaN layer 41 are each a thin layer structure in each period; specifically, the n-type GaN layer 42 has a thickness of 5 ⁇ to 150 ⁇ , and the undoped AlGaN layer 41
  • the thickness ratio of the n-type GaN layer 42 is 1:2-1:4, and the undoped AlGaN layer 41 is set without changing the total thickness of the conventional N-type layer 40 (usually 1 micrometer to 2.5 micrometers).
  • the number of superlattice structure periods composed of the n-type GaN layer 42 is 60 to 150.
  • the thickness of the n-type GaN layer 42 is set to be larger than the thickness of the undoped AlGaN layer 41, and a surface-flattened n-type impurity GaN layer 42 is formed in each period, thereby adjusting the surface flatness of the superlattice structure.
  • the extension of the lattice defect is suppressed, and on the other hand, the tensile stress generated by the undoped AlGaN layer 41 is prevented from being excessively large, so that the compressive stress generated by the n-type GaN layer 42 cannot cancel the tensile stress and cause cracks.
  • the present embodiment provides a growth method, which is specifically as follows: Sl, providing a substrate 10; S2, growing a nitride on the substrate 10 The buffer layer 20; S3, growing the n-type layer 40 on the nitride buffer layer 20; S4, continuing to grow the quantum well light-emitting layer 50 and the p-type layer 60 in the n-type layer 40.
  • the n-type layer 40 formed in the step S3 is a superlattice structure formed by alternately stacking the undoped AlGaN 41 and the n-type doped GaN layer 42 , and the super-lattice structure is not miscellaneous in the AlGaN layer.
  • the first stress generated by 41 The second stress generated by the n-type GaN layer 42 different from the first stress cancels each other, and is used to reduce the crystal defects and warpage of the N-type layer 40 due to turbulence.
  • step S1 further includes processing the substrate 10 at a high temperature in a hydrogen atmosphere of 1100 to 1200 ° C for removing impurities on the surface of the substrate 10; after step S4), a chip fabrication step is generally performed, for example, The n-electrode 70 and the p-electrode 80 are formed on the n-type layer 40 and the p-type layer 60 by sizing, development, exposure, etching, and vapor deposition, respectively.
  • the GaN buffer layer 20 is preferably grown on a sapphire substrate at a low temperature. Since the sapphire substrate and the GaN have a heterostructure, in order to further buffer the extension of the lattice mismatch defect between the substrate and the GaN epitaxial layer, the present embodiment The example further includes the step of growing a high temperature u-GaN layer 30 after step S2) to improve the quality of the underlying crystal. Thereafter, the undoped AlGaN and the n-type GaN superlattice structure are continuously grown on the u-GaN layer 30, the reaction chamber temperature is adjusted to be greater than 1050 ° C, the pressure is less than lOOtorr, and the carrier gas flow rate is controlled.
  • the AlGaN layer 41 is then grown on the undoped AlGaN layer 41 with an n-type doped GaN layer 42 having an n -type impurity concentration greater than or equal to 1 x 10 20 /cm 3 , thus circulating for 60 to 150 cycles.
  • the first stress generated by the undissimilar AlGaN layer 41 and the second stress generated by the n-type GaN layer 42 different from the first stress cancel each other, and the impurity concentration of the n-type miscellaneous GaN layer 42 is reduced to be greater than or It is equal to 1x10 ⁇ lcm 3 ⁇ resulting in crystal defects and warpage.
  • the other parameters of the structure formed by the method and the principle of action thereof are the same as those described above, and are not described here.
  • the present embodiment controls the impurity concentration of the n-type layer 40 to be greater than or equal to 1 ⁇ 10 ⁇ lcm 3 to greatly reduce the series resistance of the LED, thereby reducing the driving voltage of the chip, and the n-type layer 40.
  • the single growth mode is changed to a superlattice structure formed by the undoped AlGaN layer 41 and the n-type GaN layer 42 to reduce crystal defects and warpage caused by the n-type impurity concentration greater than or equal to 1 x 10 2o/ cm 3 .
  • the phenomenon of curvature further improving the photoelectric performance of the device.

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Abstract

一种氮化物发光二极管及其生长方法，其中结构包括基板（10），及依次形成于基板上的氮化物缓冲层（20）、n型层（40）、量子阱发光层（50）和p型层（60），n型层为未掺杂AlGaN层（41）与n型掺杂GaN层（42）交替堆叠形成的超晶格结构，控制未掺杂AlGaN层的Al组分以产生第一应力，用于抵消n型掺杂GaN层产生的第二应力，从而降低n型层因掺杂杂质时产生的晶体缺陷和翘曲。同时提供一种氮化物发光二极管的生长方法，通过控制n型层的生长温度和压力，n型掺杂GaN层的厚度大于未掺杂AlGaN层的厚度，用于改善未掺杂AlGaN层表面粗糙度，形成表面平整的n型掺杂GaN层。在改善器件串联电阻的同时，改善晶体缺陷和翘曲，进一步提高器件的光电性能。

Description

说明书 发明名称：一种氮化物发光二极管及其生长方法 技术领域
[0001] 本发明属于半导体制造技术领域， 特别涉及一种氮化物发光二极管及其生长方 法。
背景技术
[0002] 随着氮化物半导体组件应用领域的扩大， 除了要求其具有高亮度外， 提高静电 耐压与降低操作电压的重要性也随之提高， 尤其是目前市场上大尺寸、 大功率 芯片在照明、 背光源等领域的运用， 要求其在额定驱动电流吋， 减小电压和提 高发光亮度， 使其能更有效的降低能源消耗。
[0003] 中国专利文献 CN201310032282.9公幵了一种大尺寸芯片光效的外延结构及其生 长方法， 保持原来 n型 GaN的总厚度， 改变 n型 GaN层的 Si的惨杂方式， 通过周期 性的惨杂 Si和不惨杂 Si的交替生长， 惨杂 Si的 GaN为低阻值， 不惨杂 Si的 GaN为 高阻值， 禾 1」用高低电阻值的 n型 GaN在电流输送过程中使电子横向扩展能力加强 ， 一方面解决电流拥挤现象， 降低驱动电压， 另一方面使得量子阱电流均匀化 ， 总体发光面积增加， 提升了亮度和光效。
技术问题
[0004] 虽然前案在一定程度上通过解决电流拥挤现象降低了芯片的驱动电压， 但是其 并没有从根本上改善氮化镓材料导电性差， 串联电阻较高而导致的芯片驱动电 压高的问题， 以及目前市场上对低能耗 LED照明的要求， 因此， 亟需提供一种技 术可以大幅度降低芯片工作的电压以满足市场低功率、 低能耗的需求。
问题的解决方案
技术解决方案
[0005] 鉴于以上需求， 本发明的目的在于提供一种氮化物发光二极管及其生长方法， 通过提高 n型惨杂 GaN层的惨杂使其浓度为 lxl0 2。/cm 3以上， 降低发光二极管的 串联电阻与接触电阻， 降低芯片的工作电压。 同吋， 为了改善因 n型惨杂 GaN层 惨杂浓度太高而产生的晶体缺陷及翘曲现象， 在高温低压条件下采用未惨杂 A1G aN层与 n型惨杂 GaN层交替堆叠形成的超晶格结构， 并通过调节 n型惨杂 GaN层的 惨杂浓度， 使未惨杂 AlGaN层产生的第一应力与 n型惨杂 GaN层产生的与第一应 力不同的第二应力相互抵消， 降低晶体缺陷及翘曲。 另一方面， 通过控制未惨 杂 AlGaN层与 n型惨杂 GaN层的厚度， 用于调整所述超晶格结构的表面平整度， 改善所述超晶格结构的晶体质量； 减少与后续外延层的晶格失配现象及因第一 应力过大而产生裂纹和翘曲现象。 同吋， n型层采用未惨杂 AlGaN层与 n型惨杂 G aN层交替形成的超晶格结构， 可有效分散电场， 也随之提升抗静电能力。
[0006] 本发明提供的一种氮化物发光二极管， 包括一基板， 及依次形成于所述基板上 的缓冲层、 n型层、 量子阱发光层和 p型层， 所述 n型层为未惨杂 AlGaN层与 n型惨 杂 GaN层交替堆叠形成的超晶格结构， 所述未惨杂 AlGaN层产生第一应力， 抵消 所述 n型惨杂 GaN层产生的第二应力， 从而降低 n型层因惨杂吋产生的晶体缺陷及 翘曲。
[0007] 优选的， 控制所述未惨杂 AlGaN层的 A1组分， 使其产生的第一应力与所述 n型 惨杂 GaN层产生的第二应力相互抵消。
[0008] 优选的， 所述 n型惨杂 GaN层的惨杂浓度大于或等于 1x10 20/cm 3。
[0009] 优选的， 所述 n型惨杂 GaN层的惨杂浓度为 1x10 20/cm 3~lxl0 22/cm 3。
[0010] 优选的， 所述 n型 GaN层的厚度大于所述未惨杂 AlGaN层的厚度， 用于调整所 述超晶格结构的表面平整度， 改善所述超晶格结构的晶体质量。
[0011] 优选的， 所述未惨杂 AlGaN层与 n型 GaN层的厚度比为 1 :2~ 1 :4。
[0012] 优选的， 所述 n型 GaN层的厚度为 5埃〜 150埃。
[0013] 优选的， 所述未惨杂 AlGaN层中铝组分为 3<¾~8<¾。
[0014] 优选的， 所述 n型惨杂杂质为 Si、 Ge、 Sn或 Pb。
[0015] 优选的， 所述超晶格结构层的周期数为 60~150。 同吋， 本发明还提供了一种氮 化物发光二极管的生长方法， 包括以下步骤： Sl、 提供一基板； S2、 在所述基 板上生长缓冲层； S3、 在所述氮化物缓冲层生长 n型层； S4、 在所述 N型层上继 续生长量子阱发光层和 p型层； 其中， 所述步骤 S3) 中 n型层为未惨杂 AlGaN与 n 型惨杂 GaN层交替堆叠形成的超晶格结构， 所述未惨杂 AlGaN层产生第一应力， 抵消所述 n型惨杂 GaN层产生的第二应力， 从而降低 N型层因惨杂吋产生的晶体 缺陷及翘曲。
[0016] 优选的， 通过控制所述未惨杂 AlGaN层的 A1组分， 使所述未惨杂 AlGaN层产生 的第一应力与所述 n型惨杂 GaN层产生的第二应力相互抵消。
[0017] 优选的， 所述外延生长吋反应室温度大于 1050°C， 压力低于 100torr。
[0018] 优选的， 所述 n型惨杂 GaN层的惨杂浓度大于或等于 1x10 2o/cm 3， 进一步地其 惨杂浓度范围为 1x10 2(Vcm 3~lxl0 22/cm 3。
[0019] 优选的， 所述 n型 GaN层的厚度大于所述未惨杂 AlGaN层的厚度， 用于调整所 述超晶格结构的表面平整度， 改善所述超晶格结构的晶体质量， 进一步地， 所 述未惨杂 AlGaN层与 n型 GaN层的厚度比为 1:2~1:4， 其中所述 n型 GaN层的厚度为 5埃〜 150埃。
[0020] 优选的， 所述 AlGaN层中铝组分为 3<¾~8<¾。
[0021] 优选的， 所述 n型惨杂杂质为 Si、 Ge、 Sn或 Pb。
[0022] 优选的， 所述超晶格结构层的周期数为 60~150。
发明的有益效果
有益效果
[0023] 本发明至少具有以下有益效果： 1) n型层采用未惨杂 AlGaN层与 n型惨杂 GaN 层交替堆叠的超晶格结构， 使超晶格结构中未惨杂 AlGaN层产生的第一应力与所 述 n型惨杂 GaN层产生的第二应力相互抵消， 降低 n型层因惨杂浓度较高吋产生的 晶体缺陷及翘曲现象， 例如， 表面黑点和雾化问题； 2) n型层的惨杂浓度为 1x1 0 20/cm 3
以上， 降低晶体的串联电阻， 进而降低其驱动电压； 3) 控制未惨杂 AlGaN层与 n 型惨杂 GaN层的厚度， 使未惨杂 AlGaN层小于 n型惨杂 GaN层的厚度， 用于调整 所述超晶格结构的表面平整度， 改善所述超晶格结构的晶体质量， 减少与后续 外延层的晶格失配现象及因张应力过大而产生裂纹及晶体翘曲现象； 4) 未惨杂 AlGaN层与 n型惨杂 GaN层形成的超晶格结构能有效分散电场， 随之提升抗静电 能力和器件的稳定性。
对附图的简要说明
附图说明 [0024] [0024]附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本 发明的实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数 据是描述概要， 不是按比例绘制。
[0025] 图 1为本发明实施例之氮化物发光二极管结构示意图。
[0026] 图 2为本发明实施例之 N型层结构示意图。
[0027] 图 3为本发明实施例之氮化物发光二极管生长流程图。
[0028] 图 4为根据氮化物发光二极管生长流程形成的氮化物发光二极管结构示意图。
[0029] 附图标注： 10: 基板； 20: 缓冲层； 30: u-GaN层； 40: n型层； 41 : 未惨杂 A1
GaN层； 42： n型惨杂 GaN层； 50: 量子阱发光层； 60: p型层； 70: n电极； 80
： p电极。
实施该发明的最佳实施例
本发明的最佳实施方式
[0030] 下面结合附图和实施例对本发明的具体实施方式进行详细说明。
[0031] 参看附图 1， 一种氮化物发光二极管， 包括基板 10， 及依次位于基板 10上的氮 化物缓冲层 20、 n型层 40、 量子阱发光层 50和 p型层 60， 本实施例中还包括夹于 氮化物缓冲层 20和 n型层 40之间的 u-GaN层 30， 其中， 基板 10为蓝宝石平片衬底 、 蓝宝石图形化衬底、 氮化硅衬底、 GaN衬底、 硅衬底、 玻璃衬底或者金属衬底 中的任意一种， 氮化物缓冲层 20为单层结构或超晶格结构， 其组成材料为 GaN、 A1N、 AlGaN或者 Al xM yGa i— x—yN(x〉0， y〉0)中的任意一种或几种， M为铟、 硅 或金属等， p型层 60为惨杂 Mg的 GaN层。
[0032] 现有技术中， 外延生长的 n型层 40中， 其 n型惨杂浓度一般小于 1x10 llVcm 3， 因 为当 n型惨杂大于 lxl0 2。/cm 3吋， 会使晶体产生表面缺陷和翘曲现象， 例如黑点 和雾化等； 而随着其惨杂浓度的增大， n型层 40的串联电阻将降低， 进而降低整 体发光二极管的电压。 因此， 针对惨杂浓度对晶体质量和串联电阻的相反影响 结果， 如何在增大惨杂浓度降低串联电阻的前提下降低晶体产生的表面缺陷和 翘曲现象是本发明解决的关键问题。
[0033] 参看附图 2， 为解决当惨杂浓度较高吋， 晶体产生的表面缺陷和翘曲现象， 例 如黑点和雾化等， 本实施例中 n型层 40采用未惨杂 AlGaN层 41与 n型惨杂 GaN层 42 交替堆叠形成的超晶格结构， 使超晶格结构中未惨杂 AlGaN层 41产生的第一应力 与 n型惨杂 GaN层 42产生的第二应力相互抵消， 用于降低 n型层因惨杂而产生的晶 体缺陷及翘曲。 n型惨杂杂质为 Si、 Ge、 Sn或 Pb， 本实施例优选为 Si。 第一应力 与第二应力为应力方向不同或应力类型不同， 在本实施例中， 未惨杂 AlGaN层 41 产生的第一应力与 n型惨杂 GaN层 42产生的第二应力为不同类型的应力， 第一应 力为张应力， 第二应力为压应力。
[0034] 继续参看附图 2， 未惨杂 AlGaN层 41产生的张应力， 随着 A1组分的增加而增大 ， 而 n型惨杂 GaN层 42产生的压应力随着 Si惨杂浓度以及其厚度的增大而增大， 因此为了使超晶格结构中未惨杂 AlGaN层 41产生的张应力与 n型惨杂 GaN层 42产 生的压应力相互抵消， 本实施例中通过调节未惨杂 AlGaN层 41中 A1组分、 n型惨 杂 GaN层 42的 Si浓度以及 n型惨杂 GaN层 42和未惨杂 AlGaN层 41的厚度实现应力 抵消。 具体的， 未惨杂 AlGaN层 41中 A1组分为 3<¾~8<¾， Si惨杂浓度为 1x10 2Q/cm 3 ~lxl0 22/cm 3。 由于 n型惨杂 GaN层 42的 Si浓度较常规的 1x10 19/cm 3增大， 为使每 一周期内 n型 GaN层 42产生的压应力与未惨杂 AlGaN层 41产生的张应力能完全释 放并相互抵消， 每一周期内 n型 GaN层 42与未惨杂 AlGaN层 41均为薄层结构； 具 体地， n型 GaN层 42的厚度为 5埃〜 150埃， 未惨杂 AlGaN层 41与 n型 GaN层 42的厚 度比为 1 : 2-1： 4， 在不改变常规 N型层 40总厚度 （通常为 1微米〜 2.5微米） 的基 础上， 设定未惨杂 AlGaN层 41与 n型惨杂 GaN层 42组成的超晶格结构周期数为 60~ 150。 设定 n型 GaN层 42的厚度大于未惨杂 AlGaN层 41的厚度， 在每一周期内， 形 成表面平整的 n型惨杂 GaN层 42， 进而调整所述超晶格结构的表面平整度， 抑制 晶格缺陷的延伸， 另一方面防止因未惨杂 AlGaN层 41产生的张应力过大， 以至 n 型惨杂 GaN层 42产生的压应力无法抵消张应力的作用而产生裂纹。
[0035] 参看附图 3~4， 为制作上述的氮化物发光二极管， 本实施例提供了一种生长方 法， 具体如下： Sl、 提供一基板 10; S2、 在所述基板 10上生长氮化物缓冲层 20 ； S3、 在所述氮化物缓冲层 20上生长 n型层 40; S4、 在所述 n型层 40继续生长量 子阱发光层 50和 p型层 60。
[0036] 其中， 所述步骤 S3中形成的 n型层 40为未惨杂 AlGaN41与 n型惨杂 GaN层 42交替 堆叠形成的超晶格结构， 所述超晶格结构中未惨杂 AlGaN层 41产生的第一应力与 n型惨杂 GaN层 42产生的与第一应力不同的第二应力相互抵消， 用于降低 N型层 4 0因惨杂吋产生的晶体缺陷及翘曲。
[0037] 本实施例中， 步骤 S 1还包括在 1100~1200°C的氢气气氛下高温处理基板 10， 用 于清除基板 10表面的杂质； 在步骤 S4) 之后一般会进行芯片制作步骤， 例如通 过上胶、 显影、 曝光、 蚀刻、 蒸镀分别在 n型层 40和 p型层 60上制作 n电极 70、 p 电极 80。
[0038] 本实施例优选在蓝宝石衬底上低温生长 GaN缓冲层 20， 由于蓝宝石衬底与 GaN 为异质结构， 为了进一步缓冲衬底与 GaN外延层的晶格失配缺陷的延伸， 本实施 例还包括在步骤 S2) 之后生长一高温 u-GaN层 30的步骤， 提高底层晶体质量。 此 后， 在 u-GaN层 30上继续生长未惨杂 AlGaN与 n型惨杂 GaN超晶格结构， 调节反 应室温度大于 1050°C， 压力小于 lOOtorr, 并控制载气流量， 先生长未惨杂 AlGaN 层 41， 随后在未惨杂 AlGaN层 41上生长 n型惨杂浓度大于或等于 1x10 20/cm 3的 n型 惨杂 GaN层 42， 如此循环 60~150周期。 其中， 未惨杂 AlGaN层 41产生的第一应力 与 n型惨杂 GaN层 42产生的与第一应力不同的第二应力相互抵消， 降低 n型惨杂 G aN层 42的惨杂浓度大于或等于 1x10 ^lcm 3吋产生的晶体缺陷及翘曲。 通过本方 法形成的结构的其它参数及其作用原理与前述均相同， 在此不在累述。
[0039] 综上所述， 本实施例控制 n型层 40的惨杂浓度大于或等于 1x10 ^lcm 3来大幅度 降低发光二极管的串联电阻， 进而降低芯片的驱动电压， 并将 n型层 40的单一生 长方式改为未惨杂 AlGaN层 41与 n型惨杂 GaN层 42形成的超晶格结构， 降低因 n型 惨杂浓度大于或等于 1x 10 2o/cm 3带来的晶体缺陷及翘曲现象， 进一步提高器件的 光电性能。
[0040] 上述实施例仅示例性说明本发明的原理及其功效， 而非用于限制本发明。 任何 熟悉此技术的人士皆可在不违背本发明的精神及范畴下， 对上述实施例进行修 饰或改变。 因此， 举凡所属技术领域中具有通常知识者在未脱离本发明所揭示 的精神与技术思想下所完成的一切等效修饰或改变， 仍应由本发明的权利要求 所涵盖。

Claims

权利要求书
[权利要求 1] 一种氮化物发光二极管， 包括一基板， 及依次形成于所述基板上的缓 冲层、 n型层、 量子阱发光层和 p型层， 其特征在于： 所述 n型层为未 惨杂 AlGaN层与 n型惨杂 GaN层交替堆叠形成的超晶格结构， 所述未 惨杂 AlGaN层产生第一应力， 抵消所述 n型惨杂 GaN层产生的第二应 力。
[权利要求 2] 根据权利要求 1所述的氮化物发光二极管， 其特征在于： 调整所述未 惨杂 AlGaN层的 A1组分， 使所述未惨杂 AlGaN层产生的第一应力与所 述 n型惨杂 GaN层产生的第二应力相互抵消。
[权利要求 3] 根据权利要求 1所述的一种氮化物发光二极管， 其特征在于， 所述 n型 惨杂 GaN层的惨杂浓度大于或等于 1x10 2o/cm 3。
[权利要求 4] 根据权利要求 1所述的一种氮化物发光二极管， 其特征在于， 所述超 晶格结构中 n型惨杂 GaN层的厚度大于所述未惨杂 AlGaN层的厚度， 用于调整所述超晶格结构的表面平整度， 改善所述超晶格结构的晶体 质量。
[权利要求 5] 根据权利要求 4所述的一种氮化物发光二极管， 其特征在于， 所述未 惨杂 AlGaN层与 n型惨杂 GaN层的厚度比为 1 :2~ 1 :4。
[权利要求 6] 根据权利要求 1所述的一种氮化物发光二极管， 其特征在于， 所述 n型 惨杂 GaN层的厚度为 5埃~150埃。
[权利要求 7] 根据权利要求 1所述的一种氮化物发光二极管， 其特征在于， 所述未 惨杂 AlGaN层中铝组分为 3<¾~8<¾。
[权利要求 8] 根据权利要求 1所述的一种氮化物发光二极管， 其特征在于， 所述超 晶格结构的周期数为 60~150。
[权利要求 9] 一种氮化物发光二极管的生长方法， 包括以下步骤：
51、 提供一基板；
52、 在所述基板上生长缓冲层；
53、 在所述氮化物缓冲层上生长 n型层；
54、 在所述 n型层继续生长量子阱发光层和 p型层； 其特征在于： 所述步骤 S3) 中形成的 n型层为未惨杂 AlGaN与 n型惨杂 GaN层交替堆叠形成的超晶格结构， 所述未惨杂 AlGaN层产生第一应 力， 抵消所述 n型惨杂 GaN层产生的第二应力。
[权利要求 10] 根据权利要求 9所述的一种氮化物发光二极管的生长方法， 其特征在 于， 所述步骤 S3中通过控制所述未惨杂 AlGaN层的 A1组分， 使所述未 惨杂 AlGaN层产生的第一应力与所述 n型惨杂 GaN层产生的第二应力 相互抵消。
[权利要求 11] 根据权利要求 9所述的一种氮化物发光二极管的生长方法， 其特征在 于， 所述步骤 S3中生长条件为： 温度大于 1050°C， 压力小于 100torr。
[权利要求 12] 根据权利要求 9所述的一种氮化物发光二极管的生长方法， 其特征在 于， 所述 n型惨杂 GaN层的惨杂浓度大于或等于 1x10 2o/cm 3。
[权利要求 13] 根据权利要求 9所述的一种氮化物发光二极管的生长方法， 其特征在 于， 所述 n型 GaN层的厚度大于所述未惨杂 AlGaN层的厚度， 用于调 整所述超晶格结构的表面平整度， 改善所述超晶格结构的晶体质量。
[权利要求 14] 根据权利要求 9所述的一种氮化物发光二极管的生长方法， 其特征在 于： 所述 AlGaN层中铝组分为 3<¾~8<¾。
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