WO2017101175A1 - 一种薄膜晶体管及阵列基板 - Google Patents

一种薄膜晶体管及阵列基板 Download PDF

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WO2017101175A1
WO2017101175A1 PCT/CN2016/070274 CN2016070274W WO2017101175A1 WO 2017101175 A1 WO2017101175 A1 WO 2017101175A1 CN 2016070274 W CN2016070274 W CN 2016070274W WO 2017101175 A1 WO2017101175 A1 WO 2017101175A1
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layer
impedance
ohmic contact
thin film
film transistor
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PCT/CN2016/070274
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English (en)
French (fr)
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孙涛
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深圳市华星光电技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to the field of display technologies, and in particular to a thin film transistor and an array substrate.
  • the metal material of the conductive layer is mainly aluminum and molybdenum.
  • the advantages of aluminum and molybdenum are that the film forming process is simple, the adhesion and flatness are good, the softness is not easy to occur, and the film layer is not easily diffused to cause film contamination.
  • aluminum is the preferred conductive metal material of choice.
  • the resistivity of aluminum is relatively large.
  • the use of aluminum as a conductive layer easily causes a delay of the signal and affects the display effect of the display panel. Therefore, aluminum is not suitable for large-sized and high-resolution display panels.
  • ⁇ As a conductive metal material, copper has much better conductivity than aluminum.
  • UXGA Ultra-X Extended Graphics Array
  • the panel resolution can be increased by 35.2%
  • the brightness can be increased by 32%
  • the flicker and line load Can be greatly reduced. Therefore, in view of the current market demand for high-resolution panels, in the future display panels, copper is bound to replace aluminum.
  • the leakage current control of the back channel etch type TFT has always been a difficult process.
  • the leakage problem will be more obvious due to the diffusion of Cu ions, which causes the copper to be completely replaced by aluminum and applied to the flat panel display panel.
  • the current leakage of the copper is weakened by changing the metal type of the buffer metal layer and shortening the waiting time of the process.
  • this solution improves the process difficulty of preparing the array substrate and reduces the production efficiency of the array substrate.
  • an embodiment of the present invention first provides a thin film transistor including:
  • a gate insulating layer formed on the gate and covering the gate
  • the first material layer comprises: a first ohmic contact layer, a second ohmic contact layer and a high-impedance inclusion layer, the high-impedance inclusion layer being formed between the first ohmic contact layer and the second ohmic contact layer
  • the impedance is greater than the impedance of the first ohmic contact layer and the second ohmic contact layer.
  • the ratio of the impedance of the high-impedance inclusion layer to the impedance of the first ohmic contact layer ranges from [1.05, 1.45].
  • the first ohmic contact layer is in contact with the active layer, which comprises a first concentration of donor impurities, and the high-impedance interlayer contains a second concentration of donor impurities, wherein The first concentration is greater than the second concentration.
  • the high-impedance interlayer is obtained by positively epitaxy of the first ohmic contact layer.
  • the first ohmic contact layer is obtained by doping an N-type semiconductor substrate.
  • the high-impedance interlayer is formed by one or more chemical vapor deposition processes.
  • the reaction gas used in the chemical vapor deposition process comprises: nitrogen, ammonia or phosphine.
  • the constituent material of the active layer includes amorphous silicon, and the constituent material of the source/drain includes a conductive metal.
  • the thickness of the first material layer ranges from [300 ⁇ m, 400 ⁇ m]
  • the thickness of the high-impedance inclusion layer ranges from [100 ⁇ m, 200 ⁇ m].
  • the present invention also provides an array substrate comprising a plurality of thin film transistors arranged in an array, the thin film transistor being the thin film transistor according to any one of the above.
  • a high-impedance inclusion layer is formed in the ohmic contact layer of the thin film transistor provided by the present invention, and the high-impedance inclusion layer It can effectively reduce the leakage current existing between the source/drain and the active layer as a barrier layer for current flow.
  • the reduction of the leakage current of the thin film transistor can effectively improve the afterimage problem of the liquid crystal display panel using the thin film transistor.
  • the high-impedance inclusion layer can be formed by chemical vapor deposition, the production process of the thin film transistor does not increase the process difficulty of the thin film transistor.
  • 1 is a schematic structural view of a conventional thin film transistor
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 1 shows a schematic structural view of a conventional thin film transistor.
  • the conventional thin film transistor includes a glass substrate 101, a gate electrode 102, a gate insulating layer 103, an active layer 104, an ohmic contact layer 105, and source/drain electrodes 106.
  • the gate electrode 102 is formed on the glass substrate 101 and is made of a conductive metal.
  • the gate electrode 102 can be used to turn on or off the electron channel in the active layer 103.
  • the gate insulating layer 103 covers the glass substrate 101 and the gate electrode 102, and the active layer 104 is formed on the gate insulating layer 103.
  • the active layer 104 can provide a channel for electron transport, and the gate insulating layer 103 can effectively avoid electrical contact between the gate 102 and the active layer 104.
  • An ohmic contact layer 105 is formed on the active layer 104, and a source/drain 106 is formed on the ohmic contact layer 105.
  • the ohmic contact layer 105 can effectively reduce the impedance between the source/drain 105 and the active layer 103.
  • an electron channel is formed in the active layer 104.
  • a voltage is also applied to the source, electrons flow from the drain of the thin film transistor to the source through the electron channel in the active layer 104, thereby forming a guide between the source and the drain of the thin film transistor.
  • the current is passed, and the electrical connection between the source and the drain of the thin film transistor is also turned on.
  • the gate 102 of the thin film transistor is not applied with a voltage, the electron channel in the active layer 104 also disappears, thereby forming an open circuit between the source and the drain of the thin film transistor.
  • the present embodiment provides a new thin film transistor, and its structure is shown in FIG. 2 .
  • the thin film transistor provided in this embodiment includes a glass substrate 201, a gate electrode 202, a gate insulating layer 203, an active layer 204, a first material layer 205, and source/drain electrodes 206.
  • a partial enlarged view of the region A in the thin film transistor shown in FIG. 3 will be further described below as an example.
  • the gate electrode 202 is formed on the substrate 201, wherein the substrate 201 is preferably realized by glass.
  • the substrate 201 can also be implemented in other reasonable forms, and the present invention is not limited thereto.
  • the substrate 201 can also be implemented using a light transmissive resin.
  • the gate electrode 202 is formed on the substrate 201, and the gate insulating layer 203 is formed between the gate electrode 202 and the active layer 204.
  • the gate insulating layer 203 is used to achieve electrical isolation between the gate 202 and the active layer 204.
  • the material forming the gate insulating layer 203 is preferably SiN x /SiO x
  • the material forming the active layer 204 is preferably amorphous silicon.
  • the gate insulating layer 203 and/or the active layer 204 may also be implemented by other reasonable materials, and the present invention is not limited thereto.
  • the first material layer 205 is formed between the active layer 204 and the source/drain 206, and specifically includes a first ohmic contact layer 205a, a high-impedance inclusion layer 205b, and a second ohmic contact layer 205c.
  • the high-impedance inclusion layer 205b is formed between the first ohmic contact layer 205a and the second ohmic contact layer 205c, and the impedance thereof is greater than the impedances of the first ohmic contact layer 205a and the second ohmic contact layer 205c. Since the high-impedance inclusion layer 205b has a high impedance, it can effectively reduce leakage current between the active layer 204 and the source/drain 206.
  • the constituent materials of the first ohmic contact layer 205a and the second ohmic contact layer 205c may be the same or different according to actual needs, and the impedances thereof may be the same or The present invention is not limited thereto.
  • the first material layer 205 functions as an ohmic contact layer between the metal (ie, source/drain 206) and the semiconductor (ie, active layer 204).
  • the first material layer 205 also has a function as a barrier layer to hinder the electron flow between the source/drain 206 and the active layer 204, especially at the gate 202 of the thin film transistor. When a voltage is applied, a small amount of electrons flowing between the source and the drain are hindered, thereby improving the leakage current of the thin film transistor.
  • the contact resistance of an ideal ohmic contact should be small compared to a semiconductor device. When a current is passed, the voltage drop across the ohmic contact should be much less than the voltage drop of the semiconductor device itself, so that this contact does not affect the current-voltage of the device. characteristic.
  • the ratio of the impedance of the high-impedance inclusion layer 205b to the first ohmic contact layer 205a is preferably 1.1, that is, the impedance of the high-impedance inclusion layer 205b is 10% higher than the impedance of the first ohmic contact layer 205a.
  • the leakage current of the thin film transistor provided by the present embodiment is lower than that of the conventional thin film transistor. About one order of magnitude or more. It can be seen that the thin film transistor provided in this embodiment can effectively improve the leakage current problem existing in the existing thin film transistor.
  • the ratio of the impedance of the high-impedance inclusion layer 205b to the first ohmic contact layer 205a may be other reasonable values, and the present invention is not limited thereto.
  • the ratio of the impedance of the high-impedance inclusion layer 205b to the first ohmic contact layer 205a may also be other reasonable values in [1.05, 1.45] (eg, 1.07, 1.12, or 1.25, etc.).
  • the high-impedance inclusion layer 205b is formed by Chemical Vapor Deposition (CVD). Since electron mobility is larger than that of holes, in order to obtain good frequency characteristics, in the present embodiment, an N-type semiconductor material is preferably selected as the substrate.
  • the first ohmic contact layer 205a is a highly doped layer doped with a donor impurity of a first concentration.
  • the high-impedance inclusion layer is a low-doped layer doped with a second concentration of donor impurities. Wherein, the first concentration is greater than the second concentration such that the impedance of the high-impedance inclusion layer 205b is greater than the impedance of the first ohmic contact layer 205a.
  • the first ohmic contact layer 205a is formed by doping a high concentration of donor impurities into the N-type semiconductor substrate by a chemical vapor deposition process.
  • the reaction gas used preferably includes nitrogen, ammonia or phosphine.
  • the high-impedance inclusion layer 205b is formed by epitaxially elongating a high-impedance N-thin layer on the N+ substrate (ie, the first ohmic contact layer 205a).
  • the reaction gas used in the process of forming the high-impedance inclusion layer 205b by the positive epitaxy is the same as the reaction gas used in the process of forming the first ohmic contact layer 205a.
  • the reactive gas used in the process of forming the first ohmic contact layer 205a, the high-impedance inclusion layer 205b, and/or the second ohmic contact layer 205c by a chemical vapor deposition process is used.
  • Other reasonable gases may also be used, and the invention is not limited thereto.
  • the thickness of the first material layer in the thin film transistor preferably ranges from [300 ⁇ m, 400 ⁇ m]
  • the thickness of the high-impedance inclusion layer preferably ranges from [100 ⁇ m, 200 ⁇ m] .
  • the high-impedance inclusion layer 205b may also be formed by a plurality of chemical vapor deposition processes such that the high-impedance inclusion layer 205b includes a plurality of sub-material layers.
  • the high-impedance inclusion layer of the thin film transistor provided by the embodiment includes three sub-material layers (ie, the first The sub-material layer 205b_1, the second sub-material layer 205b_2, and the third sub-material layer 205b_3).
  • the impedances of the three sub-material layers may be equal or not equal (for example, the impedance of the second sub-material layer 205b_2 is greater than the impedances of the first sub-material layer 205b_1 and the third sub-material layer 205b_3).
  • the present invention also provides an array substrate in which a thin film transistor in which an array is arranged in the array substrate employs a thin film transistor as described above.
  • a high-impedance inclusion layer is formed in the ohmic contact layer of the thin film transistor provided by the present invention, and the high-impedance inclusion layer can serve as a barrier layer for current circulation, thereby effectively reducing the source/drain and active layers. The leakage current between them. The reduction of the leakage current of the thin film transistor can effectively improve the afterimage problem of the liquid crystal display panel using the thin film transistor.
  • the high-impedance inclusion layer can be formed by chemical vapor deposition, the production process of the thin film transistor does not increase the process difficulty of the thin film transistor.
  • the high-impedance inclusion layer in the thin film transistor provided by the present invention may also have a plurality of sub-material layers, and the discontinuous interface between the film layers in the sub-material layers also hinders the movement of electrons, thereby making the film
  • the leakage current of the transistor in the off state is further lowered, thereby further improving the leakage current of the thin film transistor. Therefore, when the thin film transistor is in the off state, the leakage current between the source and the drain is extremely small, and the charge stored in the pixel electrode is not leaked quickly, so that the problem of signal loss can be improved.

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Abstract

一种薄膜晶体管及阵列基板，薄膜晶体管包括：栅极（202）；栅极绝缘层（203），其形成在栅极上并覆盖栅极；有源层（204），其形成在栅极绝缘层上；第一材料层（205），其形成在有源层上；源/漏极（206），其形成在第一材料层上；其中，第一材料层包括：第一欧姆接触层（205a）、第二欧姆接触层（205c）以及高阻抗夹杂层（205b），高阻抗夹杂层形成在第一欧姆接触层与第二欧姆接触层之间，其阻抗大于第一欧姆接触层和第二欧姆接触层的阻抗。该薄膜晶体管能够有效降低源/漏极与有源层之间存在的漏电流，并且其制造工艺简单。

Description

一种薄膜晶体管及阵列基板
相关技术的交叉引用
本申请要求享有2015年12月14日提交的名称为：“一种薄膜晶体管及阵列基板”的中国专利申请CN201510925800.9的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种薄膜晶体管及阵列基板。
背景技术
随着平板显示(Flat Panel Display，简称为FPD)技术的发展，人们对显示器分辨率和画面刷新速率的要求越来越高，因此新材料和新工艺的发展也迫在眉睫。
目前在薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，简称为TFT-LCD)领域，导电层的金属材料以铝和钼为主。铝和钼的优点在于成膜工艺简单、黏附性和平坦性较好，较柔软不容易发生爬坡断线，而且不容易扩散造成膜层污染。对于小尺寸和低分辨率的显示面板而言，铝是首选的理想导电金属材料。
然而，铝的电阻率相对较大，对于大尺寸和高分辨率的显示面板而言，由于信号线较长，因此使用铝作为导电层容易引发信号的延时，影响显示面板的显示效果。因此，铝不适用于大尺寸和高分辨率的显示面板。
作为导电金属材料，铜的导电率要远远优于铝。对于15.0寸的极速扩展图形阵列(Ultra eXtended Graphics Array，简称UXGA)显示屏，采用铜取代铝作为导电金属材料，其面板分辨率可以提升35.2％，亮度可以提高32％，同时闪烁度和线负载都能大大降低。因此针对目前高分辨率面板的市场需求，在未来的显示面板中，铜势必将取代铝。
在常规的背沟道刻蚀型TFT的铝制程以及铜制程工艺中，背沟道刻蚀型TFT的漏电流控制一直都是制程难点。尤其在铜制程工艺中，由于Cu离子的扩散，漏电问题将更为明显，这也就致使铜尚未能够完全取代铝而应用到平板显示面板中。对于该问题，目前主要通过变更缓冲金属层的金属种类，并缩短制程的等待时间，以弱化铜的漏电情况。然而这一解决方案提高了制备阵列基板的工艺难度，降低了阵列基板的生产效率。
发明内容
本发明所要解决的问题是为了有效减小薄膜晶体管的漏电流现象。为解决上述问题，本发明的实施例首先提供了一种薄膜晶体管，其包括：
栅极；
栅极绝缘层，其形成在所述栅极上并覆盖所述栅极；
有源层，其形成在所述栅极绝缘层上；
第一材料层，其形成在所述有源层上；
源/漏极，其形成在所述第一材料层上；
其中，所述第一材料层包括：第一欧姆接触层、第二欧姆接触层以及高阻抗夹杂层，所述高阻抗夹杂层形成在所述第一欧姆接触层与第二欧姆接触层之间，其阻抗大于所述第一欧姆接触层和第二欧姆接触层的阻抗。
根据本发明的一个实施例，所述高阻抗夹杂层与第一欧姆接触层的阻抗之比的取值范围包括[1.05，1.45]。
根据本发明的一个实施例，所述第一欧姆接触层与所述有源层接触，其包含有第一浓度的施主杂质，所述高阻抗夹层含有第二浓度的施主杂质，其中，所述第一浓度大于第二浓度。
根据本发明的一个实施例，所述高阻抗夹层是通过对所述第一欧姆接触层进行正外延得到的。
根据本发明的一个实施例，所述第一欧姆接触层是通过对N型半导体基片进行掺杂得到的。
根据本发明的一个实施例，所述高阻抗夹层是通过一次或多次化学气相沉积工艺形成的。
根据本发明的一个实施例，所述化学气相沉积工艺中所使用的反应气体包括：氮气、氨气或磷化氢。
根据本发明的一个实施例，所述有源层的构成材料包括非晶硅，所述源/漏极的构成材料包括导电金属。
根据本发明的一个实施例，所述第一材料层的厚度的取值范围包括[300μm，400μm]，所述高阻抗夹杂层的厚度的取值范围包括[100μm，200μm]。
本发明还提供了一种阵列基板，所述阵列基板包括多个阵列排布的薄膜晶体管，所述薄膜晶体管为如上任一项所述的薄膜晶体管。
本发明所提供的薄膜晶体管的欧姆接触层中形成有一高阻抗夹杂层，该高阻抗夹杂层 能够作为电流流通的阻挡层来有效降低源/漏极与有源层之间所存在的漏电流。而薄膜薄膜晶体管漏电流的减小能够有效改善使用该薄膜晶体管的液晶显示面板所存在的残像问题。
同时，由于该高阻抗夹杂层可以通过化学气相沉积的方式来形成，因此该薄膜晶体管的生产工艺并不会增加薄膜晶体管的工艺难度。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是现有的薄膜晶体管的结构示意图；
图2是根据本发明一个实施例提供的薄膜晶体管的结构示意图；
图3是根据本发明一个实施例提供的薄膜晶体管的结构示意图；
图4是根据本发明一个实施例提供的薄膜晶体管的结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
图1示出了现有的薄膜晶体管的结构示意图。
如图1所示，现有的薄膜晶体管包括：玻璃基板101、栅极102、栅极绝缘层103、有源层104、欧姆接触层105以及源/漏极106。其中，栅极102形成在玻璃基板101上，其构成材料为导电金属，栅极102可以用来导通或关闭有源层103中的电子通道。
栅极绝缘层103覆盖在玻璃基板101和栅极102上，有源层104形成在栅极绝缘层103上。有源层104能够提供电子传输的通道，而栅极绝缘层103则能够有效避免栅极102与有源层104之间的电接触。
欧姆接触层105形成在有源层104上，源/漏极106形成在欧姆接触层105上。欧姆接触层105能够有效降低源/漏极105与有源层103之间的阻抗。
当薄膜晶体管的栅极102被施加一工作电压时，有源层104中便会形成一电子通道。此时，如果源极也被施加一电压，此时电子便会从薄膜晶体管的漏极通过有源层104中的电子通道流向源极，从而在薄膜晶体管的源极与漏极之间形成导通电流，此时薄膜晶体管的源极和漏极之间的电连接也就导通。而当薄膜晶体管的栅极102未被施加电压时，有源层104中的电子通道也随即消失，从而使得薄膜晶体管的源极与漏极之间形成断路。
上述内容描述的为理想状态下薄膜晶体管的工作状态，然而对于实际的薄膜晶体管来说，当其栅极未被施加电压时，其源极与漏极之间的电连接却并未是完全断开的，此时仍会有少量的电子可以通过有源层在薄膜晶体管的栅极与源极之间传输，而这也就导致现有的薄膜晶体管存在漏电流的问题。
为了改善现有薄膜薄膜晶体管所存在的漏电流问题，本实施例提供了一种新的薄膜晶体管，其结构示意图如图2所示。
如图2所示，本实施例所提供的薄膜晶体管包括：玻璃基板201、栅极202、栅极绝缘层203、有源层204、第一材料层205以及源/漏极206。为了更加清楚地阐述本实施例所提供的薄膜晶体管相较于现有的薄膜晶体管的不同之处，以下以图3所示的薄膜晶体管中区域A的局部放大图为例来进行进一步地说明。
如图3所示，在本实施例所提供的薄膜晶体管中，栅极202形成在基板201上，其中，基板201优选地采用玻璃实现。当然，在本发明的其他实施例中，基板201还可以采用其他合理的形式来实现，本发明不限于此。例如在本发明的一个实施例中，基板201还可以采用透光树脂来实现。
栅极202形成在基板201上，栅极绝缘层203形成在栅极202与有源层204之间。栅极绝缘层203用于实现栅极202与有源层204之间的电隔离。本实施例中，形成栅极绝缘层203的材料优选地采用SiNx/SiOx，而形成有源层204的材料优选地采用非晶硅。当然，在本发明的其他实施例中，栅极绝缘层203和/或有源层204还可以采用其他合理材料来实现，本发明同样不限于此。
第一材料层205形成在有源层204与源/漏极206之间，具体地包括：第一欧姆接触层205a、高阻抗夹杂层205b以及第二欧姆接触层205c。其中，高阻抗夹杂层205b形成在第一欧姆接触层205a与第二欧姆接触层205c之间，其阻抗大于第一欧姆接触层205a和第二欧姆接触层205c的阻抗。由于高阻抗夹杂层205b具有较高的阻抗，因此其能够有效减小有源层204与源/漏极206之间的漏电流。
需要指出的是，在本发明的不同实施例中，根据实际需要，第一欧姆接触层205a和第二欧姆接触层205c的构成材料既可以相同也可以不同，同时，其阻抗既可以相同也可 以不同，本发明不限于此。
由此可以看出，第一材料层205的一部分功能是作为金属(即源/漏极206)与半导体(即有源层204)之间的欧姆接触层。同时，第一材料层205还有一部分功能是作为阻挡层来对源/漏极206与有源层204之间的电子流通起到一定的阻碍作用，特别是在薄膜晶体管的栅极202未被施加电压时，对源极与漏极之间流通的少量电子起到阻碍作用，从而改善薄膜晶体管的漏电流问题。
理想的欧姆接触的接触电阻与半导体器件相比应当很小，当有电流通过时，欧姆接触上的电压降应当远小于半导体器件本身的电压降，因而这种接触不会影响器件的电流-电压特性。
因此，为了不在源/漏极206与有源层204之间产生明显的附加阻抗，在本实施例所提供的薄膜晶体管中，高阻抗夹杂层205b与第一欧姆接触层205a的阻抗之比的取值优选的为1.1，即高阻抗夹杂层205b的阻抗比第一欧姆接触层205a的阻抗高10％。
通过实验发现，虽然高阻抗夹杂层205b的阻抗仅比第一欧姆接触层205a的阻抗高了10％，但是相较于现有的薄膜晶体管，本实施例所提供的薄膜晶体管的漏电流降低了约一个数量级以上。由此可见，本实施例所提供的薄膜晶体管能够有效改善现有的薄膜晶体管所存在的漏电流问题。
需要指出的是，在本发明的其他实施例中，高阻抗夹杂层205b与第一欧姆接触层205a的阻抗之比还可以为其他合理值，本发明不限于此。例如，在本发明的一个实施例中，高阻抗夹杂层205b与第一欧姆接触层205a的阻抗之比还可以为[1.05，1.45]中的其他合理值(例如1.07、1.12或1.25等)。
本实施例中，高阻抗夹杂层205b是通过化学气相沉积(Chemical Vapor Deposition，简称CVD)形成的。由于电子比空穴的迁移率大，因此为了获取良好的频率特性，本实施例中，优选地选用N型半导体材料作为基片。其中，第一欧姆接触层205a为高掺杂层，其掺杂有第一浓度的施主杂质。而高阻抗夹杂层为低掺杂层，其掺杂有第二浓度的施主杂质。其中，第一浓度要大于第二浓度，以使得高阻抗夹杂层205b的阻抗大于第一欧姆接触层205a的阻抗。
本实施例中，第一欧姆接触层205a是利用化学气相沉积工艺向N型半导体基片中掺杂高浓度的施主杂质形成的。在进行化学气相沉积的过程中，所使用的反应气体优选地包括氮气、氨气或磷化氢。
为了减小肖特基二极管(Schottky Barrier Diode，简称SBD)的结电容，提高反向击穿电压，同时不使第一欧姆接触层205a与高阻抗夹杂层205b的串联电阻过大，本实施例 中，通过在N+衬底(即第一欧姆接触层205a)上正外延一高阻抗N-薄层的方式来形成高阻抗夹杂层205b。其中，优选地，在通过正外延形成高阻抗夹杂层205b的过程中所使用的反应气体与形成第一欧姆接触层205a的过程中所使用的反应气体相同。
需要指出的是，在本发明的其他实施例中，在利用化学气相沉积工艺形成第一欧姆接触层205a、高阻抗夹杂层205b和/或第二欧姆接触层205c的过程中所使用的反应气体还可以为其他合理气体，本发明不限于此。
在本发明的不同实施例中，薄膜晶体管中第一材料层的厚度的取值范围优选地包括[300μm，400μm]，而高阻抗夹杂层的厚度的取值范围优选地包括[100μm，200μm]。
需要说明的是，在本发明的其他实施例中，高阻抗夹杂层205b还可以通过多次化学气相沉积工艺形成，以使得高阻抗夹杂层205b包含多个子材料层。例如在本发明的一个实施例中，如图4所示，相较于图3所示的薄膜晶体管，该实施例所提供的薄膜晶体管的高阻抗夹杂层包含了3个子材料层(即第一子材料层205b_1、第二子材料层205b_2以及第三子材料层205b_3)。其中，根据实际需要，这3个子材料层的阻抗既可以相等，也可以不全相等(例如第二子材料层205b_2的阻抗大于第一子材料层205b_1和第三子材料层205b_3的阻抗)。
本发明还提供了一种阵列基板，其中，阵列排布在该阵列基板中的薄膜晶体管采用了如上所述的薄膜晶体管。
从上述描述中可以看出，本发明所提供的薄膜晶体管的欧姆接触层中形成有一高阻抗夹杂层，该高阻抗夹杂层能够作为电流流通的阻挡层从而有效降低源/漏极与有源层之间所存在的漏电流。而薄膜薄膜晶体管漏电流的减小能够有效改善使用该薄膜晶体管的液晶显示面板所存在的残像问题。
同时，由于该高阻抗夹杂层可以通过化学气相沉积的方式来形成，因此该薄膜晶体管的生产工艺并不会增加薄膜晶体管的工艺难度。
此外，在本发明所提供的薄膜晶体管中的高阻抗夹杂层还可以有多个子材料层构成，而这些子材料层中膜层之间的不连续界面也对电子的移动造成障碍，从而使得薄膜晶体管在关闭状态时的漏电流进一步下降，进而能够更好地改善薄膜晶体管的漏电流现象。因此，当薄膜晶体管在关闭状态时，源极与漏极之间的漏电流极为微小，储存于像素电极的电荷不至于快速泄露，故可改善信号流失的问题。
应该理解的是，本发明所公开的实施例不限于这里所公开的特定结构，而应当延伸到相关领域的普通技术人员所理解的这些特征的等同替代。还应当理解的是，在此使用的术语仅用于描述特定实施例的目的，而并不意味着限制。
虽然上述示例用于说明本发明在一个或多个应用中的原理，但对于本领域的技术人员来说，在不背离本发明的原理和思想的情况下，明显可以在形式上、用法及实施的细节上作各种修改而不用付出创造性劳动。因此，本发明由所附的权利要求书来限定。

Claims (20)

  1. 一种薄膜晶体管，其中，包括：
    栅极；
    栅极绝缘层，其形成在所述栅极上并覆盖所述栅极；
    有源层，其形成在所述栅极绝缘层上；
    第一材料层，其形成在所述有源层上；
    源/漏极，其形成在所述第一材料层上；
    其中，所述第一材料层包括：第一欧姆接触层、第二欧姆接触层以及高阻抗夹杂层，所述高阻抗夹杂层形成在所述第一欧姆接触层与第二欧姆接触层之间，其阻抗大于所述第一欧姆接触层和第二欧姆接触层的阻抗。
  2. 如权利要求1所述的薄膜晶体管，其中，所述高阻抗夹杂层与第一欧姆接触层的阻抗之比的取值范围包括[1.05，1.45]。
  3. 如权利要求1所述的薄膜晶体管，其中，所述第一欧姆接触层与所述有源层接触，其包含有第一浓度的施主杂质，所述高阻抗夹层含有第二浓度的施主杂质，其中，所述第一浓度大于第二浓度。
  4. 如权利要求3所述的薄膜晶体管，其中，所述高阻抗夹层是通过对所述第一欧姆接触层进行正外延得到的。
  5. 如权利要求3所述的薄膜晶体管，其中，所述第一欧姆接触层是通过对N型半导体基片进行掺杂得到的。
  6. 如权利要求1所述的薄膜晶体管，其中，所述高阻抗夹层是通过一次或多次化学气相沉积工艺形成的。
  7. 如权利要求2所述的薄膜晶体管，其中，所述高阻抗夹层是通过一次或多次化学气相沉积工艺形成的。
  8. 如权利要求6所述的薄膜晶体管，其中，所述化学气相沉积工艺中所使用的反应气体包括：氮气、氨气或磷化氢。
  9. 如权利要求1所述的薄膜晶体管，其中，所述有源层的构成材料包括非晶硅，所述源/漏极的构成材料包括导电金属。
  10. 如权利要求1所述的薄膜晶体管，其中，所述第一材料层的厚度的取值范围包括[300μm，400μm]，所述高阻抗夹杂层的厚度的取值范围包括[100μm，200μm]。
  11. 一种阵列基板，其中，所述阵列基板包括多个阵列排布的薄膜晶体管，所述薄膜晶体管包括：
    栅极；
    栅极绝缘层，其形成在所述栅极上并覆盖所述栅极；
    有源层，其形成在所述栅极绝缘层上；
    第一材料层，其形成在所述有源层上；
    源/漏极，其形成在所述第一材料层上；
    其中，所述第一材料层包括：第一欧姆接触层、第二欧姆接触层以及高阻抗夹杂层，所述高阻抗夹杂层形成在所述第一欧姆接触层与第二欧姆接触层之间，其阻抗大于所述第一欧姆接触层和第二欧姆接触层的阻抗。
  12. 如权利要求11所述的阵列基板，其中，所述高阻抗夹杂层与第一欧姆接触层的阻抗之比的取值范围包括[1.05，1.45]。
  13. 如权利要求11所述的阵列基板，其中，所述第一欧姆接触层与所述有源层接触，其包含有第一浓度的施主杂质，所述高阻抗夹层含有第二浓度的施主杂质，其中，所述第一浓度大于第二浓度。
  14. 如权利要求13所述的阵列基板，其中，所述高阻抗夹层是通过对所述第一欧姆接触层进行正外延得到的。
  15. 如权利要求13所述的阵列基板，其中，所述第一欧姆接触层是通过对N型半导体基片进行掺杂得到的。
  16. 如权利要求11所述的阵列基板，其中，所述高阻抗夹层是通过一次或多次化学气相沉积工艺形成的。
  17. 如权利要求12所述的阵列基板，其中，所述高阻抗夹层是通过一次或多次化学气相沉积工艺形成的。
  18. 如权利要求16所述的阵列基板，其中，所述化学气相沉积工艺中所使用的反应气体包括：氮气、氨气或磷化氢。
  19. 如权利要求11所述的阵列基板，其中，所述有源层的构成材料包括非晶硅，所述源/漏极的构成材料包括导电金属。
  20. 如权利要求11所述的阵列基板，其中，所述第一材料层的厚度的取值范围包括[300μm，400μm]，所述高阻抗夹杂层的厚度的取值范围包括[100μm，200μm]。
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