US20190140107A1 - Liquid crystal display panel - Google Patents

Liquid crystal display panel Download PDF

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US20190140107A1
US20190140107A1 US16/238,496 US201916238496A US2019140107A1 US 20190140107 A1 US20190140107 A1 US 20190140107A1 US 201916238496 A US201916238496 A US 201916238496A US 2019140107 A1 US2019140107 A1 US 2019140107A1
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layer
film layer
film
speed
active layer
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US16/238,496
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Xiaowen Lv
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H01L29/78696—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H01L29/34—
    • H01L29/66742—
    • H01L29/66765—
    • H01L29/78609—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/57—Physical imperfections the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Definitions

  • the present disclosure relates to the technical field of liquid crystal display, and in particular, to a liquid crystal display panel.
  • An active layer usually adopts an AL/AH structure.
  • AL is a main electrically-conductive channel, and is formed at a low speed, so as to ensure good thin-film quality and few interfacial defects.
  • AH formed at a high speed, has many interfacial defects, and many interfacial states in a backchannel.
  • a gate voltage Vg is a small negative voltage
  • a transistor while a transistor is in an electrically-conductive negative sub-threshold region, a small electrically-conductive channel will be formed in the backchannel, which will lead to a backchannel electric leakage.
  • a turn-off voltage of a TFT-LCD device is generally provided around the negative sub-threshold region.
  • AH is easily affected by following procedures, resulting in a high and dispersed leakage current in the backchannel and leading to problems like uneven luminance display, reliability problems, etc.
  • Performance of the sub-threshold region I-V of the device is mainly affected by the backchannel of a device and interfacial characteristics of the backchannel and a passivation layer PV.
  • the present disclosure provides a liquid crystal display panel.
  • a liquid crystal display panel comprises a thin-film transistor.
  • An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers.
  • the active layer is in contact with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.
  • the present disclosure achieves the following beneficial effects.
  • An active layer AS in the related art comprises two layers, a high-speed deposited film layer AH and a low-speed deposited film layer AL.
  • the present disclosure changes the existing two-layer structure into an AL 1 /AL 2 /AH (three-layer) structure and ensures that a sum of thicknesses of the layer AL 1 and the layer AL 2 is greater than a thickness of the electrically-conductive layer AS, so as to ensure that the active layer which connects a backchannel and a passivation layer PV is the layer AL 2 .
  • the layer AL 2 is formed at a speed higher than a speed of forming the layer AL 1 but lower than a speed of forming the layer AH, and therefore has a better film quality and interface-state density than the layer AH. In this way, a liquid crystal display panel in the present disclosure has better backchannel characteristics and a low electric leakage.
  • FIG. 1 schematically shows display of a sub-threshold region I-V in a liquid crystal display device in the related art.
  • FIG. 2 schematically shows a section of a backchannel in a liquid crystal display panel in the related art.
  • FIG. 3 schematically shows a section of a backchannel in a liquid crystal display panel in one embodiment of the present disclosure.
  • FIG. 4 schematically shows display of leakage currents at different locations in a backchannel of a liquid crystal display panel in the related art.
  • FIG. 5 schematically shows display of leakage currents at different locations in a backchannel of a liquid crystal display panel in the present disclosure.
  • an active layer AS in communication with a source and a drain of a thin-film transistor is a two-layer structure comprising a high-speed deposited film layer AH and a low-speed deposited film layer AL.
  • a gate M 1 is formed on a substrate.
  • a gate insulation layer GI is formed on the gate M 1 .
  • An active layer AS is formed on the gate insulation layer GI.
  • the active layer AS comprises a low-speed deposited film layer AL formed on the gate insolation layer GI and a high-speed deposited film layer AH formed on the low-speed deposited film layer AL.
  • An ohmic contact layer N+ is formed on the high-speed deposited film layer AH.
  • a source S and a drain D of a thin-film transistor are formed on the ohmic contact layer N+.
  • a passivation layer PV is formed on the source S and the drain D of the thin-film transistor.
  • the passivation layer PV is in contact with the high-speed deposited film layer AH of the active layer AS. Due to its high film-forming speed, the layer AH has a worse film quality and interface-state density than the layer AL, resulting in poor homogeneity and many defects of the layer AH and high leakage currents in a backchannel.
  • Speeds of forming the high-speed deposited film layer AH and the low-speed deposited film layer AL are relative to each other. In other words, the speed of forming the high-speed deposited film layer AH is faster than the speed of forming the low-speed deposited film layer AL.
  • the high-speed deposited film layer AH is formed at the commonly-used high film-forming speed in the related art and the low-speed deposited film layer AL is formed at the commonly-used low film-forming speed in the related art.
  • the present disclosure provides a liquid crystal display panel which comprises a thin-film transistor.
  • An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers.
  • the active layer is in contact with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.
  • the layer that connects the passivation layer and the active layer has a better film quality and interface-state density than the layer AH.
  • the backchannel can therefore have better characteristics and a low leakage current.
  • FIG. 3 schematically shows a section of a backchannel in a liquid crystal display panel in one embodiment of the present disclosure.
  • An active layer in FIG. 3 comprises three film layers. The present disclosure will be explained below in detail with reference to FIG. 3 .
  • a gate M 1 is formed on a substrate.
  • a gate insulation layer GI is formed on the gate M 1 .
  • An active layer AS is formed on the gate insulation layer GI.
  • the active layer AS comprises a first low-speed deposited film layer AL 1 formed on the gate insulation layer GI, a second film layer AL 2 formed on the first low-speed deposited film layer AL 1 (i.e. a first film layer), and a high-speed deposited film layer AH (i.e.
  • a third film layer formed on the second film layer AL 2 (i.e. a second film layer).
  • An ohmic contact layer N+ is formed on the high-speed deposited film layer AH.
  • a source S and a drain D of a thin-film transistor are formed on the ohmic contact layer N+.
  • a passivation layer PV is formed on the source S and the drain D of the thin-film transistor.
  • the related art in FIG. 2 adopts a two-layer structure comprising a high-speed deposited film layer AH and a low-speed deposited film layer AL.
  • the present disclosure in FIG. 3 adopts a structure of three film layers.
  • the three film layers in addition to a high-speed deposited film layer AH and a low-speed deposited film layer AL (i.e. the first low-speed deposited film layer AL 1 ), further comprises a second film layer AL 2 formed between the high-speed deposited film layer AH and the first low-speed deposited film layer AL 1 .
  • the second film layer AL 2 is formed at a speed higher than a speed of forming the layer AL 1 but lower than a speed of forming the layer AH and a better film quality and interface-state density than the AH layer.
  • the backchannel can therefore have better characteristics and a low leakage current.
  • Films formed by CVD chemical vapor deposition
  • CVD chemical vapor deposition
  • the active layer is in contact with the passivation layer on the second film layer of the active layer.
  • the backchannel is arranged to contact with the passivation layer PV on the second film layer AL 2 .
  • the second film layer AL 2 has a better film quality and interface state density than the layer AH, and therefore has better backchannel characteristics. A leakage current in the backchannel can be reduced.
  • a sum of thicknesses of the first low-speed deposited film layer AL 1 (the first film layer) and the second film layer AL 2 accounts for 1 ⁇ 3 of a thickness of the entire active layer.
  • the active layer AS in the related art comprises two layers, a high-speed deposited film layer AH and a low-speed deposited film layer AL.
  • the present disclosure changes the existing two-layer structure into an AL 1 /AL 2 /AH (three-layer) structure and ensures that the sum of the thicknesses of the layer AL 1 and the layer AL 2 is greater than the thickness of the electrically-conductive layer in the active layer AS, so as to ensure that the active layer that connects the backchannel and the passivation layer PV is the layer AL 2 .
  • the layer AL 2 is formed at a speed higher than a speed of forming the layer AL 1 and lower than a speed of forming the layer AH and therefore has a better film quality and interface-state density than the layer AH.
  • the present disclosure thus has better backchannel characteristics and a low leakage current.
  • FIG. 4 schematically shows leakage currents at three different positions on the active layer in the two-layer structure of the related art. As shown in this figure, leakage currents Ioff at certain positions in the backchannel are high, dispersed and not uniform.
  • FIG. 5 schematically shows leakage currents at three different positions on the active layer in the present disclosure. As shown in this figure, electric uniformity of the backchannel is good and there are no positions with obviously high leakage currents Ioff. As seen from FIG. 5 , the present disclosure reduces leakage currents Ioff in the backchannel and improves uniformity of a device.
  • a method for manufacturing a liquid crystal display panel comprises the following steps.
  • a gate M 1 is formed on a substrate.
  • a gate insulation layer GI is formed on the gate M 1 .
  • An active layer AS is formed on the gate insulation layer GI.
  • the active layer AS comprises a first low-speed deposited film layer AL 1 formed on the gate insulation layer GI, a second film layer formed on the first low-speed deposited film layer AL 1 (i.e. a first film layer), and a high-speed deposited film layer AH (i.e. a third film layer) formed on the second film layer AL 2 (i.e. a second film layer).
  • An ohmic contact layer N+ is formed on the high-speed deposited film layer AH.
  • FIG. 3 shows a section of a backchannel formed in this liquid crystal display panel.
  • the active layer comprises three film layers.
  • the step of forming the active layer specifically comprises steps of: forming a first film layer on the gate insulation layer; forming a second film layer on the first film layer; and forming a third film layer on the second film layer.
  • the first film layer is a low-speed deposited film layer
  • the third film layer is a high-speed deposited film layer.
  • a speed of forming the second film layer is between a speed of forming the first film layer and a speed of forming the third film layer.
  • the active layer is in contact with the passivation layer on the second film layer of the active layer.
  • a sum of thicknesses of the first film layer and the second film layer accounts for 1 ⁇ 3 of a thickness of the entire active layer.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

Disclosed is a liquid crystal display panel. The panel includes a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer contacts with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This is a divisional application of U.S. patent application Ser. No. 15/329,323, which claims the priority of Chinese patent application CN 201610613722.3, entitled “Liquid crystal display panel and method for manufacturing the same” and filed on Jul. 29, 2016, the entireties of which are incorporated herein by reference.
    • TECHNICAL FIELD
  • The present disclosure relates to the technical field of liquid crystal display, and in particular, to a liquid crystal display panel.
    • BACKGROUND
  • In recent years, large-sized and high-resolution televisions are becoming more and more popular among merchants and customers. As size of a display device becomes larger and larger, on the premise of ensuring a starting current (Ion) and a threshold voltage (Vth), electric-capacity-holding effects of a display device is becoming more and more important. Since a liquid crystal display device is in an off-state during most of the time, a leakage current exerts a great influence on display performance of the device.
  • Generally, for a BCE (B stands for base, C for collector and E for emitter) transistor structure, after a channel is formed, there are many follow-up procedures like depositing metal. The follow-up procedures will influence characteristics of a backchannel. An active layer usually adopts an AL/AH structure. AL is a main electrically-conductive channel, and is formed at a low speed, so as to ensure good thin-film quality and few interfacial defects. AH, formed at a high speed, has many interfacial defects, and many interfacial states in a backchannel. While a gate voltage Vg is a small negative voltage, in other words, while a transistor is in an electrically-conductive negative sub-threshold region, a small electrically-conductive channel will be formed in the backchannel, which will lead to a backchannel electric leakage. In the meanwhile, a turn-off voltage of a TFT-LCD device is generally provided around the negative sub-threshold region. Besides, due to poor homogeneity and many defects of the deposition, AH is easily affected by following procedures, resulting in a high and dispersed leakage current in the backchannel and leading to problems like uneven luminance display, reliability problems, etc.
  • Thus, to improve performance of a display device, it is of great significance to improve homogeneity of a backchannel and interfacial characteristics of the active layer in the backchannel. Performance of the sub-threshold region I-V of the device, as shown in FIG. 1, is mainly affected by the backchannel of a device and interfacial characteristics of the backchannel and a passivation layer PV.
    • SUMMARY
  • In order to solve the above problem, the present disclosure provides a liquid crystal display panel.
  • According to one aspect of the present disclosure, a liquid crystal display panel is provided. The liquid crystal display panel comprises a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer is in contact with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.
  • The present disclosure achieves the following beneficial effects.
  • An active layer AS in the related art comprises two layers, a high-speed deposited film layer AH and a low-speed deposited film layer AL. The present disclosure changes the existing two-layer structure into an AL1/AL2/AH (three-layer) structure and ensures that a sum of thicknesses of the layer AL1 and the layer AL2 is greater than a thickness of the electrically-conductive layer AS, so as to ensure that the active layer which connects a backchannel and a passivation layer PV is the layer AL2. The layer AL2 is formed at a speed higher than a speed of forming the layer AL1 but lower than a speed of forming the layer AH, and therefore has a better film quality and interface-state density than the layer AH. In this way, a liquid crystal display panel in the present disclosure has better backchannel characteristics and a low electric leakage.
  • Other advantages, objectives, and features of the present disclosure will be further explained in the following description, and partially become self-evident therefrom, or be understood through the embodiments of the present disclosure. The objectives and advantages of the present disclosure will be achieved through the structure specifically pointed out in the description, claims, and the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings provide further understandings of the present disclosure or the related art, and constitute one part of the description. The drawings are used for interpreting the present disclosure together with the embodiments, not for limiting the present disclosure.
  • FIG. 1 schematically shows display of a sub-threshold region I-V in a liquid crystal display device in the related art.
  • FIG. 2 schematically shows a section of a backchannel in a liquid crystal display panel in the related art.
  • FIG. 3 schematically shows a section of a backchannel in a liquid crystal display panel in one embodiment of the present disclosure.
  • FIG. 4 schematically shows display of leakage currents at different locations in a backchannel of a liquid crystal display panel in the related art.
  • FIG. 5 schematically shows display of leakage currents at different locations in a backchannel of a liquid crystal display panel in the present disclosure.
    •  DETAILED DESCRIPTION
  • The present disclosure will be explained in details with reference to the embodiments and the accompanying drawings, whereby it can be fully understood how to solve the technical problem by the technical means according to the present disclosure and achieve the technical effects thereof, and thus the technical solution according to the present disclosure can be implemented. It should be noted that, as long as there is no conflict, all the technical features mentioned in all the embodiments may be combined together in any manner, and the technical solutions obtained in this manner all fall within the scope of the present disclosure.
  • In an existing liquid crystal display panel, an active layer AS in communication with a source and a drain of a thin-film transistor is a two-layer structure comprising a high-speed deposited film layer AH and a low-speed deposited film layer AL. As illustrated in FIG. 2, a gate M1 is formed on a substrate. A gate insulation layer GI is formed on the gate M1. An active layer AS is formed on the gate insulation layer GI. The active layer AS comprises a low-speed deposited film layer AL formed on the gate insolation layer GI and a high-speed deposited film layer AH formed on the low-speed deposited film layer AL. An ohmic contact layer N+ is formed on the high-speed deposited film layer AH. A source S and a drain D of a thin-film transistor are formed on the ohmic contact layer N+. A passivation layer PV is formed on the source S and the drain D of the thin-film transistor.
  • As shown in FIG. 2, the passivation layer PV is in contact with the high-speed deposited film layer AH of the active layer AS. Due to its high film-forming speed, the layer AH has a worse film quality and interface-state density than the layer AL, resulting in poor homogeneity and many defects of the layer AH and high leakage currents in a backchannel. Speeds of forming the high-speed deposited film layer AH and the low-speed deposited film layer AL are relative to each other. In other words, the speed of forming the high-speed deposited film layer AH is faster than the speed of forming the low-speed deposited film layer AL. In the present disclosure, the high-speed deposited film layer AH is formed at the commonly-used high film-forming speed in the related art and the low-speed deposited film layer AL is formed at the commonly-used low film-forming speed in the related art.
  • To solve the above problems, the present disclosure provides a liquid crystal display panel which comprises a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer is in contact with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer. By way of this, the layer that connects the passivation layer and the active layer has a better film quality and interface-state density than the layer AH. The backchannel can therefore have better characteristics and a low leakage current.
  • FIG. 3 schematically shows a section of a backchannel in a liquid crystal display panel in one embodiment of the present disclosure. An active layer in FIG. 3 comprises three film layers. The present disclosure will be explained below in detail with reference to FIG. 3. As shown in FIG. 3, in a liquid crystal display panel, a gate M1 is formed on a substrate. A gate insulation layer GI is formed on the gate M1. An active layer AS is formed on the gate insulation layer GI. The active layer AS comprises a first low-speed deposited film layer AL1 formed on the gate insulation layer GI, a second film layer AL2 formed on the first low-speed deposited film layer AL1 (i.e. a first film layer), and a high-speed deposited film layer AH (i.e. a third film layer) formed on the second film layer AL2 (i.e. a second film layer). An ohmic contact layer N+ is formed on the high-speed deposited film layer AH. A source S and a drain D of a thin-film transistor are formed on the ohmic contact layer N+. A passivation layer PV is formed on the source S and the drain D of the thin-film transistor.
  • It can be seen from a comparison between FIG. 2 and FIG. 3 that the active layers in the two structures have different structures. The related art in FIG. 2 adopts a two-layer structure comprising a high-speed deposited film layer AH and a low-speed deposited film layer AL. The present disclosure in FIG. 3 adopts a structure of three film layers. The three film layers, in addition to a high-speed deposited film layer AH and a low-speed deposited film layer AL (i.e. the first low-speed deposited film layer AL1), further comprises a second film layer AL2 formed between the high-speed deposited film layer AH and the first low-speed deposited film layer AL1.
  • The second film layer AL2 is formed at a speed higher than a speed of forming the layer AL1 but lower than a speed of forming the layer AH and a better film quality and interface-state density than the AH layer. The backchannel can therefore have better characteristics and a low leakage current. Films formed by CVD (chemical vapor deposition) can be homogenous.
  • In one embodiment of the present disclosure, the active layer is in contact with the passivation layer on the second film layer of the active layer. As shown in FIG. 3, the backchannel is arranged to contact with the passivation layer PV on the second film layer AL2. The second film layer AL2 has a better film quality and interface state density than the layer AH, and therefore has better backchannel characteristics. A leakage current in the backchannel can be reduced.
  • To ensure thickness of an electrically-conductive layer of the backchannel and control time of this manufacturing procedure, in one embodiment of the present disclosure, a sum of thicknesses of the first low-speed deposited film layer AL1 (the first film layer) and the second film layer AL2 accounts for ⅓ of a thickness of the entire active layer.
  • The active layer AS in the related art comprises two layers, a high-speed deposited film layer AH and a low-speed deposited film layer AL. The present disclosure changes the existing two-layer structure into an AL1/AL2/AH (three-layer) structure and ensures that the sum of the thicknesses of the layer AL1 and the layer AL2 is greater than the thickness of the electrically-conductive layer in the active layer AS, so as to ensure that the active layer that connects the backchannel and the passivation layer PV is the layer AL2. This is because the layer AL2 is formed at a speed higher than a speed of forming the layer AL1 and lower than a speed of forming the layer AH and therefore has a better film quality and interface-state density than the layer AH. The present disclosure thus has better backchannel characteristics and a low leakage current.
  • FIG. 4 schematically shows leakage currents at three different positions on the active layer in the two-layer structure of the related art. As shown in this figure, leakage currents Ioff at certain positions in the backchannel are high, dispersed and not uniform.
  • FIG. 5 schematically shows leakage currents at three different positions on the active layer in the present disclosure. As shown in this figure, electric uniformity of the backchannel is good and there are no positions with obviously high leakage currents Ioff. As seen from FIG. 5, the present disclosure reduces leakage currents Ioff in the backchannel and improves uniformity of a device.
  • According to another aspect of the present disclosure, a method for manufacturing a liquid crystal display panel is provided. The method comprises the following steps. A gate M1 is formed on a substrate. A gate insulation layer GI is formed on the gate M1. An active layer AS is formed on the gate insulation layer GI. The active layer AS comprises a first low-speed deposited film layer AL1 formed on the gate insulation layer GI, a second film layer formed on the first low-speed deposited film layer AL1 (i.e. a first film layer), and a high-speed deposited film layer AH (i.e. a third film layer) formed on the second film layer AL2 (i.e. a second film layer). An ohmic contact layer N+ is formed on the high-speed deposited film layer AH. A source S and a drain D of a thin-film transistor are formed on the ohmic contact layer N+. A passivation layer PV is formed on the source S and the drain D of the thin-film transistor. The active layer is in contact with the passivation layer on a non-high-speed deposited film layer of the active layer. FIG. 3 shows a section of a backchannel formed in this liquid crystal display panel.
  • In one embodiment of the present disclosure, the active layer comprises three film layers. The step of forming the active layer specifically comprises steps of: forming a first film layer on the gate insulation layer; forming a second film layer on the first film layer; and forming a third film layer on the second film layer. The first film layer is a low-speed deposited film layer, and the third film layer is a high-speed deposited film layer. A speed of forming the second film layer is between a speed of forming the first film layer and a speed of forming the third film layer. This is realized in practice by changing a two-step deposition process into a three-step deposition process during depositing of the active layer AS by CVD and resetting etching conditions and time during etching. The manufacturing process is easy to realize.
  • In one embodiment of the present disclosure, the active layer is in contact with the passivation layer on the second film layer of the active layer.
  • In one embodiment of the present disclosure, a sum of thicknesses of the first film layer and the second film layer accounts for ⅓ of a thickness of the entire active layer.
  • The above embodiments are described only for better understanding, rather than restricting, the present disclosure. Any person skilled in the art can make amendments to the implementing forms or details without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure shall be determined by the scope as defined in the claims.

Claims (10)

What is claimed is:
1. A liquid crystal display panel, comprising a thin-film transistor, wherein:
an active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers; and
the active layer is in contact with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.
2. The panel according to claim 1, wherein the active layer comprises three film layers.
3. The panel according to claim 1, wherein a second film layer is formed between a first film layer and a third film layer, wherein:
the first film layer is a low-speed deposited film layer, and the third film layer is a high-speed deposited film layer, and
a speed of forming the second film layer is between a speed of forming the first film layer and a speed of forming the third film layer.
4. The panel according to claim 3, wherein the active layer is in contact with the passivation layer on the second film layer of the active layer.
5. The panel according to claim 3, wherein a sum of thicknesses of the first film layer and the second film layer accounts for ⅓ of a thickness of the entire active layer.
6. The panel according to claim 4, wherein a sum of thicknesses of the first film layer and the second film layer accounts for ⅓ of a thickness of the entire active layer.
7. The panel according to claim 1, further comprising a substrate, a gate formed on the substrate, and a gate insulation layer formed on the gate; wherein the active layer is formed on the gate insulation layer.
8. The panel according to claim 3, wherein an ohmic contact layer is formed on the high-speed deposited film layer.
9. The panel according to claim 8, wherein the source and the chain of the thin-film transistor are formed on the ohmic contact layer.
10. The panel according to claim 9, wherein the passivation layer is formed on the source and the drain of the thin-film transistor.
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