WO2017090413A1 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
WO2017090413A1
WO2017090413A1 PCT/JP2016/082944 JP2016082944W WO2017090413A1 WO 2017090413 A1 WO2017090413 A1 WO 2017090413A1 JP 2016082944 W JP2016082944 W JP 2016082944W WO 2017090413 A1 WO2017090413 A1 WO 2017090413A1
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WO
WIPO (PCT)
Prior art keywords
power semiconductor
semiconductor device
semiconductor element
printed circuit
circuit board
Prior art date
Application number
PCT/JP2016/082944
Other languages
French (fr)
Japanese (ja)
Inventor
伸洋 浅地
進吾 須藤
藤野　純司
吉田　博
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2017552341A priority Critical patent/JP6523482B2/en
Priority to DE112016005397.5T priority patent/DE112016005397B4/en
Priority to CN201680067437.4A priority patent/CN108292642B/en
Publication of WO2017090413A1 publication Critical patent/WO2017090413A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates to a power semiconductor device, and more particularly to a power semiconductor device including an insulating substrate on which a power semiconductor element is mounted and a printed circuit board on which a main circuit of the power semiconductor element is formed.
  • Power semiconductor devices are used to control the main power of devices in a wide range of fields such as industrial equipment, electric railways, and home appliances.
  • power semiconductor devices mounted on industrial equipment are downsized. High heat dissipation and high reliability are required.
  • power semiconductor elements such as IGBTs and FwDi are often mounted on an insulating substrate with high heat dissipation, and the circuit is configured by wiring the surface electrodes of the power semiconductor elements with, for example, aluminum wires. .
  • wiring is performed on the insulating substrate, there is a problem that the area of the expensive insulating substrate is increased, resulting in an increase in cost and an increase in the outer shape of the power semiconductor device.
  • Patent Document 1 an insulating substrate on which a semiconductor element is mounted and a printed circuit board that is wired on both sides are electrically connected with a conductive adhesive such as solder, A structure housed in the box has been proposed.
  • a power semiconductor device that switches a large current at high speed generates a large amount of heat, and a thermal expansion difference between an insulating substrate and a printed circuit board increases. Therefore, a large thermal stress is generated in the solder and the power semiconductor element existing between the insulating substrate and the printed circuit board due to the temperature cycle.
  • the thickness of the copper conductor layer in the printed circuit board needs to be 0.1 mm or more. Therefore, in particular, the thermal stress generated at the solder joint between the printed circuit board and the power semiconductor element becomes a problem. Therefore, in order to ensure the long-term reliability of the power semiconductor device, it is necessary to reduce defects due to this thermal stress.
  • Patent Document 1 discloses a structure of a power semiconductor device using an insulating substrate and a printed circuit board, but does not particularly describe reduction of thermal stress.
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide a power semiconductor device capable of ensuring long-term reliability of the power semiconductor device.
  • a power semiconductor device includes a power semiconductor element and a printed board having a conductor layer, and the electrode of the power semiconductor element and the conductor layer of the printed board are joined by solder.
  • the power semiconductor element has a metal film for bonding solder and a film not bonded to solder on the surface electrode, and the metal film is formed on the power semiconductor element.
  • a plurality of films, which are not bonded to the solder, are disposed in the center of the power semiconductor element, and constitute a part of the conductor layer and a joint part formed integrally with the conductor layer.
  • the joining portion has a notch, and the notch is disposed so as to correspond to the metal film of the semiconductor element.
  • the bonding portion is provided, and the bonding portion has a notch so that the bonding area between the electrode of the power semiconductor element and the conductor layer of the printed board is equal to the bonding portion. It becomes smaller than the bonding area in the case of not having.
  • the thermal stress acting on the solder existing between the electrode of the power semiconductor element and the conductor layer of the printed circuit board becomes smaller than in the past. . Therefore, the occurrence of defects such as breakage in the solder can be reduced and prevented, and the long-term reliability of the power semiconductor device can be ensured.
  • FIG. 1 is a conceptual diagram showing a state where a power semiconductor element is mounted on an insulating substrate in the power semiconductor device according to the first embodiment.
  • FIG. 2 is a conceptual diagram of the power semiconductor device shown in FIG. 1. In the power semiconductor device shown in FIG. 1, it is a conceptual diagram which shows the surface of the printed circuit board joined with a power semiconductor element with solder.
  • FIG. 3 is a conceptual diagram of the power semiconductor device in the AA cross section shown in FIG. 2.
  • FIG. 5 is an enlarged conceptual diagram illustrating a solder state in which a joint portion and a power semiconductor element included in the power semiconductor device illustrated in FIG. 4 are joined. It is a conceptual diagram which shows that the metal film of the power semiconductor element with which the power semiconductor device shown in FIG. 1 is provided is circular.
  • FIG. 1 is a conceptual diagram showing a state where a power semiconductor element is mounted on an insulating substrate in the power semiconductor device according to the first embodiment.
  • FIG. 2 is a conceptual diagram of the power semiconductor device shown in FIG.
  • FIG. 5 is a conceptual diagram illustrating a modification example of a junction between a junction and a power semiconductor element included in the power semiconductor device illustrated in FIG. 4.
  • FIG. 6 is a conceptual diagram illustrating a modified example of a junction between a junction and a power semiconductor element included in the power semiconductor device illustrated in FIG. 5.
  • FIG. 6 is a conceptual diagram of a power semiconductor device in a second embodiment.
  • FIG. 10 is a conceptual diagram illustrating a surface of a printed circuit board that is joined to a power semiconductor element by solder in the power semiconductor device illustrated in FIG. 9.
  • FIG. 10 is a conceptual diagram of the power semiconductor device in the BB cross section shown in FIG. 9. It is a conceptual diagram which shows the state of the junction of the junction part with which the power semiconductor device shown in FIG.
  • FIG. 11 is equipped, and a power semiconductor element.
  • FIG. 12 is a conceptual diagram illustrating a modified example of a junction between a junction and a power semiconductor element included in the power semiconductor device illustrated in FIG. 11.
  • FIG. 11 is a conceptual diagram of a power semiconductor device according to a third embodiment, corresponding to the power semiconductor device according to the first embodiment.
  • FIG. 15 is a cross-sectional view taken along the line CC shown in FIG. 14 and is a conceptual diagram of the power semiconductor device corresponding to the first embodiment.
  • FIG. 16 is a conceptual diagram illustrating a bonding state of the power semiconductor device illustrated in FIG. 15 and a bonding state between a slit and a power semiconductor element.
  • FIG. 12 is a conceptual diagram illustrating a modified example of a junction between a junction and a power semiconductor element included in the power semiconductor device illustrated in FIG. 11.
  • FIG. 11 is a conceptual diagram of a power semiconductor device according to a third embodiment, corresponding to the power semiconductor device according to the first embodiment
  • FIG. 10 is a conceptual diagram of a power semiconductor device according to a third embodiment, corresponding to the power semiconductor device according to the second embodiment.
  • FIG. 18 is a cross-sectional view taken along the line DD shown in FIG. 17, and is a conceptual diagram of the power semiconductor device corresponding to the first embodiment. It is a conceptual diagram which shows the state of the junction of the junction part and slit with which the power semiconductor device shown in FIG. 18 is equipped, and a power semiconductor element.
  • FIG. 10 is a conceptual diagram showing a state where a junction is not cut in the power semiconductor device according to the third embodiment.
  • FIG. 10 is a conceptual diagram of a power semiconductor device according to a fourth embodiment, corresponding to the first embodiment.
  • FIG. 22 is a diagram showing an EE cross section shown in FIG. 21, and a conceptual diagram of the power semiconductor device corresponding to the first embodiment.
  • FIG. 1, 2, 4, and 6 are conceptual diagrams showing a schematic structure of the power semiconductor device 100 according to the first embodiment.
  • FIG. 3 shows the proximal copper conductor layer 53 side of the printed circuit board 50. It is a conceptual diagram.
  • the power semiconductor device 100 includes power semiconductor elements 2 and 3 and a printed circuit board 50 as basic components.
  • the power semiconductor device 100 of the first embodiment can include the insulating substrate 1, the case 7, the sealing resin 6, the electrode terminal 8, and the like.
  • an IGBT 2 Insulated Gate Bipolar Transistor
  • a diode for example, FwDi
  • the insulating substrate 1 is, for example, a resin insulating sheet 1a having a thickness of 0.125 mm and a copper conductor layer 1b having a thickness of, for example, 2 mm and bonded to both surfaces facing each other in the thickness direction of the resin insulating sheet 1a. 5 mm copper conductor layer 1c.
  • the IGBT 2 and the diode 3, more specifically, the electrodes on the back side of the IGBT 2 and the diode 3 are electrically and mechanically connected to the copper conductor layer 1 c of the insulating substrate 1 by the solder 41.
  • the IGBT 2 has a size of 8 mm ⁇ 8 mm and a thickness of 0.08 mm, for example, and the diode 3 has a size of 8 mm ⁇ 6 mm and a thickness of 0.08 mm, for example.
  • an Al film to which solder is not bonded, and metal films 2a and 3a such as Au are formed so that solder bonding is possible.
  • the film to which the solder is not bonded is located at the center of the surface of the IGBT 2 and the diode 3.
  • As the solder 41 Sn—Ag—Cu based solder having a thickness of about 0.1 mm is used.
  • Such an insulating substrate 1 serves as both heat radiation of the IGBT 2 and the diode 3 and wiring in each electrode on the back surface side of both the semiconductor elements 2 and 3.
  • the printed circuit board 50 is disposed in parallel or substantially in parallel to the power semiconductor element such as IGBT 2 mounted on the insulating substrate 1.
  • the printed circuit board 50 is, for example, a core material 51 having a thickness of 0.5 mm and a material of FR-4 (Flame Retardant Type 4), and distant from the power semiconductor element on both sides in the thickness direction of the core material 51 And a proximal copper conductor layer 53 formed in the vicinity.
  • the distal copper conductor layer 52 and the proximal copper conductor layer 53 each have a thickness of, for example, 0.1 mm, and are bonded to the core material 51 by an adhesive sheet (not shown) to form a circuit pattern. Further, the distal copper conductor layer 52 and the proximal copper conductor layer 53 are electrically connected through a through hole 56.
  • the printed circuit board 50 facing each other and the semiconductor elements of the IGBT 2 and the diode 3 have an interval of 0.3 mm or more in order to ensure electrical insulation when an epoxy resin is used as the sealing resin 6. It is necessary to open.
  • the proximal copper conductor layer 53 of the printed circuit board 50 has a joint 54 which is one of the characteristic configurations in the present embodiment.
  • the joint portion 54 is a portion that electrically and mechanically joins each surface electrode of the IGBT 2 and the diode 3 and the proximal copper conductor layer 53 with the solder 42. That is, the proximal-side copper conductor layer 53 of the printed circuit board 50 is connected to the surface electrodes of the IGBT 2 and the diode 3 through the joint portion 54.
  • the junction 54 will be described in more detail below.
  • the solder 42 is, for example, a Sn—Ag—Cu solder having a thickness of 0.2 mm to 0.8 mm.
  • a case 7 made mainly of PPS (polyphenylene sulfide) is bonded to the outer edge portion of the insulating substrate 1 with a silicone adhesive (not shown), as shown in FIG. ing.
  • An electrode terminal 8 is inserted into the case 7, and an emitter electrode and a gate electrode (corresponding to a surface electrode) of a semiconductor element such as the IGBT 2 and the diode 3 are inserted into the electrode terminal 8, and the proximal side copper of the printed board 50.
  • the conductor layer 53 is electrically connected through the distal copper conductor layer 52 with a bonding wire 9 made of aluminum, for example, ⁇ 0.3 mm.
  • an epoxy resin sealing resin 6 is poured into the case 7 from the gap between the insulating substrate 1 and the printed circuit board 50 until the upper surface of the printed circuit board 50 is covered, vacuum degassed and heated to be cured. The Thereby, the IGBT 2, the diode 3, the printed board 50, and the like installed on the insulating substrate 1 are sealed with the sealing resin 6.
  • FIG. 5 shows a plan view of the joining portion 54 and shows a joining state of the joining portion 54 and the metal film 2a formed on, for example, the electrode of the IGBT 2 by the solder 42.
  • the metal films 2a are equally arranged on the plurality of electrodes in the IGBT 2, and the areas of the metal films 2a are the same.
  • the gap between the metal films 2a is set to 0.1 mm or more as an example so that the solders 42 to be joined do not come into contact with each other within a range in which the metal film 2a can be evenly disposed on each electrode of the IGBT 2.
  • each metal film 2a is set to 2 mm or more as an example from the viewpoint of convenience of supplying the solder 42.
  • the above-mentioned “equal” means a range of ⁇ 1% or less of the arrangement interval of the metal film 2a.
  • the shape of the metal film 2a is not intended to be limited to a rectangular shape, and can be any geometric shape such as a semi-circle, an ellipse, and a triangle.
  • the circular shape shown in FIG. 6 has an effect that the stress in the solder joint portion 54 is relieved as compared with the rectangular shape.
  • FIG. 5 illustrates the metal film 2 a formed on the electrode of the IGBT 2, but the same applies to the metal film 3 a formed on the electrode of the diode 3.
  • the joint 54 is included in the proximal copper conductor layer 53 of the printed circuit board 50, and forms a part of the proximal copper conductor layer 53 so as to be integrally formed with the proximal copper conductor layer 53.
  • FIG. As shown, the present embodiment has a comb-like shape composed of, for example, a concave portion 61 and a convex portion 62.
  • the metal films 2a and 3a formed on the surface electrodes of the IGBT 2 and the diode 3 are joined to the proximal copper conductor layer 53 of the printed board 50 in this embodiment.
  • the sizes of the concave portions 61 and the convex portions 62 forming the comb-teeth shape are respectively determined according to the size of the metal film 2a formed on the surface of the IGBT 2 and further the metal film 3a formed on the surface of the diode 3.
  • the width of the concave portion forming the comb tooth shape is set to 0.1 mm or more.
  • the proximal copper conductor layer 53 has a comb shape, the proximal copper conductor layer 53 is formed with a notch 60 that is a groove penetrating the proximal copper conductor layer 53. .
  • the joint area between the IGBT 2 and the diode 3, which are power semiconductor elements, and the proximal copper conductor layer 53 of the printed circuit board 50 does not have the notch 60. This is smaller than the conventional bonding area between the proximal copper conductor layer 53 and the electrode of the power semiconductor element.
  • a temperature cycle acts on the entire power semiconductor device 100, it is caused by a difference in thermal expansion coefficient between the insulating substrate 1 and the printed circuit board 50, that is, a difference in thermal expansion between the insulating substrate 1 and the printed circuit board 50.
  • the thermal stress acting on the solder 42 existing between the insulating substrate 1 and the printed circuit board 50 is smaller than that in the prior art. Therefore, in particular, it is possible to reduce and prevent the occurrence of defects such as breakage in the solder 42.
  • the joint portion 54 which is a joint portion between the proximal copper conductor layer 53 of the printed circuit board 50 and the power semiconductor element such as the IGBT 2, does not affect the temperature distribution of the power semiconductor element. Further, when the power semiconductor device 100 is in operation, the center of the power semiconductor element becomes high temperature, and therefore, if the solder 42 and the joint portion 54 are arranged in the center, the power semiconductor device 100 is easily destroyed by heat.
  • the plurality of metal films 2a and 3a arranged on the surface of the power semiconductor element such as IGBT 2 have the same area, and the central point of the power semiconductor element 21 (FIG. 5), it is preferable that the power supply semiconductor elements are arranged evenly, and the joint portions 54 are arranged corresponding to the metal films 2 a and 3 a.
  • the above “same” means a case where it falls within a range of ⁇ 1% or less with respect to the target value.
  • the bonding area of the bonding portion 54 is preferably smaller than each area of the metal film 2a and the metal film 3a.
  • the wetting angle of the solder fillet is desirably 45 degrees or less in order to reduce thermal stress.
  • wetting of the fillet is achieved by setting the bonding area of the bonding portion 54 in the range of 20% to 80% of each area of the metal films 2a and 3a. The angle can be 45 degrees or less.
  • the width of the convex portion 62 forming the joint portion 54 is 0.8 mm or less.
  • the solder 42 has a trapezoidal shape from the surface electrode toward the bonding portion 54, and a fillet is formed (FIG. 7). ). 7 illustrates the case of the diode 3, the same applies to the case of the IGBT 2.
  • solder joint between the power semiconductor element and the insulating substrate for example, a method of reflowing with a plate-like solder sandwiched therebetween or a method of applying cream solder can be applied.
  • solder bonding between the power semiconductor element and the printed circuit board 50 a method of reflowing with a plate-shaped solder sandwiched therebetween, a method of applying cream solder, and soldering to the surface electrode of the power semiconductor element in advance.
  • a method of reflowing later or a method of rejoining spherical solder in advance to the joint 54 in the proximal copper conductor layer 53 of the printed circuit board 50 and reflowing later is also applicable.
  • the joint portion 54 has the comb-shaped notch 60 as described above.
  • the thermal stress acting on the solder 42 is reduced, and the occurrence of defects in the solder 42 is reduced or prevented. From the viewpoint of doing, it is not limited to the comb shape.
  • the concave portion 61 and the convex portion 62 constituting the comb-teeth shape are not intended to be limited to a rectangular shape, and can be any geometric shape such as a semicircular shape, an elliptical shape, and a triangular shape.
  • the circular shape has an effect that the stress in the solder joint is relaxed as compared with the rectangular shape.
  • the joining portion 54 only needs to have a notch 60 of some shape.
  • the junction 54 is preferably arranged so that the junction 54 does not affect the temperature distribution of the power semiconductor element. .
  • the metal substrate using the insulating sheet 1a is used as the material of the insulating substrate 1, but the same effect can be obtained even with a ceramic substrate formed of a ceramic material such as AlN, alumina, SiN or the like. It is done.
  • Al is used for the IGBT 2 and the surface electrode of the diode as a film that does not wet the solder.
  • similar effects can be obtained by using AlN, alumina, SiN, glass, or the like.
  • PPS is used as the material of the case 7, but the same effect can be obtained by using LCP (liquid crystal polymer) having higher heat resistance.
  • the diode 3 and the IGBT 2 have a pair of 1in1 module configurations, but two pairs of 2in1 or six pairs of 6in1, and further, a power semiconductor element serving as a converter and a brake is also provided.
  • a similar effect can be obtained even in the configuration in which the devices are mounted simultaneously.
  • aluminum wire bonds are used.
  • similar effects can be obtained by using copper wires, aluminum-coated copper wires, or gold wires. Further, the same effect can be obtained with a direct potting sealing resin that is poured and cured at room temperature.
  • solder was used for the connection between the power semiconductor element and the insulating substrate 1 and the connection between the printed board 50 and the power semiconductor element
  • a conductive adhesive in which an Ag filler is dispersed in an epoxy resin or The same effect can be obtained by using Ag nanopowder or Cu nanopowder for firing the nanoparticles at a low temperature. Further, the same effect can be obtained in a transfer mold package that is sealed with a transfer mold sealing resin using a mold without using the case 7.
  • FIG. 9 and 11 are conceptual diagrams showing a schematic structure of the power semiconductor device 200 according to the second embodiment
  • FIG. 10 is a conceptual diagram showing the proximal copper conductor layer 53 side of the printed circuit board 50.
  • the joint portion 54 is included in the proximal copper conductor layer 53 of the printed circuit board 50, and joins the proximal copper conductor layer 53 and the surface electrode in the power semiconductor element such as IGBT2. It was something to do.
  • the power semiconductor device 200 according to the second embodiment includes the joint portion 54-2 that joins the distal copper conductor layer 52 of the printed circuit board 50 and the surface electrode of the power semiconductor element such as IGBT2. .
  • the power semiconductor device 200 according to the second embodiment is different from the power semiconductor device 100 according to the first embodiment only in the components related to the junction portion 54-2, and the other configurations are the same. Therefore, in the following, description will be made mainly on the joint portion 54-2, and description of the same component will be omitted.
  • the Joule heat of the power semiconductor element is conducted through the insulating substrate on which the power semiconductor element is mounted, and is connected to the insulating substrate via heat radiation grease.
  • the heat is radiated to a heat sink (not shown) connected to the copper conductor layer 1b described in the first embodiment via a heat radiation grease.
  • the joint portion 54 is wired only from the proximal copper conductor layer 53 of the printed circuit board 50 as in the first embodiment, the core material 51 having a high thermal resistance on the printed circuit board 50 is on the distal side. Since heat dissipation to the copper conductor layer 52 side is hindered, the heat dissipation path is only in the plane of the proximal copper conductor layer 53. Therefore, in the second embodiment, the joint portion 54-2 connected to the distal copper conductor layer 52 of the printed board 50 is used. The joint 54-2 will be described below.
  • the printed circuit board 50 is disposed in parallel or substantially in parallel to the power semiconductor element such as the IGBT 2 mounted on the insulating substrate 1, and includes the core material 51 and the distal side.
  • a copper conductor layer 52 and a proximal copper conductor layer 53 are provided.
  • the distal copper conductor layer 52 corresponds to a distal conductor layer located far from the power semiconductor element such as IGBT2
  • the proximal copper conductor layer 53 is adjacent to the power semiconductor element. It corresponds to the proximal conductor layer located.
  • the joint 54-2 extends from the distal copper conductor layer 52 of the printed circuit board 50 through the core material 51 to the back surface side and extends without being connected to the proximal copper conductor layer 53 of the printed circuit board 50.
  • a plurality of joint portions 54-2 are provided.
  • FIG. 12 shows a plan view of the joint portion 54-2 and shows a joining state of the joint portion 54-2 and, for example, an electrode of the IGBT 2 by the solder 42. 12 illustrates the case of the IGBT 2, the same applies to the electrode of the diode 3.
  • Such a joint 54-2 can be manufactured by drilling the core material 51 and then press-fitting a copper material into the hole. Further, in the present embodiment, for example, a spherical solder is bonded to the bonding portion 54-2 in advance, and the bonding is performed by a reflow method later.
  • the thermal resistance due to the core material 51 of the printed circuit board 50 is reduced, and the heat from the power semiconductor element such as the IGBT 2 is It can also be diffused to the distal copper conductor layer 52 of the printed circuit board 50 via 54-2. Therefore, the heat radiation efficiency of the power semiconductor element such as IGBT 2 can be improved as compared with the case of the first embodiment. Accordingly, since heat generation of the power semiconductor element can be reduced, the power semiconductor device 200 can be reduced in size and cost by reducing the size and cost of the power semiconductor element.
  • a plurality of joints 54-2 exist and are subdivided, and the area of the joint 54-2 is the same as that of the joint 54 in the first embodiment as shown in FIG.
  • the area of the metal film 2a and the metal film 3a formed on the surface electrode of the power semiconductor element can be in the range of 20% to 80%. Therefore, the thermal stress acting on the solder 42 existing between the insulating substrate 1 and the printed circuit board 50 caused by the difference in thermal expansion between the insulating substrate 1 and the printed circuit board 50 due to the temperature cycle is higher than that of the conventional case. Become smaller. Therefore, in particular, the occurrence of defects such as breakage in the solder 42 can be reduced and prevented.
  • FIG. 13 illustrates the case of the diode 3, but the same applies to the case of the IGBT 2.
  • the modified example related to the insulating substrate 1, the case 7, the wire bond, and the solder, the modified example related to the power semiconductor element, and the modified example related to the sealing resin described in the first embodiment will be described in the present embodiment.
  • the present invention can be similarly applied to the power semiconductor device 200 of the first embodiment.
  • FIG. 14 to 16 show a schematic structure of the power semiconductor device 300 according to the third embodiment.
  • 17 to 19 show a schematic structure of the power semiconductor device 400 according to the third embodiment.
  • power semiconductor device 300 corresponds to a modification of power semiconductor device 100 in the first embodiment
  • power semiconductor device 400 corresponds to a modification of power semiconductor device 200 in the second embodiment.
  • slits 55 penetrating the printed circuit board 50 are provided in the printed circuit boards 50 in the power semiconductor devices 100 and 200, respectively.
  • the power semiconductor devices 300 and 400 are different from the power semiconductor devices 100 and 200 only in the components related to the slit 55, and the rest have the same configuration. Therefore, in the following, the slit 55 will be mainly described, and the description of the same components will be omitted.
  • the sealing resin 6 is placed in the gap between the insulating substrate 1 and the printed circuit board 50. Need to be filled. Further, in the IGBT 2 and the diode 3, it is necessary to fill the space with the sealing resin 6 in order to ensure the creeping insulation distance between the front and back surfaces of each power semiconductor element.
  • the power semiconductor device 100 includes the joint 54 having a comb-teeth shape.
  • the joint portion 54 having a comb-teeth shape between the surface electrode of the power semiconductor element such as the IGBT 2 and the printed circuit board 50 an unfilled region is easily generated by entraining air. Therefore, for example, measures such as slowing the injection rate of the sealing resin 6 are required, and there is a concern that productivity may be reduced. As a countermeasure, it is effective to shorten the inflow distance of the sealing resin 6.
  • FIGS. 14 to 16 the core material 51 of the printed circuit board 50 and the distant portion of the printed circuit board 50 correspond to the center point 21 of the power semiconductor element to which the sealing resin 6 is most hardly injected.
  • a slit 55 was provided in the distal copper conductor layer 52.
  • the slit 55 is a groove that penetrates the core material 51 and the distal copper conductor layer 52 in the thickness direction, and is located corresponding to the joint 54 as described above. That is, as described in the first embodiment, the notch 60 in the joint portion 54 is positioned corresponding to the center point 21 of the power semiconductor element, so that the slit 55 corresponds to the notch 60. Will be located.
  • FIG. 16 is a diagram corresponding to FIG. 5, and is a diagram clearly showing an example of an arrangement position of the slit 55 in the printed circuit board 50 with respect to the joint portion 54.
  • FIG. 17 is a view corresponding to FIG. 12 and clearly shows the arrangement position of the slit 55 in the printed circuit board 50 with respect to the joint portion 54-2.
  • FIG. 20 shows a power semiconductor device 500 as a modification of the power semiconductor device according to the third embodiment having the slit 55.
  • the power semiconductor device 500 corresponds to a configuration that does not have the notch 60 in the proximal copper conductor layer 53, and has a plurality of slits corresponding to the center point 21 of the power semiconductor element in which the sealing resin 6 is most difficult to be injected. 55 is provided. Also in the power semiconductor device 500, the slit 55 exists in the joint portion 54 that joins the surface electrode and the proximal copper conductor layer 53 in the IGBT 2 or the like.
  • the sealing resin 6 passes through the slit 55 and between the insulating substrate 1 and the printed circuit board 50, in particular, the bonding portions 54, 54-. 2 can be filled in an unfilled region of the sealing resin 6 that may occur in step 2. Therefore, it is possible to eliminate the occurrence of the unfilled area. Therefore, the resin injection speed can be further increased. As a result, it is possible to avoid a decrease in productivity and improve productivity.
  • the slit 55 in addition to the above-described effects, the state of the fillet of the solder 42 at the joints 54 and 54-2 joined to the surface electrodes of the IGBT 2 and the diode 3 is visually inspected. It becomes easy. Therefore, there is also an effect that the bonding state inspection process can be easily performed in a short time.
  • the thermal stress acting on the solder 42 due to the temperature cycle described in the first and second embodiments is as follows. , Smaller than conventional. Therefore, in particular, the occurrence of defects such as breakage in the solder 42 can be reduced and prevented.
  • the joint portion 54 has the slit 55, so that the slit 55 can perform the same operation as the notch 60. Therefore, also in the power semiconductor device 500, it is possible to reduce and further prevent the occurrence of the above-described problems.
  • the present invention can be similarly applied to the power semiconductor devices 300, 400, and 500 of the third embodiment.
  • FIG. 21 and 22 are conceptual diagrams each showing a schematic structure of power semiconductor device 600 according to the fourth embodiment.
  • power semiconductor device 600 corresponds to a modification of power semiconductor device 100 in the first embodiment.
  • the printed circuit board 50 in the power semiconductor device 100 is provided with a through hole 58 that penetrates the core material 51 and the distal copper conductor layer 52 of the printed circuit board 50.
  • the power semiconductor device 600 is different from the power semiconductor device 100 only in the components related to the through holes 58, and the other components are the same. Therefore, in the following, the through hole 58 will be mainly described, and the description of the same components will be omitted.
  • the distal-side copper conductor layer 52 and the proximal-side copper conductor layer 53 formed on both surfaces of the core material 51 of the printed circuit board 50 are arranged asymmetrically with each other, warpage or undulation due to thermal strain occurs. Cheap. Therefore, a large thermal stress is likely to occur in the solder 42 joined to the joint portion 54. Therefore, in the power semiconductor device 600, as shown in FIGS. 21 and 22, through-holes are formed in the core material 51 and the distal copper conductor layer 52 of the printed circuit board 50 corresponding to the entire bonding portion 54 to which the solder is bonded. 58 was provided.
  • the through hole 58 is a groove that penetrates the core material 51 and the distal copper conductor layer 52 in the thickness direction, and is located corresponding to the entire joint portion 54 as described above.
  • the through hole 58 in addition to the above-described effects, it is possible to visually inspect the fillet state of the solder 42 in the joint portion 54 joined to the surface electrode of the IGBT 2 and the diode 3, Compared with the case where the slit 55 is provided in the power semiconductor device 300, it becomes easier. Therefore, there is also an effect that the bonding state inspection process can be easily performed in a short time.
  • the sealing resin 6 passes through the through-hole 58 and enters between the insulating substrate 1 and the printed circuit board 50, particularly in the bonding portion 54.
  • the filling property in the unfilled region is improved as compared with the case where the slit 55 is provided in the power semiconductor device 300. Therefore, it is possible to eliminate the occurrence of the unfilled area. Therefore, the resin injection speed can be further improved as compared with the third embodiment. As a result, it is possible to avoid a decrease in productivity and to improve productivity.
  • the present invention can be similarly applied to the power semiconductor device 600 of the fourth embodiment.

Abstract

This power semiconductor device 100, wherein electrodes of power semiconductor elements 2, 3 and a conductor layer of a printed board 50 are bonded by a solder, is additionally provided with a bonding part 54 that is formed integrally with the conductor layer. The bonding part has a comb-shaped cut 60, and is arranged so as not to be positioned at the central point 21 of a power semiconductor element.

Description

電力用半導体装置Power semiconductor device
　本発明は、電力用半導体装置に関し、詳しくは、電力用半導体素子が実装された絶縁基板と、電力用半導体素子の主回路が形成されたプリント基板とを備えた電力用半導体装置に関する。 The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device including an insulating substrate on which a power semiconductor element is mounted and a printed circuit board on which a main circuit of the power semiconductor element is formed.
　電力用半導体装置は、産業用機器、電気鉄道、家電など幅広い分野における機器の主電力（パワー）の制御に用いられ、特に産業用機器に搭載される電力用半導体装置に対しては、小型化、高放熱性、高信頼性が求められる。また電力用半導体装置では、ＩＧＢＴ及びＦｗＤｉなどの電力用半導体素子を放熱性の高い絶縁基板に実装し、電力用半導体素子の表面電極へ例えばアルミワイヤなどで配線して回路を構成する場合が多い。
　このような構造では、絶縁基板上で配線がなされるため、高価である絶縁基板の面積が大きくなりコストアップにつながると共に、電力用半導体装置の外形も大きくなるという課題がある。 Power semiconductor devices are used to control the main power of devices in a wide range of fields such as industrial equipment, electric railways, and home appliances. In particular, power semiconductor devices mounted on industrial equipment are downsized. High heat dissipation and high reliability are required. In power semiconductor devices, power semiconductor elements such as IGBTs and FwDi are often mounted on an insulating substrate with high heat dissipation, and the circuit is configured by wiring the surface electrodes of the power semiconductor elements with, for example, aluminum wires. .
In such a structure, since wiring is performed on the insulating substrate, there is a problem that the area of the expensive insulating substrate is increased, resulting in an increase in cost and an increase in the outer shape of the power semiconductor device.
　よって電力用半導体装置の小型化のため、特許文献１では、半導体素子を実装した絶縁基板と両面配線されたプリント基板とを、はんだなどの導電性接着剤で電気的に接続し、樹脂筐体内に収納された構造が提案されている。 Therefore, in order to reduce the size of the power semiconductor device, in Patent Document 1, an insulating substrate on which a semiconductor element is mounted and a printed circuit board that is wired on both sides are electrically connected with a conductive adhesive such as solder, A structure housed in the box has been proposed.
特開２０１２－７４７３０号公報JP 2012-74730 A
　一方、大電流を高速でスイッチングする電力用半導体装置では発熱量が大きく、絶縁基板とプリント基板との熱膨張差が大きくなる。よって、温度サイクルにより、絶縁基板とプリント基板との間に存在する、はんだと電力用半導体素子とに大きな熱応力が発生する。
　また、電力用半導体素子の駆動回路を形成したプリント基板に１００Ａ以上の電流を流すためには、プリント基板における銅導体層の厚みは、０．１ｍｍ以上が必要となる。よって、特にプリント基板と電力用半導体素子と間のはんだ接合部に生じる熱応力が問題となる。そのため、電力用半導体装置の長期信頼性を確保するためには、この熱応力による不具合を低減する必要がある。 On the other hand, a power semiconductor device that switches a large current at high speed generates a large amount of heat, and a thermal expansion difference between an insulating substrate and a printed circuit board increases. Therefore, a large thermal stress is generated in the solder and the power semiconductor element existing between the insulating substrate and the printed circuit board due to the temperature cycle.
Further, in order to pass a current of 100 A or more through the printed circuit board on which the drive circuit for the power semiconductor element is formed, the thickness of the copper conductor layer in the printed circuit board needs to be 0.1 mm or more. Therefore, in particular, the thermal stress generated at the solder joint between the printed circuit board and the power semiconductor element becomes a problem. Therefore, in order to ensure the long-term reliability of the power semiconductor device, it is necessary to reduce defects due to this thermal stress.
　しかしながら特許文献１は、絶縁基板及びプリント基板を用いた電力用半導体装置の構造を開示するが、熱応力の低減について特に記述していない。
　本発明は、上述の問題点を解決するためになされたものであり、電力用半導体装置の長期信頼性を確保可能な電力用半導体装置を提供することを目的とする。 However, Patent Document 1 discloses a structure of a power semiconductor device using an insulating substrate and a printed circuit board, but does not particularly describe reduction of thermal stress.
The present invention has been made to solve the above-described problems, and an object thereof is to provide a power semiconductor device capable of ensuring long-term reliability of the power semiconductor device.
　上記目的を達成するため、本発明は以下のように構成する。
　即ち、本発明の一態様における電力用半導体装置は、電力用半導体素子と、導体層を有するプリント基板とを備え、上記電力用半導体素子の電極と上記プリント基板の導体層とをはんだで接合した状態の電力用半導体装置において、上記電力用半導体素子は、表面電極に、はんだを接合するための金属膜と、はんだと接合しない膜とを有し、上記金属膜は、上記電力用半導体素子に複数配置されており、上記はんだが接合されない膜は、上記電力用半導体素子の中央に配置されており、上記導体層の一部を構成し上記導体層と一体に形成された状態の接合部をさらに備え、上記接合部は切欠きを有し、該切欠きは、上記半導体素子の金属膜に対応するように配置されていることを特徴とする。 In order to achieve the above object, the present invention is configured as follows.
That is, a power semiconductor device according to an aspect of the present invention includes a power semiconductor element and a printed board having a conductor layer, and the electrode of the power semiconductor element and the conductor layer of the printed board are joined by solder. In the power semiconductor device in a state, the power semiconductor element has a metal film for bonding solder and a film not bonded to solder on the surface electrode, and the metal film is formed on the power semiconductor element. A plurality of films, which are not bonded to the solder, are disposed in the center of the power semiconductor element, and constitute a part of the conductor layer and a joint part formed integrally with the conductor layer. In addition, the joining portion has a notch, and the notch is disposed so as to correspond to the metal film of the semiconductor element.
　本発明の一態様における電力用半導体装置によれば、接合部を備え、この接合部は切欠きを有することで、電力用半導体素子の電極とプリント基板の導体層との接合面積は、接合部を有しない場合の接合面積に比べて小さくなる。この結果、電力用半導体装置の全体に温度サイクルが作用した場合において、電力用半導体素子の電極とプリント基板の導体層との間に存在するはんだに作用する熱応力は、従来に比べて小さくなる。したがって、このはんだにおける破損等の不具合の発生を低減さらには防止することができ、電力用半導体装置の長期信頼性を確保することが可能となる。 According to the power semiconductor device of one aspect of the present invention, the bonding portion is provided, and the bonding portion has a notch so that the bonding area between the electrode of the power semiconductor element and the conductor layer of the printed board is equal to the bonding portion. It becomes smaller than the bonding area in the case of not having. As a result, when a temperature cycle acts on the entire power semiconductor device, the thermal stress acting on the solder existing between the electrode of the power semiconductor element and the conductor layer of the printed circuit board becomes smaller than in the past. . Therefore, the occurrence of defects such as breakage in the solder can be reduced and prevented, and the long-term reliability of the power semiconductor device can be ensured.
実施の形態１における電力用半導体装置で絶縁基板に電力用半導体素子が搭載された状態を示す概念図である。1 is a conceptual diagram showing a state where a power semiconductor element is mounted on an insulating substrate in the power semiconductor device according to the first embodiment. 図１に示す電力用半導体装置の概念図である。FIG. 2 is a conceptual diagram of the power semiconductor device shown in FIG. 1. 図１に示す電力用半導体装置において、電力用半導体素子とはんだで接合するプリント基板の面を示す概念図である。In the power semiconductor device shown in FIG. 1, it is a conceptual diagram which shows the surface of the printed circuit board joined with a power semiconductor element with solder. 図２に示すＡ－Ａ断面における電力用半導体装置の概念図である。FIG. 3 is a conceptual diagram of the power semiconductor device in the AA cross section shown in FIG. 2. 図４に示す電力用半導体装置に備わる接合部と電力用半導体素子とを接合したはんだの状態を拡大して示した概念図である。FIG. 5 is an enlarged conceptual diagram illustrating a solder state in which a joint portion and a power semiconductor element included in the power semiconductor device illustrated in FIG. 4 are joined. 図１に示す電力用半導体装置に備わる電力用半導体素子の金属膜が円形であることを示す概念図である。It is a conceptual diagram which shows that the metal film of the power semiconductor element with which the power semiconductor device shown in FIG. 1 is provided is circular. 図４に示す電力用半導体装置に備わる接合部と電力用半導体素子との接合の変形例を示す概念図である。FIG. 5 is a conceptual diagram illustrating a modification example of a junction between a junction and a power semiconductor element included in the power semiconductor device illustrated in FIG. 4. 図５に示す電力用半導体装置に備わる接合部と電力用半導体素子との接合の変形例を示す概念図である。FIG. 6 is a conceptual diagram illustrating a modified example of a junction between a junction and a power semiconductor element included in the power semiconductor device illustrated in FIG. 5. 実施の形態２における電力用半導体装置の概念図である。FIG. 6 is a conceptual diagram of a power semiconductor device in a second embodiment. 図９に示す電力用半導体装置において、電力用半導体素子とはんだで接合するプリント基板の面を示す概念図である。FIG. 10 is a conceptual diagram illustrating a surface of a printed circuit board that is joined to a power semiconductor element by solder in the power semiconductor device illustrated in FIG. 9. 図９に示すＢ－Ｂ断面における電力用半導体装置の概念図である。FIG. 10 is a conceptual diagram of the power semiconductor device in the BB cross section shown in FIG. 9. 図１１に示す電力用半導体装置に備わる接合部と電力用半導体素子との接合の状態を示す概念図である。It is a conceptual diagram which shows the state of the junction of the junction part with which the power semiconductor device shown in FIG. 11 is equipped, and a power semiconductor element. 図１１に示す電力用半導体装置に備わる接合部と電力用半導体素子との接合の変形例を示す概念図である。FIG. 12 is a conceptual diagram illustrating a modified example of a junction between a junction and a power semiconductor element included in the power semiconductor device illustrated in FIG. 11. 実施の形態３における電力用半導体装置で、実施の形態１に対応した電力用半導体装置における概念図である。FIG. 11 is a conceptual diagram of a power semiconductor device according to a third embodiment, corresponding to the power semiconductor device according to the first embodiment. 図１４に示すＣ－Ｃ断面を示す図であり、実施の形態１に対応した電力用半導体装置における概念図である。FIG. 15 is a cross-sectional view taken along the line CC shown in FIG. 14 and is a conceptual diagram of the power semiconductor device corresponding to the first embodiment. 図１５に示す電力用半導体装置に備わる接合部及びスリットと電力用半導体素子との接合の状態を示す概念図である。FIG. 16 is a conceptual diagram illustrating a bonding state of the power semiconductor device illustrated in FIG. 15 and a bonding state between a slit and a power semiconductor element. 実施の形態３における電力用半導体装置で、実施の形態２に対応した電力用半導体装置における概念図である。FIG. 10 is a conceptual diagram of a power semiconductor device according to a third embodiment, corresponding to the power semiconductor device according to the second embodiment. 図１７に示すＤ－Ｄ断面を示す図であり、実施の形態１に対応した電力用半導体装置における概念図である。FIG. 18 is a cross-sectional view taken along the line DD shown in FIG. 17, and is a conceptual diagram of the power semiconductor device corresponding to the first embodiment. 図１８に示す電力用半導体装置に備わる接合部及びスリットと電力用半導体素子との接合の状態を示す概念図である。It is a conceptual diagram which shows the state of the junction of the junction part and slit with which the power semiconductor device shown in FIG. 18 is equipped, and a power semiconductor element. 実施の形態３における電力用半導体装置で、接合部に切欠きを有しない場合の状態を示す概念図である。FIG. 10 is a conceptual diagram showing a state where a junction is not cut in the power semiconductor device according to the third embodiment. 実施の形態４における電力用半導体装置で、実施の形態１に対応した電力用半導体装置における概念図である。FIG. 10 is a conceptual diagram of a power semiconductor device according to a fourth embodiment, corresponding to the first embodiment. 図２１に示すＥ－Ｅ断面を示す図であり、実施の形態１に対応した電力用半導体装置における概念図である。FIG. 22 is a diagram showing an EE cross section shown in FIG. 21, and a conceptual diagram of the power semiconductor device corresponding to the first embodiment.
　実施形態である電力用半導体装置について、図を参照しながら以下に説明する。尚、各図において、同一又は同様の構成部分については同じ符号を付している。また、以下の説明が不必要に冗長になるのを避け当業者の理解を容易にするため、既によく知られた事項の詳細説明及び実質的に同一の構成に対する重複説明を省略する場合がある。また、以下の説明及び添付図面の内容は、特許請求の範囲に記載の主題を限定することを意図するものではない。 The power semiconductor device according to the embodiment will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. In addition, in order to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art, a detailed description of already well-known matters and a duplicate description of substantially the same configuration may be omitted. . Further, the contents of the following description and the accompanying drawings are not intended to limit the subject matter described in the claims.
　実施の形態１．
　図１、図２、図４、図６は、実施の形態１における電力用半導体装置１００の概略構造を示す概念図であり、図３はプリント基板５０の近位側銅導体層５３側を示す概念図である。
　電力用半導体装置１００は、基本的構成部分として、電力用半導体素子２，３と、プリント基板５０とを有する。本実施の形態１の電力用半導体装置１００では、その他に、絶縁基板１、ケース７、封止樹脂６、電極端子８等を有することができる。 Embodiment 1 FIG.
1, 2, 4, and 6 are conceptual diagrams showing a schematic structure of the power semiconductor device 100 according to the first embodiment. FIG. 3 shows the proximal copper conductor layer 53 side of the printed circuit board 50. It is a conceptual diagram.
The power semiconductor device 100 includes power semiconductor elements 2 and 3 and a printed circuit board 50 as basic components. In addition, the power semiconductor device 100 of the first embodiment can include the insulating substrate 1, the case 7, the sealing resin 6, the electrode terminal 8, and the like.
　電力用半導体素子として、本実施形態では、ＩＧＢＴ２（Insulated Gate Bipolar Transistor）及びダイオード（例えばＦｗＤｉ）３が相当する。絶縁基板１は、一例として厚さ０．１２５ｍｍの樹脂絶縁シート１ａと、樹脂絶縁シート１ａの厚み方向において対向する両面に接着された、例えば厚さ２ｍｍの銅導体層１ｂ及び例えば厚さ０．５ｍｍの銅導体層１ｃとを有する。絶縁基板１の銅導体層１ｃには、ＩＧＢＴ２及びダイオード３が、より具体的にはＩＧＢＴ２及びダイオード３における各裏面側の電極が、はんだ４１によって電気的かつ機械的に接続される。ＩＧＢＴ２は、例えば８ｍｍ×８ｍｍで厚さが０．０８ｍｍの大きさを有し、ダイオード３は、例えば８ｍｍ×６ｍｍで厚さが０．０８ｍｍの大きさを有する。ＩＧＢＴ２及びダイオード３の表面には、はんだが接合されない例えばＡｌ膜と、はんだ接合可能なように、Ａｕなどの金属膜２ａ、３ａとが形成されている。ここで、はんだが接合されない膜は、ＩＧＢＴ２及びダイオード３の表面の中央に位置する。はんだ４１は、厚みが約０．１ｍｍでＳｎ－Ａｇ－Ｃｕ系のはんだが用いられる。このような絶縁基板１は、ＩＧＢＴ２及びダイオード３の放熱と、両半導体素子２，３の裏面側の各電極における配線とを兼ねている。 As the power semiconductor element, in this embodiment, an IGBT 2 (Insulated Gate Bipolar Transistor) and a diode (for example, FwDi) 3 correspond. The insulating substrate 1 is, for example, a resin insulating sheet 1a having a thickness of 0.125 mm and a copper conductor layer 1b having a thickness of, for example, 2 mm and bonded to both surfaces facing each other in the thickness direction of the resin insulating sheet 1a. 5 mm copper conductor layer 1c. The IGBT 2 and the diode 3, more specifically, the electrodes on the back side of the IGBT 2 and the diode 3 are electrically and mechanically connected to the copper conductor layer 1 c of the insulating substrate 1 by the solder 41. The IGBT 2 has a size of 8 mm × 8 mm and a thickness of 0.08 mm, for example, and the diode 3 has a size of 8 mm × 6 mm and a thickness of 0.08 mm, for example. On the surfaces of the IGBT 2 and the diode 3, for example, an Al film to which solder is not bonded, and metal films 2a and 3a such as Au are formed so that solder bonding is possible. Here, the film to which the solder is not bonded is located at the center of the surface of the IGBT 2 and the diode 3. As the solder 41, Sn—Ag—Cu based solder having a thickness of about 0.1 mm is used. Such an insulating substrate 1 serves as both heat radiation of the IGBT 2 and the diode 3 and wiring in each electrode on the back surface side of both the semiconductor elements 2 and 3.
　プリント基板５０は、図４に示すように、絶縁基板１に実装されたＩＧＢＴ２等の電力用半導体素子に対向して平行又は略平行に配置される。プリント基板５０は、例えば、厚さが０．５ｍｍで、その材質がＦＲ－４（Flame Retardant Type 4）のコア材５１と、コア材５１の厚み方向における両面に電力用半導体素子に対して遠方に形成された遠位側銅導体層５２及び近方に形成された近位側銅導体層５３とを有する。遠位側銅導体層５２及び近位側銅導体層５３は、それぞれ厚さが例えば０．１ｍｍで、接着シート（図示せず）によってコア材５１に接着され、回路パターンを形成する。また、遠位側銅導体層５２と近位側銅導体層５３とはスルーホール５６を介して電気的に連結されている。 As shown in FIG. 4, the printed circuit board 50 is disposed in parallel or substantially in parallel to the power semiconductor element such as IGBT 2 mounted on the insulating substrate 1. The printed circuit board 50 is, for example, a core material 51 having a thickness of 0.5 mm and a material of FR-4 (Flame Retardant Type 4), and distant from the power semiconductor element on both sides in the thickness direction of the core material 51 And a proximal copper conductor layer 53 formed in the vicinity. The distal copper conductor layer 52 and the proximal copper conductor layer 53 each have a thickness of, for example, 0.1 mm, and are bonded to the core material 51 by an adhesive sheet (not shown) to form a circuit pattern. Further, the distal copper conductor layer 52 and the proximal copper conductor layer 53 are electrically connected through a through hole 56.
　ここで、互いに対向するプリント基板５０と、ＩＧＢＴ２及びダイオード３の半導体素子とは、封止樹脂６にエポキシ樹脂を用いた場合には、電気的絶縁を確保するために０．３ｍｍ以上の間隔をあける必要がある。
　またプリント基板５０の近位側銅導体層５３は、本実施形態において特徴的構成の一つである接合部５４を有する。接合部５４は、ＩＧＢＴ２及びダイオード３における各表面電極と近位側銅導体層５３とを、はんだ４２によって電気的かつ機械的に接合する部分である。つまり接合部５４を介して、プリント基板５０の近位側銅導体層５３とＩＧＢＴ２及びダイオード３における各表面電極とが接続される。接合部５４については、以下でさらに詳しく説明する。尚、はんだ４２は、例えば、厚みが０．２ｍｍから０．８ｍｍでＳｎ－Ａｇ－Ｃｕ系のはんだである。 Here, the printed circuit board 50 facing each other and the semiconductor elements of the IGBT 2 and the diode 3 have an interval of 0.3 mm or more in order to ensure electrical insulation when an epoxy resin is used as the sealing resin 6. It is necessary to open.
Further, the proximal copper conductor layer 53 of the printed circuit board 50 has a joint 54 which is one of the characteristic configurations in the present embodiment. The joint portion 54 is a portion that electrically and mechanically joins each surface electrode of the IGBT 2 and the diode 3 and the proximal copper conductor layer 53 with the solder 42. That is, the proximal-side copper conductor layer 53 of the printed circuit board 50 is connected to the surface electrodes of the IGBT 2 and the diode 3 through the joint portion 54. The junction 54 will be described in more detail below. The solder 42 is, for example, a Sn—Ag—Cu solder having a thickness of 0.2 mm to 0.8 mm.
　電力用半導体装置１００のその他の構成として、絶縁基板１の外縁部分には、図４に示すように、主にＰＰＳ（ポリフェニレンサルファイド）からなるケース７がシリコーン接着剤（図示せず）で接着されている。ケース７には、電極端子８がインサートされており、電極端子８には、ＩＧＢＴ２及びダイオード３などの半導体素子のエミッタ電極及びゲート電極（表面電極に相当）が、プリント基板５０の近位側銅導体層５３から遠位側銅導体層５２を介し、アルミニウム製の例えばφ０．３ｍｍのボンディングワイヤ９にて、それぞれ電気的に接続されている。
　また、ケース７の内側には、絶縁基板１とプリント基板５０との隙間からプリント基板５０の上面を覆うまでエポキシ樹脂製の封止樹脂６を注入し、真空脱泡して加熱して硬化される。これにて絶縁基板１に設置されたＩＧＢＴ２、ダイオード３、プリント基板５０等は、封止樹脂６にて封止される。 As another configuration of the power semiconductor device 100, a case 7 made mainly of PPS (polyphenylene sulfide) is bonded to the outer edge portion of the insulating substrate 1 with a silicone adhesive (not shown), as shown in FIG. ing. An electrode terminal 8 is inserted into the case 7, and an emitter electrode and a gate electrode (corresponding to a surface electrode) of a semiconductor element such as the IGBT 2 and the diode 3 are inserted into the electrode terminal 8, and the proximal side copper of the printed board 50. The conductor layer 53 is electrically connected through the distal copper conductor layer 52 with a bonding wire 9 made of aluminum, for example, φ0.3 mm.
Further, an epoxy resin sealing resin 6 is poured into the case 7 from the gap between the insulating substrate 1 and the printed circuit board 50 until the upper surface of the printed circuit board 50 is covered, vacuum degassed and heated to be cured. The Thereby, the IGBT 2, the diode 3, the printed board 50, and the like installed on the insulating substrate 1 are sealed with the sealing resin 6.
　次に、接合部５４について詳しく説明する。
　図５は、接合部５４の平面図を示すと共に、接合部５４と、例えばＩＧＢＴ２の電極に形成された金属膜２ａとのはんだ４２による接合状態を示している。
　金属膜２ａは、ＩＧＢＴ２における複数の電極上に、それぞれ均等に配置されており、各々の金属膜２ａの面積は同等である。各金属膜２ａ同士の隙間は、ＩＧＢＴ２の各電極上に金属膜２ａが均等に配置できる範囲内で、接合されるはんだ４２同士が接触しないように、一例として０．１ｍｍ以上にしている。また、各金属膜２ａのサイズは、はんだ４２の供給の利便性の観点から、一例として２ｍｍ幅以上にしている。尚、上述の「均等」とは、金属膜２ａの配置間隔の±１％以下の範囲を意味する。 Next, the joint portion 54 will be described in detail.
FIG. 5 shows a plan view of the joining portion 54 and shows a joining state of the joining portion 54 and the metal film 2a formed on, for example, the electrode of the IGBT 2 by the solder 42.
The metal films 2a are equally arranged on the plurality of electrodes in the IGBT 2, and the areas of the metal films 2a are the same. The gap between the metal films 2a is set to 0.1 mm or more as an example so that the solders 42 to be joined do not come into contact with each other within a range in which the metal film 2a can be evenly disposed on each electrode of the IGBT 2. In addition, the size of each metal film 2a is set to 2 mm or more as an example from the viewpoint of convenience of supplying the solder 42. The above-mentioned “equal” means a range of ± 1% or less of the arrangement interval of the metal film 2a.
　また、金属膜２ａの形状は、矩形状に限定する意図ではなく、例えば半円形、楕円形、三角形等の任意の幾何学的形状が可能である。例えば図６に示す円形形状は、矩形形状の場合に比べて、はんだ接合部５４における応力が緩和されるという効果もある。
　尚、図５は、ＩＧＢＴ２の電極に形成された金属膜２ａを図示するが、ダイオード３の電極に形成された金属膜３ａについても同様である。 The shape of the metal film 2a is not intended to be limited to a rectangular shape, and can be any geometric shape such as a semi-circle, an ellipse, and a triangle. For example, the circular shape shown in FIG. 6 has an effect that the stress in the solder joint portion 54 is relieved as compared with the rectangular shape.
FIG. 5 illustrates the metal film 2 a formed on the electrode of the IGBT 2, but the same applies to the metal film 3 a formed on the electrode of the diode 3.
　接合部５４は、プリント基板５０の近位側銅導体層５３に含まれ、近位側銅導体層５３の一部を構成して近位側銅導体層５３と一体に形成され、図５に示すように本実施の形態では、例えば凹部６１及び凸部６２で構成した櫛歯形状を有する。このような接合部５４において、ＩＧＢＴ２及びダイオード３の表面電極に形成された金属膜２ａ、３ａと、本実施形態ではプリント基板５０の近位側銅導体層５３とが接合される。そのため、櫛歯形状を形成する凹部６１及び凸部６２のサイズは、ＩＧＢＴ２の表面に形成された金属膜２ａ、さらにはダイオード３の表面に形成された金属膜３ａのサイズに応じてそれぞれ決定される。櫛歯形状を形成する凹部の幅は、一例として０．１ｍｍ以上にしている。
　また、近位側銅導体層５３が櫛歯形状を有することで、近位側銅導体層５３には近位側銅導体層５３を貫通する溝である切欠き６０が形成されることになる。 The joint 54 is included in the proximal copper conductor layer 53 of the printed circuit board 50, and forms a part of the proximal copper conductor layer 53 so as to be integrally formed with the proximal copper conductor layer 53. FIG. As shown, the present embodiment has a comb-like shape composed of, for example, a concave portion 61 and a convex portion 62. In such a joint portion 54, the metal films 2a and 3a formed on the surface electrodes of the IGBT 2 and the diode 3 are joined to the proximal copper conductor layer 53 of the printed board 50 in this embodiment. Therefore, the sizes of the concave portions 61 and the convex portions 62 forming the comb-teeth shape are respectively determined according to the size of the metal film 2a formed on the surface of the IGBT 2 and further the metal film 3a formed on the surface of the diode 3. The As an example, the width of the concave portion forming the comb tooth shape is set to 0.1 mm or more.
Further, since the proximal copper conductor layer 53 has a comb shape, the proximal copper conductor layer 53 is formed with a notch 60 that is a groove penetrating the proximal copper conductor layer 53. .
　このような櫛歯形状の接合部５４を用いることで、電力用半導体素子であるＩＧＢＴ２及びダイオード３と、プリント基板５０の近位側銅導体層５３との接合面積は、切欠き６０を有しない従来の、近位側銅導体層５３と電力用半導体素子の電極との接合面積と比べて小さくなる。この結果、電力用半導体装置１００の全体に温度サイクルが作用した場合において、絶縁基板１とプリント基板５０との熱膨張係数の差、つまり絶縁基板１とプリント基板５０との熱膨張差に起因して発生する、絶縁基板１とプリント基板５０との間に存在するはんだ４２に作用する熱応力は、従来に比べて小さくなる。したがって、特に、はんだ４２における破損等の不具合の発生を低減さらには防止することが可能になる。 By using such a comb-shaped joint 54, the joint area between the IGBT 2 and the diode 3, which are power semiconductor elements, and the proximal copper conductor layer 53 of the printed circuit board 50 does not have the notch 60. This is smaller than the conventional bonding area between the proximal copper conductor layer 53 and the electrode of the power semiconductor element. As a result, when a temperature cycle acts on the entire power semiconductor device 100, it is caused by a difference in thermal expansion coefficient between the insulating substrate 1 and the printed circuit board 50, that is, a difference in thermal expansion between the insulating substrate 1 and the printed circuit board 50. The thermal stress acting on the solder 42 existing between the insulating substrate 1 and the printed circuit board 50 is smaller than that in the prior art. Therefore, in particular, it is possible to reduce and prevent the occurrence of defects such as breakage in the solder 42.
　さらにまた、電力用半導体装置１００にあっては、プリント基板５０に大電流（上述したように例えば１００Ａ以上）が流れることから、プリント基板５０では発熱が大きくなる。よって、プリント基板５０の近位側銅導体層５３とＩＧＢＴ２等の電力用半導体素子との接合部分となる接合部５４が電力用半導体素子の温度分布に影響を与えないようにするのが好ましい。また、電力用半導体装置１００の動作時には、電力用半導体素子の中央が高温になるため、中央にはんだ４２及び接合部５４が配置されると熱破壊しやすい。このような熱破壊を防止するため本実施形態では、ＩＧＢＴ２等の電力用半導体素子表面に配置された複数の金属膜２ａ、３ａは、それぞれの面積が同一であり、電力用半導体素子の中心点２１（図５）を回避するように、電力用半導体素子に対して均等に配置され、金属膜２ａ、３ａに対応して接合部５４が配置されるのがよい。尚、ここで上記「同一」とは、目標値に対して±１％以下の範囲に含まれる場合を意味する。 Furthermore, in the power semiconductor device 100, since a large current (for example, 100 A or more as described above) flows through the printed circuit board 50, the printed circuit board 50 generates a large amount of heat. Therefore, it is preferable that the joint portion 54, which is a joint portion between the proximal copper conductor layer 53 of the printed circuit board 50 and the power semiconductor element such as the IGBT 2, does not affect the temperature distribution of the power semiconductor element. Further, when the power semiconductor device 100 is in operation, the center of the power semiconductor element becomes high temperature, and therefore, if the solder 42 and the joint portion 54 are arranged in the center, the power semiconductor device 100 is easily destroyed by heat. In order to prevent such thermal destruction, in the present embodiment, the plurality of metal films 2a and 3a arranged on the surface of the power semiconductor element such as IGBT 2 have the same area, and the central point of the power semiconductor element 21 (FIG. 5), it is preferable that the power supply semiconductor elements are arranged evenly, and the joint portions 54 are arranged corresponding to the metal films 2 a and 3 a. Here, the above “same” means a case where it falls within a range of ± 1% or less with respect to the target value.
　また、接合部５４と、電力用半導体素子の表面電極に形成された金属膜２ａ及び金属膜３ａとを接合するはんだ４２には、熱応力を低減するためにフィレットを形成することが望ましい。そのため、接合部５４の接合面積は、金属膜２ａ及び金属膜３ａの各面積よりも小さくするのがよい。はんだフィレットのぬれ角は、熱応力を低減するために４５度以下にするのが望ましい。はんだ４２の高さが例えば０．２ｍｍから０．８ｍｍである場合、接合部５４の接合面積を、金属膜２ａ、３ａの各面積の２０％から８０％の範囲にすることで、フィレットのぬれ角を４５度以下にすることができる。例えば金属膜２ａ、３ａが１ｍｍ角の場合には、接合部５４を形成する凸部６２の幅を０．８ｍｍ以下にすることが望ましい。このように金属膜２ａ、３ａの面積を、接合部５４の接合面積よりも大きくすることで、はんだ４２は、表面電極から接合部５４の方へ台形形状となり、フィレットが形成される（図７）。尚、図７は、ダイオード３の場合を図示するが、ＩＧＢＴ２の場合についても同様である。 In addition, it is desirable to form a fillet in the solder 42 for joining the joining portion 54 to the metal film 2a and the metal film 3a formed on the surface electrode of the power semiconductor element in order to reduce thermal stress. For this reason, the bonding area of the bonding portion 54 is preferably smaller than each area of the metal film 2a and the metal film 3a. The wetting angle of the solder fillet is desirably 45 degrees or less in order to reduce thermal stress. When the height of the solder 42 is, for example, 0.2 mm to 0.8 mm, wetting of the fillet is achieved by setting the bonding area of the bonding portion 54 in the range of 20% to 80% of each area of the metal films 2a and 3a. The angle can be 45 degrees or less. For example, when the metal films 2a and 3a are 1 mm square, it is desirable that the width of the convex portion 62 forming the joint portion 54 is 0.8 mm or less. Thus, by making the area of the metal films 2a and 3a larger than the bonding area of the bonding portion 54, the solder 42 has a trapezoidal shape from the surface electrode toward the bonding portion 54, and a fillet is formed (FIG. 7). ). 7 illustrates the case of the diode 3, the same applies to the case of the IGBT 2.
　電力用半導体素子と絶縁基板１とのはんだ接合については、例えば、板状はんだを間に挟んでリフローする方法、あるいはクリームはんだを塗布しておく方法等も適用可能である。
　また、電力用半導体素子とプリント基板５０とのはんだ接合については、板状はんだを間に挟んでリフローする方法、クリームはんだを塗布しておく方法、電力用半導体素子の表面電極に予めはんだ接合しておき、後にリフローする方法、又は、プリント基板５０の近位側銅導体層５３における接合部５４に予め球状のはんだを接合しておき、後にリフローする方法も適用可能である。 As for the solder joint between the power semiconductor element and the insulating substrate 1, for example, a method of reflowing with a plate-like solder sandwiched therebetween or a method of applying cream solder can be applied.
As for the solder bonding between the power semiconductor element and the printed circuit board 50, a method of reflowing with a plate-shaped solder sandwiched therebetween, a method of applying cream solder, and soldering to the surface electrode of the power semiconductor element in advance. A method of reflowing later or a method of rejoining spherical solder in advance to the joint 54 in the proximal copper conductor layer 53 of the printed circuit board 50 and reflowing later is also applicable.
　また、本実施の形態１では、接合部５４は、上述のように櫛歯形状の切欠き６０を有するが、はんだ４２に作用する熱応力の低減を図り、はんだ４２における不具合発生を低減、防止するという観点から、櫛歯形状に限定するものではない。また、櫛歯形状を構成する凹部６１及び凸部６２は、矩形状に限定する意図ではなく、例えば半円形、楕円形、三角形等の任意の幾何学的形状が可能である。例えば図８のように、円形形状では、矩形形状の場合に比べてはんだ接合部における応力が緩和されるという効果もある。要するに接合部５４は、何らかの形状の切欠き６０を有すればよい。
　ここで接合部５４が任意形状の切欠き６０を有する場合においても、上述したように、接合部５４が電力用半導体素子の温度分布に影響を与えないように接合部５４を配置するのが良い。 In the first embodiment, the joint portion 54 has the comb-shaped notch 60 as described above. However, the thermal stress acting on the solder 42 is reduced, and the occurrence of defects in the solder 42 is reduced or prevented. From the viewpoint of doing, it is not limited to the comb shape. Further, the concave portion 61 and the convex portion 62 constituting the comb-teeth shape are not intended to be limited to a rectangular shape, and can be any geometric shape such as a semicircular shape, an elliptical shape, and a triangular shape. For example, as shown in FIG. 8, the circular shape has an effect that the stress in the solder joint is relaxed as compared with the rectangular shape. In short, the joining portion 54 only needs to have a notch 60 of some shape.
Here, even when the junction 54 has the notch 60 having an arbitrary shape, as described above, the junction 54 is preferably arranged so that the junction 54 does not affect the temperature distribution of the power semiconductor element. .
　さらにまた、本実施の形態１では、絶縁基板１の材料として絶縁シート１ａを用いた金属基板を用いたが、ＡｌＮ、アルミナ、ＳｉＮなどのセラミック材料で形成されたセラミック基板でも同様の効果が得られる。
　また本実施の形態１では、ＩＧＢＴ２及びダイオードの表面電極について、はんだが濡れない膜としてＡｌを用いたが、ＡｌＮ、アルミナ、ＳｉＮ、ガラスなどを用いても同様の効果が得られる。
　また本実施の形態１では、ケース７の材料としてＰＰＳを用いたが、より耐熱性の高いＬＣＰ（液晶ポリマー）を用いても同様の効果が得られる。
　また本実施の形態１では、ダイオード３とＩＧＢＴ２とが一対の、１ｉｎ１でのモジュール構成であるが、二対の２ｉｎ１、あるいは六対の６ｉｎ１、さらには、コンバータとブレーキとなる電力用半導体素子も同時搭載された構成でも同様の効果が得られる。
　また本実施の形態１では、アルミニウム製のワイヤボンドを用いたが、銅製ワイヤ、あるいはアルミ被服銅ワイヤ、又は金ワイヤを用いても同様の効果が得られる。
　また、ダイレクトポッティング封止樹脂については，流し込んで常温硬化させる種類のものでも同様の効果が得られる。
　また、電力用半導体素子と絶縁基板１との接続、及びプリント基板５０と電力用半導体素子との接続に、はんだを用いたが、Ａｇフィラーをエポキシ樹脂に分散させた導電性接着剤、又は、ナノ粒子を低温焼成させるＡｇナノパウダあるいはＣｕナノパウダなどを用いても同様の効果が得られる。
　また、ケース７を用いずに金型を用いてトランスファモールド封止樹脂によって封止するトランスファモールドパッケージにおいても、同様の効果が得られる。 Furthermore, in the first embodiment, the metal substrate using the insulating sheet 1a is used as the material of the insulating substrate 1, but the same effect can be obtained even with a ceramic substrate formed of a ceramic material such as AlN, alumina, SiN or the like. It is done.
In the first embodiment, Al is used for the IGBT 2 and the surface electrode of the diode as a film that does not wet the solder. However, similar effects can be obtained by using AlN, alumina, SiN, glass, or the like.
In the first embodiment, PPS is used as the material of the case 7, but the same effect can be obtained by using LCP (liquid crystal polymer) having higher heat resistance.
In the first embodiment, the diode 3 and the IGBT 2 have a pair of 1in1 module configurations, but two pairs of 2in1 or six pairs of 6in1, and further, a power semiconductor element serving as a converter and a brake is also provided. A similar effect can be obtained even in the configuration in which the devices are mounted simultaneously.
In the first embodiment, aluminum wire bonds are used. However, similar effects can be obtained by using copper wires, aluminum-coated copper wires, or gold wires.
Further, the same effect can be obtained with a direct potting sealing resin that is poured and cured at room temperature.
Moreover, although the solder was used for the connection between the power semiconductor element and the insulating substrate 1 and the connection between the printed board 50 and the power semiconductor element, a conductive adhesive in which an Ag filler is dispersed in an epoxy resin, or The same effect can be obtained by using Ag nanopowder or Cu nanopowder for firing the nanoparticles at a low temperature.
Further, the same effect can be obtained in a transfer mold package that is sealed with a transfer mold sealing resin using a mold without using the case 7.
　実施の形態２．
　図９及び図１１は、実施の形態２における電力用半導体装置２００の概略構造を示す概念図であり、図１０は、プリント基板５０の近位側銅導体層５３側を示す概念図である。上述の実施の形態１では、接合部５４は、プリント基板５０の近位側銅導体層５３に含まれ、近位側銅導体層５３とＩＧＢＴ２等の電力用半導体素子における表面電極との接合を行うものであった。これに対して実施の形態２における電力用半導体装置２００では、プリント基板５０の遠位側銅導体層５２とＩＧＢＴ２等の電力用半導体素子における表面電極との接合を行う接合部５４－２を有する。
　実施の形態２における電力用半導体装置２００は、実施の形態１における電力用半導体装置１００と、この接合部５４－２に関する構成部分のみで相違し、その他は同じ構成を有する。したがって以下では、主に接合部５４－２について説明を行い、同じ構成部分の説明は省略する。 Embodiment 2. FIG.
9 and 11 are conceptual diagrams showing a schematic structure of the power semiconductor device 200 according to the second embodiment, and FIG. 10 is a conceptual diagram showing the proximal copper conductor layer 53 side of the printed circuit board 50. In the first embodiment described above, the joint portion 54 is included in the proximal copper conductor layer 53 of the printed circuit board 50, and joins the proximal copper conductor layer 53 and the surface electrode in the power semiconductor element such as IGBT2. It was something to do. On the other hand, the power semiconductor device 200 according to the second embodiment includes the joint portion 54-2 that joins the distal copper conductor layer 52 of the printed circuit board 50 and the surface electrode of the power semiconductor element such as IGBT2. .
The power semiconductor device 200 according to the second embodiment is different from the power semiconductor device 100 according to the first embodiment only in the components related to the junction portion 54-2, and the other configurations are the same. Therefore, in the following, description will be made mainly on the joint portion 54-2, and description of the same component will be omitted.
　まず一般的内容の説明を行う。特に電力用半導体装置の小型化及び低コスト化のためには、ＩＧＢＴ２、ダイオード３等の電力用半導体素子を小型化することが望ましいが、電流密度が高くなることによる発熱を抑制する必要がある。一般的な電力用半導体装置では、電力用半導体素子のジュール熱は、電力用半導体素子を実装した絶縁基板を伝導して、放熱グリースを介して絶縁基板に接続された、具体的には実施の形態１にて説明した銅導体層１ｂに放熱グリースを介して接続された、ヒートシンク（図示せず）へ放熱される。電力用半導体素子の放熱性をより向上させるためには、電力用半導体素子の裏面側への、つまりヒートシンク側への、放熱経路だけでなく、電力用半導体素子の表面側からもプリント基板を介して放熱させるのが効果的である。 First, general contents will be explained. In particular, in order to reduce the size and cost of the power semiconductor device, it is desirable to reduce the size of the power semiconductor elements such as the IGBT 2 and the diode 3, but it is necessary to suppress heat generation due to an increase in current density. . In a general power semiconductor device, the Joule heat of the power semiconductor element is conducted through the insulating substrate on which the power semiconductor element is mounted, and is connected to the insulating substrate via heat radiation grease. The heat is radiated to a heat sink (not shown) connected to the copper conductor layer 1b described in the first embodiment via a heat radiation grease. In order to further improve the heat dissipation of the power semiconductor element, not only the heat dissipation path to the back side of the power semiconductor element, that is, to the heat sink side, but also from the surface side of the power semiconductor element via the printed circuit board. It is effective to dissipate heat.
　しかしながら、実施の形態１のように、接合部５４がプリント基板５０の近位側銅導体層５３からのみ配線されている場合には、プリント基板５０における熱抵抗の高いコア材５１が遠位側銅導体層５２側への放熱を妨げることから、放熱経路は、近位側銅導体層５３の面内のみとなる。
　そこで、本実施の形態２では、プリント基板５０の遠位側銅導体層５２に接続した接合部５４－２を用いる。以下に接合部５４－２について説明する。 However, when the joint portion 54 is wired only from the proximal copper conductor layer 53 of the printed circuit board 50 as in the first embodiment, the core material 51 having a high thermal resistance on the printed circuit board 50 is on the distal side. Since heat dissipation to the copper conductor layer 52 side is hindered, the heat dissipation path is only in the plane of the proximal copper conductor layer 53.
Therefore, in the second embodiment, the joint portion 54-2 connected to the distal copper conductor layer 52 of the printed board 50 is used. The joint 54-2 will be described below.
　プリント基板５０は、実施の形態１での説明と同様に、絶縁基板１に実装されたＩＧＢＴ２等の電力用半導体素子に対向して平行又は略平行に配置され、コア材５１と、遠位側銅導体層５２及び近位側銅導体層５３とを有する。ここで、遠位側銅導体層５２は、ＩＧＢＴ２等の電力用半導体素子から遠方に位置する遠位側導体層に相当し、近位側銅導体層５３は、電力用半導体素子に近接して位置する近位側導体層に相当する。 Similar to the description in the first embodiment, the printed circuit board 50 is disposed in parallel or substantially in parallel to the power semiconductor element such as the IGBT 2 mounted on the insulating substrate 1, and includes the core material 51 and the distal side. A copper conductor layer 52 and a proximal copper conductor layer 53 are provided. Here, the distal copper conductor layer 52 corresponds to a distal conductor layer located far from the power semiconductor element such as IGBT2, and the proximal copper conductor layer 53 is adjacent to the power semiconductor element. It corresponds to the proximal conductor layer located.
　接合部５４－２は、プリント基板５０の遠位側銅導体層５２からコア材５１を貫通して裏面側に配線されプリント基板５０の近位側銅導体層５３と接続することなく延在し、ＩＧＢＴ２等の電力用半導体素子の表面電極に、はんだで接合される部材である。また、接合部５４－２は、複数個設けられる。
　図１２は、接合部５４－２の平面図を示すと共に、接合部５４－２と、例えばＩＧＢＴ２の電極とのはんだ４２による接合状態を示している。尚、図１２は、ＩＧＢＴ２の場合を図示するが、ダイオード３の電極の場合も同様である。 The joint 54-2 extends from the distal copper conductor layer 52 of the printed circuit board 50 through the core material 51 to the back surface side and extends without being connected to the proximal copper conductor layer 53 of the printed circuit board 50. , A member that is joined to the surface electrode of a power semiconductor element such as IGBT2 by soldering. In addition, a plurality of joint portions 54-2 are provided.
FIG. 12 shows a plan view of the joint portion 54-2 and shows a joining state of the joint portion 54-2 and, for example, an electrode of the IGBT 2 by the solder 42. 12 illustrates the case of the IGBT 2, the same applies to the electrode of the diode 3.
　このような接合部５４－２は、コア材５１を穴加工した後、該穴に銅材を圧入することで製造できる。また、接合部５４－２と電力用半導体素子の表面電極との接合は、本実施形態では例えば、接合部５４－２に予め球状のはんだを接合しておき、後にリフローする方法で接合する。 Such a joint 54-2 can be manufactured by drilling the core material 51 and then press-fitting a copper material into the hole. Further, in the present embodiment, for example, a spherical solder is bonded to the bonding portion 54-2 in advance, and the bonding is performed by a reflow method later.
　このように接合部５４－２を遠位側銅導体層５２から配線することで、プリント基板５０のコア材５１による熱抵抗が低減し、ＩＧＢＴ２等の電力用半導体素子からの熱は、接合部５４－２を介してプリント基板５０の遠位側銅導体層５２へも放散させることができる。よって、ＩＧＢＴ２等の電力用半導体素子の放熱効率は、実施の形態１の場合に比べて向上させることができる。よって、電力用半導体素子の発熱を低減できるため、電力用半導体素子の小型化、低コスト化により電力用半導体装置２００の小型化、低コスト化を実現することができる。 By wiring the joint 54-2 from the distal copper conductor layer 52 in this manner, the thermal resistance due to the core material 51 of the printed circuit board 50 is reduced, and the heat from the power semiconductor element such as the IGBT 2 is It can also be diffused to the distal copper conductor layer 52 of the printed circuit board 50 via 54-2. Therefore, the heat radiation efficiency of the power semiconductor element such as IGBT 2 can be improved as compared with the case of the first embodiment. Accordingly, since heat generation of the power semiconductor element can be reduced, the power semiconductor device 200 can be reduced in size and cost by reducing the size and cost of the power semiconductor element.
　また、接合部５４－２は、複数個存在して細分化されており、接合部５４－２の面積は、図１３に示すように、実施の形態１における接合部５４の場合と同様に、電力用半導体素子の表面電極に形成された金属膜２ａ及び金属膜３ａの面積の例えば２０％から８０％の範囲にすることができる。よって、温度サイクルにより、絶縁基板１とプリント基板５０との熱膨張差に起因して発生する、絶縁基板１とプリント基板５０との間に存在するはんだ４２に作用する熱応力は、従来に比べて小さくなる。したがって、特に、はんだ４２における破損等の不具合の発生を低減さらには防止することができる。
　尚、図１３は、ダイオード３の場合を図示するが、ＩＧＢＴ２の場合についても同様である。 Further, a plurality of joints 54-2 exist and are subdivided, and the area of the joint 54-2 is the same as that of the joint 54 in the first embodiment as shown in FIG. For example, the area of the metal film 2a and the metal film 3a formed on the surface electrode of the power semiconductor element can be in the range of 20% to 80%. Therefore, the thermal stress acting on the solder 42 existing between the insulating substrate 1 and the printed circuit board 50 caused by the difference in thermal expansion between the insulating substrate 1 and the printed circuit board 50 due to the temperature cycle is higher than that of the conventional case. Become smaller. Therefore, in particular, the occurrence of defects such as breakage in the solder 42 can be reduced and prevented.
FIG. 13 illustrates the case of the diode 3, but the same applies to the case of the IGBT 2.
　また、実施の形態１において説明した、絶縁基板１、ケース７、ワイヤボンド、及びはんだの各材料に関する変形例、電力用半導体素子に関する変形例、並びに、封止樹脂に関する変形例については、本実施の形態１の電力用半導体装置２００にも同様に適用することができる。 In addition, the modified example related to the insulating substrate 1, the case 7, the wire bond, and the solder, the modified example related to the power semiconductor element, and the modified example related to the sealing resin described in the first embodiment will be described in the present embodiment. The present invention can be similarly applied to the power semiconductor device 200 of the first embodiment.
　実施の形態３．
　図１４から図１６は、実施の形態３における電力用半導体装置３００の概略構造を示す。また、図１７から図１９には、実施の形態３における電力用半導体装置４００の概略構造を示す。
　ここで電力用半導体装置３００は、実施の形態１における電力用半導体装置１００の変形例に相当し、電力用半導体装置４００は、実施の形態２における電力用半導体装置２００の変形例に相当する。 Embodiment 3 FIG.
14 to 16 show a schematic structure of the power semiconductor device 300 according to the third embodiment. 17 to 19 show a schematic structure of the power semiconductor device 400 according to the third embodiment.
Here, power semiconductor device 300 corresponds to a modification of power semiconductor device 100 in the first embodiment, and power semiconductor device 400 corresponds to a modification of power semiconductor device 200 in the second embodiment.
　実施の形態３における電力用半導体装置３００、４００は、それぞれ、電力用半導体装置１００、２００におけるプリント基板５０に、プリント基板５０を貫通するスリット５５を設けたものである。電力用半導体装置３００、４００は、電力用半導体装置１００、２００と、スリット５５に関する構成部分のみで相違し、その他はそれぞれ同じ構成を有する。したがって以下では、主にスリット５５について説明を行い、同じ構成部分の説明は省略する。 In the power semiconductor devices 300 and 400 in the third embodiment, slits 55 penetrating the printed circuit board 50 are provided in the printed circuit boards 50 in the power semiconductor devices 100 and 200, respectively. The power semiconductor devices 300 and 400 are different from the power semiconductor devices 100 and 200 only in the components related to the slit 55, and the rest have the same configuration. Therefore, in the following, the slit 55 will be mainly described, and the description of the same components will be omitted.
　互いに対向して配置されている絶縁基板１とプリント基板５０とは、互いに電気的に絶縁されている必要があるため、絶縁基板１とプリント基板５０との間の隙間には封止樹脂６を充填する必要がある。また、ＩＧＢＴ２及びダイオード３において、それぞれの電力用半導体素子の表裏の沿面絶縁距離を確保するためには、空間に封止樹脂６が充填されている必要がある。 Since the insulating substrate 1 and the printed circuit board 50 that are disposed to face each other need to be electrically insulated from each other, the sealing resin 6 is placed in the gap between the insulating substrate 1 and the printed circuit board 50. Need to be filled. Further, in the IGBT 2 and the diode 3, it is necessary to fill the space with the sealing resin 6 in order to ensure the creeping insulation distance between the front and back surfaces of each power semiconductor element.
　しかしながら、絶縁基板１とプリント基板５０との間隙は約０．３ｍｍから０．９ｍｍであるため、封止樹脂６が充填されにくく、未充填領域が発生する可能性がある。特に、例えば実施の形態１における電力用半導体装置１００では、櫛歯形状を有する接合部５４を備えている。ＩＧＢＴ２等の電力用半導体素子の表面電極とプリント基板５０との間における、櫛歯形状を有する接合部５４では、空気を巻き込むことで未充填領域が発生し易い。よって、例えば封止樹脂６の注入速度を遅くするなどの対策が必要となり、生産性が低下する懸念がある。この対策として、封止樹脂６の流入距離を短くすることが効果的である。 However, since the gap between the insulating substrate 1 and the printed circuit board 50 is about 0.3 mm to 0.9 mm, it is difficult to fill the sealing resin 6 and an unfilled region may occur. In particular, for example, the power semiconductor device 100 according to the first embodiment includes the joint 54 having a comb-teeth shape. In the joint portion 54 having a comb-teeth shape between the surface electrode of the power semiconductor element such as the IGBT 2 and the printed circuit board 50, an unfilled region is easily generated by entraining air. Therefore, for example, measures such as slowing the injection rate of the sealing resin 6 are required, and there is a concern that productivity may be reduced. As a countermeasure, it is effective to shorten the inflow distance of the sealing resin 6.
　そこで、電力用半導体装置３００では、図１４から図１６に示すように、封止樹脂６が最も注入されにくい電力用半導体素子の中心点２１に対応して、プリント基板５０のコア材５１及び遠位側銅導体層５２にスリット５５を設けた。このスリット５５は、コア材５１と遠位側銅導体層５２をその厚み方向に貫通する溝であり、上述のように接合部５４に対応して位置する。即ち、実施の形態１で説明したように、接合部５４における切欠き６０は、電力用半導体素子の中心点２１に対応して位置させていることから、スリット５５は、切欠き６０に対応して位置することになる。
　尚、図１６は、図５に対応した図であり、接合部５４に対する、プリント基板５０におけるスリット５５の配置位置の例を明示した図である。 Therefore, in the power semiconductor device 300, as shown in FIGS. 14 to 16, the core material 51 of the printed circuit board 50 and the distant portion of the printed circuit board 50 correspond to the center point 21 of the power semiconductor element to which the sealing resin 6 is most hardly injected. A slit 55 was provided in the distal copper conductor layer 52. The slit 55 is a groove that penetrates the core material 51 and the distal copper conductor layer 52 in the thickness direction, and is located corresponding to the joint 54 as described above. That is, as described in the first embodiment, the notch 60 in the joint portion 54 is positioned corresponding to the center point 21 of the power semiconductor element, so that the slit 55 corresponds to the notch 60. Will be located.
FIG. 16 is a diagram corresponding to FIG. 5, and is a diagram clearly showing an example of an arrangement position of the slit 55 in the printed circuit board 50 with respect to the joint portion 54.
　電力用半導体装置２００に対応した電力用半導体装置４００（図１７）においても、電力用半導体装置３００と同様に、図１９に示すように、封止樹脂６が最も注入されにくい各接合部５４－２同士の隙間に対応して、プリント基板５０のコア材５１に複数のスリット５５を設けた。尚、図１９は、図１２に対応した図であり、接合部５４－２に対する、プリント基板５０におけるスリット５５の配置位置を明示した図である。 Also in the power semiconductor device 400 (FIG. 17) corresponding to the power semiconductor device 200, as in the power semiconductor device 300, as shown in FIG. A plurality of slits 55 are provided in the core material 51 of the printed circuit board 50 in correspondence with the gap between the two. FIG. 19 is a view corresponding to FIG. 12 and clearly shows the arrangement position of the slit 55 in the printed circuit board 50 with respect to the joint portion 54-2.
　また図２０には、スリット５５を有する実施の形態３における電力用半導体装置の変形例としての電力用半導体装置５００を示す。電力用半導体装置５００は、近位側銅導体層５３における切欠き６０を有しない構成に相当し、封止樹脂６が最も注入されにくい電力用半導体素子の中心点２１に対応して複数のスリット５５を設けた構成を有する。電力用半導体装置５００においてもスリット５５は、ＩＧＢＴ２等における表面電極と近位側銅導体層５３とを接合する接合部５４に存在する。 FIG. 20 shows a power semiconductor device 500 as a modification of the power semiconductor device according to the third embodiment having the slit 55. The power semiconductor device 500 corresponds to a configuration that does not have the notch 60 in the proximal copper conductor layer 53, and has a plurality of slits corresponding to the center point 21 of the power semiconductor element in which the sealing resin 6 is most difficult to be injected. 55 is provided. Also in the power semiconductor device 500, the slit 55 exists in the joint portion 54 that joins the surface electrode and the proximal copper conductor layer 53 in the IGBT 2 or the like.
　それぞれの電力用半導体装置３００、４００、５００においてスリット５５を設けたことで、封止樹脂６は、スリット５５を通り、絶縁基板１とプリント基板５０との間へ、特に接合部５４、５４－２において生じる可能性がある封止樹脂６の未充填領域へ、充填可能となる。よって、未充填領域の発生を解消することが可能となる。したがって、樹脂注入速度をさらに上げることが可能となる。その結果、生産性の低下を避けることができ生産性向上につなげることが可能である。 By providing the slit 55 in each of the power semiconductor devices 300, 400, and 500, the sealing resin 6 passes through the slit 55 and between the insulating substrate 1 and the printed circuit board 50, in particular, the bonding portions 54, 54-. 2 can be filled in an unfilled region of the sealing resin 6 that may occur in step 2. Therefore, it is possible to eliminate the occurrence of the unfilled area. Therefore, the resin injection speed can be further increased. As a result, it is possible to avoid a decrease in productivity and improve productivity.
　また、スリット５５を設けたことで、上述の効果に加えて、ＩＧＢＴ２及びダイオード３の表面電極に接合されている接合部５４、５４－２におけるはんだ４２のフィレットの状態などを目視等で検査することが容易になる。よって、接合状態の検査工程を短時間で容易に行うことができるという効果も生じる。 Further, by providing the slit 55, in addition to the above-described effects, the state of the fillet of the solder 42 at the joints 54 and 54-2 joined to the surface electrodes of the IGBT 2 and the diode 3 is visually inspected. It becomes easy. Therefore, there is also an effect that the bonding state inspection process can be easily performed in a short time.
　本実施の形態３の電力用半導体装置３００、４００においても、接合部５４、５４－２を有することから、実施の形態１、２にて説明した、温度サイクルによるはんだ４２に作用する熱応力は、従来に比べて小さくなる。したがって、特に、はんだ４２における破損等の不具合の発生を低減さらには防止することができる。 Since the power semiconductor devices 300 and 400 of the third embodiment also have the joint portions 54 and 54-2, the thermal stress acting on the solder 42 due to the temperature cycle described in the first and second embodiments is as follows. , Smaller than conventional. Therefore, in particular, the occurrence of defects such as breakage in the solder 42 can be reduced and prevented.
　また、電力用半導体装置５００においても、切欠き６０は設けていないものの、接合部５４はスリット５５を有することから、スリット５５が切欠き６０と同等の作用を行うことができる。よって、電力用半導体装置５００においても上述の不具合の発生の低減さらには防止を図ることができる。 Also, in the power semiconductor device 500, although the notch 60 is not provided, the joint portion 54 has the slit 55, so that the slit 55 can perform the same operation as the notch 60. Therefore, also in the power semiconductor device 500, it is possible to reduce and further prevent the occurrence of the above-described problems.
　尚、実施の形態１、２において説明した、絶縁基板１、ケース７、ワイヤボンド、及びはんだの各材料に関する変形例、電力用半導体素子に関する変形例、並びに、封止樹脂に関する変形例については、本実施の形態３の電力用半導体装置３００、４００、５００にも同様に適用することができる。 In addition, about the modification regarding each material of the insulated substrate 1, case 7, wire bond, and solder demonstrated in Embodiment 1, 2, about the modification regarding a power semiconductor element, and the modification regarding a sealing resin, The present invention can be similarly applied to the power semiconductor devices 300, 400, and 500 of the third embodiment.
　実施の形態４．
　図２１及び図２２は、それぞれ実施の形態４における電力用半導体装置６００の概略構造を示す概念図である。ここで電力用半導体装置６００は、実施の形態１における電力用半導体装置１００の変形例に相当する。
　実施の形態４における電力用半導体装置６００は、電力用半導体装置１００におけるプリント基板５０に、プリント基板５０のコア材５１及び遠位側銅導体層５２を貫通する貫通孔５８を設けたものである。電力用半導体装置６００は、電力用半導体装置１００に対して、貫通孔５８に関する構成部分のみで相違し、その他はそれぞれ同じ構成を有する。したがって以下では、主に貫通孔５８について説明を行い、同じ構成部分の説明は省略する。 Embodiment 4 FIG.
21 and 22 are conceptual diagrams each showing a schematic structure of power semiconductor device 600 according to the fourth embodiment. Here, power semiconductor device 600 corresponds to a modification of power semiconductor device 100 in the first embodiment.
In the power semiconductor device 600 according to the fourth embodiment, the printed circuit board 50 in the power semiconductor device 100 is provided with a through hole 58 that penetrates the core material 51 and the distal copper conductor layer 52 of the printed circuit board 50. . The power semiconductor device 600 is different from the power semiconductor device 100 only in the components related to the through holes 58, and the other components are the same. Therefore, in the following, the through hole 58 will be mainly described, and the description of the same components will be omitted.
　プリント基板５０のコア材５１の両面に形成された遠位側銅導体層５２と近位側銅導体層５３とは、互いは非対称に配置されているため、熱ひずみによる反りあるいはうねりが発生しやすい。そのため、接合部５４に接合されたはんだ４２には、大きな熱応力が発生しやすい。
　そこで、電力用半導体装置６００では、図２１及び図２２に示すように、はんだを接合する接合部５４全体に対応して、プリント基板５０のコア材５１及び遠位側銅導体層５２に貫通孔５８を設けた。この貫通孔５８は、コア材５１及び遠位側銅導体層５２をその厚み方向に貫通する溝であり、上述のように接合部５４全体に対応して位置する。
　このように電力用半導体装置６００において貫通孔５８を設けたことで、接合部５４の周辺における、うねりを抑制することができ、はんだ４２に発生する熱応力を低減することができる。 Since the distal-side copper conductor layer 52 and the proximal-side copper conductor layer 53 formed on both surfaces of the core material 51 of the printed circuit board 50 are arranged asymmetrically with each other, warpage or undulation due to thermal strain occurs. Cheap. Therefore, a large thermal stress is likely to occur in the solder 42 joined to the joint portion 54.
Therefore, in the power semiconductor device 600, as shown in FIGS. 21 and 22, through-holes are formed in the core material 51 and the distal copper conductor layer 52 of the printed circuit board 50 corresponding to the entire bonding portion 54 to which the solder is bonded. 58 was provided. The through hole 58 is a groove that penetrates the core material 51 and the distal copper conductor layer 52 in the thickness direction, and is located corresponding to the entire joint portion 54 as described above.
By providing the through hole 58 in the power semiconductor device 600 as described above, it is possible to suppress the undulation around the joint portion 54 and to reduce the thermal stress generated in the solder 42.
　また、貫通孔５８を設けたことで、上述の効果に加えて、ＩＧＢＴ２及びダイオード３の表面電極に接合されている接合部５４におけるはんだ４２のフィレットの状態などを目視等で検査することが、電力用半導体装置３００においてスリット５５を設ける場合に比べて、より容易になる。よって、接合状態の検査工程を短時間で容易に行うことができるという効果も生じる。 Further, by providing the through hole 58, in addition to the above-described effects, it is possible to visually inspect the fillet state of the solder 42 in the joint portion 54 joined to the surface electrode of the IGBT 2 and the diode 3, Compared with the case where the slit 55 is provided in the power semiconductor device 300, it becomes easier. Therefore, there is also an effect that the bonding state inspection process can be easily performed in a short time.
　また、貫通孔５８を設けたことで、封止樹脂６は、貫通孔５８を通り、絶縁基板１とプリント基板５０との間へ、特に接合部５４において生じる可能性がある封止樹脂６の未充填領域への充填性が、電力用半導体装置３００においてスリット５５を設ける場合よりも向上する。よって、未充填領域の発生を解消することも可能となる。
　したがって、実施の形態３に比べて樹脂注入速度をさらに向上させることが可能となる。その結果、生産性の低下を避けることができ、生産性向上につなげることが可能である。 Further, since the through-hole 58 is provided, the sealing resin 6 passes through the through-hole 58 and enters between the insulating substrate 1 and the printed circuit board 50, particularly in the bonding portion 54. The filling property in the unfilled region is improved as compared with the case where the slit 55 is provided in the power semiconductor device 300. Therefore, it is possible to eliminate the occurrence of the unfilled area.
Therefore, the resin injection speed can be further improved as compared with the third embodiment. As a result, it is possible to avoid a decrease in productivity and to improve productivity.
　尚、実施の形態１において説明した、絶縁基板１、ケース７、ワイヤボンド、及びはんだの各材料に関する変形例、電力用半導体素子に関する変形例、並びに、封止樹脂に関する変形例については、本実施の形態４の電力用半導体装置６００にも同様に適用することができる。 In addition, about the modification regarding each material of the insulating substrate 1, the case 7, the wire bond, and the solder described in the first embodiment, the modification regarding the power semiconductor element, and the modification regarding the sealing resin, The present invention can be similarly applied to the power semiconductor device 600 of the fourth embodiment.
　また、上述した各実施の形態を組み合わせた構成を採ることも可能であり、また、異なる実施の形態に示される構成部分同士を組み合わせることも可能である。 Further, it is possible to adopt a configuration in which the above-described embodiments are combined, and it is also possible to combine components shown in different embodiments.
　本発明は、添付図面を参照しながら好ましい実施形態に関連して充分に記載されているが、この技術の熟練した人々にとっては種々の変形あるいは修正は明白である。そのような変形あるいは修正は、添付した請求の範囲による本発明の範囲から外れない限りにおいて、その中に含まれると理解されるべきである。
　又、２０１５年１１月２５日に出願された、日本国特許出願Ｎｏ．特願２０１５－２２９８５５号の明細書、図面、特許請求の範囲、及び要約書の開示内容の全ては、参考として本明細書中に編入されるものである。 Although the present invention has been fully described in connection with preferred embodiments with reference to the accompanying drawings, various changes and modifications will be apparent to those skilled in the art. Such changes and modifications are to be understood as being included therein, so long as they do not depart from the scope of the present invention according to the appended claims.
In addition, Japanese Patent Application No. The entire contents of the specification, drawings, claims, and abstract of Japanese Patent Application No. 2015-229855 are incorporated herein by reference.
　１　絶縁基板、２　ＩＧＢＴ、３　ダイオード、２１　中心点、
　４１、４２　はんだ、５０　プリント基板、５２　遠位側銅導体層、
　５３　近位側銅導体層、５４、５４－２　接合部、５５　スリット、５８　貫通孔、
　１００、２００、３００、４００、５００、６００　電力用半導体装置。 1 insulating substrate, 2 IGBT, 3 diode, 21 center point,
41, 42 solder, 50 printed circuit board, 52 distal copper conductor layer,
53 Proximal copper conductor layer, 54, 54-2 joint, 55 slit, 58 through hole,
100, 200, 300, 400, 500, 600 Power semiconductor device.

Claims (9)

  1. 　電力用半導体素子と、導体層を有するプリント基板とを備え、上記電力用半導体素子の電極と上記プリント基板の導体層とをはんだで接合した状態の電力用半導体装置において、
    　上記電力用半導体素子は、表面電極に、はんだを接合するための金属膜と、はんだと接合しない膜とを有し、
    　上記金属膜は、上記電力用半導体素子に複数配置されており、
    上記はんだが接合されない膜は、上記電力用半導体素子の中央に配置されており、
    　上記導体層の一部を構成し上記導体層と一体に形成された状態の接合部をさらに備え、
    　上記接合部は切欠きを有し、該切欠きは、上記半導体素子の金属膜に対応するように配置されている、
    ことを特徴とする電力用半導体装置。     In a power semiconductor device comprising a power semiconductor element and a printed circuit board having a conductor layer, wherein the electrode of the power semiconductor element and the conductor layer of the printed circuit board are joined by solder,
    The power semiconductor element has a metal film for bonding solder and a film not bonded to solder on the surface electrode,
    A plurality of the metal films are disposed on the power semiconductor element,
    The film to which the solder is not bonded is disposed at the center of the power semiconductor element,
    A part of the conductor layer is formed and further provided with a joint portion formed integrally with the conductor layer,
    The joint has a notch, and the notch is disposed so as to correspond to the metal film of the semiconductor element.
    A power semiconductor device.
  2. 　上記切欠きは櫛歯形状である、請求項１に記載の電力用半導体装置。 The power semiconductor device according to claim 1, wherein the notch has a comb-teeth shape.
  3. 　複数の上記金属膜はそれぞれ同一の面積であり、電力用半導体素子の表面に等間隔に位置しており、上記櫛歯形状の切欠きの凸部は、上記金属膜に対応して等間隔に位置する、請求項１又は２に記載の電力用半導体装置。 The plurality of metal films have the same area and are located at equal intervals on the surface of the power semiconductor element, and the convex portions of the comb-shaped notches are equally spaced corresponding to the metal film. The power semiconductor device according to claim 1, wherein the power semiconductor device is located.
  4. 　上記櫛歯形状の切欠きの凸部は、上記金属膜の面積よりも小さい、請求項１から３のいずれか１項に記載の電力用半導体装置。 The power semiconductor device according to any one of claims 1 to 3, wherein the convex portion of the comb-shaped notch is smaller than an area of the metal film.
  5. 　上記金属膜の形状は、矩形もしくは円形である、請求項１から４のいずれか１項に記載の電力用半導体装置。 5. The power semiconductor device according to claim 1, wherein the metal film has a rectangular or circular shape.
  6. 　上記櫛歯形状における凸部及び凹部の形状は、矩形もしくは円形である、請求項１から４のいずれか１項に記載の電力用半導体装置。 5. The power semiconductor device according to claim 1, wherein the shape of the convex part and the concave part in the comb-teeth shape is a rectangle or a circle.
  7. 　電力用半導体素子と、導体層を有するプリント基板とを備え、上記電力用半導体素子の電極と上記プリント基板の導体層とをはんだで接合した電力用半導体装置において、
    　上記プリント基板は、上記電力用半導体素子に対向して位置し、その厚み方向における両面にそれぞれ導体層を有し、
    　それぞれの上記導体層のうち、上記電力用半導体素子から遠方に位置する遠位側導体層と接合し、かつ上記プリント基板を貫通して、上記電力用半導体素子に近接して位置する近位側導体層に接続することなく延在し、上記電力用半導体素子の電極にはんだで接合した状態にある複数の接合部をさらに備えた、
    ことを特徴とする電力用半導体装置。     In a power semiconductor device comprising a power semiconductor element and a printed circuit board having a conductor layer, wherein the electrode of the power semiconductor element and the conductor layer of the printed circuit board are joined by solder,
    The printed circuit board is positioned to face the power semiconductor element, and has a conductor layer on each surface in the thickness direction,
    Of each of the conductor layers, a proximal side that is bonded to a distal conductor layer located far from the power semiconductor element, penetrates the printed circuit board, and is located close to the power semiconductor element. A plurality of joints extending without being connected to the conductor layer and being joined to the electrodes of the power semiconductor element by solder;
    A power semiconductor device.
  8. 　上記プリント基板は、当該プリント基板を貫通するスリットを有し、このスリットは、上記接合部に対応して位置する、請求項７に記載の電力用半導体装置。 The power semiconductor device according to claim 7, wherein the printed circuit board has a slit penetrating the printed circuit board, and the slit is positioned corresponding to the joint portion.
  9. 　上記プリント基板は、当該プリント基板を貫通する貫通孔を有し、この貫通孔は、上記接合部の全面に対応して位置する、請求項７に記載の電力用半導体装置。 The power semiconductor device according to claim 7, wherein the printed circuit board has a through hole penetrating the printed circuit board, and the through hole is positioned corresponding to the entire surface of the joint portion.
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