Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/60—Wet etching
  • H10P50/64—Wet etching of semiconductor materials
  • H10P50/642—Chemical etching
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/34—Deposited materials, e.g. layers
  • H10P14/3438—Doping during depositing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
  • H10P32/20—Diffusion for doping of insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
  • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
  • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
  • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
  • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
  • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
  • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
  • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
  • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
  • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Definitions

• the present invention relates to the field of semiconductor manufacturing and semiconductor devices, and more particularly, to a method for bottom-up deposition of a film in a recessed feature.
• the processing method includes a) providing a substrate containing a recessed feature having a bottom and a sidewall, b) depositing a film on the bottom and on the sidewall of the recessed feature, c) treating the film with a gas phase plasma to activate the film on the sidewall for faster etching than the film on the bottom of the recessed feature, and d) selectively etching the treated film from the sidewall.
• the method further includes repeating steps b) - d) at least once until the film at the bottom of the recessed feature has a desired thickness.
• the recessed feature may be filled with the film.
• the processing method includes a) providing a substrate containing a recessed feature having a bottom and a sidewall, b) depositing a film on the bottom and on the sidewall of the recessed feature, and c) covering the film at the bottom of the recessed feature with a mask layer.
• FIGs. 2A-2F schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention
• FIGs. 4A-4E schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention
• FIG. 5 is process flow diagram for processing a substrate according to an embodiment of the invention.
• FIGs. 6A-6H schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
• FIG. 1 is a process flow diagram for processing a substrate according to an embodiment of the invention
• FIGs. 2A-2F schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
• the process flow 1 includes, in 100, providing a substrate 200 containing a film 202 thereon having a recessed feature 204 with a bottom 203 and a sidewall 201. This is schematically shown in FIG. 2A.
• the recessed feature 204 can, for example, have a width 207 that is less than 200nm, less than lOOnm, less than 50nm, less than 25nm, less than 20nm, or less than lOnm. In other examples, the recessed feature 204 can have a width 207 that is between 5nm and lOnm, between lOnm and 20nm, between 20nm and 50nm, between 50nm and lOOnm.
• the width 207 can also be referred to as a critical dimension (CD).
• the recessed feature 204 can, for example, have a depth of 25nm, 50nm, lOOnm, 200nm, or greater than 200nm.
• the substrate 200 and the film 202, and therefore the bottom 203 and the sidewall 201 may contain different materials.
• the different materials may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal-containing material.
• the dielectric material may be selected from the group consisting of S1O2, SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.
• the high-k material may be selected from the group consisting of Hf02 ; r02, T1O2, and AI2O3.
• the metal and the metal- containing material may be selected from the group consisting of Cu, Al, Ta, Ru, TaN, TaC, and TaCN.
• the recessed feature 204 may be formed using well-known lithography and etching processes. Although not shown in FIG. 2A, a patterned mask layer may be present on the field area 211 and defining the opening of the recessed feature 204.
• the process flow 1 further includes, in 102, depositing a film 208 on the bottom 203 and on the sidewall 201.
• the film 208 may be deposited by atomic layer deposition (ALD).
• ALD atomic layer deposition
• the film 208 may be selected from the group consisting of a dielectric material, a metal, and a metal-containing material.
• the material of the film 208 may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal- containing material.
• the dielectric material may selected from the group consisting of Si0 2 , SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.
• the high-k material may be selected from the group consisting of HfC , Zr0 2 , Ti0 2 , and AI2O3.
• the film 208 may be selected from the group consisting of a metal oxide film, a metal nitride film, a metal oxynitride film, a metal silicate film, and a combination thereof.
• the metal and the metal-containing material may be selected from the group consisting of Cu, Al, Ta, Ru, TaN, TaC, and TaCN.
• the film 208 includes a metal oxide film that is deposited using ALD by a) pulsing a metal-containing precursor into a process chamber containing the substrate, b) purging the process chamber with an inert gas, c) pulsing an oxygen-containing precursor into the process chamber, d) purging the process chamber with an inert gas, and e) repeating a) - d) at least once.
• the etching removes the film 208 from the sidewall 201 but the mask layer 206 protects the film 208 under the mask layer 206 from etching.
• the etch gases and the etch conditions may be selected for providing efficient removal of the film 208 that is not protected by the mask layer 206.
• the process flow 1 further includes, in 108, removing the mask layer 206 to expose the film 208 on the bottom 203 of the recessed feature 204.
• the process conditions may be selected for providing efficient removal of the mask layer 206. According to one
• step 106 may be repeated following the step 108 to clean or thin the film 208.
• FIG. 3 is process flow diagram for processing a substrate according to an embodiment of the invention
• FIGs. 4A-4D schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
• the high-k material may be selected from the group consisting of Hf0 2 , Zrf3 ⁇ 4, Ti0 2 , and AI2O3.
• the metal and the metal-containing material may be selected from the group consisting of Cu, Al, Ta, Ru, TaN, TaC, and TaCN.
• the substrate 400 and the film 402, and therefore the bottom 403 and the sidewall 401 may contain different materials.
• the different materials may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal-containing material.
• the dielectric material may be selected from the group consisting of S1O2, SiON, SiN, a high-k material, a low-k material, or an ultra-low-k material.
• the high-k material may be selected from the group consisting of HfCh, ZrC>2, Ti0 2 , and AI2O3.
• the metal and the metal-containing material may be selected from the group consisting of Cu, Al, Ta, Ru, TaN, TaC, and TaCN.
• the recessed feature 404 may be formed using well-known lithography and etching processes. Although not shown in FIG. 4A, a patterned mask layer may be present on the field area 411 and defining the opening of the recessed feature 404.
• the process flow 3 further includes, in 302, depositing a film 408 on the bottom 403 and on the sidewall 401. This is schematically shown in FIG. 4B.
• the film 408 may be deposited by ALD.
• the film 408 may be selected from the group consisting of a dielectric material, a metal, and a metal-containing material.
• the material of the film 408 may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal- containing material.
• the dielectric material may selected from the group consisting of Si0 2 , SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.
• the high-k material may be selected from the group consisting of HfC , Zr(3 ⁇ 4, Ti0 2 , and AI2O3.
• the film 408 may be selected from the group consisting of a metal oxide film, a metal nitride film, a metal oxynitride film, a metal silicate film, and a combination thereof.
• the metal and the metal-containing material may be selected from the group consisting of Cu, Al, Ta, Ru, TaN, TaC, and TaCN.
• the film 408 includes a metal oxide film that is deposited using ALD by a) pulsing a metal-containing precursor into a process chamber containing the substrate, b) purging the process chamber with an inert gas, c) pulsing an oxygen-containing precursor into the process chamber, d) purging the process chamber with an inert gas, and e) repeating a) - d) at least once.
• a thickness of the film 408 can be lOnm or less, 5nm or less, 4nm or less, between lnm and 2nm, between 2nm and 4nm, between 4nm and 6nm, between 6nm and 8nm, or between 2nm and 6nm.
• Plasma activation of the film 408 can include disrupting the crystalline structure of the film 408 by the plasma species, thereby enabling faster etching of the treated film 413 in a subsequent selective etching process.
• the gas phase plasma can contain or consist of Ar gas.
• the process flow 3 further includes, in 306, selectively etching the treated film 413 from the sidewall 401 and the field area 411. As depicted in FIG. 4D, the etching selectively removes the treated film 413 from the sidewall 401 and the field area 411 due to the higher etch rate of the treated film 413 on the sidewall 401 and the field area 411 than the film 408 on the bottom 403.
• steps 302-306 may be repeated until the film 408 has a desired thickness.
• steps 302-308 may be repeated until the recessed feature 404is filled with the film 412.
• FIG. 5 is process flow diagram for processing a substrate according to an embodiment of the invention
• FIGs. 6A-6H schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
• the process flow 5 includes, in 500, providing a substrate 600 containing a film 602 thereon having a recessed feature 604 with a bottom 603 and a sidewall 601.
• the substrate 600 and the film 602, and therefore the bottom 603 and the sidewall 601 may contain the same material.
• the material of the bottom 603 and the sidewall 601 may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal-containing material.
• the dielectric material may selected from the group consisting of S1O2, SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.
• the high-k material may be selected from the group consisting of Hf02, Zr0 2 , Ti0 2 , and AI2O3.
• the metal and the metal-containing material may be selected from the group consisting of Cu, Al, Ta, Ru, TaN, TaC, and TaCN.
• the substrate 600 and the film 602, and therefore the bottom 603 and the sidewall 601 may contain different materials.
• the different materials may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal-containing material.
• the dielectric material may be selected from the group consisting of S1O2, SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.
• the high-k material may be selected from the group consisting of HfC , ZrC , T1O2, and AI2O3.
• the metal and the metal- containing material may be selected from the group consisting of Cu, Al, Ta, Ru, TaN, TaC, and TaCN.
• the recessed feature 604 may be formed using well-known lithography and etching processes. Although not shown in FIG. 6A, a patterned mask layer may be present on the field area 211 and defining the opening of the recessed feature 604.
• the material of the film 608 may be selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal- containing material.
• the dielectric material may selected from the group consisting of Si0 2 , SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.
• the high-k material may be selected from the group consisting of HfC , Zr0 2 , Ti0 2 , and AI2O3.
• the film 608 may be selected from the group consisting of a metal oxide film, a metal nitride film, a metal oxynitride film, a metal silicate film, and a combination thereof.
• the metal and the metal-containing material may be selected from the group consisting of Cu, Al. Ta, Ru, TaN, TaC, and TaCN.
• the film 608 includes a metal oxide film that is deposited using ALD by a) pulsing a metal-containing precursor into a process chamber containing the substrate, b) purging the process chamber with an inert gas, c) pulsing an oxygen-containing precursor into the process chamber, d) purging the process chamber with an inert gas, and e) repeating a) - d) at least once.
• a thickness of the film 608 can be lOnm or less, 5nm or less, 4nm or less, between lnm and 2nm, between 2nm and 4nm, between 4nm and 6nm, between 6nm and 8nm, or between 2nm and 6nm.
• the process flow 5 further includes, in 504, covering the film 608 at the bottom 603 of the recessed feature 604 with a mask layer 606. This is depicted in FIG. 6C.
• the mask layer 606 can, for example, contain a photoresist, a hard mask, Si0 2 , or SiN.
• the process flow 5 further includes, in 506, depositing a dopant film 609 in the recessed feature 604. This is depicted in FIG. 6D.
• the dopant film 609 can include an oxide layer (e.g., Si0 2 ), a nitride layer (e.g., SiN), an oxynitride layer (e.g., SiON), or a combination of two or more thereof.
• the dopant film 609 can include one or more dopants from Group IIIA of the Periodic Table of the Elements: boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl); and Group VA: nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi).
• the dopant film 609 can contain low dopant levels, for example between about 0.5 and about 5 atomic % dopant.
• the dopant film 609 can contain medium dopant levels, for example between about 5 and about 20 atomic % dopant.
• the dopant film 609 can contain high dopant levels, for example greater than 20 atomic percent dopant.
• the process flow 5 further includes, in 508, annealing the substrate to diffuse a dopant from the dopant film 609 into the film 608 on the sidewall 601 to activate the film 608 on the sidewall 601 for faster etching than the film 608 on the bottom 603 of the recessed feature 604. It is contemplated that the dopants disrupt the crystalline structure of the film 608, thereby enabling fast etching of the film 608 in a subsequent selective etching process.
• the process flow 5 further includes, in 510, etching the dopant film 609 and the film 608 from the sidewall 601 and the field area 611. As depicted in FIG. 6E, the etching removes the dopant film 609 and the field area 61 lfrom the sidewall 601 but the mask layer 606 protects the film 608 under the mask layer 606 from etching.
• the etch gases and the etch conditions may be selected for providing efficient removal of the dopant film 609 and the film 608 that is not protected by the mask layer 606.
• Step 10 may be performed in one or more etching steps using one or more etching recipes.
• the process flow 5 further includes, in 512, removing the mask layer 606 from the film 608 on the bottom 603 of the recessed feature 604. This is depicted in FIG. 6G.
• steps 502-512 may be repeated until the film 608 has a desired thickness.
• the recessed feature 604 may be filled with film 608.

Landscapes

• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Drying Of Semiconductors (AREA)
• Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• General Chemical & Material Sciences (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=58387284

Family Applications (1)

Country Status (5)

Families Citing this family (2)

Citations (5)

Family Cites Families (9)

• 2016
  • 2016-09-22 WO PCT/US2016/053099 patent/WO2017053558A1/en not_active Ceased
  • 2016-09-22 US US15/273,124 patent/US10079151B2/en active Active
  • 2016-09-22 JP JP2018515543A patent/JP6842616B2/ja active Active
  • 2016-09-22 KR KR1020187009280A patent/KR102522329B1/ko active Active
  • 2016-09-23 TW TW105130711A patent/TWI656580B/zh active

Patent Citations (5)

Also Published As

Similar Documents

Legal Events