WO2017049853A1 - Goa单元、栅极驱动电路及显示装置 - Google Patents

Goa单元、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2017049853A1
WO2017049853A1 PCT/CN2016/073981 CN2016073981W WO2017049853A1 WO 2017049853 A1 WO2017049853 A1 WO 2017049853A1 CN 2016073981 W CN2016073981 W CN 2016073981W WO 2017049853 A1 WO2017049853 A1 WO 2017049853A1
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Prior art keywords
transistor
module
goa unit
sub
submodule
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PCT/CN2016/073981
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English (en)
French (fr)
Inventor
上官星辰
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/324,881 priority Critical patent/US20170301277A1/en
Priority to EP16822364.2A priority patent/EP3355295A4/en
Publication of WO2017049853A1 publication Critical patent/WO2017049853A1/zh
Priority to US16/670,065 priority patent/US11127336B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA unit, a gate driving circuit, and a display device.
  • the gate driving circuit provides an on signal to enable a plurality of rows of pixels to be sequentially turned on one by one to realize display.
  • the gate driving circuit includes a multi-stage shift register, each shift register corresponding to one row of pixels, and when a row of pixels is pre-opened, a shift register corresponding to the row of pixels generates a driving signal to input to the row The pixel is connected to the gate line, thereby driving the row of pixels to be turned on.
  • GOA Gate on Array
  • each stage of the GOA unit outputs a turn-off signal after being driven to open a row of pixels corresponding thereto and is in a flooding state.
  • the GOA unit in the floating state is easily turned on by the coupled signal, causing a row of pixels corresponding to the GOA unit to be charged and turned on, thereby displaying an erroneous image, that is, a so-called "painting" occurs.
  • Different phenomenon due to signal crosstalk, the GOA unit in the floating state is easily turned on by the coupled signal, causing a row of pixels corresponding to the GOA unit to be charged and turned on, thereby displaying an erroneous image, that is, a so-called "painting" occurs.
  • embodiments of the present invention provide a GOA unit, a gate driving circuit, and a display device, which can avoid a false opening of a row of pixels corresponding to the GOA unit, so that the row of pixels It will not be charged and display the wrong image, thus overcoming the so-called "painting" phenomenon.
  • An embodiment of the present invention provides a GOA unit, which includes a driving module, and the driving module a block for outputting a first clock signal from an output of the GOA unit, the GOA unit further comprising a pull-down module coupled to the driver module and to the at least one low voltage terminal, and for the GOA
  • the unit When the unit outputs the shutdown signal, the low voltage signal provided by the at least one low voltage terminal is input to the control terminal of the driving module, so that the driving module is turned off under the control of the low voltage terminal.
  • the pull-down module may include a first sub-module, a second sub-module, and a third sub-module.
  • the first end of the first submodule is connected to the control end of the driving module, the second end of the first submodule is connected to the at least one low voltage end, and the third end of the first submodule is combined with the second submodule and the third submodule connection.
  • the first end of the second submodule is connected to the input signal end, the second end of the second submodule is connected to the second clock signal, and the third end of the second submodule is connected to the third end of the first submodule.
  • the first end of the third submodule is connected to the at least one low voltage end, the second end of the third submodule is connected to the control end of the driving module, and the third end of the third submodule is connected to the third end of the first submodule .
  • the pull down module may further include a fourth submodule.
  • the first end of the fourth submodule is connected to the output end of the GOA unit, the second end of the fourth submodule is connected to the at least one low voltage end, the third end of the fourth submodule and the third end of the second submodule
  • the terminal is connected to the third end of the third submodule.
  • the second sub-module may include a first transistor and a second transistor.
  • the first transistor is controlled to be the second end of the second sub-module and is connected to the second clock signal.
  • the source of the first transistor is the first end of the second sub-module and is connected to the input signal terminal, and the drain of the first transistor The pole is connected to the control electrode and the source of the second transistor.
  • the drain of the second transistor is a third end of the second sub-module and is coupled to the third end of the first sub-module.
  • a high voltage or a second clock signal can be input from the input signal terminal.
  • the third sub-module may include a third transistor.
  • the third transistor is controlled to be the second end of the third sub-module and is connected to the control terminal of the driving module, the source of the third transistor is the first end of the third sub-module, and is connected to a low voltage terminal, the third transistor The drain is the third end of the third sub-module and is connected to the third end of the first sub-module.
  • the first sub-module may include a fourth transistor.
  • the fourth transistor is controlled to be the third end of the first sub-module, and is connected to the second sub-module, the third sub-module, the source of the fourth transistor is the second end of the first sub-module, and the at least one low-voltage end Connect,
  • the drain of the fourth transistor is the first end of the first sub-module and is coupled to the control terminal of the drive module.
  • the fourth sub-module may include a fifth transistor.
  • the fifth transistor is controlled to be the third end of the fourth sub-module, and is connected to the third end of the second sub-module and the third end of the third sub-module, and the source of the fifth transistor is the second end of the fourth sub-module And connected to the at least one low voltage terminal, the drain of the fifth transistor being the first end of the fourth submodule and connected to the output of the GOA unit.
  • the first sub-module may include a fourth transistor
  • the second sub-module may include a first transistor and a second transistor
  • the third sub-module may include a third transistor.
  • the control electrode of the first transistor is connected to the second clock signal
  • the source of the first transistor is connected to the input signal terminal
  • the drain of the first transistor is connected to the control electrode and the source of the second transistor.
  • the drain of the second transistor is coupled to the gate of the fourth transistor.
  • the control electrode of the third transistor is connected to the control terminal of the driving module
  • the source of the third transistor is connected to at least one low voltage terminal
  • the drain of the third transistor is connected to the control electrode of the fourth transistor.
  • the source of the fourth transistor is coupled to at least one low voltage terminal, and the drain of the fourth transistor is coupled to the control terminal of the driver module.
  • a high voltage or a second clock signal can be input from the input signal terminal.
  • the low voltage terminal connected to the source of the third transistor and the low voltage terminal connected to the source of the fourth transistor may be the same voltage terminal.
  • the pull-down module may further include a fourth sub-module, and the fourth sub-module may include a fifth transistor.
  • the gate of the fifth transistor is coupled to the gate of the fourth transistor, the source of the fifth transistor is coupled to at least one low voltage terminal, and the drain of the fifth transistor is coupled to the output of the GOA cell.
  • the low voltage terminal connected to the source of the third transistor, the low voltage terminal connected to the source of the fourth transistor, and the low voltage terminal connected to the source of the fifth transistor may be the same voltage terminal.
  • the GOA unit may also include a pull up module.
  • the output of the pull-up module is connected to the driving module for inputting a pull-up signal to the driving module, and the pull-up signal turns on the driving module.
  • the drive module can include a drive transistor.
  • the control of the driving transistor is extremely driven by the control terminal of the module and is connected to the output terminal of the pull-up module to drive the source of the transistor Connected to the first clock signal, the drain of the drive transistor is coupled to the output of the GOA unit.
  • the GOA unit may also include a reset module.
  • the reset module is coupled to the drive module for inputting a low voltage signal to the control terminal of the drive module and the output of the GOA unit, the low voltage signal turning off the drive module and pulling down a signal output by the GOA unit.
  • the pull-up module may include a sixth transistor and a first capacitor.
  • the gate and source of the sixth transistor are connected to the pull-up signal, and the drain of the sixth transistor is connected to the gate of the drive transistor.
  • a first end of the first capacitor is coupled between a drain of the sixth transistor and a control electrode of the drive transistor, and a second end of the first capacitor is coupled to an output of the GOA unit.
  • the reset module may include an eighth transistor and a ninth transistor.
  • the control electrode of the eighth transistor is connected to the reset signal terminal, the source of the eighth transistor is connected to at least one low voltage terminal, and the drain of the eighth transistor is connected to the control terminal of the driving module.
  • the control electrode of the ninth transistor is connected to the reset signal terminal, the source of the ninth transistor is connected to at least one low voltage terminal, and the drain of the ninth transistor is connected to the output terminal of the GOA unit.
  • the voltage input from the input signal terminal may be equal to the turn-on voltage of the gate drive circuit.
  • Embodiments of the present invention also provide a gate driving circuit including the above GOA unit.
  • Embodiments of the present invention also provide a display device including the above-described gate driving circuit.
  • the pull-down module when the output is off, communicates the control end of the driving module with at least one low voltage end, and the at least one low voltage end inputs a low voltage signal to the control end of the driving module. So that the driving module will remain off during the output of the GOA unit to close the signal, so that the driving module can be prevented from being turned on by the signal coupled due to signal crosstalk, and in the case of coupling the incoming signal, the GOA unit will be maintained.
  • the gate driving circuit provided by the embodiment of the invention adopts the above-mentioned GOA unit, so that the erroneous opening of each row of pixels corresponding to each level of the GOA unit can be avoided, so that the pixels of each row are not charged and the wrong image is displayed, thereby overcoming the so-called “painting difference”. "phenomenon.
  • the display device provided by the embodiment of the invention adopts the above-mentioned gate driving circuit, so that the erroneous opening of each row of pixels corresponding to each level of the GOA unit can be avoided, so that the pixels of each row are not charged and the wrong image is displayed, thereby overcoming the so-called “painting difference”. "phenomenon.
  • FIG. 1 is a schematic structural diagram of a GOA unit according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a GOA unit according to an embodiment of the present invention.
  • FIG 3 is a timing diagram of signals in the circuit diagram shown in Figure 2;
  • FIG. 4 is a circuit diagram of a GOA unit according to an embodiment of the present invention.
  • FIG. 5 is a circuit diagram of a GOA unit according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a GOA unit in accordance with an embodiment of the present invention.
  • FIG. 1 shows a schematic diagram of a GOA unit in accordance with an embodiment of the present invention.
  • the GOA unit includes a driving module 1 and a pull-down module 2.
  • the driving module 1 is for outputting the first clock signal CLK from the output terminal OUTPUT of the GOA unit.
  • the pull-down module 2 is connected to the drive module 1 and is connected to the low voltage terminal VSS.
  • the pull-down module 2 is configured to input a low voltage signal provided by the low voltage terminal VSS to the control terminal of the driving module 1 when the GOA unit outputs a shutdown signal, so that the driving module 1 is in a closed state under the control of the low voltage signal.
  • the pull-down module 2 when the GOA unit outputs a shutdown signal, the pull-down module 2 will The low voltage signal provided by the low voltage terminal VSS is input to the control terminal of the driving module 1, so that the driving module 1 remains closed during the output of the GOA unit to close the signal, so that the driving module 1 can be prevented from being coupled due to signal crosstalk.
  • the signal is turned on, and in the case of coupling the incoming signal, the GOA unit maintains the state of the output off signal without erroneously outputting the drive signal as described in the prior art, thereby avoiding correspondence with the GOA unit
  • the line of pixels is turned on by mistake, so that the pixels of the line are not charged and the wrong image is displayed, overcoming the so-called "painting" phenomenon.
  • the GOA unit further comprises a pull-up module 3.
  • the output of the pull-up module 3 is connected to the driving module 1 for inputting a pull-up signal to the driving module 1, and the pull-up signal will pull up the node PU (ie, the node between the pull-up module 3 and the driving module 1) The potential is pulled high, so that the drive module 1 is turned on.
  • the pull-up signal is an STV signal, that is, a display start signal. If the GOA unit is located in any row of the second row or after the gate driving circuit, the pull-up signal is a signal outputted by the output terminal OUTPUT of the GOA unit of the previous row.
  • the GOA unit also includes a reset module 4.
  • the reset module 4 is connected to the driving module 1 for inputting a low voltage signal to the control terminal of the driving module 1 and the output terminal OUTPUT of the GOA unit to turn off the driving module 1 and output the signal of the GOA unit drop down.
  • FIG. 2 is a circuit diagram of a GOA unit according to an embodiment of the present invention
  • FIG. 3 is a timing chart of signals in the circuit diagram shown in FIG. 2.
  • the circuit structure of the GOA unit and the working principle of the GOA unit in the embodiment of the present invention are described and illustrated below with reference to FIG. 2 and FIG. 3.
  • each thin film transistor is shown as an N-type transistor. It should be understood that each thin film transistor may also be a P-type transistor.
  • the pull-down module 2 may include a first sub-module 21, a second sub-module 22, and a third sub-module 23.
  • the first end of the first sub-module 21 is connected to the control end of the driving module 1, the second end of the first sub-module 21 is connected to the low-voltage end VSS, and the third end of the first sub-module 21 and the second sub-module 22 are The third sub-module 23 is connected.
  • the first end of the second sub-module 22 is connected to the input signal end, the second end of the second sub-module 22 is connected to the second clock signal CLKB, and the third end of the second sub-module 22 is connected to the third end of the first sub-module 21 .
  • the first end of the third sub-module 23 is connected to the low voltage terminal VSS, the second end of the third sub-module 23 is connected to the control end of the driving module 1, and the third end of the third sub-module 23 and the first sub-module 21 Three-terminal connection.
  • the input signal terminal may be the high voltage terminal VGH, or the second clock signal CLKB may be input from the input signal terminal.
  • the first sub-module 21 may include a fourth transistor M4.
  • the fourth transistor M4 is controlled to be the third end of the first sub-module 21 and is connected to the second sub-module 22 and the third sub-module 23, the source of the fourth transistor M4 being the second end of the first sub-module 21, and Connected to the low voltage terminal VSS, the drain of the fourth transistor M4 is the first end of the first submodule 21 and is connected to the control terminal of the driving module 1.
  • the second sub-module 22 may include a first transistor M1 and a second transistor M2.
  • the control of the first transistor M1 is substantially the second end of the second sub-module 22, and is connected to the second clock signal CLKB
  • the source of the first transistor M1 is the first end of the second sub-module 22, and the input signal end (ie The high voltage terminal VGH) is connected
  • the drain of the first transistor M1 is connected to the control electrode and the source of the second transistor M2.
  • the drain of the second transistor M2 is the third end of the second sub-module 22 and is connected to the third end of the first sub-module 21.
  • the third sub-module 23 may include a third transistor M3.
  • the third transistor M3 is controlled to be the second end of the third sub-module 23 and is connected to the control terminal of the driving module 1, the source of the third transistor M3 being the first end of the third sub-module 23, and with a low voltage
  • the terminal VSS is connected, the drain of the third transistor M3 is the third end of the third sub-module 23, and is connected to the third end of the first sub-module 21.
  • the drive module 1 may include a drive transistor M7.
  • the control of the driving transistor M7 drives the control terminal of the module 1 and is connected to the output terminal of the pull-up module 3.
  • the source of the driving transistor M7 is connected to the first clock signal CLK, and the drain of the driving transistor M7 is connected to the GOA unit.
  • the output terminal is connected to OUTPUT.
  • the pull-up module 3 may include a sixth transistor M6 and a first capacitor C1.
  • the gate and source of the sixth transistor M6 are connected to the pull-up signal, and the drain of the sixth transistor M6 is connected to the gate of the driving transistor M7.
  • the first end of the first capacitor C1 is connected between the drain of the sixth transistor M6 and the control electrode of the driving transistor M7, and the second end of the first capacitor C1 is connected to the output terminal OUTPUT of the GOA unit.
  • the reset module 4 may include an eighth transistor M8 and a ninth transistor M9. Eighth crystal
  • the control electrode of the body tube M8 is connected to the reset signal terminal Reset, the source of the eighth transistor M8 is connected to the low voltage terminal VSS, and the drain of the eighth transistor M8 is connected to the control electrode of the driving transistor M7.
  • the gate of the ninth transistor M9 is connected to the reset signal terminal Reset, the source of the ninth transistor M9 is connected to the low voltage terminal VSS, and the drain of the ninth transistor M9 is connected to the output terminal OUTPUT of the GOA unit.
  • each element in the GOA unit of the embodiment of the present invention may include the following first to fourth stages.
  • the second clock signal CLKB is at a high level, causing the first transistor M1 and the second transistor M2 to be turned on.
  • the reset signal Reset is at a low level, and the eighth transistor M8 and the ninth transistor M9 are turned off.
  • the pull-up signal (here, the STV signal indicating that the GOA unit is located in the first row of the gate drive circuit) is at a high level, pulling the potential of the pull-up node PU high.
  • the driving transistor M7 is turned on, and the first clock signal CLK is output from the output terminal OUTPUT through the driving transistor M7, and is input to the second end of the first capacitor, and at the same time
  • the three transistor M3 is turned on, and the gate of the fourth transistor M4 is connected to the low voltage terminal VSS, causing it to be turned off in the first phase.
  • the STV signal goes low, turning off the sixth transistor M6, so that the pull-up node PU remains high and is in a floating state, and the first clock signal CLK changes from low to high.
  • Leveling the output terminal OUTPUT of the GOA unit is outputted to a high level, and the second end of the first capacitor C1 is charged, so that the first capacitor C1 is bootstrapped, so that the potential of the pull-up node PU is further raised.
  • the reset signal Reset changes from a low level to a high level, causing the eighth transistor M8 and the ninth transistor M9 to be turned on, thereby connecting the pull-up node PU to the low voltage terminal VSS, and the output terminal OUTPUT of the GOA unit. Also connected to the low voltage terminal VSS, in which case the drive transistor M7 is turned off and the GOA unit outputs a turn-off signal.
  • the second clock signal CLKB is at a high level, causing the first transistor M1 and the second transistor M2 to be turned on, so that the potential of the gate of the fourth transistor M4 is at a high level, and the fourth transistor M4 is turned on.
  • the low voltage terminal VSS is connected to the control electrode of the driving transistor M7 via the fourth transistor M4, so that the driving transistor M7 maintains the off state at this stage without being miscoupled into the signal of the GOA unit. Turning on does not cause the GOA unit to output an erroneous driving signal, preventing a line of pixels corresponding to the GOA unit from being erroneously opened to display an erroneous image.
  • the GOA unit of the embodiment of the present invention when the GOA unit outputs a shutdown signal, the GOA unit can be prevented from being mistakenly opened and errored.
  • the drive signal is output to prevent the display device from displaying an error.
  • circuit structure of the GOA unit is not limited to the structure shown in FIG. 2.
  • the pull-down unit 2 further includes a fourth sub-module 24.
  • the first end of the fourth sub-module 24 is connected to the output terminal OUTPUT of the GOA unit, the second end of the fourth sub-module 24 is connected to the low voltage terminal VSS, and the third end of the fourth sub-module 24 is connected to the second sub-module.
  • the third end of 22 is connected to the third end of the third sub-module 23.
  • the fourth sub-module 24 may include a fifth transistor M5.
  • the fifth transistor M5 is controlled to be the third end of the fourth sub-module 24, and is connected to the drain of the second transistor M2 in the second sub-module 22 and the drain of the third transistor M3 in the third sub-module 23,
  • the source of the fifth transistor M5 is the second end of the fourth sub-module 24, and is connected to the low voltage terminal VSS, the drain of the fifth transistor M5 is the first end of the fourth sub-module 24, and the output of the GOA unit End OUTPUT connection.
  • the second terminal and the output terminal OUTPUT of the first capacitor C1 are both connected to the low voltage terminal VSS, further ensuring that the signal output from the output terminal OUTPUT of the GOA unit is a shutdown signal.
  • the adverse effects of the signals coupled into the GOA unit on the GOA unit are improved to a greater extent.
  • the low voltage terminals connected to the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are the same low voltage terminals to reduce the number of power ports that need to be set. Further, the low voltage terminal connected to the pull-down module 2 and the low voltage terminal connected to the reset module 4 have the same voltage to reduce the number of power ports to be set.
  • the pull-down module 2 can also be connected to a plurality of low voltage terminals.
  • the source of the third transistor M3 is connected to the first low voltage terminal VSS1.
  • the source of the fourth transistor M4 is connected to the second low voltage terminal VSS2.
  • the source of the third transistor M3 is connected to the first low voltage terminal VSS1, and the source of the fourth transistor M4 and the source of the fifth transistor M5 are both connected to the second low voltage terminal VSS2.
  • the low voltage terminal connected to the source of the fourth transistor M4 and the low voltage terminal connected to the source of the fifth transistor M5 may also be different low voltage terminals.
  • the GOA unit When the GOA unit outputs a turn-off signal, the low voltage terminal connected to the source of the fourth transistor M4 inputs a low voltage signal to the gate of the driving transistor M7.
  • the low voltage terminal connected to the pull-down module 2 and the low voltage terminal connected to the reset module 4 may be different low voltage terminals, as long as the low voltage signal outputted from the low voltage terminal connected thereto can turn off the driving transistor M7. Just fine.
  • the voltage input from the input signal terminal may be equal to the turn-on voltage of the gate driving circuit.
  • the voltage output from the high voltage terminal VGH may be equal to the turn-on voltage of the gate drive circuit.
  • the high voltage existing in the gate driving circuit can be directly borrowed, the number of power ports can be reduced, and the circuit structure can be simplified.
  • the signal waveform of the second clock signal CLKB is not limited to the waveform shown in FIG. 3, as long as the control electrode of the fourth transistor M4 is at the upper pull-up point PU.
  • the voltage is low (for the embodiment in which the pull-down module 2 includes the fifth transistor M5, it is also necessary to satisfy the voltage of the gate of the fifth transistor M5 to a low level).
  • the pull-down module 2 connects the control terminal of the driving module 1 to the low voltage terminal VSS, and the low voltage terminal VSS inputs a low voltage signal to the control terminal of the driving module 1.
  • the driving module 1 is kept closed during the output of the GOA unit to close the signal, so that the driving module 1 can be prevented from being turned on by the signal coupled due to signal crosstalk, and in the case of coupling the incoming signal, the GOA unit is maintained.
  • An embodiment of the present invention further provides a gate driving circuit, and the gate driving circuit package
  • the GOA unit provided by the above embodiment is included.
  • the gate driving circuit of the embodiment adopts the GOA unit provided in the above embodiment, which can avoid the false opening of each row of pixels corresponding to each level of the GOA unit, so that each row of pixels is not charged and displays an erroneous image, thereby overcoming the so-called " The phenomenon of painting is different.
  • the embodiment of the invention further provides a display device, which comprises the gate drive circuit provided by the above embodiment.
  • the display device of the embodiment adopts the gate driving circuit provided by the above embodiment, which can avoid the false opening of each row of pixels corresponding to each level of the GOA unit, so that each row of pixels is not charged and displays an erroneous image, thereby overcoming the so-called “ The phenomenon of painting is different.

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Abstract

一种GOA单元、栅极驱动电路及显示装置。所述GOA单元包括驱动模块（1），其用于将第一时钟信号（CLK）从所述GOA单元的输出端（OUTPUT）输出。所述GOA单元还包括下拉模块（2），其与驱动模块（1）连接以及与至少一个低电压端（VSS）连接，并且用于在所述GOA单元输出关闭信号时将至少一个低电压端（VSS）提供的低电压信号输入到驱动模块（1）的控制端，以使驱动模块（1）处于关闭状态。所述GOA单元可以避免与所述GOA单元对应的一行像素的误开启，使该行像素不会被充电而显示错误的图像，从而克服所谓"画异"现象。

Description

GOA单元、栅极驱动电路及显示装置 技术领域
本发明涉及显示技术领域，具体地涉及GOA单元、栅极驱动电路及显示装置。
背景技术
在显示装置中，栅极驱动电路提供开启信号，使多行像素依次、逐行开启，从而实现显示。一般地，栅极驱动电路包括多级移位寄存器，每级移位寄存器与一行像素对应，并且预开启一行像素时，与该行像素对应的移位寄存器生成驱动信号，以输入到与该行像素连接的栅线中，从而驱动该行像素开启。
目前，为了实现显示装置的轻薄化，越来越多的栅极驱动电路采用GOA(Gate on Array)技术，在该技术中把栅极驱动芯片制备在阵列基板上。在采用GOA技术的栅极驱动电路中，将移位寄存器称之为GOA单元。
在现有的显示装置中，每级GOA单元在驱动与其对应的一行像素开启后输出关闭信号并处于悬浮(Flooding)状态。在此情况下，由于信号串扰，处于悬浮状态的GOA单元容易被耦合进入的信号误开启，从而导致与该GOA单元对应的一行像素被充电而开启，从而显示错误的图像，即出现所谓“画异”现象。
发明内容
为了解决现有技术中存在的至少上述技术问题，本发明实施例提供了GOA单元、栅极驱动电路及显示装置，其可以避免与所述GOA单元对应的一行像素的误开启，使该行像素不会被充电而显示错误的图像，从而克服所谓“画异”现象。
本发明实施例提供一种GOA单元，其包括驱动模块，该驱动模 块用于将第一时钟信号从所述GOA单元的输出端输出，所述GOA单元还包括下拉模块，该下拉模块与驱动模块连接以及与至少一个低电压端连接，并且用于在所述GOA单元输出关闭信号时将至少一个低电压端提供的低电压信号输入到驱动模块的控制端，以使驱动模块在该低电压端的控制下处于关闭状态。
所述下拉模块可以包括第一子模块、第二子模块和第三子模块。第一子模块的第一端与驱动模块的控制端连接，第一子模块的第二端与至少一个低电压端连接，第一子模块的第三端与第二子模块和第三子模块连接。第二子模块的第一端与输入信号端连接，第二子模块的第二端与第二时钟信号连接，第二子模块的第三端与第一子模块的第三端连接。第三子模块的第一端与至少一个低电压端连接，第三子模块的第二端与驱动模块的控制端连接，第三子模块的第三端与第一子模块的第三端连接。
所述下拉模块还可以包括第四子模块。第四子模块的第一端与所述GOA单元的输出端连接，第四子模块的第二端与至少一个低电压端连接，第四子模块的第三端与第二子模块的第三端和第三子模块的第三端连接。
所述第二子模块可以包括第一晶体管和第二晶体管。第一晶体管的控制极为第二子模块的第二端，并且与第二时钟信号连接，第一晶体管的源极为第二子模块的第一端，并且与输入信号端连接，第一晶体管的漏极与第二晶体管的控制极和源极连接。第二晶体管的漏极为第二子模块的第三端，并且与第一子模块的第三端连接。从输入信号端可以输入高电压或第二时钟信号。
所述第三子模块可以包括第三晶体管。第三晶体管的控制极为第三子模块的第二端，并且与驱动模块的控制端连接，第三晶体管的源极为第三子模块的第一端，并且与一低电压端连接，第三晶体管的漏极为第三子模块的第三端，并且与第一子模块的第三端连接。
所述第一子模块可以包括第四晶体管。第四晶体管的控制极为第一子模块的第三端，并且与第二子模块、第三子模块连接，第四晶体管的源极为第一子模块的第二端，并且与至少一个低电压端连接， 第四晶体管的漏极为第一子模块的第一端，并且与驱动模块的控制端连接。
所述第四子模块可以包括第五晶体管。第五晶体管的控制极为第四子模块的第三端，并且与第二子模块的第三端和第三子模块的第三端连接，第五晶体管的源极为第四子模块的第二端，并且与至少一个低电压端连接，第五晶体管的漏极为第四子模块的第一端，并且与所述GOA单元的输出端连接。
所述第一子模块可以包括第四晶体管，所述第二子模块可以包括第一晶体管和第二晶体管，并且所述第三子模块可以包括第三晶体管。第一晶体管的控制极与第二时钟信号连接，第一晶体管的源极与输入信号端连接，第一晶体管的漏极与第二晶体管的控制极和源极连接。第二晶体管的漏极与第四晶体管的控制极连接。第三晶体管的控制极与驱动模块的控制端连接，第三晶体管的源极与至少一个低电压端连接，第三晶体管的漏极与第四晶体管的控制极连接。第四晶体管的源极与至少一个低电压端连接，第四晶体管的漏极与驱动模块的控制端连接。从所述输入信号端可以输入高电压或第二时钟信号。
与第三晶体管的源极连接的低电压端和与第四晶体管的源极连接的低电压端可以为同一电压端。
所述下拉模块还可以包括第四子模块，所述第四子模块可以包括第五晶体管。第五晶体管的控制极与第四晶体管的控制极连接，第五晶体管的源极和至少一个低电压端连接，第五晶体管的漏极与所述GOA单元的输出端连接。
与第三晶体管的源极连接的低电压端、与第四晶体管的源极连接的低电压端和与第五晶体管的源极连接的低电压端可以为同一电压端。
所述GOA单元还可以包括上拉模块。上拉模块的输出端与驱动模块连接，以用于向驱动模块输入上拉信号，该上拉信号使驱动模块开启。
所述驱动模块可以包括驱动晶体管。驱动晶体管的控制极为驱动模块的控制端，并且与上拉模块的输出端连接，驱动晶体管的源极 与第一时钟信号连接，驱动晶体管的漏极与所述GOA单元的输出端连接。
所述GOA单元还可以包括复位模块。复位模块与驱动模块连接，以用于向驱动模块的控制端及所述GOA单元的输出端输入低电压信号，该低电压信号将所述驱动模块关闭并且将所述GOA单元输出的信号下拉。
所述上拉模块可以包括第六晶体管和第一电容器。第六晶体管的控制极和源极与上拉信号连接，第六晶体管的漏极与驱动晶体管的控制极连接。第一电容器的第一端连接在第六晶体管的漏极与驱动晶体管的控制极之间，第一电容器的第二端与所述GOA单元的输出端连接。
所述复位模块可以包括第八晶体管和第九晶体管。第八晶体管的控制极与复位信号端连接，第八晶体管的源极与至少一个低电压端连接，第八晶体管的漏极与驱动模块的控制端连接。第九晶体管的控制极与复位信号端连接，第九晶体管的源极与至少一个低电压端连接，第九晶体管的漏极与所述GOA单元的输出端连接。
从所述输入信号端输入的电压可以等于栅极驱动电路的开启电压。
本发明实施例还提供一种栅极驱动电路，其包括上述GOA单元。
本发明实施例还提供一种显示装置，其包括上述栅极驱动电路。
在本发明实施例提供的GOA单元中，在其输出关闭信号时，下拉模块将驱动模块的控制端与至少一个低电压端连通，该至少一个低电压端向驱动模块的控制端输入低电压信号，使得驱动模块在所述GOA单元输出关闭信号的过程中会保持关闭，从而可以避免驱动模块被因信号串扰而耦合进入的信号开启，并且在耦合进入信号的情况下，所述GOA单元会维持输出关闭信号的状态，而不会如现有技术中所述的错误地输出驱动信号，从而避免了与所述GOA单元对应的一行像素的误开启，使该行像素不会被充电而显示错误的图像，克服所谓“画异”现象。
本发明实施例提供的栅极驱动电路采用上述GOA单元，从而可以避免分别与各级GOA单元对应的各行像素的误开启，使各行像素不会被充电而显示错误的图像，克服所谓“画异”现象。
本发明实施例提供的显示装置采用上述栅极驱动电路，从而可以避免分别与各级GOA单元对应的各行像素的误开启，使各行像素不会被充电而显示错误的图像，克服所谓“画异”现象。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1为根据本发明实施例的GOA单元的结构示意图；
图2为根据本发明实施例的GOA单元的电路示意图；
图3为图2所示的电路图中各信号的时序图；
图4为根据本发明实施例的GOA单元的电路示意图；
图5为根据本发明实施例的GOA单元的电路示意图；以及
图6为根据本发明实施例的GOA单元的电路示意图。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
本发明实施例提供一种GOA单元。图1示出了根据本发明实施例的GOA单元的示意图。如图1所示，所述GOA单元包括驱动模块1和下拉模块2。驱动模块1用于将第一时钟信号CLK从所述GOA单元的输出端OUTPUT输出。下拉模块2与驱动模块1连接，并且与低电压端VSS连接。下拉模块2用于在所述GOA单元输出关闭信号时将低电压端VSS提供的低电压信号输入到驱动模块1的控制端，以使驱动模块1在低电压信号的控制下处于关闭状态。
本实施例中，在所述GOA单元输出关闭信号时，下拉模块2将 低电压端VSS提供的低电压信号输入到驱动模块1的控制端，使得驱动模块1在所述GOA单元输出关闭信号的过程中保持关闭，从而可以避免驱动模块1被因信号串扰而耦合进入的信号开启，并且在耦合进入信号的情况下，所述GOA单元会维持输出关闭信号的状态，而不会如现有技术中所述的错误地输出驱动信号，从而避免了与所述GOA单元对应的一行像素的误开启，使该行像素不会被充电而显示错误的图像，克服所谓“画异”现象。
此外，所述GOA单元还包括上拉模块3。上拉模块3的输出端与驱动模块1连接，用于向驱动模块1输入上拉信号，所述上拉信号将上拉结点PU(即，上拉模块3与驱动模块1之间的节点)的电位拉高，从而使驱动模块1开启。
本实施例中，若所述GOA单元位于栅极驱动电路的第一行，则所述上拉信号为STV信号，即显示的起始信号。若所述GOA单元位于栅极驱动电路的第二行或之后的任意一行，则所述上拉信号为上一行GOA单元的输出端OUTPUT输出的信号。
此外，所述GOA单元还包括复位模块4。复位模块4与驱动模块1连接，用于向驱动模块1的控制端及所述GOA单元的输出端OUTPUT输入低电压信号，以将所述驱动模块1关闭，并且将所述GOA单元输出的信号下拉。
图2示出了根据本发明实施例的GOA单元的电路图，图3为图2所示的电路图中各信号的时序图。下面结合图2和图3对本发明实施例中GOA单元的电路结构以及所述GOA单元的工作原理进行描述和说明。需要说明的是，在图2中，各薄膜晶体管示出为N型晶体管。应当理解的是，各薄膜晶体管也可以为P型晶体管。
参照图2，下拉模块2可以包括第一子模块21、第二子模块22和第三子模块23。第一子模块21的第一端与驱动模块1的控制端连接，第一子模块21的第二端与低电压端VSS连接，第一子模块21的第三端与第二子模块22和第三子模块23连接。第二子模块22的第一端连接输入信号端，第二子模块22的第二端连接第二时钟信号CLKB，第二子模块22的第三端和第一子模块21的第三端连接。第 三子模块23的第一端与低电压端VSS连接，第三子模块23的第二端与驱动模块1的控制端连接，第三子模块23的第三端与第一子模块21的第三端连接。本实施例中，所述输入信号端可以为高电压端VGH，或者从所述输入信号端可以输入第二时钟信号CLKB。
具体地，如图2所示，第一子模块21可以包括第四晶体管M4。第四晶体管M4的控制极为第一子模块21的第三端，并且与第二子模块22、第三子模块23连接，第四晶体管M4的源极为第一子模块21的第二端，并且与低电压端VSS连接，第四晶体管M4的漏极为第一子模块21的第一端，并且与驱动模块1的控制端连接。
第二子模块22可以包括第一晶体管M1和第二晶体管M2。第一晶体管M1的控制极为第二子模块22的第二端，并且与第二时钟信号CLKB连接，第一晶体管M1的源极为第二子模块22的第一端，并且与输入信号端(即高电压端VGH)连接，第一晶体管M1的漏极与第二晶体管M2的控制极和源极连接。第二晶体管M2的漏极为所述第二子模块22的第三端，并且与第一子模块21的第三端连接。
第三子模块23可以包括第三晶体管M3。第三晶体管M3的控制极为第三子模块23的第二端，并且与驱动模块1的控制端连接，第三晶体管M3的源极为所述第三子模块23的第一端，并且与低电压端VSS连接，第三晶体管M3的漏极为所述第三子模块23的第三端，并且与第一子模块21的第三端连接。
驱动模块1可以包括驱动晶体管M7。驱动晶体管M7的控制极为驱动模块1的控制端，并且与上拉模块3的输出端连接，驱动晶体管M7的源极与第一时钟信号CLK连接，驱动晶体管M7的漏极与所述GOA单元的输出端OUTPUT连接。
上拉模块3可以包括第六晶体管M6和第一电容器C1。第六晶体管M6的控制极和源极与上拉信号连接，第六晶体管M6的漏极与驱动晶体管M7的控制极连接。第一电容器C1的第一端连接在所述第六晶体管M6的漏极与驱动晶体管M7的控制极之间，第一电容器C1的第二端与所述GOA单元的输出端OUTPUT连接。
复位模块4可以包括第八晶体管M8和第九晶体管M9。第八晶 体管M8的控制极与复位信号端Reset连接，第八晶体管M8的源极与低电压端VSS连接，第八晶体管M8的漏极与驱动晶体管M7的控制极连接。第九晶体管M9的控制极与复位信号端Reset连接，第九晶体管M9的源极与低电压端VSS连接，第九晶体管M9的漏极与所述GOA单元的输出端OUTPUT连接。
本发明实施例的GOA单元中各元件的操作过程可以包括以下第一阶段至第四阶段。
在第一阶段，第二时钟信号CLKB为高电平，使第一晶体管M1和第二晶体管M2开启。复位信号Reset为低电平，使第八晶体管M8和第九晶体管M9关闭。上拉信号(在此为STV信号，表示该GOA单元位于栅极驱动电路的第一行)为高电平，将上拉结点PU的电位拉高。在此情况下，第一电容器C1的第一端被充电，驱动晶体管M7开启，进而第一时钟信号CLK通过驱动晶体管M7从输出端OUTPUT输出，并输入到第一电容器的第二端，同时第三晶体管M3被开启，进而第四晶体管M4的控制极与低电压端VSS连接，使其在该第一阶段关闭。
在第二阶段，STV信号变为低电平，使第六晶体管M6关闭，这样使上拉结点PU保持高电平并且处于悬浮状态，而第一时钟信号CLK由低电平变为高电平，使GOA单元的输出端OUTPUT输出高电平，同时对第一电容器C1的第二端充电，使第一电容器C1自举，使上拉结点PU的电位进一步升高。
在第三阶段，复位信号Reset由低电平变为高电平，使第八晶体管M8和第九晶体管M9开启，从而使上拉结点PU与低电压端VSS连接，GOA单元的输出端OUTPUT也与低电压端VSS连接，在此情况下，驱动晶体管M7关闭，GOA单元输出关闭信号。
在第四阶段，第二时钟信号CLKB为高电平，使第一晶体管M1和第二晶体管M2开启，从而使第四晶体管M4的控制极的电位为高电平，将第四晶体管M4打开，在此情况下，低电压端VSS经第四晶体管M4与驱动晶体管M7的控制极连接，从而驱动晶体管M7在该阶段会维持关闭状态，而不会被耦合进入该GOA单元中的信号误 开启，不会使所述GOA单元输出错误的驱动信号，防止与所述GOA单元对应的一行像素被错误的打开而显示错误的图像。
上面结合附图对本发明实施例的GOA单元的结构和其每个循环周期的工作原理进行了说明和描述，根据上述描述可知，在GOA单元输出关闭信号时，可以避免GOA单元被误开启而错误地输出驱动信号，防止显示装置显示错误。
在本发明实施例中，GOA单元的电路结构并不限于图2所示的结构。
图4示出了根据本发明实施例的GOA单元的电路图。具体地，如图4所示，下拉单元2还包括第四子模块24。第四子模块24的第一端与所述GOA单元的输出端OUTPUT连接，第四子模块24的第二端与低电压端VSS连接，第四子模块24的第三端与第二子模块22的第三端和第三子模块23的第三端连接。具体地，第四子模块24可以包括第五晶体管M5。第五晶体管M5的控制极为第四子模块24的第三端，并且与第二子模块22中的第二晶体管M2的漏极以及第三子模块23中的第三晶体管M3的漏极连接，第五晶体管M5的源极为第四子模块24的第二端，并且与低电压端VSS连接，第五晶体管M5的漏极为第四子模块24的第一端，并且与所述GOA单元的输出端OUTPUT连接。本实施例中，可以在GOA单元输出关闭信号时，使第一电容器C1的第二端和输出端OUTPUT均与低电压端VSS连接，进一步保证从GOA单元的输出端OUTPUT输出的信号为关闭信号，更大程度地改善被耦合进入该GOA单元的信号对GOA单元的不良影响。
在图4所示的实施例中，与第三晶体管M3、第四晶体管M4和第五晶体管M5连接的低电压端为相同的低电压端，以减少需要设置的电源端口的数量。此外，与下拉模块2连接的低电压端和与复位模块4连接的低电压端的电压相同，以减少需要设置的电源端口的数量。
本发明其他实施例中，下拉模块2还可以与多个低电压端连接。例如，如图5所示，第三晶体管M3的源极与第一低电压端VSS1连 接，第四晶体管M4的源极与第二低电压端VSS2连接。此外，如图6所示，第三晶体管M3的源极与第一低电压端VSS1连接，第四晶体管M4的源极和第五晶体管M5的源极均与第二低电压端VSS2连接。可以理解的是，对于图6所示实施例而言，与第四晶体管M4的源极连接的低电压端和与第五晶体管M5的源极连接的低电压端也可以为不同的低电压端。在所述GOA单元输出关闭信号时，与第四晶体管M4的源极连接的低电压端向驱动晶体管M7的控制极输入低电压信号。
此外，与下拉模块2连接的低电压端和与复位模块4连接的低电压端可以为不同的低电压端，只要与其二者连接的低电压端所输出的低电压信号能够使驱动晶体管M7关闭即可。
本发明实施例中，从所述输入信号端输入的电压可以等于栅极驱动电路的开启电压。例如，高电压端VGH输出的电压可以等于栅极驱动电路的开启电压。在此情况下，可以直接借用栅极驱动电路中已有的高电压，可以减少电源端口的数量，并简化电路结构。
此外，需要说明的是，本发明实施例中，第二时钟信号CLKB的信号波形并不限于图3所示的波形，只要在上拉结点PU为高电平时第四晶体管M4的控制极的电压为低电平(对于下拉模块2包含第五晶体管M5的实施例而言，还需满足将第五晶体管M5的控制极的电压拉至低电平)即可。
根据本发明实施例的GOA单元中，在其输出关闭信号时，下拉模块2将驱动模块1的控制端与低电压端VSS连通，低电压端VSS向驱动模块1的控制端输入低电压信号，使得驱动模块1在所述GOA单元输出关闭信号的过程中保持关闭，从而可以避免驱动模块1被因信号串扰而耦合进入的信号开启，并且在耦合进入信号的情况下，所述GOA单元会维持输出关闭信号的状态，而不会如现有技术中所述的错误地输出驱动信号，从而避免了与所述GOA单元对应的一行像素的误开启，使该行像素不会被充电而显示错误的图像，进而克服所谓“画异”现象。
本发明实施例还提供一种栅极驱动电路，所述栅极驱动电路包 括上述实施例提供的GOA单元。
本实施例的栅极驱动电路采用上述实施例提供的GOA单元，可以避免分别与各级GOA单元对应的各行像素的误开启，使各行像素不会被充电而显示错误的图像，从而克服所谓“画异”现象。
本发明实施例还提供一种显示装置，所述显示装置包括上述实施例提供的栅极驱动电路。
本实施例的显示装置采用上述实施例提供的栅极驱动电路，可以避免分别与各级GOA单元对应的各行像素的误开启，使各行像素不会被充电而显示错误的图像，从而克服所谓“画异”现象。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为落入本发明的保护范围。

Claims (19)

  1. 一种GOA单元，包括：
    驱动模块，其用于将第一时钟信号从所述GOA单元的输出端输出；以及
    下拉模块，其与所述驱动模块连接以及与至少一个低电压端连接，并且用于在所述GOA单元输出关闭信号时将所述至少一个低电压端提供的低电压信号输入到所述驱动模块的控制端，以使所述驱动模块处于关闭状态。
  2. 根据权利要求1所述的GOA单元，其中所述下拉模块包括第一子模块、第二子模块和第三子模块，
    所述第一子模块的第一端与所述驱动模块的控制端连接，所述第一子模块的第二端与所述至少一个低电压端连接，所述第一子模块的第三端与所述第二子模块和所述第三子模块连接，
    所述第二子模块的第一端与输入信号端连接，所述第二子模块的第二端与第二时钟信号连接，所述第二子模块的第三端与所述第一子模块的第三端连接，
    所述第三子模块的第一端与所述至少一个低电压端连接，所述第三子模块的第二端与所述驱动模块的控制端连接，所述第三子模块的第三端与所述第一子模块的第三端连接。
  3. 根据权利要求2所述的GOA单元，其中所述下拉模块还包括第四子模块，
    所述第四子模块的第一端与所述GOA单元的输出端连接，所述第四子模块的第二端与所述至少一个低电压端连接，所述第四子模块的第三端与所述第二子模块的第三端和所述第三子模块的第三端连接。
  4. 根据权利要求2或3所述的GOA单元，其中所述第二子模 块包括第一晶体管和第二晶体管，
    所述第一晶体管的控制极为所述第二子模块的第二端，并且与第二时钟信号连接，所述第一晶体管的源极为所述第二子模块的第一端，并且与所述输入信号端连接，所述第一晶体管的漏极与所述第二晶体管的控制极和源极连接，
    所述第二晶体管的漏极为所述第二子模块的第三端，并且与所述第一子模块的第三端连接，
    从所述输入信号端输入高电压或第二时钟信号。
  5. 根据权利要求2或3所述的GOA单元，其中所述第三子模块包括第三晶体管，
    所述第三晶体管的控制极为所述第三子模块的第二端，并且与所述驱动模块的控制端连接，所述第三晶体管的源极为所述第三子模块的第一端，并且与所述至少一个低电压端连接，所述第三晶体管的漏极为所述第三子模块的第三端，并且与所述第一子模块的第三端连接。
  6. 根据权利要求2或3所述的GOA单元，其中所述第一子模块包括第四晶体管，
    所述第四晶体管的控制极为所述第一子模块的第三端，并且与所述第二子模块和所述第三子模块连接，所述第四晶体管的源极为所述第一子模块的第二端，并且与所述至少一个低电压端连接，所述第四晶体管的漏极为所述第一子模块的第一端，并且与所述驱动模块的控制端连接。
  7. 根据权利要求3所述的GOA单元，其中，所述第四子模块包括第五晶体管，
    所述第五晶体管的控制极为所述第四子模块的第三端，并且与所述第二子模块的第三端和所述第三子模块的第三端连接，所述第五晶体管的源极为所述第四子模块的第二端，并且与所述至少一个低电 压端连接，所述第五晶体管的漏极为第四子模块的第一端，并且与所述GOA单元的输出端连接。
  8. 根据权利要求2所述的GOA单元，其中所述第一子模块包括第四晶体管，所述第二子模块包括第一晶体管和第二晶体管，所述第三子模块包括第三晶体管，
    所述第一晶体管的控制极与所述第二时钟信号连接，所述第一晶体管的源极与所述输入信号端连接，所述第一晶体管的漏极与所述第二晶体管的控制极和源极连接，
    所述第二晶体管的漏极与所述第四晶体管的控制极连接，
    所述第三晶体管的控制极与所述驱动模块的控制端连接，所述第三晶体管的源极与所述至少一个低电压端连接，所述第三晶体管的漏极与所述第四晶体管的控制极连接，
    所述第四晶体管的源极与所述至少一个低电压端连接，所述第四晶体管的漏极与所述驱动模块的控制端连接，
    从所述输入信号端输入高电压或第二时钟信号。
  9. 根据权利要求8所述的GOA单元，其中与所述第三晶体管的源极连接的低电压端和与所述第四晶体管的源极连接的低电压端为同一电压端。
  10. 根据权利要求8所述的GOA单元，其中所述下拉模块还包括第四子模块，所述第四子模块包括第五晶体管，
    所述第五晶体管的控制极与所述第四晶体管的控制极连接，所述第五晶体管的源极与所述至少一个低电压端连接，所述第五晶体管的漏极与所述GOA单元的输出端连接。
  11. 根据权利要求10所述的GOA单元，其中与所述第三晶体管的源极连接的低电压端、与所述第四晶体管的源极连接的低电压端和与所述第五晶体管的源极连接的低电压端为同一电压端。
  12. 根据权利要求1所述的GOA单元，还包括上拉模块，其中所述上拉模块的输出端与所述驱动模块连接，以用于向所述驱动模块输入上拉信号，所述上拉信号使所述驱动模块开启。
  13. 根据权利要求12所述的GOA单元，其中所述驱动模块包括驱动晶体管，
    所述驱动晶体管的控制极为所述驱动模块的控制端，并且与所述上拉模块的输出端连接，所述驱动晶体管的源极与第一时钟信号连接，所述驱动晶体管的漏极与所述GOA单元的输出端连接。
  14. 根据权利要求12或13所述的GOA单元，还包括复位模块，其中所述复位模块与所述驱动模块连接，以用于向所述驱动模块的控制端及所述GOA单元的输出端输入低电压信号，所述低电压信号将所述驱动模块关闭并且将所述GOA单元输出的信号下拉。
  15. 根据权利要求13所述的GOA单元，其中所述上拉模块包括第六晶体管和第一电容器，
    所述第六晶体管的控制极和源极与所述上拉信号连接，所述第六晶体管的漏极与所述驱动晶体管的控制极连接；
    所述第一电容器的第一端连接在所述第六晶体管的漏极与所述驱动晶体管的控制极之间，所述第一电容器的第二端与所述GOA单元的输出端连接。
  16. 根据权利要求14所述的GOA单元，其中所述复位模块包括第八晶体管和第九晶体管，
    所述第八晶体管的控制极与复位信号端连接，所述第八晶体管的源极与所述至少一个低电压端连接，所述第八晶体管的漏极与所述驱动模块的控制端连接，
    所述第九晶体管的控制极与所述复位信号端连接，所述第九晶 体管的源极与所述至少一个低电压端连接，所述第九晶体管的漏极与所述GOA单元的输出端连接。
  17. 根据权利要求4或8所述的GOA单元，其中从所述输入信号端输入的电压等于栅极驱动电路的开启电压。
  18. 一种栅极驱动电路，包括权利要求1至17中任意一项所述的GOA单元。
  19. 一种显示装置，包括权利要求18所述的栅极驱动电路。
PCT/CN2016/073981 2015-09-23 2016-02-18 Goa单元、栅极驱动电路及显示装置 WO2017049853A1 (zh)

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