WO2017037996A1 - 部品、基板モジュール、機器、および光学フィルタ - Google Patents
部品、基板モジュール、機器、および光学フィルタ Download PDFInfo
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- WO2017037996A1 WO2017037996A1 PCT/JP2016/003430 JP2016003430W WO2017037996A1 WO 2017037996 A1 WO2017037996 A1 WO 2017037996A1 JP 2016003430 W JP2016003430 W JP 2016003430W WO 2017037996 A1 WO2017037996 A1 WO 2017037996A1
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- 229910052681 coesite Inorganic materials 0.000 claims description 3
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Definitions
- the present technology relates to a light emitting element and other components, a substrate module configured by mounting this component, a device including the substrate module, and an optical filter using the component.
- Patent Document 1 discloses a semiconductor element connected to a submount via a solder layer. Electrode layers are provided on the upper surface and the lower surface of the semiconductor element, respectively. The lower electrode layer is connected to a metal thin film provided on the upper surface of the submount via a solder layer. The lower surface side electrode layer is not formed in the entire region of the lower surface of the semiconductor element, but is not formed at the end portion in the longitudinal direction of the lower surface, and those end portions of the semiconductor layer are exposed. The solder layer has poor wettability with respect to the semiconductor layer and good wettability with respect to the electrode layer.
- solder layer does not adhere to both end portions of the semiconductor element, and the solder swells (crawls up) on the side surface (including the laser emission surface) of the semiconductor element is prevented (for example, in the description of Patent Document 1) [0010], [0017], [0029], see FIGS.
- the electronic device described in Patent Document 2 includes an electronic component (semiconductor chip), a printed circuit board on which a noble metal layer is printed, and solder for joining them.
- the back electrode of the semiconductor chip and the noble metal layer of the printed board are joined by solder.
- the noble metal layer is provided in a continuous annular shape so as to surround the projection area (component projection area) of the semiconductor chip.
- the molten solder wets and spreads along the noble metal layer into a continuous ring surrounding the entire outer periphery of the component projection area, so that the thickness of the solder is uniform at the four corners of the component projection area. It becomes easy to. Therefore, the inclination of the semiconductor chip is prevented when the semiconductor chip is mounted (see, for example, paragraphs [0052], [0078], [0079] of FIG. 1A to FIG. 1C). .
- JP 2010-171047 A JP 2010-245161
- An object of the present disclosure is to provide a technique capable of suppressing the inclination of a component connected to a substrate.
- a component according to the present technology includes a main body, a first layer, and a second layer.
- the main body has a bottom surface.
- the first layer is provided on the bottom surface of the main body and has a bottom surface.
- the second layer is a second layer which is bonded to the metal bonding material on the substrate and is physically integrated.
- the second layer has a wettability higher than the wettability of the first layer with respect to the metal bonding material in a molten state, and the second layer has a wettability higher than that of the first layer.
- the first layer is provided so as to protrude from the bottom surface side so that at least a part of the bottom surface is exposed.
- the wettability of the second layer with respect to the metal bonding material in the molten state is higher than that of the first layer, and the bottom surface of the first layer is exposed on the entire outer peripheral side of the second layer.
- the position of the surface of the metal bonding material is determined so that the surface of the metal bonding material is formed from the vicinity of the boundary between the first layer and the second layer on the bottom surface of this layer.
- the second layer is provided so as to protrude from the bottom surface side of the first layer. Thereby, the side surface of the main body is not wetted by the metal bonding material in the molten state, and the occurrence of tilting of the parts can be suppressed.
- the main body is not limited to a material composed of one kind of element, and may be composed of a compound or a multilayer material.
- the first layer may be configured to have non-wetting properties with respect to the metal bonding material.
- the boundary surface of the metal bonding material is surely formed in the vicinity between the second layer having relatively high wettability and the first layer having non-wetting property.
- the first layer may have a non-exposed bottom region covered with the second layer other than the exposed bottom region.
- the bottom surface of the first layer is viewed in a cross-section in the stacking direction of the first layer and the second layer, and the exposed bottom surface region of the bottom surface of the first layer has a first width.
- the non-exposed bottom surface region may have a second width smaller than the first width.
- the bottom surface of the first layer is viewed in a cross section in the stacking direction of the first layer and the second layer, and the width of the exposed bottom surface region of the bottom surface of the first layer is the second layer.
- This layer may be configured to be larger than the protruding height in the protruding direction from the bottom surface of the first layer.
- the width of the exposed region of the bottom surface of the first layer that is unlikely to get wet with the metal bonding material is configured to be larger than the protruding height of the second layer that is likely to get wet with the metal bonding material. The possibility that the side surface of the main body gets wet with the metal bonding material can be further reduced.
- the main body may include a semiconductor material as a main constituent material, the first layer may be an insulating material, and the second layer may be an electrode.
- the first layer may be configured to have non-wetting properties with respect to the metal bonding material.
- the first layer may contain SiO2, SiN, or a poly resin.
- the at least bottom layer of the second layer may be composed of the Au.
- the volume amount occupied by the Au in the second layer may be 3% or less of the volume amount of the metal bonding material.
- the second layer may contain Pt or Ni.
- a substrate module according to the present technology includes the above component, a substrate having a bonding layer, and a metal bonding material that connects the component to the bonding layer of the substrate.
- the component projection area in which the component is projected onto the substrate may be arranged on the inner side of the outer peripheral edge of the contact area where the bonding layer and the metal bonding material are in contact with each other.
- the substrate module may further include a film having an opening facing the bonding layer, and an opening shape of the opening having a protrusion radially from the center.
- the metal bonding material may be configured in a planar shape substantially the same as the opening shape of the opening provided in the opening of the film.
- the component is fixed to a region corresponding to the central portion of the metal bonding material, and the protrusions of the opening of the film are substantially equiangular with each other along at least three directions in rotational symmetry from the central portion.
- the tip may be arranged on a circumference centered on the central portion and may be tapered toward the tip.
- the metal bonding material provided in the opening of the film and the bonding layer may be connected.
- the thickness of the metal bonding material may be 2 ⁇ m or more and 1/2 or less of the width of the second layer of the component.
- the device according to the present technology or the optical filter includes the substrate module.
- FIG. 1A is a plan view showing a component according to an embodiment of the present technology.
- FIG. 1B is a partial cross-sectional view thereof, and
- FIG. 1C is a bottom view thereof.
- FIG. 2 is a diagram for explaining wettability.
- 3A to 3C are a plan view, a partial cross-sectional view, and a bottom view showing the light-emitting element.
- FIG. 4A is a cross-sectional view showing a substrate module including the light emitting element, and FIG. 4B is a plan view thereof.
- 5A to 5C show a substrate module in which a light emitting device according to a reference example is mounted on a substrate.
- 6A to 6C show a substrate module according to Comparative Example 1.
- FIG. 7 is a diagram for explaining a problem caused by a film (electrode film) of an electrode layer formed on a semiconductor wafer being not uniform on one semiconductor wafer.
- 8A to 8D show a substrate module according to Comparative Example 2.
- FIG. 9 is a diagram for explaining the behavior when the solder melts in the reflow process.
- FIG. 10 shows a state in which the light emitting device according to the comparative example 1 is bonded to the substrate by solder reflow.
- FIG. 11 shows a state in which the light-emitting element according to Comparative Example 2 is bonded to the substrate by solder reflow.
- FIG. 12 shows a state in which the light-emitting element according to the present technology is bonded to the substrate by solder reflow.
- FIG. 13 is a photomicrograph of a substrate module having solder on which a bridge made of an AuSn alloy is formed.
- FIG. 14 is a graph showing an example of a temperature profile of a reflow process using Sn-based solder.
- FIG. 15 is a graph showing an actual measurement of the relationship between the thickness of the solder and the inclination of the light emitting element.
- FIG. 16 is a graph showing the relationship between the width of the electrode layer and the inclination of the light emitting element having the electrode layer;
- FIG. 17 is a cross-sectional view of a component according to another embodiment 1 of the present technology.
- 18A is a cross-sectional view taken along line AA in FIG. 18B.
- FIG. 18B is a plan view of a substrate module according to another embodiment 3;
- FIG. 19 is a cross-sectional view illustrating a component according to still another embodiment of the present technology.
- top”, “bottom”, “left”, “right”, “vertical”, “horizontal”, “bottom” are used to indicate the direction and position of parts and devices. May be used, but this is only for convenience of explanation. That is, these terms are often used for easy understanding of the explanation, and may not coincide with the direction and position in the scene where the device or device is actually manufactured or used.
- FIG. 1A is a plan view showing components according to an embodiment of the present technology.
- FIG. 1B is a partial cross-sectional view thereof, and
- FIG. 1C is a bottom view thereof.
- the component 20 is used as one light-emitting element or as one component included in the optical filter.
- the component 20 includes a main body 22, a first layer 24, and a second layer 26.
- the main body 22 has a top surface and a bottom surface.
- the first layer 24 is provided on the bottom surface of the main body 22.
- the second layer 26 is provided so as to protrude from the bottom surface 245 of the first layer 24.
- An opening 24a is provided at a predetermined position of the first layer 24, for example, the center, but this is not essential.
- the main body 22 is typically configured in a rectangular parallelepiped shape or a cubic shape.
- the main body 22 may have another prismatic shape or a cylindrical shape.
- the shape of the first layer 24 and the second layer 26 is not particularly limited as long as the first layer 24 and the second layer 26 are configured in the same shape as the main body 22, similar to the main body 22, and / or a shape close to them as seen in the bottom view shown in FIG. 1C. Good.
- the second layer 26 is physically provided integrally. That is, a plurality of second layers 26 are not provided.
- the second layer 26 is an electrode as will be described later, it constitutes a single electrode (single-side single electrode).
- the second layer 26 has a bottom surface of the first layer 24 such that a part of the bottom surface 245 of the first layer 24 is exposed on the entire outer peripheral side of the second layer 26. It protrudes downward from H.245.
- the protruding direction is not limited to being perpendicular to the bottom surface 245 of the first layer 24, and may be provided with an inclination.
- the second layer 26 protrudes from the bottom surface 245 of the first layer 24, and the first layer 24 is covered with the second layer 26 other than the exposed region 245a of the bottom surface 245. And a non-exposed bottom region 245b.
- This component 20 is connected to a board (not shown).
- the second layer 26 is bonded onto the substrate via a metal bonding material.
- solder is used as the metal bonding material, as will be described later.
- the second layer 26 is made of a material having a wettability higher than that of the first layer 24 with respect to the metal bonding material.
- the first layer 24 is composed of a material that is non-wetting with respect to the metal bonding material.
- wetting is defined by the contact angle of a metal bonding material in a molten state with respect to the surface of the material (layer) as shown in FIG.
- the contact angle ⁇ is in the range of 1 ° to 90 °, 1 ° to 70 °, or 1 ° to 60 °, or 10 ° to 50 °, the material exhibits high wettability. If the contact angle ⁇ is greater than 90 ° and less than 180 °, greater than 70 ° and less than 180 °, or greater than 60 ° and less than 180 °, it exhibits non-wetting properties.
- the relationship of the thicknesses of the main body 22, the first layer 24, and the second layer 26 in the vertical direction in the figure is: main body 22> second layer 26> first layer 24.
- the relationship between these thicknesses can be changed as appropriate according to the type of the component 20.
- 3A to 3C are a plan view, a partial cross-sectional view, and a bottom view showing the light-emitting element 10.
- the light emitting element 10 is typically a light emitting diode, a laser diode, or the like. Since the basic configuration of the light emitting element 10 is the same as the configuration of the component 20 described with reference to FIGS. 1A to 1C, detailed description of the same portions will be simplified or omitted.
- the light emitting element 10 includes a semiconductor layer 12 as a main body, an insulating layer 14 as a first layer, and an electrode layer 16 as a second layer.
- An upper electrode 17 is connected to the upper part of the semiconductor layer 12.
- the semiconductor layer 12 is provided with a first conductivity type layer made of an n-type or p-type semiconductor, a second conductivity type layer made of a semiconductor of a conductivity type different from the first conductivity type layer, and between them.
- An active layer formed.
- An opening 14 a is provided at a predetermined position of the insulating layer 14, for example, at the center.
- the electrode layer 16 is in contact with the first conductivity type layer of the semiconductor layer 12 through the opening 14a.
- the upper electrode 17 is in contact with the second conductivity type layer of the semiconductor layer 12.
- the electrode layer 16 that is the second layer protrudes downward from the insulating layer 14 so that the bottom surface 145 of the insulating layer 14 is exposed on the entire outer peripheral side of the electrode layer 16. Is provided. With such a structure, the bottom surface 145 has an exposed region 145a and a non-exposed bottom region 145b.
- the material of the semiconductor layer 12 known materials such as a gallium compound semiconductor and a phosphorus compound semiconductor are used. However, the material is not particularly limited as long as it is a material capable of emitting light by this structure.
- the wettability of the electrode layer 16 with respect to solder as a metal bonding material is higher than that of the insulating layer 14. As described with reference to FIG. 2, the wettability is defined by the contact angle of the metal bonding material in the molten state with respect to the electrode layer 16 and the insulating layer 14.
- the material of the insulating layer 14 is used as the material of the insulating layer 14.
- the thickness of the insulating layer 14 is preferably 2 nm or more and 500 nm or less, and more preferably 4 nm or more and 250 nm or less. These insulating layers 14 are non-wetting with respect to solder.
- the material of the insulating layer 14 may be, for example, a poly resin.
- the width of the insulating layer 14 is preferably 5 ⁇ m or more and 500 ⁇ m or less, and more preferably 5 ⁇ m or more and 250 ⁇ m or less.
- the “width” is the length of one side when the outer shape of the insulating layer 14 is a triangle or a rectangle when viewed in the stacking direction of each layer (that is, when viewed in a plane as in FIGS. 3A and 3C).
- the “width” is the length of the longest diagonal line (line connecting two vertexes).
- the “width” is a diameter or a major axis.
- the electrode layer 16 for example, a platinum group element such as Pt, Au, or Ni is used. Or the electrode layer 16 may be comprised by multiple layers with such materials. Typically, the electrode layer 16 is composed of three layers of Ti, Pt, and Au from the insulating layer 14 side. Ti has a function of improving the adhesion between Au or Pt and the insulating layer 14. Au has a function of preventing oxidation on the surface of the electrode layer 16.
- the thickness of the electrode layer 16 is preferably 10 nm or more and 500 nm or less, more preferably 20 nm or more and 400 nm or less.
- the electrode layer 16 is composed of Ti, Pt, and Au as described above
- examples of the film thickness are as follows. Ti is 0.1 ⁇ m, Pt is 0.2 ⁇ m, and Au is 0.05 ⁇ m. Of course, each film thickness is not limited to these values.
- the light emitting element 10 is manufactured by, for example, photolithography and an etching process using a resist as a mask. By this process, the interface between the electrode layer 16 and the insulating layer 14 can be formed with high accuracy.
- the outer shape of the light-emitting element 10 is, for example, rectangular when viewed in the stacking direction of each layer (vertical direction in the figure). Similarly, the outer shapes of the insulating layer 14 and the electrode layer 16 are also rectangular. These outer shapes are not limited to rectangles, and may be configured by pentagons or more. Alternatively, the outer shape may be a circle or an ellipse.
- the width of the light emitting element 10 is, for example, 5 ⁇ m or more and 300 ⁇ m or less.
- the length of one side of the light emitting element 10 is, for example, 5 ⁇ m or more and 300 ⁇ m or less.
- the light emitting element 10 is rectangular, it may be rectangular or square.
- the lower limit of the short side is 5 ⁇ m and the upper limit of the long side is 300 ⁇ m.
- the length of the longest diagonal is set to 5 ⁇ m or more and 300 ⁇ m or less, and is a circle or an ellipse
- the diameter or length of the major axis is set to 5 ⁇ m or more and 300 ⁇ m or less.
- the width of the electrode layer 16 is set to 4 ⁇ m or more and 200 ⁇ m or less, for example.
- the length of one side is set to, for example, 4 ⁇ m or more and 200 ⁇ m or less (see FIG. 3C).
- the length of the longest diagonal line is set within the above range, and is set to 4 ⁇ m or more and 200 ⁇ m or less. Is set to 4 ⁇ m or more and 200 ⁇ m or less.
- the length of one side, diagonal line, diameter or major axis of the electrode layer 16 is 10 to 190, 10 to 100, 10 to 50, 10 to 30, 10 to 20, 10 to 15, 5 to 100, 10 to 50, It is set to 5 to 15, 5 to 10, 5 to 9, 5 to 8, or 5 to 7 (unit: ⁇ m).
- FIG. 4A is a cross-sectional view showing a substrate module including the light emitting element 10.
- FIG. 4B is a plan view thereof.
- the board module 100 includes a board (for example, a circuit board for mounting) 50, the light emitting element 10 mounted on the board 50, and a metal bonding material that connects them.
- the substrate 50 has a substrate electrode layer 51 as a bonding layer.
- the electrode layer 16 of the light emitting element 10 is connected to the substrate electrode layer 51 via the solder 23 as a metal bonding material. Since the wettability of the solder 23 in the molten state with respect to the electrode layer 16 and the insulating layer 14 is different, the solder 23 is solidified and formed as shown in the figure. That is, since the insulating layer 14 has non-wetting property and the electrode layer 16 has wetting property, the solder 23 is prevented from coming into contact with the insulating layer 14 in a state where the solder 23 is solidified, and the electrode 23 The layer 16 is provided so as to contact the entire bottom surface and side surface. In other words, the position of the surface of the solder 23 is determined such that the surface of the solder 23 is formed near the boundary between the insulating layer 14 and the electrode layer 16 on the bottom surface 145 of the insulating layer 14.
- a rectangular component projection area PA indicated by oblique lines obtained by projecting the light emitting element 10 onto the substrate 50 is an outer peripheral edge of the solder 23 in a solidified state (the substrate electrode layer 51 of the solder 23).
- the outer peripheral edge of the contact area in contact with 231) is arranged on the inner side.
- the ratio (wa: wb) between the width wa of the component projection area PA and the width wb of the contact area of the solder 23 is set to 1: 1.1 to 3, preferably 1: 1.1 to 2. Is done.
- the width of the substrate electrode layer 51 (the width in the left-right direction in the figure) and the width of the outer peripheral edge of the solder 23 (the outer peripheral edge of the contact contact area) are the same.
- the width of the substrate electrode layer 51 may be wider than the width of the outer peripheral edge of the solder 23.
- the “width” referred to here can also be defined with the same meaning as the definition of “width” described above.
- the side surface of the semiconductor layer 12 is not wetted by the solder 23 in the molten state, and the occurrence of the tilt of the light emitting element 10 can be suppressed.
- the width of the substrate electrode layer 51 is preferably set to 115% or more and 300% or less of the width of the light emitting element 10 (semiconductor layer 12) in the same direction, and more preferably set to 130% or more and 200% or less. .
- the width of the bottom surface of the solder 23 (that is, the width of the contact region) is preferably set to 115% or more and 300% or less of the width in the same direction of the light emitting element 10 (semiconductor layer 12), and more preferably 130% or more. Set to 200% or less.
- FIG. 5A shows a substrate module in which the light emitting device 110 according to the reference example is mounted on the substrate without tilting.
- 5B and 5C show a substrate module in which the light emitting element 110 according to the reference example is inclined and mounted on the substrate 50.
- molten solder a sufficient amount of molten solder is used to center the light emitting element 110 by the surface tension of solder that is in a molten state in a reflow process (hereinafter referred to as molten solder) and to suppress the inclination of the light emitting element 110. Is required. This is because the light emitting element 110 on the molten solder can move to some extent in a direction parallel to the mounting surface of the substrate 50 (the upper surface of the substrate electrode layer 51).
- Centering is positioning to the center in the contact area (in the present embodiment, coincides with the upper surface area of the substrate electrode layer 51). In the case of this embodiment, centering is performed by self-alignment. “Inclination” means an inclination due to rotation of the light emitting element 110 around an axis parallel to the mounting surface of the substrate 50.
- the parallelism between the plurality of electrodes and the solder can be maintained. This is because most of the elements having a plurality of general electrodes are positioned in an even arrangement on the bottom surface of the light emitting element, and the plurality of electrodes serve as a base (leg part) at the time of bonding. Because. Therefore, it is easy to suppress the inclination of a light emitting element having a plurality of electrodes on the bottom surface.
- the molten solder 23 may spread and spread in layers other than the electrode 36. There is also a risk of tilting.
- the difficulty level differs between a light-emitting element having a single electrode on one side and a light-emitting element having a plurality of electrodes on one side, and the difficulty level of a light-emitting element having a single electrode is markedly increased. Therefore, some device is required for the structure of the light emitting element having a single electrode or the structure on the substrate 50 side.
- the wettability of the electrode layer 16 and the insulating layer 14 with respect to the solder 23 is different, and the insulating layer is formed on the entire outer peripheral side of the electrode layer 16.
- 14 is provided to protrude downward from the insulating layer 14 so that the bottom surface 145 of the 14 is exposed. That is, the electrode layer 16 and the insulating layer 14 have a so-called “screw-back” structure or an “overhang” structure.
- the bottom surface 145 of the insulating layer 14 prevents the solder 23 from getting wet or scooping up, so that the contact angle of the solder 23 with respect to the electrode layer 16 is stabilized. Thereby, the inclination of the light emitting element 10 can be suppressed.
- FIG. 6A shows a substrate module according to Comparative Example 1.
- the light emitting element 120 of the substrate module according to Comparative Example 1 is the same as the light emitting element 10 according to the present technology in that the insulating layer 44 and the electrode layer 46 are provided below the semiconductor layer 12.
- the light emitting element 10 and the light emitting element 120 are different in that the insulating layer 44 and the electrode layer 46 have substantially the same thickness, that is, their bottom surfaces are substantially flush with each other.
- the component 20 and the light emitting element 10 according to the present technology are configured such that the first layer 24 is the second layer 26 other than the exposed region 245 a in the bottom surface 245.
- the structure of the light emitting element 120 according to the comparative example 1 is different also in that it has a covered non-exposed bottom surface region 245b.
- FIGS. 6B and 6C are enlarged views of the main part of the substrate module shown in FIG. 6A.
- a slight difference in the thickness of the electrode caused by a manufacturing error of the light emitting element 120 causes a difference in the way of wetting at the peripheral edge of the electrode. That is, the contact angle of the solder 23 to the light emitting element 120 may vary.
- FIG. 6B shows a form in which, for example, the thickness of the electrode layer 46 is slightly smaller than the thickness of the insulating layer 44
- FIG. 6C shows a form in which those thicknesses are the same.
- the light emitting element 10 tends to be inclined.
- FIG. 7 shows that the electrode layer film (electrode film) 46 ′ formed on the semiconductor wafer W is not uniform on one semiconductor wafer in the process of manufacturing the light emitting device 10 shown in FIG. 6A. It is a figure explaining the problem which arises by a cause. That is, the film thickness of the electrode film 46 ′ on the semiconductor wafer W tends to be thicker at the center of the semiconductor wafer W and thinner at the edge. This is as described in FIGS. 6B and 6C. In FIG. 7, light emitting elements having different electrode layer 46 thicknesses are indicated by reference numerals 120A and 120B.
- an electrode film 46 ′ having a different inclination may be formed depending on the region on the semiconductor wafer W.
- the electrode film 46 ′ has an inclination as described above, it becomes more difficult to suppress the inclination of the light emitting element 10.
- the light-emitting element including the inclined electrode layer 46 is denoted by reference numerals 120 ⁇ / b> C and 120 ⁇ / b> D.
- FIG. 8A shows a substrate module according to Comparative Example 2.
- the light emitting element 10 of the substrate module according to the comparative example 2 includes an insulating layer 54 and an electrode layer 56 having substantially the same area when viewed in the stacking direction.
- 8B to 8D are enlarged views of main parts of the substrate module of FIG. 8A, respectively.
- the width of the electrode layer 56 may differ from the width of the insulating layer 54 due to manufacturing errors. Since the insulating layer 54 according to these examples is not a surface bearing structure (the exposed bottom surface 145 of the insulating layer 14 as illustrated in FIG. 3B) as in the present technology, the contact angle of the solder 23 to the light emitting element 130 is set. Variations are likely to occur. Therefore, depending on the contact angle, the light emitting element 130 is likely to be inclined.
- FIG. 9 is a diagram for explaining the behavior when the solder 23 melts in the reflow process.
- FIG. 10 shows a state in which the light emitting element 120 according to the comparative example 1 is bonded to the substrate 50 by reflow of the solder 23.
- the width of the solder 23 width in the direction parallel to the mounting surface of the substrate 50
- the shape of the molten solder 23 is a dome shape as shown in the left figure.
- the light emitting element 120 is pushed up at a stretch to become.
- the molten solder 23 extends beyond the side surface of the insulating film 44 and spreads to the side surface of the semiconductor layer 12. As a result, the possibility that the light emitting element 120 tilts increases.
- FIG. 11 shows a state in which the light emitting element 130 according to the comparative example 2 is joined to the substrate 50 by reflow of the solder 23 as in FIG.
- the bonding operation in this case also exhibits the same behavior as in the case of FIG. 10, and the possibility that the light emitting element 130 tilts increases.
- FIG. 12 shows a state in which the light emitting element 10 according to the present technology is bonded to the substrate 50 by reflow of the solder 23.
- the solder 23 When the solder 23 is in a solidified state, the solder 23 and the insulating layer 14 are separated from each other.
- the solder 23 is melted, the molten solder 23 climbing up to the electrode layer 16 having high wettability is received by the region 145 a exposed on the entire outer peripheral side of the electrode layer 16. In this way, the insulating layer 14 can stop the molten solder 23. Thereby, the light emitting element 10 can maintain a horizontal state without inclining.
- the weight of the light emitting element is very light. Therefore, if the wettability of the solder which is a metal bonding material is slightly reduced (for example, if the thickness of Au in the electrode layer 16 is reduced), solder bonding becomes difficult. For example, in a manufacturing process, when a plurality of light-emitting elements continuously bonded on a semiconductor wafer are separately etched for each light-emitting element, when an electrode is used as a mask, the electrode layer is etched and thinned.
- the Au when Au is used for the lowermost layer of the electrode layer (the layer closest to the substrate side), the Au may be lost by etching. In this case, solder bonding becomes difficult as described above. It is also conceivable that Au peeled off by etching adheres to the side surface of the insulating layer or the side surface of the semiconductor. In this case, in the solder reflow process, there is a possibility that the molten solder travels along the Au and spreads to the side surface of the semiconductor. In this case, as described above, the light emitting element may be inclined with respect to the substrate. As a result, there is a risk that the yield will decrease.
- the Au layer is excessively thick to make the electrode layer 16 have high solder wettability, Au diffuses into the solder (Sn), and a brittle AuSn alloy IMC (Inner Metallic Compound) grows. To do. That is, a bridge (or column) made of an AuSn alloy is formed between the electrode layer Au and the substrate electrode layer in the Sn solder. When the bridge is formed in the solder in this manner, the movement of the light emitting element is hindered in the reflow process, and self alignment becomes difficult.
- FIG. 13 is a photomicrograph of a substrate module having solder on which such an AuSn-IMC bridge is formed. As can be seen from this photograph, if the Au thickness is too thick, bridges made of AuSn alloy are excessively formed, and the light emitting element may be fixed in an inclined state. As a result of investigation by the inventors, it has been found that the upper limit of the thickness of Au that is not adversely affected is 3% or less of the solder by weight.
- the thickness of the oxidation preventing Au layer of the electrode layer 16 is 10 nm or more and 100 nm or less, preferably 20 nm.
- the thickness is 80 nm or less, more preferably 30 nm or more and 70 nm or less, or 40 nm or more and 60 nm or less. Typically, it is about 50 nm.
- a photolithography process instead of a process of separating a plurality of light-emitting elements continuously bonded on a semiconductor wafer by separation etching. That is, by using the resist as a mask, the problem that the electrode material adheres to the side surface of the insulating layer or the side surface of the semiconductor using the electrode as a mask is solved.
- the thickness of the solder is smaller than about 2 ⁇ m, the light emitting element cannot be self-aligned by the above-described AuSn-IMC. This is the same when the solder is made of SnAg-based or SnAgCu-based material. The reason is the reflow temperature. When the reflow process is performed with Sn-based solder, the temperature profile uses substantially the same conditions.
- FIG. 14 is a graph showing an example of a temperature profile of a reflow process using Sn-based solder.
- Solder melts at the highest temperature, for example, around 245 ° C.
- thin Au formed on the surface of the electrode layer of the light emitting element or the substrate electrode layer diffuses into the molten solder, and AuSn-IMC diffuses.
- the diffusion depth is approximately 2 ⁇ m. That is, in order for the light-emitting element 10 according to the present technology to be self-aligned and horizontal, it is desirable that the solder thickness be 2 ⁇ m or more.
- thermo profile shown in FIG. 14 is merely an example, and the present technology may take other temperature profiles.
- FIG. 15 is a graph showing an actual measurement of the relationship between the thickness of the solder 23 and the inclination of the light emitting element 10.
- the length (that is, the width) of one side of the rectangular electrode layer 16 in the light emitting element 10 having a rectangular outer shape was set to 13 ⁇ m.
- the electrode layer 16 was made of Ti, Pt, and Au, and the thicknesses thereof were 0.1 ⁇ m, 0.2 ⁇ m, and 0.05 ⁇ m, respectively.
- the thickness of the solder is preferably half or less of the width of the electrode layer 16 (in this example, 6.5 ⁇ m or less).
- the present technology desirably satisfies the following conditions in order to suppress the inclination of the light emitting element 10.
- the volume of Au provided on the surface layer of the electrode layer 16 is 3% or less of the volume of the solder 23.
- the thickness of the Sn-based solder (solidified state) is 2 ⁇ m or more and 1/2 or less of the width of one side of the electrode layer 16 of the light emitting element 10.
- FIG. 16 is a graph showing the results of the verification, and shows the relationship between the width of the electrode layer 16 (in the case of a rectangle, the length of one side) and the actual inclination.
- the width of the rectangular light emitting element 10 and the width of the insulating layer 14 were fixed at 15 ⁇ m, and the width of the electrode layer 16 was changed. From the experimental results shown in FIG. 16, the effect of the unique structure according to the present technology was confirmed although there was some instability. In other words, it was confirmed that the inclination of the electrode layer 16 tends to increase because the exposed region 145a of the bottom surface 145 of the insulating layer 14 decreases as the width increases beyond a predetermined width (9 ⁇ m in the experiment). .
- FIG. 17 is a cross-sectional view of a component according to another embodiment 1.
- the width (first width) w1 of a region 245a (hereinafter referred to as an exposed bottom surface region) exposed on the entire outer peripheral side of the second layer 26 in the bottom surface 245 of the first layer. Is configured to be wider than the width w2 in the same direction of the non-exposed bottom surface region 245b.
- the exposed bottom surface region 245a of the first layer 24 has a rectangular opening pattern shape when seen in a plan view.
- the alignment accuracy at the time of exposure for forming this opening pattern by photolithography is higher than the alignment accuracy in an apparatus for mounting this component on a substrate.
- the result is that the deviation margin (allowable deviation) of the exposure apparatus having high alignment accuracy is set smaller than the deviation margin of the mounting apparatus having lower alignment accuracy. .
- the deviation margin of the mounting apparatus having low accuracy is increased.
- FIG. 17 is referred to as a cross-sectional view of a component according to another embodiment 2.
- the width w1 of the exposed bottom surface region 245a is larger than the protruding height h1 of the second layer 26 in the protruding direction from the bottom surface of the first layer 24.
- the main body 22 is configured such that the width w1 of the exposed bottom surface region that is unlikely to get wet with the metal bonding material is larger than the protrusion height h1 of the second layer 26 that is highly likely to get wet with the metal bonding material. It is possible to further reduce the possibility that the side surface of the metal is wet with the metal bonding material.
- FIG. 18B is a plan view of a substrate module according to another embodiment 3, and FIG. 18A is a cross-sectional view taken along line AA in FIG. 18B.
- the substrate module includes a substrate 50, an insulating film (film) 5 having openings 5 a and 5 b, a substrate electrode layer (bonding layer) 51, solder patterns (metal bonding materials) 23 a and 23 b, and a light emitting element 10.
- the light emitting element 10 and the substrate electrode layer 51 are connected by solder patterns 23a and 23b provided in the opening 5a.
- the opening shape of the opening 5a of the insulating film 5 has protrusions (for example, four) radially from the center of the opening 5a.
- the solder pattern 23 a has a planar shape substantially the same as the opening shape of the opening 5 a at the opening 5 a of the insulating film 5.
- the light emitting element 10 is fixed to a region corresponding to the central portion of the opening 5a.
- the bottom surface of the light emitting element 10 has a shape such as a polygon of a triangle or more, a circle, an ellipse, and the like. In FIG. 18, it is a rectangle.
- the protrusions of the opening 5a are arranged at substantially equal angles with each other along at least three directions in rotational symmetry from the central part, and the tip thereof is arranged on a circumference centering on the central part, And it has the shape which becomes thin toward the front-end
- substantially equiangular includes an error range of angles within a range in which the protrusion can effectively position the element.
- protrusions For example, 3 to 6 protrusions or more are provided. In FIG. 18B, there are four protrusions.
- the light-emitting element 10 is surely self-aligned with the central portion of the opening 5a. 7).
- the form in which the second layer 26 protrudes from the bottom face 245 side of the first layer 24, and the form in which the entire bottom face 245 is exposed are also within the scope of the present technology. included. That is, in this embodiment, the second layer 26 protrudes from the bottom surface side of the first layer 24 so that the outer peripheral side surface 26b of the second layer 26 protrudes from within the opening 24a of the first layer 24. Yes.
- the light emitting element 10 has been described as an example of the component 20 (see FIGS. 1A to 1C) according to the above embodiment, but the present technology may be applied to a component that constitutes an optical filter, for example.
- the main body may constitute a mirror or a light transmitting part.
- An optical filter such as a color filter or a polarizing filter can be realized by arranging a plurality of components on a substrate in a matrix or zigzag pattern.
- the main body of the component is not limited to the semiconductor layer 12 and may be a metal or a resin. A transparent resin may be used as the resin.
- the first layer 24 is not limited to a material having an electrical insulating function
- the second layer 26 is not limited to a material having a conductive function.
- a metal other than solder may be employed as the metal bonding material.
- Examples of the device using the light emitting element 10 include a display device, a scanner, or a printer.
- the light emitting elements 10 are used in a display device, the light emitting elements 10 are arranged on the substrate so that each light emitting element 10 corresponds to each pixel.
- the plurality of light emitting elements 10 are used in a scanner, a printer, or the like, they are used as light sources for irradiating light for reading and photosensitive.
- this technique can also take the following structures.
- the component according to (1) or (2), The first layer has a non-exposed bottom surface region covered with the second layer other than the exposed bottom surface region.
- the bottom surface of the first layer is seen in a cross section in the stacking direction of the first layer and the second layer, Of the bottom surface of the first layer, the exposed bottom surface region has a first width, The non-exposed bottom surface region has a second width smaller than the first width.
- the main body has a semiconductor material as a main constituent material, The first layer is made of an insulating material; The second layer is an electrode.
- the component according to (7) above, The first layer includes SiO2, SiN, or a poly resin.
- the component according to any one of (6) to (8) A component in which at least the bottom layer of the second layer is made of the Au.
- the component according to (9) above, The volume amount occupied by the Au in the second layer is 3% or less of the volume amount of the metal bonding material.
- the second layer includes Pt or Ni.
- the parts are A body having a bottom surface; A first layer provided on a bottom surface of the main body and having a bottom surface; A single second layer that is bonded to the metal bonding material and is physically integrated, and has higher wettability than the first layer with respect to the metal bonding material in a molten state.
- a second layer protruding from the bottom surface side of the first layer so that at least a part of the bottom surface of the first layer is exposed on the entire outer peripheral side of the second layer. Having a substrate module.
- the board module according to (12) A component projection region in which the component is projected onto the substrate is disposed on the inner side of an outer peripheral edge of a contact region where the bonding layer and the metal bonding material are in contact with each other.
- the film further includes an opening facing the bonding layer, and the opening shape of the opening has a protrusion radially from the center,
- the metal bonding material is provided in the opening of the film, and is configured in a planar shape substantially the same as the opening shape of the opening,
- the component is fixed to a region corresponding to the central portion of the metal bonding material,
- the protrusions of the opening of the membrane are arranged at substantially equal angles to each other along at least three directions in rotational symmetry from the central portion, and the tip thereof is a circumference centered on the central portion.
- a substrate module in which the metal bonding material provided in the opening of the film is connected to the bonding layer is connected to the bonding layer.
- the parts are A body having a bottom surface; A first layer provided on a bottom surface of the main body and having a bottom surface; A single second layer that is bonded to the metal bonding material and is physically integrated, and has higher wettability than the first layer with respect to the metal bonding material in a molten state.
- a second layer protruding from the bottom surface side of the first layer so that at least a part of the bottom surface of the first layer is exposed on the entire outer peripheral side of the second layer.
- SYMBOLS 5 Insulating film 5a ... Opening part 10 ... Light emitting element 12 ... Semiconductor layer 14 ... Insulating layer 16 ... Electrode layer 20, 20A ... Component 22 ... Main body 23a ... Solder pattern 23 ... Solder 24 ... 1st layer 26 ... 2nd Layer 50 ... Substrate 51 ... Substrate electrode layer (bonding layer) DESCRIPTION OF SYMBOLS 100 ... Substrate module 145, 245 ... Bottom face 145a, 245a ... Exposed area of bottom face (exposed bottom area) 145b, 245b ... non-exposed bottom region
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
前記本体は、底面を有する。
前記第1の層は、前記本体の底面に設けられ、底面を有する。
前記第2の層は、基板上の金属接合材に接合され物理的に一体に設けられた第2の層である。前記第2の層は、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられている。
なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。
(1)電極層16のうち、当該電極層16の表層に設けられたAuの体積量が、半田23の体積量の3%以下であること。
(2)Sn系の半田(固化状態)の厚さは、2μm以上であり、かつ、発光素子10の電極層16の一辺の幅の1/2以下であること。
7.他の種々の実施形態
(1)
底面を有する本体と、
前記本体の底面に設けられ、底面を有する第1の層と、
基板上の金属接合材に接合され物理的に一体に設けられた第2の層であって、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられた第2の層と
を具備する部品。
(2)
前記(1)に記載の部品であって、
前記第1の層が、前記金属接合材に対して非濡れ性を持つように構成される
部品。
(3)
前記(1)または(2)に記載の部品であって、
前記第1の層は、前記露出した底面領域以外の、前記第2の層で覆われた非露出底面領域を有する
部品。
(4)
前記(3)に記載の部品であって、
前記第1の層の底面は、前記第1の層および前記第2の層の積層方向の断面で見て、
前記第1の層の底面のうち前記露出した底面領域は、第1の幅でなり、
前記非露出底面領域は、前記第1の幅より小さい第2の幅でなる
部品。
(5)
前記(3)または(4)に記載の部品であって、
前記第1の層の底面は、前記第1の層および前記第2の層の積層方向の断面で見て、
前記第1の層の底面のうち前記露出した底面領域の幅は、前記第2の層の、前記第1の層の底面からの突出方向における突出高さより大きく構成されている
部品。
(6)
前記(1)に記載の部品であって、
前記本体は、半導体材料を主要構成材料として有し、
前記第1の層は、絶縁材料でなり、
前記第2の層は、電極である
部品。
(7)
前記(6)に記載の部品であって、
前記第1の層が、前記金属接合材に対して非濡れ性を持つように構成される
部品。
(8)
前記(7)記載の部品であって、
前記第1の層は、SiO2、SiN、または、ポリ系樹脂を含む
部品。
(9)
前記(6)から(8)のうちいずれか1項に記載の部品であって、
前記第2の層の少なくとも底面の層が、前記Auにより構成される
部品。
(10)
前記(9)に記載の部品であって、
前記第2の層のうち前記Auが占める体積量が、前記金属接合材の体積量の3%以下である
部品。
(11)
前記(6)から(10)のうちいずれか1項に記載の部品であって、
前記第2の層は、Pt、またはNiを含む
部品。
(12)
部品と、
接合層を有する基板と、
前記部品を前記基板の前記接合層に接続する金属接合材とを具備し、
前記部品は、
底面を有する本体と、
前記本体の底面に設けられ、底面を有する第1の層と、
前記金属接合材に接合され物理的に一体に設けられた単一の第2の層であって、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられた第2の層とを有する
基板モジュール。
(13)
前記(12)に記載の基板モジュールであって、
前記部品を前記基板に投射した部品投射領域が、前記接合層と前記金属接合材とが接触する接触領域の外周縁より内側に配置される
基板モジュール。
(14)
前記(12)に記載の基板モジュールであって、
前記接合層に対向して開口部を有するとともに、前記開口部の開口形状が中央部から放射状に突起部を有してなる膜をさらに具備し、
前記金属接合材は、前記膜の前記開口部に設けられた、前記開口部の開口形状と略同一の平面形状で構成され、
前記部品は、前記金属接合材の前記中央部に対応する領域に固定され、
前記膜の開口部の前記突起部は、前記中央部から回転対称に少なくとも3方向に沿って互いに実質的に等角度を保って配置されるとともに、その先端が前記中央部を中心とした円周上に配置され、かつ前記先端に向かって細くなる形状を有し、
前記膜の開口部内に設けられた前記金属接合材と、前記接合層とが接続されている
基板モジュール。
(15)
前記(12)から(14)のうちいずれか1項に記載の基板モジュールであって、
前記金属接合材の厚さが、2μm以上であり、かつ、前記部品の前記第2の層の幅の1/2以下である
基板モジュール。
(16)
部品と、
接合層を有する基板と、
前記部品を前記基板の前記接合層に接続する金属接合材とを具備し、
前記部品は、
底面を有する本体と、
前記本体の底面に設けられ、底面を有する第1の層と、
前記金属接合材に接合され物理的に一体に設けられた単一の第2の層であって、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられた第2の層とを有する
機器。
(17)
部品と、
接合層を有する基板と、
前記部品を前記基板の前記接合層に接続する金属接合材とを具備し、
前記部品は、
底面を有する本体と、
前記本体の底面に設けられ、底面を有する第1の層と、
前記金属接合材に接合され物理的に一体に設けられた単一の第2の層であって、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられた第2の層とを有する
光学フィルタ。
5a…開口部
10…発光素子
12…半導体層
14…絶縁層
16…電極層
20、20A…部品
22…本体
23a…半田パターン
23…半田
24…第1の層
26…第2の層
50…基板
51…基板電極層(接合層)
100…基板モジュール
145、245…底面
145a、245a…底面の露出した領域(露出底面領域)
145b、245b…非露出底面領域
Claims (17)
- 底面を有する本体と、
前記本体の底面に設けられ、底面を有する第1の層と、
基板上の金属接合材に接合され物理的に一体に設けられた第2の層であって、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられた第2の層と
を具備する部品。 - 請求項1に記載の部品であって、
前記第1の層が、前記金属接合材に対して非濡れ性を持つように構成される
部品。 - 請求項1に記載の部品であって、
前記第1の層は、前記露出した底面領域以外の、前記第2の層で覆われた非露出底面領域を有する
部品。 - 請求項3に記載の部品であって、
前記第1の層の底面は、前記第1の層および前記第2の層の積層方向の断面で見て、
前記第1の層の底面のうち前記露出した底面領域は、第1の幅でなり、
前記非露出底面領域は、前記第1の幅より小さい第2の幅でなる
部品。 - 請求項3に記載の部品であって、
前記第1の層の底面は、前記第1の層および前記第2の層の積層方向の断面で見て、
前記第1の層の底面のうち前記露出した底面領域の幅は、前記第2の層の、前記第1の層の底面からの突出方向における突出高さより大きく構成されている
部品。 - 請求項1に記載の部品であって、
前記本体は、半導体材料を主要構成材料として有し、
前記第1の層は、絶縁材料でなり、
前記第2の層は、電極である
部品。 - 請求項6に記載の部品であって、
前記第1の層が、前記金属接合材に対して非濡れ性を持つように構成される
部品。 - 請求項7に記載の部品であって、
前記第1の層は、SiO2、SiN、または、ポリ系樹脂を含む
部品。 - 請求項6に記載の部品であって、
前記第2の層の少なくとも底面の層が、前記Auにより構成される
部品。 - 請求項9に記載の部品であって、
前記第2の層のうち前記Auが占める体積量が、前記金属接合材の体積量の3%以下である
部品。 - 請求項6に記載の部品であって、
前記第2の層は、Pt、またはNiを含む
部品。 - 部品と、
接合層を有する基板と、
前記部品を前記基板の前記接合層に接続する金属接合材とを具備し、
前記部品は、
底面を有する本体と、
前記本体の底面に設けられ、底面を有する第1の層と、
前記金属接合材に接合され物理的に一体に設けられた単一の第2の層であって、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられた第2の層とを有する
基板モジュール。 - 請求項12に記載の基板モジュールであって、
前記部品を前記基板に投射した部品投射領域が、前記接合層と前記金属接合材とが接触する接触領域の外周縁より内側に配置される
基板モジュール。 - 請求項12に記載の基板モジュールであって、
前記接合層に対向して開口部を有するとともに、前記開口部の開口形状が中央部から放射状に突起部を有してなる膜をさらに具備し、
前記金属接合材は、前記膜の前記開口部に設けられた、前記開口部の開口形状と略同一の平面形状で構成され、
前記部品は、前記金属接合材の前記中央部に対応する領域に固定され、
前記膜の開口部の前記突起部は、前記中央部から回転対称に少なくとも3方向に沿って互いに実質的に等角度を保って配置されるとともに、その先端が前記中央部を中心とした円周上に配置され、かつ前記先端に向かって細くなる形状を有し、
前記膜の開口部内に設けられた前記金属接合材と、前記接合層とが接続されている
基板モジュール。 - 請求項12に記載の基板モジュールであって、
前記金属接合材の厚さが、2μm以上であり、かつ、前記部品の前記第2の層の幅の1/2以下である
基板モジュール。 - 部品と、
接合層を有する基板と、
前記部品を前記基板の前記接合層に接続する金属接合材とを具備し、
前記部品は、
底面を有する本体と、
前記本体の底面に設けられ、底面を有する第1の層と、
前記金属接合材に接合され物理的に一体に設けられた単一の第2の層であって、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられた第2の層とを有する
機器。 - 部品と、
接合層を有する基板と、
前記部品を前記基板の前記接合層に接続する金属接合材とを具備し、
前記部品は、
底面を有する本体と、
前記本体の底面に設けられ、底面を有する第1の層と、
前記金属接合材に接合され物理的に一体に設けられた単一の第2の層であって、溶融状態にある前記金属接合材に対して、前記第1の層の濡れ性より高い濡れ性を持ち、前記第2の層の全外周側で前記第1の層の底面の少なくとも一部が露出するように、前記第1の層の底面側から突出して設けられた第2の層とを有する
光学フィルタ。
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US15/752,271 US10483438B2 (en) | 2015-09-04 | 2016-07-22 | Component, substrate module, apparatus, and optical filter |
CN201680048754.1A CN107924846A (zh) | 2015-09-04 | 2016-07-22 | 部件、基板模块、设备和光学滤波器 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019207984A (ja) * | 2018-05-30 | 2019-12-05 | 住友電工デバイス・イノベーション株式会社 | 半導体装置およびその製造方法 |
JP2021118199A (ja) * | 2020-01-22 | 2021-08-10 | スタンレー電気株式会社 | 深紫外光を発する発光装置及びそれを用いた水殺菌装置 |
US11362024B2 (en) | 2018-05-30 | 2022-06-14 | Sumitomo Electric Device Innovations, Inc. | Semiconductor device and method of manufacturing the same |
Families Citing this family (2)
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DE112020000921A5 (de) * | 2019-02-25 | 2021-11-04 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Kontrollierte benetzung bei der herstellung von elektronischen bauteilen |
JP2021141235A (ja) | 2020-03-06 | 2021-09-16 | 株式会社東芝 | 半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258459A (ja) * | 2007-04-06 | 2008-10-23 | Toshiba Corp | 発光装置及びその製造方法 |
JP2010171047A (ja) * | 2009-01-20 | 2010-08-05 | Mitsubishi Electric Corp | 半導体レーザ装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7211833B2 (en) * | 2001-07-23 | 2007-05-01 | Cree, Inc. | Light emitting diodes including barrier layers/sublayers |
US20050194584A1 (en) * | 2003-11-12 | 2005-09-08 | Slater David B.Jr. | LED fabrication via ion implant isolation |
JP4709563B2 (ja) * | 2005-03-31 | 2011-06-22 | 株式会社東芝 | 半導体装置の製造方法 |
JP2010034130A (ja) * | 2008-07-25 | 2010-02-12 | Sumitomo Electric Ind Ltd | 面発光装置およびその製造方法 |
JP4888473B2 (ja) * | 2008-11-20 | 2012-02-29 | ソニー株式会社 | 実装基板 |
JP2010245161A (ja) * | 2009-04-02 | 2010-10-28 | Denso Corp | 電子装置およびその製造方法 |
JP2011223035A (ja) * | 2011-07-25 | 2011-11-04 | Toshiba Corp | 半導体装置 |
-
2016
- 2016-07-22 US US15/752,271 patent/US10483438B2/en active Active
- 2016-07-22 JP JP2017537198A patent/JP6969379B2/ja active Active
- 2016-07-22 CN CN201680048754.1A patent/CN107924846A/zh active Pending
- 2016-07-22 WO PCT/JP2016/003430 patent/WO2017037996A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258459A (ja) * | 2007-04-06 | 2008-10-23 | Toshiba Corp | 発光装置及びその製造方法 |
JP2010171047A (ja) * | 2009-01-20 | 2010-08-05 | Mitsubishi Electric Corp | 半導体レーザ装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019207984A (ja) * | 2018-05-30 | 2019-12-05 | 住友電工デバイス・イノベーション株式会社 | 半導体装置およびその製造方法 |
US11362024B2 (en) | 2018-05-30 | 2022-06-14 | Sumitomo Electric Device Innovations, Inc. | Semiconductor device and method of manufacturing the same |
JP7095844B2 (ja) | 2018-05-30 | 2022-07-05 | 住友電工デバイス・イノベーション株式会社 | 半導体装置およびその製造方法 |
JP2021118199A (ja) * | 2020-01-22 | 2021-08-10 | スタンレー電気株式会社 | 深紫外光を発する発光装置及びそれを用いた水殺菌装置 |
JP7397687B2 (ja) | 2020-01-22 | 2023-12-13 | スタンレー電気株式会社 | 深紫外光を発する発光装置及びそれを用いた水殺菌装置 |
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US20180240942A1 (en) | 2018-08-23 |
JP6969379B2 (ja) | 2021-11-24 |
JPWO2017037996A1 (ja) | 2018-06-21 |
CN107924846A (zh) | 2018-04-17 |
US10483438B2 (en) | 2019-11-19 |
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