WO2017028328A1 - 驱动电路以及移位寄存电路 - Google Patents

驱动电路以及移位寄存电路 Download PDF

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Publication number
WO2017028328A1
WO2017028328A1 PCT/CN2015/088020 CN2015088020W WO2017028328A1 WO 2017028328 A1 WO2017028328 A1 WO 2017028328A1 CN 2015088020 W CN2015088020 W CN 2015088020W WO 2017028328 A1 WO2017028328 A1 WO 2017028328A1
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Prior art keywords
circuit
gate
pulse
inverter
transmission
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English (en)
French (fr)
Inventor
郝思坤
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/888,427 priority Critical patent/US9858876B2/en
Publication of WO2017028328A1 publication Critical patent/WO2017028328A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3625—Control of matrices with row and column drivers using a passive matrix using active addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a driving circuit and a shift register circuit.
  • the GOA (Gate Driver OnArray) circuit is a driving method in which a gate scan driving circuit is fabricated on an Array substrate by using an Array process of a conventional liquid crystal display to realize progressive scanning. It has the advantages of reduced production costs and a narrow bezel design for use with a variety of displays.
  • the GOA circuit has two basic functions: the first is to input the gate drive pulse, drive the gate line in the panel, open the TFT (Thin Film Transistor) in the display area, and perform the pixel on the gate line. Charging; the second is shift register, after the output of the nth gate drive pulse is completed, the output of n+1 gate drive pulses can be performed by clock control, and then transmitted.
  • the GOA circuit includes a pull-up circuit, a pull-up control circuit, a pull-down circuit, a pull-down control circuit, and an increase in potential rise.
  • Boost circuit Specifically, the pull-up circuit is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal low to low after the output of the scan signal, that is, the potential of the gate of the thin film transistor is pulled low to a low potential;
  • the pull-down hold circuit is responsible for the signal of the scan signal and the pull-up circuit (commonly called For Q point) to remain in the off state (ie set negative potential), there are usually two pull-down holding circuits alternated.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • the LTPS Low Temperature Poly-silicon
  • CMOS Complementary Metal Oxide Semiconductor
  • the embodiment of the invention provides a driving circuit and a shift register circuit, which are suitable for a CMOS process, and have low power consumption and wide noise tolerance.
  • the invention provides a driving circuit comprising a plurality of cascaded shift register circuits, each shift register circuit comprising a clock control transmission circuit and a latch circuit, wherein the clock control transmission circuit is triggered by the first clock pulse
  • the driving pulse of the Q point of the first two stages is transmitted to the latch circuit, and is latched by the latch circuit, and the latch circuit is further triggered by the second clock pulse to output the gate driving pulse and the driving pulse of the Q point, and the clock control
  • the transmission circuit and the NAND gate latch circuit are respectively triggered by a rising edge;
  • the latch circuit includes at least a first transmission gate, a second transmission gate, a first inverter and a second inverter, and a NOR gate, wherein the first transmission The first control end of the door and the second control end of the second transmission gate are connected to the output end of the clock control transmission circuit, the input end of the first transmission gate is connected to the Q point of the first two stages, and the second control end of the first transmission door is The first control end of the second
  • the clock control transmission circuit inverts the first clock pulse during the transmission of the first clock pulse.
  • the output end of the second inverter outputs a driving pulse at the Q point.
  • the latch circuit further comprises a multi-stage inverter circuit connected to the output of the NOR gate.
  • the multi-stage inverter circuit includes three inverters.
  • the input terminal of the first transfer gate is connected to the STV pulse.
  • the present invention also provides a driving circuit comprising a plurality of cascaded shift register circuits, each shift register circuit comprising a clock control transmission circuit and a latch circuit, wherein the clock control transmission circuit is triggered by the first clock pulse The driving pulse of the Q point of the first two stages is transmitted to the latch circuit, and is latched by the latch circuit, and the latch circuit is further triggered by the second clock pulse to output the gate driving pulse and the driving pulse of the Q point.
  • the clock control transmission circuit and the NAND gate latch circuit are respectively triggered by rising edges.
  • the latch circuit includes at least a first transmission gate, a second transmission gate, a first inverter, and a a second inverter and a NOR gate, wherein the first control end of the first transmission gate and the second control end of the second transmission gate are connected to the output end of the clock control transmission circuit, and the input end of the first transmission gate is connected to the first two stages At point Q, the second control end of the first transmission gate and the first control end of the second transmission gate are both connected to the first clock pulse, and the output end of the first transmission gate is connected to the input end of the second transmission gate and the first inverter
  • the input end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter and the output end of the second transmission gate are connected to the first input end of the NOR gate, A second input of the NOR gate is coupled to the second clock pulse.
  • the clock control transmission circuit inverts the first clock pulse during the transmission of the first clock pulse.
  • the output end of the second inverter outputs a driving pulse at the Q point.
  • the latch circuit further comprises a multi-stage inverter circuit connected to the output of the NOR gate.
  • the multi-stage inverter circuit includes three inverters.
  • the input terminal of the first transfer gate is connected to the STV pulse.
  • the present invention also provides a shift register circuit including a clock control transmission circuit and a latch circuit, wherein the clock control transmission circuit is triggered by the first clock pulse to transmit the drive pulses of the first two stages of the Q point to the latch circuit. And latched by the latch circuit, the latch circuit is further triggered by the second clock pulse to output the gate drive pulse and the drive pulse of the Q point.
  • the latch circuit further comprises a multi-stage inverter circuit connected to the output of the NOR gate.
  • the beneficial effects of the present invention are: the invention is triggered by the first clock pulse of the clock signal by the clock control transmission circuit, and the driving pulse of the Q point of the first two stages is transmitted to the latch circuit, and is performed by the latch circuit.
  • the latching circuit is further triggered by the second clock pulse to output a driving pulse, which can be applied to a CMOS process, and has low power consumption and wide noise margin.
  • FIG. 1 is a schematic structural view of a driving circuit according to an embodiment of the present invention.
  • Figure 2 is a circuit diagram of the shift register circuit of Figure 1;
  • Figure 3 is a circuit diagram of the shift register circuit of the first stage of Figure 1;
  • Figure 4 is a circuit diagram of the shift register circuit of the second stage of Figure 1;
  • Figure 5 is an ideal timing diagram of the shift register circuit of the first stage and the shift register circuit of the second stage of Figure 1;
  • Figure 6 is a circuit diagram of the m-th stage shift register circuit of Figure 1;
  • Figure 7 is a circuit diagram of the shift register circuit of the m+1th stage of Figure 1;
  • Figure 8 is a circuit diagram of the shift register circuit of the m+2th stage of Figure 1;
  • Figure 9 is a circuit diagram of the shift register circuit of the m+3th stage of Figure 1;
  • Fig. 10 is a timing chart showing the simulation of the driving circuit of the embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention.
  • the driving circuit 1 disclosed in this embodiment includes a plurality of shift register circuits 10 arranged in cascade, each shift register circuit 10 includes a clock control transmission circuit 11 and a NOR gate latch circuit 12,
  • the clock control transmission circuit 11 is triggered by the first clock pulse to transmit the drive pulse Q n-2 of the first two stages to the latch circuit 12, and is latched by the latch circuit 12, and the latch circuit 12 is further
  • the second clock pulse is triggered to output a drive pulse.
  • the clock control transmission circuit 11 inverts the first clock pulse during the transmission of the first clock pulse.
  • the clock control transmission circuit 11 and the latch circuit 12 are respectively triggered by rising edges.
  • the signal transmission is controlled by the clock control transmission circuit 11, and the signal is latched by the latch circuit 12, which can be applied to the CMOS process, and has low power consumption and wide noise tolerance.
  • the clock control transmission circuit 11 is preferably an inverter.
  • the latch circuit 12 includes at least a first transmission gate 121, a second transmission gate 122, a first inverter 123, The second inverter 124, the NOR gate 125 and the multi-stage inverter circuit 126, wherein the first control end of the first transmission gate 123 and the second control end of the second transmission gate 122 are connected to the output end of the clock control transmission circuit 11.
  • the input end of the first transmission gate 121 is connected to the Q point Q n-2 of the first two stages, and the second control end of the first transmission gate 121 and the first control end of the second transmission gate 122 are connected to the first clock pulse CK1,
  • the output end of the first transmission gate 121 is connected to the input end of the second transmission gate 122 and the input end of the first inverter 123, and the output end of the first inverter 123 is connected to the input end of the second inverter 124.
  • the output of the second inverter 124 and the output of the second transmission gate 122 are both connected to the first input of the NOR gate 125, and the second input of the NOT gate 125 is connected to the second clock pulse CK3.
  • the multi-stage inverter circuit 126 is connected to the output of the NOR gate 125 to boost the driving capability of the driving circuit 1; the multi-stage inverting circuit 126 preferably includes three inverters arranged in series.
  • the output terminal of the second inverter 124 outputs the driving pulse Q n at the Q point, and the output terminal of the multi-stage inverter circuit 126 outputs the driving pulse G n , n is an integer greater than or equal to 1.
  • the drive circuit 1 includes a shift register circuit 10 of the initial stage and a shift register circuit 10 of a general stage.
  • the shift register circuit 10 of the initial stage includes a shift register circuit 10 of the first stage and a shift register circuit 10 of the second stage.
  • the first clock pulse is the clock pulse CK1
  • the second clock pulse is the clock pulse CK3
  • the input end of the first transmission gate 121 is connected to the STV pulse
  • the second The output terminal of the inverter 124 outputs the drive pulse Q 1 of the Q point of the first stage
  • the output terminal of the multi-stage inverter circuit 126 outputs the drive pulse G 1 of the first stage.
  • the first clock pulse is the clock pulse CK2
  • the second clock pulse is the clock pulse CK4
  • the input end of the first transmission gate 121 is connected to the STV pulse
  • the second The output terminal of the inverter 124 outputs the drive pulse Q2 of the Q-point of the second stage
  • the output terminal of the multi-stage inverter circuit 126 outputs the drive pulse G 2 of the second stage.
  • the STV pulse is preferably an initial control signal.
  • Figure 5 is a theoretical timing diagram of the STV pulse and the clock pulses CK1, CK2, CK3, and CK4, with the ordinate being the voltage and the abscissa being the time.
  • the clock control transmission circuit 11 triggers the first transmission gate 121 to be turned on, the second transmission gate 121 is turned off, and the first transmission gate 121 will STV.
  • the clock control transmission circuit 11 triggers the first transmission gate 121 to be turned on, the second transmission gate 121 is turned off, and the first transmission gate 121 will STV.
  • the pulse is transmitted to the first inverter 123, and then transmitted to the driving pulse Q 2 of the Q point of the second stage through the second inverter 124, the STV pulse is at a high level, and the driving pulse Q 2 at the Q point is also a high level.
  • the clock pulse CK4 When the clock pulse CK4 is a rising edge, the clock pulse CK4 triggers the NOR gate 125 of the driving circuit 1, and the driving pulse Q 2 of the Q point is transmitted to the driving pulse of the second stage through the NOR gate 125 and the multi-stage inverting circuit 126. G 2 , at this time, the drive pulse G 2 is also at a high level.
  • the shift register circuit 10 of the general stage is the shift register circuit 10 of the third stage or the third stage or higher.
  • the first clock pulse is the clock pulse CK1
  • the second clock pulse is the clock pulse CK3
  • the first transmission gate 121 The input terminal is connected to the Q point Q m-2 of the first two stages, the output end of the second inverter 124 outputs the drive pulse Q m of the Q point of the mth stage, and the output end of the multistage inverter circuit 126 outputs the mth stage.
  • Drive pulse G m As shown in FIG. 6, in the shift register circuit 10 of the mth (m is n is greater than or equal to 3) stage, the first clock pulse is the clock pulse CK1, the second clock pulse is the clock pulse CK3, and the first transmission gate 121
  • the input terminal is connected to the Q point Q m-2 of the first two stages, the output end of the second inverter 124 outputs the drive pulse Q m of the Q point of the mth stage, and the output end
  • the first clock pulse is the clock pulse CK2
  • the second clock pulse is the clock pulse CK4
  • the input end of the first transmission gate 121 is connected to the first two stages.
  • the Q point Q m-1 the output end of the second inverter 124 outputs the drive pulse Q m+1 of the qth order of the m+1th stage
  • the output end of the multistage inverter circuit 126 outputs the m+1th stage Drive pulse G m+1 .
  • the first clock pulse is the clock pulse CK3
  • the second clock pulse is the clock pulse CK1
  • the input end of the first transmission gate 121 is connected to the first two stages.
  • the Q point Q m the output end of the second inverter 124 outputs the drive pulse Q m+2 of the qth point of the m+ 2th stage
  • the output end of the multistage inverter circuit 126 outputs the drive pulse of the m+2th stage.
  • G m+2 .
  • the first clock pulse is the clock pulse CK4
  • the second clock pulse is the clock pulse CK2
  • the input end of the first transmission gate 121 is connected to the first two stages.
  • the Q point Q m+1 the output end of the second inverter 124 outputs the driving pulse Q m+3 of the qth point of the m+ 3th stage
  • the output end of the multi-stage inverting circuit 126 outputs the m+3th stage.
  • Drive pulse G m+3 As shown in FIG. 9, in the shift register circuit 10 of the m+3th stage, the first clock pulse is the clock pulse CK4, the second clock pulse is the clock pulse CK2, and the input end of the first transmission gate 121 is connected to the first two stages.
  • the Q point Q m+1 the output end of the second inverter 124 outputs the driving pulse Q m+3 of the qth point of the m+ 3th stage
  • the output end of the multi-stage inverting circuit 126 outputs the m+3th stage
  • FIG. 10 is a schematic timing diagram of a driving circuit according to an embodiment of the present invention, wherein the ordinate is voltage and the abscissa is time.
  • the first simulation 10 stage shift register circuit 10 to the fifth-stage shift register circuit 10 of the pulse STV, clock pulses CK1, CK2, CK3 and a drive pulse CK4, Q points Q 1, Q 2, Timing diagrams of Q 3 , Q 4 and Q 5 and drive pulses G 1 , G 2 , G 3 , G 4 and G 5 , as can be seen from the figure, the analog timing of the NAND latched drive circuit and Figure 5 The theoretical timing in the same is the same.
  • the present invention also provides a NAND latched shift register circuit, or a NAND latch shift register circuit 10 including a clock control transfer circuit 11 and a NOR gate latch circuit 12.
  • the NOR gate latch circuit 12 includes at least a first transfer gate 121, a second transfer gate 122, a first inverter 123, a second inverter 124, a NOT gate 125, and a multi-stage inversion.
  • the circuit 126 wherein the first control end of the first transmission gate 123 and the second control end of the second transmission gate 122 are connected to the output end of the clock control transmission circuit 11, and the input end of the first transmission gate 121 is connected to the Q points of the first two stages.
  • the second control end of the first transmission gate 121 and the first control end of the second transmission gate 122 are connected to the first clock pulse, and the output end of the first transmission gate 121 is connected to the input end of the second transmission gate 122
  • an input end of the first inverter 123, an output end of the first inverter 123 is connected to an input end of the second inverter 124, an output end of the second inverter 124 and an output end of the second transfer gate 122
  • the first input of the NOR gate 125 is connected to the second input of the NOR gate 125.
  • the multi-stage inverter circuit 126 is connected to the output of the NOR gate 125 to boost the driving capability of the driving circuit 1; the multi-stage inverting circuit 126 preferably includes three inverters arranged in series.
  • the output terminal of the second inverter 124 outputs the driving pulse Q n at the Q point, and the output terminal of the multi-stage inverter circuit 126 outputs the driving pulse G n , n is an integer greater than or equal to 1.
  • the driving pulse disclosed in the present invention is preferably a gate driving pulse.
  • the driving circuit of the present invention triggers the first clock pulse of the clock signal through the clock control transmission circuit to transmit the driving pulse of the previous stage to the latch circuit, and is latched by the latch circuit to latch The circuit is further triggered by the second clock pulse to output a driving pulse, which can be applied to a CMOS process, and has low power consumption and wide noise margin.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

本发明公开了一种驱动电路以及移位寄存电路。该驱动电路包括多个级联设置的移位寄存电路，每一移位寄存电路包括时钟控制传输电路以及锁存电路，其中时钟控制传输电路由第一时钟脉冲进行触发将前两级的Q点的驱动脉冲传输至锁存电路，并由锁存电路进行锁存，锁存电路进一步由第二时钟脉冲进行触发进而输出栅极驱动脉冲和Q点的驱动脉冲。通过以上方式，本发明的的驱动电路能够适用于CMOS制程，功耗低、噪声容限宽。

Description

驱动电路以及移位寄存电路 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种驱动电路以及移位寄存电路。
背景技术
GOA(Gate Driver OnArray)电路是利用现有的液晶显示器的Array制程将栅极扫描驱动电路制作在Array基板上，以实现逐行扫描的驱动方式。其具有降低生产成本和窄边框设计的优点，为多种显示器所使用。GOA电路要具有两项基本功能：第一是输入栅极驱动脉冲，驱动面板内的栅极线，打开显示区内的TFT(Thin Film Transistor，薄膜场效应晶体管)，由栅极线对像素进行充电；第二是移位寄存，当第n个栅极驱动脉冲输出完成后，可以通过时钟控制进行n+1个栅极驱动脉冲的输出，并依此传递下去。
GOA电路包括上拉电路(Pull-up circuit)、上拉控制电路(Pull-up control circuit)、下拉电路(Pull-down circuit)、下拉控制电路(Pull-down control circuit)以及负责电位抬升的上升电路(Boost circuit)。具体地，上拉电路主要负责将输入的时钟讯号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速将扫描信号拉低为低电位，即薄膜晶体管的栅极的电位拉低为低电位；下拉保持电路则负责将扫描信号和上拉电路的信号(通常称为Q点)保持在关闭状态(即设定的负电位)，通常有两个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
不同的GOA电路可以使用不同的制程。LTPS(Low Temperature Poly-silicon，低温多晶硅)制程具有高电子迁移率和技术成熟的优点，目前被中小尺寸显示器广泛使用。CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)LTPS制程具有低功耗、电子迁移率高、噪声容限宽等优点。而现有技术的GOA电路的制程不能适用于CMOS制程，功耗高。
发明内容
本发明实施例提供了一种驱动电路以及移位寄存电路，以适用于CMOS制程，功耗低、噪声容限宽。
本发明提供一种驱动电路，其包括多个级联设置的移位寄存电路，每一移位寄存电路包括时钟控制传输电路以及锁存电路，其中时钟控制传输电路由第一时钟脉冲进行触发将前两级的Q点的驱动脉冲传输至锁存电路，并由锁存电路进行锁存，锁存电路进一步由第二时钟脉冲进行触发进而输出栅极驱动脉冲和Q点的驱动脉冲，时钟控制传输电路和或非门锁存电路分别为上升沿触发；锁存电路至少包括第一传输门、第二传输门、第一反相器和第二反相器以及或非门，其中第一传输门的第一控制端和第二传输门的第二控制端连接时钟控制传输电路的输出端，第一传输门的输入端连接前两级的Q点，第一传输门的第二控制端和第二传输门的第一控制端均连接第一时钟脉冲，第一传输门的输出端连接第二传输门的输入端和第一反相器的输入端，第一反相器的输出端与第二反相器的输入端连接，第二反相器的输出端与第二传输门的输出端均连接或非门的第一输入端，或非门的第二输入端连接第二时钟脉冲。
其中，时钟控制传输电路在传输第一时钟脉冲的过程中对第一时钟脉冲进行反相。
其中，第二反相器的输出端输出Q点的驱动脉冲。
其中，锁存电路进一步包括与或非门的输出端连接的多级反相电路。
其中，多级反相电路的包括三个反相器。
其中，在第一级的移位寄存电路和第二级的移位寄存电路中，第一传输门的输入端连接STV脉冲。
本发明还提供一种驱动电路，其包括多个级联设置的移位寄存电路，每一移位寄存电路包括时钟控制传输电路以及锁存电路，其中时钟控制传输电路由第一时钟脉冲进行触发将前两级的Q点的驱动脉冲传输至锁存电路，并由锁存电路进行锁存，锁存电路进一步由第二时钟脉冲进行触发进而输出栅极驱动脉冲和Q点的驱动脉冲。
其中，时钟控制传输电路和或非门锁存电路分别为上升沿触发。
其中，锁存电路至少包括第一传输门、第二传输门、第一反相器和第 二反相器以及或非门，其中第一传输门的第一控制端和第二传输门的第二控制端连接时钟控制传输电路的输出端，第一传输门的输入端连接前两级的Q点，第一传输门的第二控制端和第二传输门的第一控制端均连接第一时钟脉冲，第一传输门的输出端连接第二传输门的输入端和第一反相器的输入端，第一反相器的输出端与第二反相器的输入端连接，第二反相器的输出端与第二传输门的输出端均连接或非门的第一输入端，或非门的第二输入端连接第二时钟脉冲。
其中，时钟控制传输电路在传输第一时钟脉冲的过程中对第一时钟脉冲进行反相。
其中，第二反相器的输出端输出Q点的驱动脉冲。
其中，锁存电路进一步包括与或非门的输出端连接的多级反相电路。
其中，多级反相电路的包括三个反相器。
其中，在第一级的移位寄存电路和第二级的移位寄存电路中，第一传输门的输入端连接STV脉冲。
本发明还提供一种移位寄存电路，其包括时钟控制传输电路以及锁存电路，其中时钟控制传输电路由第一时钟脉冲进行触发将前两级的Q点的驱动脉冲传输至锁存电路，并由锁存电路进行锁存，锁存电路进一步由第二时钟脉冲进行触发进而输出栅极驱动脉冲和Q点的驱动脉冲。
其中，锁存电路进一步包括与或非门的输出端连接的多级反相电路。
通过上述方案，本发明的有益效果是：本发明通过时钟控制传输电路由时钟信号的第一时钟脉冲进行触发将前两级的Q点的驱动脉冲传输至锁存电路，并由锁存电路进行锁存，锁存电路进一步由第二时钟脉冲进行触发进而输出驱动脉冲，能够适用于CMOS制程，功耗低、噪声容限宽。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明实施例的的驱动电路的结构示意图；
图2是图1中的移位寄存电路的电路图；
图3是图1中的第一级的移位寄存电路的电路图；
图4是图1中的第二级的移位寄存电路的电路图；
图5是图1中的第一级的移位寄存电路和第二级的移位寄存电路的理想时序图；
图6是图1中的第m级的移位寄存电路的电路图；
图7是图1中的第m+1级的移位寄存电路的电路图；
图8是图1中的第m+2级的移位寄存电路的电路图；
图9是图1中的第m+3级的移位寄存电路的电路图；
图10是本发明实施例的驱动电路的模拟时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明实施例的驱动电路的结构示意图。如图1所示，本实施例所揭示的驱动电路1包括多个级联设置的移位寄存电路10，每一移位寄存电路10包括时钟控制传输电路11以及或非门锁存电路12，其中时钟控制传输电路11由第一时钟脉冲进行触发将前两级的Q点的驱动脉冲Qn-2传输至锁存电路12，并由锁存电路12进行锁存，锁存电路12进一步由第二时钟脉冲进行触发进而输出驱动脉冲。其中时钟控制传输电路11在传输第一时钟脉冲的过程中对第一时钟脉冲进行反相。并且时钟控制传输电路11和锁存电路12分别为上升沿触发。本发明实施例通过时钟控制传输电路11控制信号传递，通过锁存电路12锁存信号，能够适用于CMOS制程，功耗低、噪声容限宽。
在更具体的实施例中，时钟控制传输电路11优选为反相器，如图2所示，锁存电路12至少包括第一传输门121、第二传输门122、第一反相器123、第二反相器124、或非门125以及多级反相电路126，其中第一传输 门123的第一控制端和第二传输门122的第二控制端连接时钟控制传输电路11的输出端，第一传输门121的输入端连接前两级的Q点Qn-2，第一传输门121的第二控制端和第二传输门122的第一控制端均连接第一时钟脉冲CK1，第一传输门121的输出端连接第二传输门122的输入端和第一反相器123的输入端，第一反相器123的输出端与第二反相器124的输入端连接，第二反相器124的输出端与第二传输门122的输出端均连接或非门125的第一输入端，或非门125的第二输入端连接第二时钟脉冲CK3。多级反相电路126与或非门125的输出端连接，以提升驱动电路1的驱动能力；多级反相电路126优选包括串联设置的三个反相器。其中，第二反相器124的输出端输出Q点的驱动脉冲Qn，多级反相电路126的输出端输出驱动脉冲Gn，n为大于等于1的整数。
驱动电路1包括起始级的移位寄存电路10和一般级的移位寄存电路10。起始级的移位寄存电路10包括第一级的移位寄存电路10和第二级的移位寄存电路10。如图3所示，在第一级的移位寄存电路10中，第一时钟脉冲为时钟脉冲CK1，第二时钟脉冲为时钟脉冲CK3，第一传输门121的输入端连接STV脉冲，第二反相器124的输出端输出第一级的Q点的驱动脉冲Q1，多级反相电路126的输出端输出第一级的驱动脉冲G1。如图4所示，在第二级的移位寄存电路10中，第一时钟脉冲为时钟脉冲CK2，第二时钟脉冲为时钟脉冲CK4，第一传输门121的输入端连接STV脉冲，第二反相器124的输出端输出第二级的Q点的驱动脉冲Q2，多级反相电路126的输出端输出第二级的驱动脉冲G2。其中，STV脉冲优选为起始控制信号。
图5为STV脉冲和时钟脉冲CK1、CK2、CK3以及CK4的理论时序图，纵坐标为电压，横坐标为时间。在第一级的移位寄存电路10中，当时钟脉冲CK1为上升沿时，时钟控制传输电路11触发第一传输门121导通，第二传输门121断开，第一传输门121将STV脉冲传输至第一反相器123，再经过第二反相器124传输到第一级的Q点的驱动脉冲Q1，STV脉冲为高电平，Q点的驱动脉冲Q1也是高电平；当时钟脉冲CK3为上升沿时，时钟脉冲CK3触发驱动电路1的或非门125，Q点的驱动脉冲Q1经过或非门125和多级反相电路126传输到第一级的驱动脉冲G1，此时驱动脉冲G1也是高电平。在第二级的移位寄存电路10中，当时钟脉冲CK2为上升沿时，时钟 控制传输电路11触发第一传输门121导通，第二传输门121断开，第一传输门121将STV脉冲传输至第一反相器123，再经过第二反相器124传输到第二级的Q点的驱动脉冲Q2，STV脉冲为高电平，Q点的驱动脉冲Q2也是高电平；当时钟脉冲CK4为上升沿时，时钟脉冲CK4触发驱动电路1的或非门125，Q点的驱动脉冲Q2经过或非门125和多级反相电路126传输到第二级的驱动脉冲G2，此时驱动脉冲G2也是高电平。
一般级的移位寄存电路10为第三级或第三级以上的移位寄存电路10。如图6所示，在第m(m为n大于或等于3)级的移位寄存电路10中，第一时钟脉冲为时钟脉冲CK1，第二时钟脉冲为时钟脉冲CK3，第一传输门121的输入端连接前两级的Q点Qm-2，第二反相器124的输出端输出第m级的Q点的驱动脉冲Qm，多级反相电路126的输出端输出第m级的驱动脉冲Gm。
如图7所示，在第m+1级的移位寄存电路10中，第一时钟脉冲为时钟脉冲CK2，第二时钟脉冲为时钟脉冲CK4，第一传输门121的输入端连接前两级的Q点Qm-1，第二反相器124的输出端输出第m+1级的Q点的驱动脉冲Qm+1，多级反相电路126的输出端输出第m+1级的驱动脉冲Gm+1。
如图8所示，在第m+2级的移位寄存电路10中，第一时钟脉冲为时钟脉冲CK3，第二时钟脉冲为时钟脉冲CK1，第一传输门121的输入端连接前两级的Q点Qm，第二反相器124的输出端输出第m+2级的Q点的驱动脉冲Qm+2，多级反相电路126的输出端输出第m+2级的驱动脉冲Gm+2。
如图9所示，在第m+3级的移位寄存电路10中，第一时钟脉冲为时钟脉冲CK4，第二时钟脉冲为时钟脉冲CK2，第一传输门121的输入端连接前两级的Q点Qm+1，第二反相器124的输出端输出第m+3级的Q点的驱动脉冲Qm+3，多级反相电路126的输出端输出第m+3级的驱动脉冲Gm+3。
图10为本发明实施例的驱动电路的模拟时序图，纵坐标为电压，横坐标为时间。其中，图10模拟出第一级的移位寄存电路10至第五级的移位寄存电路10的STV脉冲、时钟脉冲CK1、CK2、CK3以及CK4、Q点的驱动脉冲Q1、Q2、Q3、Q4以及Q5和驱动脉冲G1、G2、G3、G4以及G5的时序图，从图中可以看出，或非门锁存的驱动电路的模拟时序与图5中的理论时序相同。
本发明还提供一种或非门锁存的移位寄存电路，或非门锁存的移位寄存电路10包括时钟控制传输电路11以及或非门锁存电路12。如图2所示，或非门锁存电路12至少包括第一传输门121、第二传输门122、第一反相器123、第二反相器124、或非门125以及多级反相电路126，其中第一传输门123的第一控制端和第二传输门122的第二控制端连接时钟控制传输电路11的输出端，第一传输门121的输入端连接前两级的Q点Qn+2，第一传输门121的第二控制端和第二传输门122的第一控制端均连接第一时钟脉冲，第一传输门121的输出端连接第二传输门122的输入端和第一反相器123的输入端，第一反相器123的输出端与第二反相器124的输入端连接，第二反相器124的输出端与第二传输门122的输出端均连接或非门125的第一输入端，或非门125的第二输入端连接第二时钟脉冲。多级反相电路126与或非门125的输出端连接，以提升驱动电路1的驱动能力；多级反相电路126优选包括串联设置的三个反相器。其中，第二反相器124的输出端输出Q点的驱动脉冲Qn，多级反相电路126的输出端输出驱动脉冲Gn，n为大于等于1的整数。
值得注意的是，本发明所揭示的驱动脉冲优选为栅极驱动脉冲。
综上所述，本发明的的驱动电路通过时钟控制传输电路由时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至锁存电路，并由锁存电路进行锁存，锁存电路进一步由第二时钟脉冲进行触发进而输出驱动脉冲，能够适用于CMOS制程，功耗低、噪声容限宽。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种驱动电路，其中，所述驱动电路包括多个级联设置的移位寄存电路，每一所述移位寄存电路包括时钟控制传输电路以及锁存电路，其中所述时钟控制传输电路由第一时钟脉冲进行触发将前两级的Q点的驱动脉冲传输至所述锁存电路，并由所述锁存电路进行锁存，所述锁存电路进一步由第二时钟脉冲进行触发进而输出栅极驱动脉冲和Q点的驱动脉冲，所述时钟控制传输电路和所述锁存电路分别为上升沿触发；
    其中，所述锁存电路至少包括第一传输门、第二传输门、第一反相器和第二反相器以及或非门，其中所述第一传输门的第一控制端和所述第二传输门的第二控制端连接所述时钟控制传输电路的输出端，所述第一传输门的输入端连接所述前两级的Q点，所述第一传输门的第二控制端和所述第二传输门的第一控制端均连接所述第一时钟脉冲，所述第一传输门的输出端连接所述第二传输门的输入端和所述第一反相器的输入端，所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端与所述第二传输门的输出端均连接所述或非门的第一输入端，所述或非门的第二输入端连接所述第二时钟脉冲。
  2. 根据权利要求1所述的驱动电路，其中，所述时钟控制传输电路在传输所述第一时钟脉冲的过程中对所述第一时钟脉冲进行反相。
  3. 根据权利要求1所述的驱动电路，其中，所述第二反相器的输出端输出所述Q点的驱动脉冲。
  4. 根据权利要求1所述的驱动电路，其中，所述锁存电路进一步包括与所述或非门的输出端连接的多级反相电路。
  5. 根据权利要求4所述的驱动电路，其中，所述多级反相电路的包括三个反相器。
  6. 根据权利要求1所述的驱动电路，其中，在第一级的移位寄存电路和第二级的移位寄存电路中，所述第一传输门的输入端连接STV脉冲。
  7. 一种驱动电路，其中，所述驱动电路包括多个级联设置的移位寄存电路，每一所述移位寄存电路包括时钟控制传输电路以及锁存电路，其中所述时钟控制传输电路由第一时钟脉冲进行触发将前两级的Q点的驱动脉 冲传输至所述锁存电路，并由所述锁存电路进行锁存，所述锁存电路进一步由第二时钟脉冲进行触发进而输出栅极驱动脉冲和Q点的驱动脉冲。
  8. 根据权利要求7所述的驱动电路，其中，所述时钟控制传输电路和所述锁存电路分别为上升沿触发。
  9. 根据权利要求7所述的驱动电路，其中，所述锁存电路至少包括第一传输门、第二传输门、第一反相器和第二反相器以及或非门，其中所述第一传输门的第一控制端和所述第二传输门的第二控制端连接所述时钟控制传输电路的输出端，所述第一传输门的输入端连接所述前两级的Q点，所述第一传输门的第二控制端和所述第二传输门的第一控制端均连接所述第一时钟脉冲，所述第一传输门的输出端连接所述第二传输门的输入端和所述第一反相器的输入端，所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端与所述第二传输门的输出端均连接所述或非门的第一输入端，所述或非门的第二输入端连接所述第二时钟脉冲。
  10. 根据权利要求9所述的驱动电路，其中，所述时钟控制传输电路在传输所述第一时钟脉冲的过程中对所述第一时钟脉冲进行反相。
  11. 根据权利要求9所述的驱动电路，其中，所述第二反相器的输出端输出所述Q点的驱动脉冲。
  12. 根据权利要求9所述的驱动电路，其中，所述锁存电路进一步包括与所述或非门的输出端连接的多级反相电路。
  13. 根据权利要求12所述的驱动电路，其中，所述多级反相电路的包括三个反相器。
  14. 根据权利要求9所述的驱动电路，其中，在第一级的移位寄存电路和第二级的移位寄存电路中，所述第一传输门的输入端连接STV脉冲。
  15. 一种移位寄存电路，其中，所述移位寄存电路包括时钟控制传输电路以及锁存电路，其中所述时钟控制传输电路由第一时钟脉冲进行触发将前两级的Q点的驱动脉冲传输至所述锁存电路，并由所述锁存电路进行锁存，所述锁存电路进一步由第二时钟脉冲进行触发进而输出栅极驱动脉冲和Q点的驱动脉冲。
  16. 根据权利要求15所述的移位寄存电路，其中，所述锁存电路进一 步包括与或非门的输出端连接的多级反相电路。
PCT/CN2015/088020 2015-08-18 2015-08-25 驱动电路以及移位寄存电路 Ceased WO2017028328A1 (zh)

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170358266A1 (en) * 2016-06-13 2017-12-14 Wuhan China Star Optoelectronics Technology Co., Ltd. Goa circuit and liquid crystal display
CN106098015B (zh) * 2016-08-23 2018-11-23 武汉华星光电技术有限公司 栅极驱动电路
EP3379814A1 (en) * 2017-03-23 2018-09-26 Christian Rymarenko Converting media using mobile devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104332144A (zh) * 2014-11-05 2015-02-04 深圳市华星光电技术有限公司 液晶显示面板及其栅极驱动电路
CN104537995A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 栅极驱动电路以及移位寄存器
CN104732940A (zh) * 2015-03-30 2015-06-24 深圳市华星光电技术有限公司 Cmos栅极驱动电路
CN105096864A (zh) * 2015-08-05 2015-11-25 深圳市华星光电技术有限公司 驱动电路以及移位寄存电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10250866B4 (de) * 2002-10-31 2009-01-02 Qimonda Ag D-Flipflop
GB2397710A (en) * 2003-01-25 2004-07-28 Sharp Kk A shift register for an LCD driver, comprising reset-dominant RS flip-flops
KR100566814B1 (ko) * 2003-07-24 2006-04-03 엘지.필립스 엘시디 주식회사 쉬프트 레지스터
US7564440B2 (en) * 2005-01-18 2009-07-21 Tpo Displays Corp. Shift register unit
TWM307928U (en) * 2006-07-10 2007-03-11 Silicon Touch Tech Inc Control circuit for automatically generating latch signal to control LED device according to input data signal and clock signal
KR101277975B1 (ko) * 2006-09-07 2013-06-27 엘지디스플레이 주식회사 쉬프트 레지스터 및 이를 구비한 데이터 드라이버,액정표시장치
BRPI1012072A2 (pt) * 2009-06-17 2016-03-22 Sharp Kk registrador de deslocamento, circuito de excitação de vídeo, painel de exibição e dispositivo de exibição
KR101170241B1 (ko) * 2010-06-03 2012-07-31 하이디스 테크놀로지 주식회사 Ｅｐｄ 및 디스플레이 장치의 구동회로
KR101749756B1 (ko) * 2010-10-28 2017-06-22 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 이용한 표시장치
US9136013B2 (en) * 2011-11-25 2015-09-15 Boe Technology Group Co., Ltd. Shift register, gate driver, and display device
CN103594118B (zh) * 2012-08-17 2016-09-07 瀚宇彩晶股份有限公司 液晶显示器及其双向移位寄存装置
CN103198867A (zh) * 2013-03-29 2013-07-10 合肥京东方光电科技有限公司 移位寄存器、栅极驱动电路及显示装置
JP2015201175A (ja) * 2014-03-31 2015-11-12 株式会社ジャパンディスプレイ タッチ駆動装置、タッチ検出装置、及びタッチ検出機能付き表示装置
CN104537996A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 与非门锁存的驱动电路以及与非门锁存的移位寄存器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104332144A (zh) * 2014-11-05 2015-02-04 深圳市华星光电技术有限公司 液晶显示面板及其栅极驱动电路
CN104537995A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 栅极驱动电路以及移位寄存器
CN104732940A (zh) * 2015-03-30 2015-06-24 深圳市华星光电技术有限公司 Cmos栅极驱动电路
CN105096864A (zh) * 2015-08-05 2015-11-25 深圳市华星光电技术有限公司 驱动电路以及移位寄存电路

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