WO2017020332A1 - 驱动电路以及移位寄存电路 - Google Patents

驱动电路以及移位寄存电路 Download PDF

Info

Publication number
WO2017020332A1
WO2017020332A1 PCT/CN2015/086737 CN2015086737W WO2017020332A1 WO 2017020332 A1 WO2017020332 A1 WO 2017020332A1 CN 2015086737 W CN2015086737 W CN 2015086737W WO 2017020332 A1 WO2017020332 A1 WO 2017020332A1
Authority
WO
WIPO (PCT)
Prior art keywords
transmission
signal
circuit
gate
inverter
Prior art date
Application number
PCT/CN2015/086737
Other languages
English (en)
French (fr)
Inventor
郝思坤
Original Assignee
深圳市华星光电技术有限公司
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司, 武汉华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/775,719 priority Critical patent/US9672936B2/en
Publication of WO2017020332A1 publication Critical patent/WO2017020332A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a driving circuit and a shift register circuit.
  • the GOA (Gate Driver On Array) circuit is a driving method in which a gate scanning driving circuit is fabricated on an Array substrate by using an Array process of a conventional liquid crystal display to realize progressive scanning. It has the advantages of reduced production costs and a narrow bezel design for use with a variety of displays.
  • the GOA circuit has two basic functions: the first is to input a gate drive pulse, drive the gate line in the panel, open a TFT (Thin Film Transistor) in the display area, and charge the pixel by the gate line; The second is shift register. When the output of the nth gate drive pulse is completed, the output of n+1 gate drive pulses can be performed by clock control, and then transmitted.
  • the GOA circuit includes a pull-up circuit, a pull-up control circuit, a pull-down circuit, a pull-down control circuit, and an increase in potential rise.
  • Boost circuit Specifically, the pull-up circuit is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal low to low after the output of the scan signal, that is, the potential of the gate of the thin film transistor is pulled low to a low potential;
  • the pull-down hold circuit is responsible for the signal of the scan signal and the pull-up circuit (commonly called For Q point) to remain in the off state (ie set negative potential), there are usually two pull-down holding circuits alternated.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • the LTPS Low Temperature Poly-silicon
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • the embodiment of the invention provides a driving circuit and a shift register circuit, which are suitable for a CMOS process, and have low power consumption and wide noise tolerance.
  • the present invention provides a driving circuit including a plurality of cascaded shift register circuits, each shift register circuit including a transfer gate latch circuit and a signal transfer circuit, wherein the transfer gate latch circuit includes a transfer gate, A clock signal triggers the transmission gate, and the first two stages of the transmission signal are output to the signal transmission circuit through the transmission gate to form a current stage transmission signal; the second clock signal controls the current stage transmission signal to generate a current stage gate drive signal through the signal transmission circuit; The transmission gate latch circuit and the signal transmission circuit are triggered by a rising edge; the first clock signal is offset by one-half of a clock cycle to obtain a second clock signal.
  • the transmission gate latch circuit further includes at least a first inverter, the first clock signal is connected to the first control end of the transmission gate, and the first clock signal is connected to the second control end of the transmission gate via the first inverter.
  • the transmission gate latch circuit further includes a capacitor, a second inverter and a third inverter. One end of the capacitor is connected to the output end of the transmission gate, the other end is grounded, and the second inverter and the third inverter stage are connected. At the output end of the transmission gate, the first two stages of the transmission signal are sequentially outputted to the signal transmission circuit through the transmission gate, the second inverter and the third inverter to form a current stage transmission signal.
  • the signal transmission circuit includes at least one NAND gate, and the second clock signal controls the current stage transmission signal to generate a gate driving signal through the NAND gate.
  • the signal transmission circuit further comprises a multi-stage cascaded inverter circuit connected to the output of the NAND gate.
  • the multi-stage cascaded inverter circuit includes three inverters.
  • the clock signal of the adjacent shift register circuit is shifted by one quarter clock cycle.
  • the present invention also provides a driving circuit comprising a plurality of cascaded shift register circuits, each shift register circuit comprising a transfer gate latch circuit and a signal transfer circuit, wherein the transfer gate latch circuit comprises a transfer gate,
  • the first clock signal triggers the transmission gate, and the first two stages of the transmission signal are output to the signal transmission circuit through the transmission gate to form a current stage transmission signal; and the second clock signal controls the current stage transmission signal to generate the current stage gate drive signal through the signal transmission circuit.
  • the transmission gate latch circuit and the signal transmission circuit are triggered by rising edges.
  • the transmission gate latch circuit further includes at least a first inverter, the first clock signal is connected to the first control end of the transmission gate, and the first clock signal is connected to the second control end of the transmission gate via the first inverter.
  • the transmission gate latch circuit further includes a capacitor, a second inverter and a third inverter. One end of the capacitor is connected to the output end of the transmission gate, the other end is grounded, and the second inverter and the third inverter stage are connected. At the output end of the transmission gate, the first two stages of the transmission signal pass through the transmission gate, the second inverter and the third inverter output in turn. To the signal transmission circuit, the current level transmission signal is formed.
  • the signal transmission circuit includes at least one NAND gate, and the second clock signal controls the current stage transmission signal to generate a gate driving signal through the NAND gate.
  • the signal transmission circuit further comprises a multi-stage cascaded inverter circuit connected to the output of the NAND gate.
  • the multi-stage cascaded inverter circuit includes three inverters.
  • the first clock signal is offset by one-half of a clock cycle to obtain a second clock signal.
  • the clock signal of the adjacent shift register circuit is shifted by one quarter clock cycle.
  • the present invention also provides a shift register circuit including a transfer gate latch circuit and a signal transfer circuit, wherein the first clock signal triggers the transfer gate latch circuit to output the first two stages of the transfer signal to the signal through the transfer gate latch circuit
  • the transmission circuit forms a current stage transmission signal; the second clock signal controls the current stage transmission signal to generate a current stage gate drive signal through the signal transmission circuit.
  • the transmission gate latch circuit further includes at least a first inverter, the first clock signal is connected to the first control end of the transmission gate, and the first clock signal is connected to the second control end of the transmission gate via the first inverter.
  • the transmission gate latch circuit further includes a capacitor, a second inverter and a third inverter. One end of the capacitor is connected to the output end of the transmission gate, the other end is grounded, and the second inverter and the third inverter stage are connected. At the output end of the transmission gate, the first two stages of the transmission signal are sequentially outputted to the signal transmission circuit through the transmission gate, the second inverter and the third inverter to form a current stage transmission signal.
  • the signal transmission circuit includes at least one NAND gate, and the second clock signal controls the current stage transmission signal to generate a gate driving signal through the NAND gate.
  • the present invention has the beneficial effects that the present invention constitutes a driving circuit by a plurality of cascaded shift register circuits, each of which includes a transmission gate latch circuit and a signal transmission circuit, wherein the transfer gate latch
  • the circuit includes a transmission gate, the first clock signal triggers the transmission gate, and the first two stages of the transmission signal are output to the signal transmission circuit through the transmission gate to form a current stage transmission signal; the second clock signal controls the current stage transmission signal to generate the current through the signal transmission circuit.
  • the gate drive signal can be applied to CMOS processes with low power consumption and wide noise margin.
  • FIG. 1 is a schematic structural view of a driving circuit according to an embodiment of the present invention.
  • Figure 2 is a circuit diagram of the shift register circuit of Figure 1;
  • Figure 3 is a circuit diagram of the shift register circuit of the first stage of Figure 1;
  • Figure 4 is a circuit diagram of the shift register circuit of the second stage of Figure 1;
  • Figure 5 is a timing diagram of the shift register circuit of the first stage and the shift register circuit of the second stage of Figure 1;
  • Figure 6 is a circuit diagram of the m-th stage shift register circuit of Figure 1;
  • Figure 7 is a circuit diagram of the shift register circuit of the m+1th stage of Figure 1;
  • Figure 8 is a circuit diagram of the shift register circuit of the m+2th stage of Figure 1;
  • Figure 9 is a circuit diagram of the shift register circuit of the m+3th stage of Figure 1;
  • Fig. 10 is a timing chart showing the simulation of the driving circuit of the embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention.
  • the drive circuit 1 includes a plurality of cascaded shift register circuits 10, each shift register circuit 10 includes a transfer gate latch circuit 11 and a signal transfer circuit 12, wherein the transfer gate latch circuit 11 includes a transmission gate, the first clock signal triggers the transmission gate, and the first two stages of the transmission signal Q n-2 are output to the signal transmission circuit 12 through the transmission gate to form a current stage transmission signal Q n ; the second clock signal controls the current stage transmission signal Q
  • the current stage gate drive signal G n is generated by the signal transmission circuit 12.
  • the transmission gate latch circuit 11 and the signal transmission circuit 12 are respectively triggered by rising edges.
  • the signal is latched by the transmission gate latch circuit 11, and the signal transmission circuit 12 controls the signal transmission to generate a gate driving signal, which can be applied to a CMOS process, and has low power consumption and wide noise tolerance.
  • the transmission gate latch circuit 11 further includes at least a first inverter 111 connected to the first control terminal of the transmission gate 112, the first clock signal 13 The second control terminal of the transmission gate 112 is connected via the first inverter 111.
  • the transmission gate latch circuit 11 further includes a capacitor C, a second inverter 113 and a third 114. One end of the capacitor C is connected to the output end of the transmission gate 112, the other end is grounded, the second inverter 113 and the third inverter are inverted.
  • the 114 is cascaded at the output of the transmission gate 112. The first two stages of the transmission signal Q n-2 sequentially pass through the transmission gate 112, the second inverter 113 and the third inverter 114 to the signal transmission circuit 12 to form a current stage transmission. Signal Q n latches the signal.
  • the signal transmission circuit 12 includes at least a NAND gate 121 and a plurality of cascaded inverter circuits 122.
  • the second clock signal 14 controls the current stage transmission signal Q n to generate a gate drive signal G n through the NAND gate 121, that is, to latch The signal forms a gate driving signal and is transmitted to the corresponding gate.
  • the multi-stage cascaded inverter circuit 122 is connected to the output terminal of the NAND gate 121 to improve the driving capability of the driving circuit 1.
  • the multi-stage cascaded inverter circuit 122 preferably includes three inverters arranged in series.
  • the first clock signal 13 is offset by one-half of a clock cycle to obtain a second clock signal 14.
  • the drive circuit 1 includes a shift register circuit 10 of the initial stage and a shift register circuit 10 of a general stage.
  • the shift register circuit 10 of the initial stage includes a shift register circuit 10 of the first stage and a shift register circuit 10 of the second stage.
  • the first clock signal 13 is the clock CK1
  • the second clock signal 14 is the clock CK3
  • the input end of the transmission gate 112 is connected to the start (Start Voltage, STV).
  • the pulse when the clock CK1 is a rising edge, controls the first control terminal of the transmission gate 112, and the clock CK1 controls the second control terminal of the transmission gate 112 via the first inverter 111.
  • the output of the third inverter 114 outputs a drive pulse Q 1 of the Q point of the first stage to latch the signal.
  • the output terminal of the multi-stage inverter circuit 122 outputs the gate drive signal G 1 of the first stage, and the latched signal forms a gate drive signal, and is further transmitted to the corresponding gate.
  • the clock CK3 is separated from the clock CK1 by one-half clock cycle, and can be obtained by shifting the clock CK1 forward or backward by one-half clock cycle. As shown in FIG.
  • the first clock signal 13 is the clock CK2
  • the second clock signal is the clock CK4
  • the input end of the transfer gate 112 is connected to the STV pulse
  • the third inverter The output terminal of 114 outputs the drive pulse Q 2 of the Q point of the second stage
  • the output terminal of the multi-stage inverter circuit 122 outputs the gate drive signal G 2 of the second stage.
  • the clock CK4 is separated from the clock CK2 by one-half clock cycle, and can be obtained by shifting the clock CK2 forward or backward by one-half clock cycle.
  • the clock signal of the adjacent shift register circuit is shifted by one quarter of a clock cycle.
  • the clock CK2 is separated from the clock CK1 by a quarter of a clock cycle, and can be obtained by shifting the clock CK1 backward by a quarter of a clock cycle, or by shifting forward by three quarters of a clock cycle.
  • the corresponding clock CK4 can be obtained by shifting the clock CK1 backward by three-quarters of a clock cycle, or by shifting forward by a quarter of a clock cycle.
  • FIG. 5 is a theoretical timing diagram of the STV pulse and the clocks CK1, CK2, CK3, and CK4 in FIGS. 3-4, with the ordinate being the voltage and the abscissa being the time.
  • the transfer gate latch circuit 11 triggers the transfer gate 112 to be turned on, and the transfer gate 112 transmits the STV pulse to the second inverter 113, and then passes through
  • the third inverter 114 transmits the driving pulse Q 1 to the Q point of the first stage, the STV pulse is at a high level, and the driving pulse Q 1 at the Q point is also a high level; when the clock CK3 is a rising edge, the clock CK3 is triggered.
  • the NAND gate 121 of the driving circuit 1 and the driving pulse Q 1 at the Q point are transmitted to the gate driving signal G 1 of the first stage through the NAND gate 121 and the multi-stage inverter circuit 122, and the gate driving signal G 1 is also High level.
  • the transfer gate latch circuit 11 triggers the transfer gate 112 to be turned on, and the transfer gate 112 transmits the STV pulse to the second inverter 113, and then passes through
  • the third inverter 114 transmits the driving pulse Q 2 to the Q point of the second stage, the STV pulse is at a high level, and the driving pulse Q 2 at the Q point is also a high level; when the clock CK4 is a rising edge, the clock CK4 is triggered.
  • the NAND gate 121 of the driving circuit 1 and the driving pulse Q 2 at the Q point are transmitted to the gate driving signal G 2 of the second stage through the NAND gate 121 and the multi-stage inverter circuit 122, and the gate driving of the second stage at this time Signal G 2 is also high.
  • the shift register circuit 10 of the general stage is the shift register circuit 10 of the third stage or the third stage or higher.
  • the first clock signal is the clock CK1
  • the second clock signal is the clock CK3
  • the input terminal of the transmission gate 112 is connected.
  • the first two levels of Q point Q m-2 .
  • the output terminal of the third inverter 114 outputs the driving pulse Q m of the q-th order of the m-th stage.
  • the output terminal of the multi-stage inverter circuit 122 outputs the gate drive signal Gm of the mth stage .
  • the clock CK3 is different from the clock CK1 by one-half clock cycle.
  • the first clock signal is the clock CK2
  • the second clock signal is the clock CK4
  • the input end of the transmission gate 112 is connected to the Q point Q of the first two stages. M-1 .
  • the output terminal of the third inverter 114 outputs the driving pulse Q m+1 of the q-th order of the m+ 1th stage
  • the clock CK4 is the rising edge
  • the output of the multi-stage inverter circuit 122 is output.
  • the clock CK4 is different from the clock CK2 by one-half clock cycle.
  • the clock CK2 is separated from the clock CK1 by a quarter of a clock cycle.
  • the first clock signal is the clock CK3
  • the second clock signal is the clock CK1
  • the input end of the transmission gate 112 is connected to the Q point Q of the first two stages. m .
  • the output terminal of the third inverter 114 outputs the driving pulse Q m+2 of the qth point of the m+2th stage.
  • the output terminal of the multi-stage inverter circuit 126 outputs the gate drive signal G m+2 of the m+2th stage.
  • the first clock signal is the clock CK4
  • the second clock signal is the clock CK2
  • the input end of the first transmission gate 121 is connected to the first two stages of Q. Point Q m+1 .
  • the output terminal of the third inverter 114 outputs the drive pulse Q m+3 of the qth point of the m+3th stage.
  • the output terminal of the multi-stage inverter circuit 122 outputs the gate drive signal G m+3 of the m+3th stage.
  • FIG. 10 is a schematic timing diagram of a driving circuit according to an embodiment of the present invention, wherein the ordinate is voltage and the abscissa is time.
  • FIG. 10 simulates the clocks CK, XCK of the shift register circuit 10 of the m- 1th stage to the shift register circuit 10 of the m+1th stage, and the gate drive signals G m-1 , G m , and G m . +1 timing diagram.
  • This timing chart corresponds to the drive circuit diagrams in FIGS. 6-9, in which the clock CK1 and the clock CK2 correspond to CK in FIG. 10, and the clock CK3 and the clock CK4 correspond to XCK in FIG.
  • the analog timing of the driver circuit is the same as the desired theoretical timing, and can be applied to a CMOS process with low power consumption and wide noise margin.
  • the present invention also provides a shift register circuit that includes a transfer gate latch circuit 11 and a signal transfer circuit 12.
  • the transfer gate latch circuit 11 includes at least a transfer gate 112, a first inverter 111, a capacitor C, a second inverter 113, and a second inverter 114.
  • the first clock signal 13 is coupled to the first control terminal of the transmission gate 112, and the first clock signal 13 is coupled to the second control terminal of the transmission gate 112 via the first inverter 111.
  • One end of the capacitor C is connected to the output end of the transmission gate 112, and the other end is grounded, and the second inverter 113 and the third inverter 114 are cascaded at the output end of the transmission gate 112.
  • the first two stages of the transmission signal Q n-2 sequentially pass through the transmission gate 112, the second inverter 113 and the third inverter 114 to the signal transmission circuit 12 to form a current stage transmission signal Q. n , the signal is latched.
  • the signal transmission circuit 12 includes at least a NAND gate 121 and a multi-stage inverter circuit 122.
  • the second clock signal 14 and the current stage transmission signal Q n are respectively two input ends of the NAND gate 121, and the multi-stage cascaded inverter circuit 122 is connected to the output end of the NAND gate 121 to boost the driving of the driving circuit 1. ability.
  • 14 current-level control signal by generating a transmission signal Q n gate drive signal G n NAND gate 121, the latches in the second clock signal forming a gate driving signal transmitted to the corresponding gate.
  • the multi-stage cascaded inverter circuit 122 preferably includes three inverters arranged in series.
  • the first clock signal 13 is shifted forward or backward by one-half of a clock cycle to obtain a second clock signal 14.
  • the output terminal of the second inverter 114 outputs a driving pulse Q n at the Q point, and the output terminal of the multi-stage inverter circuit 122 outputs a driving pulse G n , n being an integer greater than or equal to 1.
  • the driving circuit of the present invention triggers the transmission gate in the transmission gate latch circuit by the first clock signal, and outputs the first two stages of transmission signals to the signal transmission circuit through the transmission gate to form a current level transmission signal;
  • the clock signal controls the current stage transmission signal to generate the current stage gate through the signal transmission circuit
  • the drive signal can be applied to CMOS processes with low power consumption and wide noise margin.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种驱动电路（1）以及移位寄存电路（10）。该驱动电路（1）包括多个级联设置的移位寄存电路（10），每一移位寄存电路（10）包括传输门锁存电路（11）和信号传输电路（12），其中传输门锁存电路（11）包括一传输门（112），第一时钟信号（13）触发传输门（112），将前第二级传输信号（Qn-2）通过传输门（112）输出至信号传输电路（12），形成当前级传输信号（Qn）；第二时钟信号（14）控制当前级传输信号（Qn）通过信号传输电路（12）产生当前级栅极驱动信号（Gn）。通过以上方式，所述驱动电路（1）能够适用于CMOS制程，功耗低、噪声容限宽。

Description

驱动电路以及移位寄存电路 【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种驱动电路以及移位寄存电路。
【背景技术】
GOA(Gate Driver On Array)电路是利用现有的液晶显示器的Array制程将栅极扫描驱动电路制作在Array基板上，以实现逐行扫描的驱动方式。其具有降低生产成本和窄边框设计的优点，为多种显示器所使用。GOA电路要具有两项基本功能：第一是输入栅极驱动脉冲，驱动面板内的栅极线，打开显示区内的TFT(Thin Film Transistor，薄膜晶体管)，由栅极线对像素进行充电；第二是移位寄存，当第n个栅极驱动脉冲输出完成后，可以通过时钟控制进行n+1个栅极驱动脉冲的输出，并依此传递下去。
GOA电路包括上拉电路(Pull-up circuit)、上拉控制电路(Pull-up control circuit)、下拉电路(Pull-down circuit)、下拉控制电路(Pull-down control circuit)以及负责电位抬升的上升电路(Boost circuit)。具体地，上拉电路主要负责将输入的时钟讯号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速将扫描信号拉低为低电位，即薄膜晶体管的栅极的电位拉低为低电位；下拉保持电路则负责将扫描信号和上拉电路的信号(通常称为Q点)保持在关闭状态(即设定的负电位)，通常有两个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
不同的GOA电路可以使用不同的制程。LTPS(Low Temperature Poly-silicon，低温多晶硅)制程具有高电子迁移率和技术成熟的优点，目前被中小尺寸显示器广泛使用。CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)LTPS制程具有低功耗、电子迁移率高、噪声容限宽等优点，因此逐渐为面板厂商使用，如此需要开发与CMOS LTPS制程对应的GOA电路。
【发明内容】
本发明实施例提供了一种驱动电路以及移位寄存电路，以适用于CMOS制程，功耗低、噪声容限宽。
本发明提供一种驱动电路，其包括多个级联设置的移位寄存电路，每一移位寄存电路包括传输门锁存电路和信号传输电路，其中传输门锁存电路包括一传输门，第一时钟信号触发传输门，将前两级传输信号通过传输门输出至信号传输电路，形成当前级传输信号；第二时钟信号控制当前级传输信号通过信号传输电路产生当前级栅极驱动信号；其中，传输门锁存电路和信号传输电路为上升沿触发；第一时钟信号偏移二分之一个时钟周期得到第二时钟信号。
其中，传输门锁存电路还至少包括第一反相器，第一时钟信号连接传输门的第一控制端，第一时钟信号经过第一反相器连接传输门的第二控制端。
其中，传输门锁存电路还包括一电容、第二反相器和第三反相器，电容一端连接在传输门的输出端，另一端接地，第二反相器和第三反相器级联在传输门的输出端，前两级传输信号依次通过传输门、第二反相器和第三反相器输出至信号传输电路，形成当前级传输信号。
其中，信号传输电路至少包括一与非门，第二时钟信号控制当前级传输信号通过与非门产生栅极驱动信号。
其中，信号传输电路进一步包括与与非门的输出端连接的多级级联的反相电路。
其中，多级级联的反相电路包括三个反相器。
其中，相邻的移位寄存电路的时钟信号偏移四分之一个时钟周期。
本发明还提供一种驱动电路，其包括多个级联设置的移位寄存电路，每一移位寄存电路包括传输门锁存电路和信号传输电路，其中传输门锁存电路包括一传输门，第一时钟信号触发传输门，将前两级传输信号通过传输门输出至信号传输电路，形成当前级传输信号；第二时钟信号控制当前级传输信号通过信号传输电路产生当前级栅极驱动信号。
其中，传输门锁存电路和信号传输电路为上升沿触发。
其中，传输门锁存电路还至少包括第一反相器，第一时钟信号连接传输门的第一控制端，第一时钟信号经过第一反相器连接传输门的第二控制端。
其中，传输门锁存电路还包括一电容、第二反相器和第三反相器，电容一端连接在传输门的输出端，另一端接地，第二反相器和第三反相器级联在传输门的输出端，前两级传输信号依次通过传输门、第二反相器和第三反相器输出 至信号传输电路，形成当前级传输信号。
其中，信号传输电路至少包括一与非门，第二时钟信号控制当前级传输信号通过与非门产生栅极驱动信号。
其中，信号传输电路进一步包括与与非门的输出端连接的多级级联的反相电路。
其中，多级级联的反相电路包括三个反相器。
其中，第一时钟信号偏移二分之一个时钟周期得到第二时钟信号。
其中，相邻的移位寄存电路的时钟信号偏移四分之一个时钟周期。
本发明还提供一种移位寄存电路，其包括传输门锁存电路和信号传输电路，其中第一时钟信号触发传输门锁存电路，将前两级传输信号通过传输门锁存电路输出至信号传输电路，形成当前级传输信号；第二时钟信号控制当前级传输信号通过信号传输电路产生当前级栅极驱动信号。
其中，传输门锁存电路还至少包括第一反相器，第一时钟信号连接传输门的第一控制端，第一时钟信号经过第一反相器连接传输门的第二控制端。
其中，传输门锁存电路还包括一电容、第二反相器和第三反相器，电容一端连接在传输门的输出端，另一端接地，第二反相器和第三反相器级联在传输门的输出端，前两级传输信号依次通过传输门、第二反相器和第三反相器输出至信号传输电路，形成当前级传输信号。
其中，信号传输电路至少包括一与非门，第二时钟信号控制当前级传输信号通过与非门产生栅极驱动信号。
通过上述方案，本发明的有益效果是：本发明通过多个级联设置的移位寄存电路构成驱动电路，每一移位寄存电路包括传输门锁存电路和信号传输电路，其中传输门锁存电路包括一传输门，第一时钟信号触发传输门，将前两级传输信号通过传输门输出至信号传输电路，形成当前级传输信号；第二时钟信号控制当前级传输信号通过信号传输电路产生当前级栅极驱动信号，能够适用于CMOS制程，功耗低、噪声容限宽。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。其中：
图1是本发明实施例的的驱动电路的结构示意图；
图2是图1中的移位寄存电路的电路图；
图3是图1中的第一级的移位寄存电路的电路图；
图4是图1中的第二级的移位寄存电路的电路图；
图5是图1中的第一级的移位寄存电路和第二级的移位寄存电路的时序图；
图6是图1中的第m级的移位寄存电路的电路图；
图7是图1中的第m+1级的移位寄存电路的电路图；
图8是图1中的第m+2级的移位寄存电路的电路图；
图9是图1中的第m+3级的移位寄存电路的电路图；
图10是本发明实施例的驱动电路的模拟时序图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明实施例的驱动电路的结构示意图。如图1所示，驱动电路1包括多个级联设置的移位寄存电路10，每一移位寄存电路10包括传输门锁存电路11和信号传输电路12，其中传输门锁存电路11包括一传输门，第一时钟信号触发传输门，将前两级传输信号Qn-2通过传输门输出至信号传输电路12，形成当前级传输信号Qn；第二时钟信号控制当前级传输信号Qn通过信号传输电路12产生当前级栅极驱动信号Gn。其中传输门锁存电路11和信号传输电路12分别为上升沿触发。本发明实施例通过传输门锁存电路11锁存信号，通过信号传输电路12控制信号传递，产生栅极驱动信号，能够适用于CMOS制程，功耗低、噪声容限宽。
在更具体的实施例中，如图2所示，传输门锁存电路11还至少包括第一反相器111，第一时钟信号13连接传输门112的第一控制端，第一时钟信号13经过第一反相器111连接传输门112的第二控制端。
传输门锁存电路11还包括一电容C、第二反相器113和第三114，电容C一端连接在传输门112的输出端，另一端接地，第二反相器113和第三反相器 114级联在传输门112的输出端，前两级传输信号Qn-2依次通过传输门112、第二反相器113和第三反相器114至信号传输电路12，形成当前级传输信号Qn，将信号锁存。
信号传输电路12至少包括一与非门121和多级级联的反相电路122，第二时钟信号14控制当前级传输信号Qn通过与非门121产生栅极驱动信号Gn，即将锁存的信号形成栅极驱动信号，传输至对应的栅极，多级级联的反相电路122连接在与非门121的输出端，以提升驱动电路1的驱动能力。多级级联的反相电路122优选地包括串联设置的三个反相器。第一时钟信号13偏移二分之一个时钟周期得到第二时钟信号14。
驱动电路1包括起始级的移位寄存电路10和一般级的移位寄存电路10。起始级的移位寄存电路10包括第一级的移位寄存电路10和第二级的移位寄存电路10。如图3所示，在第一级的移位寄存电路10中，第一时钟信号13为时钟CK1，第二时钟信号14为时钟CK3，传输门112的输入端连接起始(Start Voltage，STV)脉冲，时钟CK1为上升沿时，控制传输门112的第一控制端，时钟CK1经过第一反相器111控制传输门112的第二控制端。第三反相器114的输出端输出第一级的Q点的驱动脉冲Q1，以将信号锁存。在时钟CK3为上升沿时，多级反相电路122的输出端输出第一级的栅极驱动信号G1，将锁存的信号形成栅极驱动信号，进而传输至对应的栅极。其中时钟CK3与时钟CK1相差二分之一个时钟周期，可以通过时钟CK1向前或向后移二分之一个时钟周期获得。如图4所示，在第二级的移位寄存电路10中，第一时钟信号13为时钟CK2，第二时钟信号为时钟CK4，传输门112的输入端连接STV脉冲，第三反相器114的输出端输出第二级的Q点的驱动脉冲Q2，多级反相电路122的输出端输出第二级的栅极驱动信号G2。其中时钟CK4与时钟CK2相差二分之一个时钟周期，可以通过时钟CK2向前或向后移二分之一个时钟周期获得。相邻的移位寄存电路的时钟信号偏移四分之一个时钟周期。具体地，时钟CK2与时钟CK1相差四分之一个时钟周期，可以通过将时钟CK1向后移四分之一个时钟周期，或向前移四分之三个时钟周期获得。对应地时钟CK4可以通过将时钟CK1向后移四分之三时钟周期，或向前移四分之一时钟周期获得。
图5为图3-图4中的STV脉冲和时钟CK1、CK2、CK3以及CK4的理论时序图，纵坐标为电压，横坐标为时间。在第一级的移位寄存电路10中，当时钟CK1为上升沿时，传输门锁存电路11触发传输门112导通，传输门112将 STV脉冲传输至第二反相器113，再经过第三反相器114传输到第一级的Q点的驱动脉冲Q1，STV脉冲为高电平，Q点的驱动脉冲Q1也是高电平；当时钟CK3为上升沿时，时钟CK3触发驱动电路1的与非门121，Q点的驱动脉冲Q1经过与非门121和多级反相电路122传输到第一级的栅极驱动信号G1，此时栅极驱动信号G1也是高电平。在第二级的移位寄存电路10中，当时钟CK2为上升沿时，传输门锁存电路11触发传输门112导通，传输门112将STV脉冲传输至第二反相器113，再经过第三反相器114传输到第二级的Q点的驱动脉冲Q2，STV脉冲为高电平，Q点的驱动脉冲Q2也是高电平；当时钟CK4为上升沿时，时钟CK4触发驱动电路1的与非门121，Q点的驱动脉冲Q2经过与非门121和多级反相电路122传输到第二级的栅极驱动信号G2，此时第二级的栅极驱动信号G2也是高电平。
一般级的移位寄存电路10为第三级或第三级以上的移位寄存电路10。如图6所示，在第m(m为n大于或等于3)级的移位寄存电路10中，第一时钟信号为时钟CK1，第二时钟信号为时钟CK3，传输门112的输入端连接前两级的Q点Qm-2。时钟CK1为上升沿时，第三反相器114的输出端输出第m级的Q点的驱动脉冲Qm。时钟CK3为上升沿时，多级反相电路122的输出端输出第m级的栅极驱动信号Gm。其中，时钟CK3与时钟CK1相差二分之一个时钟周期。
如图7所示，在第m+1级的移位寄存电路10中，第一时钟信号为时钟CK2，第二时钟信号为时钟CK4，传输门112的输入端连接前两级的Q点Qm-1。时钟CK2为上升沿时，第三反相器114的输出端输出第m+1级的Q点的驱动脉冲Qm+1，时钟CK4为上升沿时，多级反相电路122的输出端输出第m+1级的栅极驱动信号Gm+1。其中，时钟CK4与时钟CK2相差二分之一个时钟周期。而时钟CK2与时钟CK1相差四分之一个时钟周期。
如图8所示，在第m+2级的移位寄存电路10中，第一时钟信号为时钟CK3，第二时钟信号为时钟CK1，传输门112的输入端连接前两级的Q点Qm。时钟CK3为上升沿时，第三反相器114的输出端输出第m+2级的Q点的驱动脉冲Qm+2。时钟CK1为上升沿时，多级反相电路126的输出端输出第m+2级的栅极驱动信号Gm+2。
如图9所示，在第m+3级的移位寄存电路10中，第一时钟信号为时钟CK4，第二时钟信号为时钟CK2，第一传输门121的输入端连接前两级的Q点Qm+1。 时钟CK4为上升沿时，第三反相器114的输出端输出第m+3级的Q点的驱动脉冲Qm+3。时钟CK2为上升沿时，多级反相电路122的输出端输出第m+3级的栅极驱动信号Gm+3。
图10为本发明实施例的驱动电路的模拟时序图，纵坐标为电压，横坐标为时间。其中，图10模拟出第m-1级的移位寄存电路10至第m+1级的移位寄存电路10的时钟CK、XCK，和栅极驱动信号Gm-1、Gm以及Gm+1的时序图。该时序图与图6-图9中的驱动电路图相对应，其中时钟CK1和时钟CK2对应图10中的CK，而时钟CK3和时钟CK4对应图10中的XCK。从图中可以看出，驱动电路的模拟时序与期望的理论时序相同，能够适用于CMOS制程，功耗低、噪声容限宽。
本发明还提供一种移位寄存电路，非门锁存的移位寄存电路10包括传输门锁存电路11以及信号传输电路12。参见图2，传输门锁存电路11至少包括传输门112、第一反相器111、电容C、第二反相器113、第二反相器114。第一时钟信号13连接传输门112的第一控制端，第一时钟信号13经过第一反相器111连接传输门112的第二控制端。电容C一端连接在传输门112的输出端，另一端接地，第二反相器113和第三反相器114级联在传输门112的输出端。第一时钟信号13为上升沿时，前两级传输信号Qn-2依次通过传输门112、第二反相器113和第三反相器114至信号传输电路12，形成当前级传输信号Qn，将信号锁存。
信号传输电路12至少包括与非门121以及多级反相电路122。第二时钟信号14和当前级传输信号Qn分别为与非门121的两个输入端，多级级联的反相电路122连接在与非门121的输出端，以提升驱动电路1的驱动能力。第二时钟信号14控制当前级传输信号Qn通过与非门121产生栅极驱动信号Gn，即将锁存的信号形成栅极驱动信号，传输至对应的栅极。其中，多级级联的反相电路122优选地包括串联设置的三个反相器。第一时钟信号13向前或向后偏移二分之一个时钟周期得到第二时钟信号14。第二反相器114的输出端输出Q点的驱动脉冲Qn，多级反相电路122的输出端输出驱动脉冲Gn，n为大于等于1的整数。
综上所述，本发明的的驱动电路通过第一时钟信号触发传输门锁存电路中的传输门，将前两级传输信号通过传输门输出至信号传输电路，形成当前级传输信号；第二时钟信号控制当前级传输信号通过信号传输电路产生当前级栅极 驱动信号，能够适用于CMOS制程，功耗低、噪声容限宽。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种驱动电路，其中，所述驱动电路包括多个级联设置的移位寄存电路，每一所述移位寄存电路包括传输门锁存电路和信号传输电路，其中所述传输门锁存电路包括一传输门，第一时钟信号触发所述传输门，将前两级传输信号通过所述传输门输出至所述信号传输电路，形成当前级传输信号；第二时钟信号控制所述当前级传输信号通过所述信号传输电路产生当前级栅极驱动信号；
    其中，所述传输门锁存电路和所述信号传输电路为上升沿触发；所述第一时钟信号偏移二分之一个时钟周期得到所述第二时钟信号。
  2. 根据权利要求1所述的驱动电路，其中，所述传输门锁存电路还至少包括第一反相器，所述第一时钟信号连接所述传输门的第一控制端，所述第一时钟信号经过所述第一反相器连接所述传输门的第二控制端。
  3. 根据权利要求2所述的驱动电路，其中，所述传输门锁存电路还包括一电容、第二反相器和第三反相器，所述电容一端连接在所述传输门的输出端，另一端接地，所述第二反相器和所述第三反相器级联在所述传输门的输出端，所述前两级传输信号依次通过所述传输门、所述第二反相器和所述第三反相器输出至所述信号传输电路，形成当前级传输信号。
  4. 根据权利要求1所述的驱动电路，其中，所述信号传输电路至少包括一与非门，第二时钟信号控制所述当前级传输信号通过所述与非门产生所述栅极驱动信号。
  5. 根据权利要求4所述的驱动电路，其中，所述信号传输电路进一步包括与所述与非门的输出端连接的多级级联的反相电路。
  6. 根据权利要求5所述的驱动电路，其中，所述多级级联的反相电路包括三个反相器。
  7. 根据权利要求1所述的驱动电路，其中，相邻的所述移位寄存电路的所述时钟信号偏移四分之一个时钟周期。
  8. 一种驱动电路，其中，所述驱动电路包括多个级联设置的移位寄存电路，每一所述移位寄存电路包括传输门锁存电路和信号传输电路，其中所述传输门锁存电路包括一传输门，第一时钟信号触发所述传输门，将前两级传输信号通过所述传输门输出至所述信号传输电路，形成当前级传输信号；第二时钟信号 控制所述当前级传输信号通过所述信号传输电路产生当前级栅极驱动信号。
  9. 根据权利要求8所述的驱动电路，其中，所述传输门锁存电路和所述信号传输电路为上升沿触发。
  10. 根据权利要求8所述的驱动电路，其中，所述传输门锁存电路还至少包括第一反相器，所述第一时钟信号连接所述传输门的第一控制端，所述第一时钟信号经过所述第一反相器连接所述传输门的第二控制端。
  11. 根据权利要求10所述的驱动电路，其中，所述传输门锁存电路还包括一电容、第二反相器和第三反相器，所述电容一端连接在所述传输门的输出端，另一端接地，所述第二反相器和所述第三反相器级联在所述传输门的输出端，所述前两级传输信号依次通过所述传输门、所述第二反相器和所述第三反相器输出至所述信号传输电路，形成当前级传输信号。
  12. 根据权利要求8所述的驱动电路，其中，所述信号传输电路至少包括一与非门，第二时钟信号控制所述当前级传输信号通过所述与非门产生所述栅极驱动信号。
  13. 根据权利要求12所述的驱动电路，其中，所述信号传输电路进一步包括与所述与非门的输出端连接的多级级联的反相电路。
  14. 根据权利要求13所述的驱动电路，其中，所述多级级联的反相电路包括三个反相器。
  15. 根据权利要求8任一项所述的驱动电路，其中，所述第一时钟信号偏移二分之一个时钟周期得到所述第二时钟信号。
  16. 根据权利要求8所述的驱动电路，其中，相邻的所述移位寄存电路的所述时钟信号偏移四分之一个时钟周期。
  17. 一种移位寄存电路，其中，所述移位寄存电路包括传输门锁存电路和信号传输电路，其中第一时钟信号触发所述传输门锁存电路，将前两级传输信号通过所述传输门锁存电路输出至所述信号传输电路，形成当前级传输信号；第二时钟信号控制所述当前级传输信号通过所述信号传输电路产生当前级栅极驱动信号。
  18. 根据权利要求17所述的移位寄存电路，其中，所述传输门锁存电路还至少包括第一反相器，所述第一时钟信号连接所述传输门的第一控制端，所述第一时钟信号经过所述第一反相器连接所述传输门的第二控制端。
  19. 根据权利要求18所述的移位寄存电路，其中，所述传输门锁存电路还 包括一电容、第二反相器和第三反相器，所述电容一端连接在所述传输门的输出端，另一端接地，所述第二反相器和所述第三反相器级联在所述传输门的输出端，所述前两级传输信号依次通过所述传输门、所述第二反相器和所述第三反相器输出至所述信号传输电路，形成当前级传输信号。
  20. 根据权利要求17所述的移位寄存电路，其中，所述信号传输电路至少包括一与非门，第二时钟信号控制所述当前级传输信号通过所述与非门产生所述栅极驱动信号。
PCT/CN2015/086737 2015-08-05 2015-08-12 驱动电路以及移位寄存电路 WO2017020332A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/775,719 US9672936B2 (en) 2015-08-05 2015-08-12 Driving circuits and the shift register circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510475825.3 2015-08-05
CN201510475825.3A CN105096864A (zh) 2015-08-05 2015-08-05 驱动电路以及移位寄存电路

Publications (1)

Publication Number Publication Date
WO2017020332A1 true WO2017020332A1 (zh) 2017-02-09

Family

ID=54577156

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/086737 WO2017020332A1 (zh) 2015-08-05 2015-08-12 驱动电路以及移位寄存电路

Country Status (3)

Country Link
US (1) US9672936B2 (zh)
CN (1) CN105096864A (zh)
WO (1) WO2017020332A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105161061B (zh) 2015-08-18 2017-11-10 深圳市华星光电技术有限公司 驱动电路以及移位寄存电路
CN107564459B (zh) * 2017-10-31 2021-01-05 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN112799465A (zh) * 2019-10-28 2021-05-14 京东方科技集团股份有限公司 控制信号发生器及其驱动方法
CN112542140B (zh) * 2020-12-16 2022-05-31 合肥京东方卓印科技有限公司 一种移位寄存器、栅极驱动电路以及驱动方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063079A1 (en) * 2001-10-02 2003-04-03 Shinichi Abe Flip-flop circuit, shift register and scan driving circuit for display device
US20060145998A1 (en) * 2004-12-31 2006-07-06 Lg. Philips Lcd Co., Ltd. Driving unit for liquid crystal display device
CN104392686A (zh) * 2014-10-21 2015-03-04 厦门天马微电子有限公司 移位寄存单元及驱动电路及显示装置
CN104485061A (zh) * 2014-12-23 2015-04-01 上海天马有机发光显示技术有限公司 动态逻辑电路、栅极驱动电路、显示面板及显示装置
CN104537996A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 与非门锁存的驱动电路以及与非门锁存的移位寄存器
CN104599622A (zh) * 2015-02-13 2015-05-06 上海天马有机发光显示技术有限公司 动态逻辑电路、栅极驱动电路、显示面板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239206A (en) * 1990-03-06 1993-08-24 Advanced Micro Devices, Inc. Synchronous circuit with clock skew compensating function and circuits utilizing same
JP2003115194A (ja) * 2001-10-01 2003-04-18 Texas Instr Japan Ltd シフトレジスタ
TWI354994B (en) * 2007-11-16 2011-12-21 Au Optronics Corp Switch set of bi-directional shift register module

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063079A1 (en) * 2001-10-02 2003-04-03 Shinichi Abe Flip-flop circuit, shift register and scan driving circuit for display device
US20060145998A1 (en) * 2004-12-31 2006-07-06 Lg. Philips Lcd Co., Ltd. Driving unit for liquid crystal display device
CN104392686A (zh) * 2014-10-21 2015-03-04 厦门天马微电子有限公司 移位寄存单元及驱动电路及显示装置
CN104485061A (zh) * 2014-12-23 2015-04-01 上海天马有机发光显示技术有限公司 动态逻辑电路、栅极驱动电路、显示面板及显示装置
CN104537996A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 与非门锁存的驱动电路以及与非门锁存的移位寄存器
CN104599622A (zh) * 2015-02-13 2015-05-06 上海天马有机发光显示技术有限公司 动态逻辑电路、栅极驱动电路、显示面板及显示装置

Also Published As

Publication number Publication date
US9672936B2 (en) 2017-06-06
CN105096864A (zh) 2015-11-25
US20170040068A1 (en) 2017-02-09

Similar Documents

Publication Publication Date Title
TWI491175B (zh) 移位暫存器
WO2016106821A1 (zh) 栅极驱动电路以及移位寄存器
TWI619104B (zh) Shift register unit and driving method thereof, gate driving circuit and display device
KR102178652B1 (ko) Goa 회로
US9543040B2 (en) Shift register unit and driving method thereof, gate driver and display device
WO2017107295A1 (zh) 适用于In Cell型触控显示面板的的GOA电路
KR102057818B1 (ko) 낸드 래치의 구동 회로 및 낸드 래치의 시프트 레지스터
WO2018059159A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US9007294B2 (en) Shifting register, gate driving apparatus and display apparatus
WO2016074395A1 (zh) 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
WO2018059075A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
TWI571842B (zh) 閘極掃描器驅動電路及其移位暫存器
WO2017181481A1 (zh) 减小时钟信号负载的cmos goa电路
WO2015010364A1 (zh) 移位寄存器单元、栅极驱动电路及显示器件
JP2019532321A (ja) Ｇｏａ回路
WO2014205897A1 (zh) 移位寄存器单元、栅极驱动电路及显示装置
WO2017020332A1 (zh) 驱动电路以及移位寄存电路
WO2016106823A1 (zh) 液晶显示装置及其栅极驱动器
WO2016106815A1 (zh) 显示装置及其栅极驱动电路
US9905313B2 (en) Gate drive circuit and shift register circuit
WO2017028328A1 (zh) 驱动电路以及移位寄存电路
TWI410947B (zh) 移位暫存器

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14775719

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15900106

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15900106

Country of ref document: EP

Kind code of ref document: A1