WO2017024610A1 - 一种驱动电路 - Google Patents

一种驱动电路 Download PDF

Info

Publication number
WO2017024610A1
WO2017024610A1 PCT/CN2015/087798 CN2015087798W WO2017024610A1 WO 2017024610 A1 WO2017024610 A1 WO 2017024610A1 CN 2015087798 W CN2015087798 W CN 2015087798W WO 2017024610 A1 WO2017024610 A1 WO 2017024610A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
signal
module
pulse
pulse signal
Prior art date
Application number
PCT/CN2015/087798
Other languages
English (en)
French (fr)
Inventor
熊志
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/785,852 priority Critical patent/US9886929B2/en
Publication of WO2017024610A1 publication Critical patent/WO2017024610A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/16—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source
    • G09G3/18—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a driving circuit.
  • the liquid crystal panel is driven by a DC voltage
  • the screen maintains a still picture or a small change screen for a long time, even if the content of the display screen is changed, the phenomenon of the previous image trace can still be seen on the liquid crystal screen.
  • This phenomenon is called "DC residual".
  • the scan driver chip output pin is connected to the gate of each row of thin film transistors, so that each row of thin film transistors is turned on and off at the same time.
  • the timing control chip continuously outputs the data signal to the data driving chip. If the data driving chip receives a data, the driving voltage is pushed out, and the driving voltage time of the data driving chip output is inconsistent.
  • the industry introduces pulse signals TP and POL signals in the timing control chip and the data driving chip.
  • the introduction of the TP and POL signals of the timing control chip and the data driving chip leads to an increase in the number of pins of the timing control chip and the data driving chip, an increase in the cost of the two chips, and an increase in the area of the printed circuit board carrying the two chips.
  • the technical problem to be solved by the present invention is to provide a timing control chip, a data driving chip and a driving circuit, so as to reduce the number and area of chip pins of the timing control chip and the data driving chip.
  • the cost can also reduce the area of the printed circuit board carrying the timing control chip and the data driving chip.
  • the present invention provides a timing control chip for use in a driving circuit of a liquid crystal display to connect a data driving chip in the driving circuit, wherein the timing control chip comprises:
  • a pulse signal generating module configured to generate a first pulse signal and a second pulse signal
  • the data signal sending module has a data signal, the data signal sending module includes a data output pin, and the data signal includes a valid data segment and an invalid data segment;
  • a synthesis module is connected between the pulse signal generation module and the data signal transmission module, and configured to synthesize the first and second pulse signals into the invalid data segment of the data signal to form a composite Data signal, and transmitting the synthesized data signal to the data signal sending module; wherein the first and second pulse signals and the valid data segment have at least a preset first time interval, the first a second time interval between the second pulse signals; wherein a data output pin of the data signal transmitting module is configured to be connected to the data driving chip to send the synthesized data signal to the data driving a chip, wherein the data driving chip decomposes the first and second pulse signals to capture a state of the second pulse signal when the first pulse signal is at a first edge, thereby The state of the second pulse signal controls the polarity of the output drive voltage.
  • the synthesis module includes a first synthesis unit and a second synthesis unit, and the first and second synthesis units are both connected between the pulse signal generation module and the data signal transmission module, and the first synthesis The unit is configured to synthesize a first pulse signal into the data signal, and the second synthesis unit is configured to synthesize a second pulse signal into the data signal to form the synthesized data signal.
  • the duty ratios of the first and second pulse signals are different.
  • the first pulse signal is a TP signal
  • the second pulse signal is a POL signal
  • the data signal further includes a reset segment, the reset segment being located between the invalid data segment and the valid data segment.
  • the first or second pulse data connected to the reset segment and the reset data segment have a preset third time interval.
  • the invention also provides a data driving chip, which is applied to a driving circuit of a liquid crystal display, A timing control chip is connected, wherein the data driving chip comprises:
  • the data receiving module includes a data receiving pin, and the data receiving pin is configured to be connected to a data output pin of the timing control chip to receive a synthesized data signal output by the timing control chip;
  • the invalid data segment of the synthesized data signal has a first pulse signal and a second pulse signal, and the first and second pulse signals and the valid data segment have at least a preset first time interval, and the first a second preset time interval between the second pulse signals;
  • the decomposition module is connected to the data receiving module to decompose the composite data signal to obtain the first and second pulse signals respectively;
  • the voltage data control module being coupled to the decomposition module to receive the first and second pulse signals to capture the second when the first pulse signal is at a first edge The state of the pulse signal, thereby controlling the polarity of the output driving voltage according to the state of the captured second pulse signal.
  • the decomposition module includes a first decomposition unit and a second decomposition unit, wherein the first and second decomposition units are both connected to the data receiving module, and the first decomposition unit is configured to perform the synthesized data signal. Decomposing to obtain the first pulse signal, the second decomposition unit is configured to decompose the synthesized data signal to obtain the second pulse signal.
  • the duty ratios of the first and second pulse signals are different.
  • the first pulse signal is a TP signal
  • the second pulse signal is a POL signal
  • the present invention also provides a driving circuit for use in a liquid crystal display, the driving circuit comprising:
  • timing control chip includes:
  • a pulse signal generating module configured to generate a first pulse signal and a second pulse signal
  • the data signal sending module has a data signal, the data signal sending module includes a data output pin, and the data signal includes a valid data segment and an invalid data segment;
  • the synthesis module is connected between the pulse signal generation module and the data signal transmission module, and configured to synthesize the first and second pulse signals into the invalid data segment of the data signal to form a composite Data signal, and transmitting the synthesized data signal to the data signal sending module; wherein the first and second pulse signals and the valid data segment have at least a preset first time interval, the first a second time interval between the second pulse signals;
  • the data driving chip comprising:
  • the data receiving module includes a data receiving pin, and the data receiving pin is configured to be connected to a data output pin of the timing control chip to receive a synthesized data signal output by the timing control chip;
  • the decomposition module is connected to the data receiving module to decompose the composite data signal to obtain the first and second pulse signals respectively;
  • the voltage data control module being coupled to the decomposition module to receive the first and second pulse signals to capture the second when the first pulse signal is at a first edge The state of the pulse signal, thereby controlling the polarity of the output driving voltage according to the state of the captured second pulse signal.
  • the synthesis module includes a first synthesis unit and a second synthesis unit, and the first and second synthesis units are both connected between the pulse signal generation module and the data signal transmission module, and the first synthesis The unit is configured to synthesize a first pulse signal into the data signal, and the second synthesis unit is configured to synthesize a second pulse signal into the data signal to form the synthesized data signal.
  • the decomposition module includes a first decomposition unit and a second decomposition unit, wherein the first and second decomposition units are both connected to the data receiving module, and the first decomposition unit is configured to perform the synthesized data signal. Decomposing to obtain the first pulse signal, the second decomposition unit is configured to decompose the synthesized data signal to obtain the second pulse signal.
  • the duty ratios of the first and second pulse signals are different.
  • the first pulse signal is a TP signal
  • the second pulse signal is a POL signal
  • the data signal further includes a reset segment, the reset segment being located between the invalid data segment and the valid data segment.
  • a timing control chip is applied to a driving circuit of a liquid crystal display to connect a data driving chip in the driving circuit, and the timing control chip comprises a pulse signal generating module, a data signal transmitting module and a synthesizing module.
  • the pulse signal generating module is configured to generate a first pulse signal and a second pulse signal;
  • the data signal sending module includes a data output pin, the data signal includes a valid data segment and an invalid data segment;
  • the synthesizing module is connected to Between the pulse signal generating module and the data signal transmitting module, the first and second pulse signals are synthesized into an invalid data segment of the data signal to form a synthesized data signal, and the synthesized data is Signal transmission to the data signal a transmitting module, wherein the first and second pulse signals and the valid data segment have at least a preset first time interval, and the first and second pulse signals have a preset second time interval;
  • a data output pin of the data signal sending module is configured to be connected to the data driving chip, to send the synth
  • the timing control chip reduces the pulse signal output pin compared to the existing timing control chip, thereby achieving the purpose of reducing the number of pins of the timing control chip and reducing the area and cost of the timing control chip. Thereby reducing the area of the printed circuit board carrying the timing control chip.
  • FIG. 1 is a block diagram of a timing control chip according to a first embodiment of the present invention
  • FIG. 2 is a waveform diagram of first and second pulse signals generated by the pulse signal generating module of FIG. 1;
  • FIG. 3 is a schematic diagram of data segments of a synthesized data signal output by the timing control chip of FIG. 1;
  • FIG. 4 is a block diagram of a data driving chip according to a second embodiment of the present invention.
  • FIG. 5 is a block diagram of a driving circuit according to a third embodiment of the present invention.
  • a first embodiment of the present invention provides a timing control chip 100.
  • the timing control chip 100 is applied to a driving circuit of a liquid crystal display to connect the driving circuit The data driver chip in the middle.
  • the timing control chip 100 includes a pulse signal generation module 10, a data signal transmission module 20, and a synthesis module 30.
  • the pulse signal generating module 10 is configured to generate a first pulse signal 11 and a second pulse signal 12.
  • the first pulse signal 11 is a TP signal.
  • the second pulse signal 12 is a POL signal.
  • the data signal transmitting module 20 has a data signal 21.
  • the data signal transmitting module 20 includes a data output pin 22.
  • the data output pin 21 is for outputting the data signal.
  • the data signal 21 includes a valid data segment 211 and an invalid data segment 212.
  • the synthesis module 30 is connected between the pulse signal generation module 10 and the data signal transmission module 20 for synthesizing the first and second pulse signals 11 and 12 to the invalid data segment 212 of the data signal 21 Medium to form a composite data signal 31, and to transmit the synthesized data signal 31 to the data signal transmitting module 20.
  • the first and second pulse signals 11 and 12 and the valid data segment 21 have at least a preset first time interval T1.
  • the first and second pulse signals 11 and 12 have a preset second time interval T2.
  • the data output pin 22 of the data signal sending module 20 is configured to be connected to the data driving chip, to send the synthesized data signal 31 to the data driving chip, so that the data driving chip is decomposed First and second pulse signals 11 and 12, thereby grasping the state of the second pulse signal 12 when the first pulse signal 11 is at the first edge, and further according to the captured second pulse signal
  • the state of 12 controls the polarity of the output drive voltage.
  • the duty ratios of the first pulse signal 11 and the second pulse signal 12 are different.
  • the first edge of the first pulse signal 11 may be a rising edge.
  • the data driving chip grabs the state of the second pulse signal 12 when the first pulse signal 11 is at the rising edge, and controls the output driving voltage according to the state of the captured second pulse signal 12 Polarity.
  • the first and second pulse signals 11 and 12 and the valid data segment 21 have at least a predetermined first time interval T1 to prevent mixing with valid data in the valid data segment 21.
  • the time interval between the pulse signal closest to the valid data segment 211 and the valid data segment 211 in the first and second pulse signals 11 and 12 is the preset first time interval T1.
  • the synthesizing module 30 is connected between the pulse signal generating module 10 and the data signal transmitting module 20 for synthesizing the first and second pulse signals to the data signal.
  • the invalid data segment 212 of 21 is formed to form a composite data signal 31, and the composite data signal 31 is transmitted to the data signal transmitting module 20.
  • the first and second pulse signals 11 and 12 and the valid data segment 21 have a preset first time interval T1.
  • the first and second pulse signals 11 and 12 have a preset second time interval T2.
  • the data output pin 22 of the data signal sending module 20 is configured to be connected to the data driving chip, to send the synthesized data signal 31 to the data driving chip, so that the data driving chip is decomposed First and second pulse signals 11 and 12, thereby grasping the state of the second pulse signal 12 when the first pulse signal 11 is at the first edge, and further according to the captured second pulse signal
  • the state of 12 controls the polarity of the output drive voltage. Therefore, the timing control chip 100 reduces the pulse signal output pin compared to the existing timing control chip, thereby reducing the number of pins of the timing control chip 100, reducing the area of the timing control chip 100 and The purpose of the cost, in turn, reduces the area of the printed circuit board carrying the timing control chip 100.
  • the synthesizing module 30 includes a first synthesizing unit 32 and a second synthesizing unit 33.
  • the first and second synthesizing units 32 and 33 are both connected between the pulse signal generating module 10 and the data signal transmitting module 20.
  • the first synthesizing unit 32 is configured to synthesize the first pulse signal 11 into the data signal 21.
  • the second synthesizing unit 12 is configured to synthesize the second pulse signal 12 into the data signal 21 to form the synthesized data signal 31.
  • first and second pulse signals 11 and 12 are respectively synthesized into the data signal 21 through the first and second combining units 32 and 33, thereby achieving independent control and providing flexible synthesis. Sex.
  • the data signal 21 further includes a reset segment 213.
  • the reset segment 213 is located between the invalid data segment 212 and the valid data segment 211.
  • the function of the reset segment 213 is that when the reset segment 213 is read, it means that the next data segment that needs to be read is the valid data segment 211.
  • a second aspect of the present invention provides a data driving chip 400.
  • the data driving chip 400 is applied to a driving circuit of a liquid crystal display to connect the timing control chip 100.
  • the data driving chip 400 includes a data receiving module 410, a decomposition module 412, and a voltage output control module 413.
  • the data receiving module 410 includes a data receiving pin 411.
  • the data receiving pin 411 is used
  • the data output pin 22 is connected to the timing control chip 100 to receive the synthesized data signal 31 output by the timing control chip 100.
  • the invalid data segment 212 of the synthesized data signal 31 has a first pulse signal 11 and a second pulse signal 12.
  • the first and second pulse signals 11 and 12 and the valid data segment 211 have at least a preset first time interval T1.
  • the first and second pulse signals 11 and 12 have at least a second predetermined time interval T2.
  • the decomposition module 412 is coupled to the data receiving module 410 to decompose the composite data signal 31 to obtain the first and second pulse signals 11 and 12, respectively.
  • the voltage data control module 413 is coupled to the decomposition module 412 to receive the first and second pulse signals 11 and 12 to capture the first pulse of the first pulse signal 11 The state of the two pulse signals 12, thereby controlling the polarity of the output driving voltage according to the state of the captured second pulse signal 12.
  • the decomposition module 412 is coupled to the data receiving module 410 to the synthesized data.
  • the signal 31 is decomposed to obtain the first and second pulse signals 11 and 12, respectively.
  • the voltage data control module 413 is coupled to the decomposition module 412 to receive the first and second pulse signals 11 and 12 to capture the first pulse of the first pulse signal 11 The state of the two pulse signals 12, thereby controlling the polarity of the output driving voltage according to the state of the captured second pulse signal 12.
  • the data driving chip 400 reduces the pulse signal receiving pin compared to the existing data driving chip, thereby reducing the number of pins of the data driving chip 400, reducing the area of the data driving chip 400 and The purpose of the cost, in turn, reduces the area of the printed circuit board carrying the data drive chip 400.
  • the decomposition module 412 includes a first decomposition unit 4121 and a second decomposition unit 4122.
  • the first and second decomposition units 4121 and 4122 are both connected to the data receiving module 410.
  • the first decomposing unit 4121 is configured to decompose the synthesized data signal 31 to obtain the first pulse signal 11.
  • the second decomposing unit 4122 is configured to decompose the synthesized data signal 12 to obtain the second pulse signal 12.
  • first and second pulse signals 11 and 12 are respectively decomposed by the first and second decomposing units 4121 and 4122, thereby achieving independent control and providing flexibility of decomposition.
  • a third embodiment of the present invention provides a driving circuit 500.
  • the drive The circuit is used in a liquid crystal display.
  • the driving circuit 500 includes a timing control chip and a data driving chip.
  • the timing control chip is the timing control chip 100 provided in the first aspect.
  • the data driving chip is the data driving chip 400 provided by the second solution described above.
  • the timing control chip 100 is connected to the data receiving pin 411 of the data driving chip 400 through the data output pin 22, thereby implementing connection of the timing control chip 100 and the data driving chip 400.
  • timing control chip 100 and the data driving chip 400 have been described in detail in the first and second aspects, and will not be further described herein.
  • the synthesizing module 30 is connected between the pulse signal generating module 10 and the data signal transmitting module 20 for synthesizing the first and second pulse signals to the invalid data of the data signal 21.
  • a composite data signal 31 is formed, and the synthesized data signal 31 is transmitted to the data receiving module 410 through the data output pin 22 and the data receiving pin 411 of the data driving chip 400.
  • the decomposition module 412 is coupled to the data receiving module 410 to decompose the composite data signal 31 to obtain the first and second pulse signals 11 and 12, respectively.
  • the voltage data control module 413 is coupled to the decomposition module 412 to receive the first and second pulse signals 11 and 12 to capture the first pulse of the first pulse signal 11 The state of the two pulse signals 12, thereby controlling the polarity of the output driving voltage according to the state of the captured second pulse signal 12. Therefore, in the present invention, the timing control chip 100 reduces the pulse signal output pin compared to the existing timing control chip, and the data driving chip 400 reduces the pulse signal receiving compared to the existing data driving chip. a pin, thereby reducing the number of pins of the timing control chip 100 and the data driving chip 400, reducing the area and cost of the timing control chip 100 and the data driving chip 400, and further reducing The area of the printed circuit board carrying the timing control chip 100 and the data driving chip 400 is reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Multimedia (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

公开了一种时序控制芯片（100），该芯片（100）包括脉冲信号生成模块（10）、数据信号发送模块（20）及合成模块（30），脉冲信号生成模块（10）用于生成第一脉冲信号及第二脉冲信号，数据信号发送模块（20）具有数据信号，数据信号包括有效数据段及无效数据段，合成模块（30）将第一及第二脉冲信号合成至数据信号的无效数据段中，以形成合成数据信号，并将合成数据信号传输至数据信号发送模块（20）；数据信号发送模块（20）用于连接至数据驱动芯片，以使数据驱动芯片分解出第一及第二脉冲信号，从而在第一脉冲信号的处于第一沿时抓取第二脉冲信号的状态，进而根据抓取到的第二脉冲信号的状态控制输出的驱动电压的极性。因此，该电路减少了时序控制芯片的引脚数量、面积及成本。还提供了一种数据驱动芯片及驱动电路。

Description

一种驱动电路
本发明要求2015年8月10日递交的发明名称为“一种驱动电路”的申请号201510485609.7的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其涉及一种驱动电路。
背景技术
在液晶的生成过程中，由于无法将液晶完全纯化，而带入一些可移动离子。当施加电压时，这些可移动离子会受到电极上与其极性相反的电荷吸引而向电极移动。当施加电压的平均值不为零时，离子会趋向其中一个电极移动，直到移动至液晶与取向膜的界面而被固定。固定在液晶与取向膜界面的离子会与电极上相反极性的电荷形成内部电场，改变透射率-电压关系曲线。若液晶面板采用直流电压驱动，当屏幕较长时间保持一幅静止画面或变动较少画面时，即使改变显示画面的内容，液晶屏幕上仍然可以看到之前图像痕迹的现象。这种现象称为“直流残留”。扫描驱动芯片输出引脚连接至每一行薄膜电晶体的栅极、使得每行薄膜电晶体开启、关断时间一致。而时序控制芯片持续输出数据信号给数据驱动芯片，若数据驱动芯片每接到一笔数据，就推出驱动电压、将导致数据驱动芯片输出的驱动电压时间不一致。为解决直流残留、驱动电压时间不一致，业界在时序控制芯片、数据驱动芯片中引入脉冲信号TP、POL信号。时序控制芯片、数据驱动芯片的TP、POL信号的引入，导致时序控制芯片及数据驱动芯片的引脚数量增加、两种芯片成本上升，同时承载该两芯片的印刷电路板的面积增加。
发明内容
本发明所要解决的技术问题在于提供一种时序控制芯片、数据驱动芯片及驱动电路，以达到减少时序控制芯片及数据驱动芯片的芯片引脚数量、面积、 成本，同时还可以减小承载时序控制芯片及数据驱动芯片的印刷电路板的面积。
为了实现上述目的，本发明实施方式提供如下技术方案：
本发明供了一种时序控制芯片，应用于液晶显示器的驱动电路中，以连接所述驱动电路中的数据驱动芯片，其特征在于：所述时序控制芯片包括：
脉冲信号生成模块，所述脉冲信号生成模块用于生成第一脉冲信号及第二脉冲信号；
数据信号发送模块，所述数据信号发送模块具有数据信号，所述数据信号发送模块包括数据输出引脚，所述数据信号包括有效数据段及无效数据段；
合成模块，所述合成模块连接至所述脉冲信号生成模块及所述数据信号发送模块之间，用于将第一及第二脉冲信号合成至所述数据信号的无效数据段中，以形成合成数据信号，并将所述合成数据信号传输至所述数据信号发送模块；其中，所述第一及第二脉冲信号与所述有效数据段至少具有预设第一时间间隔，所述第一及第二脉冲信号之间具有预设第二时间间隔；其中，所述数据信号发送模块的数据输出引脚用于连接至所述数据驱动芯片，以将所述合成数据信号发送至所述数据驱动芯片，使得所述数据驱动芯片分解出第一及第二脉冲信号，以在所述第一脉冲信号的处于第一沿时抓取所述第二脉冲信号的状态，从而根据抓取到的所述第二脉冲信号的状态控制输出的驱动电压的极性。
其中，所述合成模块包括第一合成单元及第二合成单元，所述第一及第二合成单元均连接至所述脉冲信号生成模块及所述数据信号发送模块之间，所述第一合成单元用于将第一脉冲信号合成至所述数据信号中，所述第二合成单元用于将第二脉冲信号合成至所述数据信号中，从而形成所述合成数据信号。
其中，所述第一及第二脉冲信号的占空比不同。
其中，所述第一脉冲信号为TP信号，所述第二脉冲信号为POL信号。
其中，所述数据信号还包括复位段，所述复位段位于所述无效数据段与有效数据段之间。
其中，与所述复位段相连的第一或第二脉冲数据与所述复位数据段之间具有预设第三时间间隔。
本发明还提供了一种数据驱动芯片，应用于液晶显示器的驱动电路中，以 连接时序控制芯片，其特征在于：所述数据驱动芯片包括：
数据接收模块，所述数据接收模块包括数据接收引脚，所述数据接收引脚用于连接至所述时序控制芯片的数据输出引脚，以接收时序控制芯片输出的合成数据信号；其中，所述合成数据信号的无效数据段中具有第一脉冲信号及第二脉冲信号，所述第一及第二脉冲信号与所述有效数据段至少具有预设第一时间间隔，且所述第一及第二脉冲信号之间具有第二预设时间间隔；
分解模块，所述分解模块连接所述数据接收模块，以对所述合成数据信号进行分解，以分别得到所述第一及第二脉冲信号；
电压输出控制模块，所述电压数据控制模块连接至所述分解模块，以接收所述第一及第二脉冲信号，以在所述第一脉冲信号的处于第一沿时抓取所述第二脉冲信号的状态，从而根据抓取到的所述第二脉冲信号的状态控制输出的驱动电压的极性。
其中，所述分解模块包括第一分解单元及第二分解单元，所述第一及第二分解单元均连接至所述数据接收模块，所述第一分解单元用于对所述合成数据信号进行分解，以得到所述第一脉冲信号，所述第二分解单元用于对所述合成数据信号进行分解，以得到所述第二脉冲信号。
其中，所述第一及第二脉冲信号的占空比不同。
其中，所述第一脉冲信号为TP信号，所述第二脉冲信号为POL信号。
本发明还提供了一种驱动电路，应用于液晶显示器中，所述驱动电路包括：
时序控制芯片，所述时序控制芯片包括：
脉冲信号生成模块，所述脉冲信号生成模块用于生成第一脉冲信号及第二脉冲信号；
数据信号发送模块，所述数据信号发送模块具有数据信号，所述数据信号发送模块包括数据输出引脚，所述数据信号包括有效数据段及无效数据段；
合成模块，所述合成模块连接至所述脉冲信号生成模块及所述数据信号发送模块之间，用于将第一及第二脉冲信号合成至所述数据信号的无效数据段中，以形成合成数据信号，并将所述合成数据信号传输至所述数据信号发送模块；其中，所述第一及第二脉冲信号与所述有效数据段至少具有预设第一时间间隔，所述第一及第二脉冲信号之间具有预设第二时间间隔；
数据驱动芯片，所述数据驱动芯片包括：
数据接收模块，所述数据接收模块包括数据接收引脚，所述数据接收引脚用于连接至所述时序控制芯片的数据输出引脚，以接收时序控制芯片输出的合成数据信号；
分解模块，所述分解模块连接所述数据接收模块，以对所述合成数据信号进行分解，以分别得到所述第一及第二脉冲信号；
电压输出控制模块，所述电压数据控制模块连接至所述分解模块，以接收所述第一及第二脉冲信号，以在所述第一脉冲信号的处于第一沿时抓取所述第二脉冲信号的状态，从而根据抓取到的所述第二脉冲信号的状态控制输出的驱动电压的极性。
其中，所述合成模块包括第一合成单元及第二合成单元，所述第一及第二合成单元均连接至所述脉冲信号生成模块及所述数据信号发送模块之间，所述第一合成单元用于将第一脉冲信号合成至所述数据信号中，所述第二合成单元用于将第二脉冲信号合成至所述数据信号中，从而形成所述合成数据信号。
其中，所述分解模块包括第一分解单元及第二分解单元，所述第一及第二分解单元均连接至所述数据接收模块，所述第一分解单元用于对所述合成数据信号进行分解，以得到所述第一脉冲信号，所述第二分解单元用于对所述合成数据信号进行分解，以得到所述第二脉冲信号。
其中，所述第一及第二脉冲信号的占空比不同。
其中，所述第一脉冲信号为TP信号，所述第二脉冲信号为POL信号。
其中，所述数据信号还包括复位段，所述复位段位于所述无效数据段与有效数据段之间。
本发明一种时序控制芯片，应用于液晶显示器的驱动电路中，以连接所述驱动电路中的数据驱动芯片，所述时序控制芯片包括脉冲信号生成模块、数据信号发送模块及合成模块。所述脉冲信号生成模块用于生成第一脉冲信号及第二脉冲信号；所述数据信号发送模块包括数据输出引脚，所述数据信号包括有效数据段及无效数据段；所述合成模块连接至所述脉冲信号生成模块及所述数据信号发送模块之间，用于将第一及第二脉冲信号合成至所述数据信号的无效数据段中，以形成合成数据信号，并将所述合成数据信号传输至所述数据信号 发送模块；其中，所述第一及第二脉冲信号与所述有效数据段至少具有预设第一时间间隔，所述第一及第二脉冲信号之间具有预设第二时间间隔；其中，所述数据信号发送模块的数据输出引脚用于连接至所述数据驱动芯片，以将所述合成数据信号发送至所述数据驱动芯片，以使所述数据驱动芯片分解出第一及第二脉冲信号，从而在所述第一脉冲信号的处于第一沿时抓取所述第二脉冲信号的状态，进而根据抓取到的所述第二脉冲信号的状态控制输出的驱动电压的极性。因此，所述时序控制芯片相较于现有的时序控制芯片减少了脉冲信号输出引脚，从而达到了减少所述时序控制芯片的引脚数量，减小了时序控制芯片的面积及成本的目的，进而减少了承载所述时序控制芯片的印刷电路板的面积。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以如这些附图获得其他的附图。
图1是本发明第一方案实施例提供的一种时序控制芯片的框图；
图2是图1中脉冲信号生成模块产生的第一及第二脉冲信号的波形图；
图3是图1时序控制芯片输出的合成数据信号的数据段示意图；
图4是本发明第二方案实施例提供的一种数据驱动芯片的框图；
图5是本发明第三方案实施例提供的一种驱动电路的框图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
请参阅图1至图3，本发明第一方案实施例提供一种时序控制芯片100。所述时序控制芯片100应用于液晶显示器的驱动电路中，以连接所述驱动电路 中的数据驱动芯片。所述时序控制芯片100包括脉冲信号生成模块10、数据信号发送模块20及合成模块30。
所述脉冲信号生成模块10用于生成第一脉冲信号11及第二脉冲信号12。
其中，在本实施例中，所述第一脉冲信号11为TP信号。所述第二脉冲信号12为POL信号。
所述数据信号发送模块20具有数据信号21。所述数据信号发送模块20包括数据输出引脚22。所述数据输出引脚21用于输出所述数据信号。所述数据信号21包括有效数据段211及无效数据段212。
所述合成模块30连接至所述脉冲信号生成模块10及所述数据信号发送模块20之间，用于将第一及第二脉冲信号11及12合成至所述数据信号21的无效数据段212中，以形成合成数据信号31，并将所述合成数据信号31传输至所述数据信号发送模块20。其中，所述第一及第二脉冲信号11及12与所述有效数据段21至少具有预设第一时间间隔T1。所述第一及第二脉冲信号11及12之间具有预设第二时间间隔T2。其中，所述数据信号发送模块20的数据输出引脚22用于连接至所述数据驱动芯片，以将所述合成数据信号31发送至所述数据驱动芯片，以使所述数据驱动芯片分解出第一及第二脉冲信号11及12，从而在所述第一脉冲信号11的处于第一沿时抓取所述第二脉冲信号12的状态，进而根据抓取到的所述第二脉冲信号12的状态控制输出的驱动电压的极性。
需要说明的是，在本实施方式中，所述第一脉冲信号11及所述第二脉冲信号12的占空比不同。所述第一脉冲信号11的第一沿可以为上升沿。所述数据驱动芯片在所述第一脉冲信号11的处于上升沿时抓取所述第二脉冲信号12的状态，并根据抓取到的所述第二脉冲信号12的状态控制输出的驱动电压的极性。所述第一及第二脉冲信号11及12与所述有效数据段21至少具有预设第一时间间隔T1，以防止和有效数据段21中的有效数据混合。当所述第一及第二脉冲信号11及12中距离所述有效数据段211最近的脉冲信号与所述有效数据段211之间的时间间隔为所述预设第一时间间隔T1。
在本实施例中，所述合成模块30连接至所述脉冲信号生成模块10及所述数据信号发送模块20之间，用于将第一及第二脉冲信号合成至所述数据信号 21的无效数据段212中，以形成合成数据信号31，并将所述合成数据信号31传输至所述数据信号发送模块20。其中，所述第一及第二脉冲信号11及12与所述有效数据段21具有预设第一时间间隔T1。所述第一及第二脉冲信号11及12之间具有预设第二时间间隔T2。其中，所述数据信号发送模块20的数据输出引脚22用于连接至所述数据驱动芯片，以将所述合成数据信号31发送至所述数据驱动芯片，以使所述数据驱动芯片分解出第一及第二脉冲信号11及12，从而在所述第一脉冲信号11的处于第一沿时抓取所述第二脉冲信号12的状态，进而根据抓取到的所述第二脉冲信号12的状态控制输出的驱动电压的极性。因此，所述时序控制芯片100相较于现有的时序控制芯片减少了脉冲信号输出引脚，从而达到了减少所述时序控制芯片100的引脚数量，减小了时序控制芯片100的面积及成本的目的，进而减少了承载所述时序控制芯片100的印刷电路板的面积。
可选地，所述合成模块30包括第一合成单元32及第二合成单元33。所述第一及第二合成单元32及33均连接至所述脉冲信号生成模块10及所述数据信号发送模块20之间。所述第一合成单元32用于将第一脉冲信号11合成至所述数据信号21中。所述第二合成单元12用于将第二脉冲信号12合成至所述数据信号21中，从而形成所述合成数据信号31。
需要说明的是，所述第一及第二脉冲信号11及12分别通过第一及第二合成单元32及33合成至所述数据信号21中，从而实现了分别独立控制，提供了合成的灵活性。
可选地，所述数据信号21还包括复位段213。所述复位段213位于所述无效数据段212与有效数据段211之间。
需要说明的是，所述复位段213的作用是当读取到所述复位段213时，即意味着需要读取的下一数据段为有效数据段211。
请参阅图4，本发明第二方案提供一种数据驱动芯片400。所述数据驱动芯片400应用于液晶显示器的驱动电路中，以连接时序控制芯片100。所述数据驱动芯片400包括数据接收模块410、分解模块412及电压输出控制模块413。
所述数据接收模块410包括数据接收引脚411。所述数据接收引脚411用 于连接至所述时序控制芯片100的数据输出引脚22，以接收时序控制芯片100输出的合成数据信号31。其中，所述合成数据信号31的无效数据段212中具有第一脉冲信号11及第二脉冲信号12。所述第一及第二脉冲信号11及12与所述有效数据段211至少具有预设第一时间间隔T1。所述第一及第二脉冲信号11及12之间至少具有第二预设时间间隔T2。
所述分解模块412连接所述数据接收模块410，以对所述合成数据信号31进行分解，以分别得到所述第一及第二脉冲信号11及12。
所述电压数据控制模块413连接至所述分解模块412，以接收所述第一及第二脉冲信号11及12，以在所述第一脉冲信号11的处于第一沿时抓取所述第二脉冲信号12的状态，从而根据抓取到的所述第二脉冲信号12的状态控制输出的驱动电压的极性。
在本实施例中，由于第一及第二脉冲信号11及12合成在所述数据信号21中形成合成数据信号30，所述分解模块412连接所述数据接收模块410，以对所述合成数据信号31进行分解，以分别得到所述第一及第二脉冲信号11及12。所述电压数据控制模块413连接至所述分解模块412，以接收所述第一及第二脉冲信号11及12，以在所述第一脉冲信号11的处于第一沿时抓取所述第二脉冲信号12的状态，从而根据抓取到的所述第二脉冲信号12的状态控制输出的驱动电压的极性。因此，所述数据驱动芯片400相较于现有的数据驱动芯片减少了脉冲信号接收引脚，从而达到了减少所述数据驱动芯片400的引脚数量，减小了数据驱动芯片400的面积及成本的目的，进而减少了承载所述数据驱动芯片400的印刷电路板的面积。
可选地，所述分解模块412包括第一分解单元4121及第二分解单元4122。所述第一及第二分解单元4121及4122均连接至所述数据接收模块410。所述第一分解单元4121用于对所述合成数据信号31进行分解，以得到所述第一脉冲信号11。所述第二分解单元4122用于对所述合成数据信号12进行分解，以得到所述第二脉冲信号12。
需要说明的是，所述第一及第二脉冲信号11及12分别由第一及第二分解单元4121及4122分解出来，从而实现了分别独立控制，提供了分解的灵活性。
请参阅图5，本发明第三方案实施例提供了一种驱动电路500。所述驱动 电路应用于液晶显示器中。所述驱动电路500包括时序控制芯片及数据驱动芯片。在本实施方式中，所述时序控制芯片为上述第一方案提供的时序控制芯片100。所述数据驱动芯片为上述第二方案提供的数据驱动芯片400。所述时序控制芯片100通过所述数据输出引脚22连接至所述数据驱动芯片400的数据接收引脚411，从而实现所述时序控制芯片100与所述数据驱动芯片400的连接。
其中，所述时序控制芯片100及所述数据驱动芯片400的结构及功能已在上述第一方案及第二方案中进行了详细的阐述，在此不再进行赘述。
在本实施中，所述合成模块30连接至所述脉冲信号生成模块10及所述数据信号发送模块20之间，用于将第一及第二脉冲信号合成至所述数据信号21的无效数据段212中，以形成合成数据信号31，并将所述合成数据信号31通过所述数据输出引脚22及所述数据驱动芯片400的数据接收引脚411传输至所述数据接收模块410。所述分解模块412连接所述数据接收模块410，以对所述合成数据信号31进行分解，以分别得到所述第一及第二脉冲信号11及12。所述电压数据控制模块413连接至所述分解模块412，以接收所述第一及第二脉冲信号11及12，以在所述第一脉冲信号11的处于第一沿时抓取所述第二脉冲信号12的状态，从而根据抓取到的所述第二脉冲信号12的状态控制输出的驱动电压的极性。因此，在本发明中，所述时序控制芯片100相较于现有的时序控制芯片减少了脉冲信号输出引脚、所述数据驱动芯片400相较于现有的数据驱动芯片减少了脉冲信号接收引脚，从而达到了减少所述时序控制芯片100及所述数据驱动芯片400的引脚数量，减小了所述时序控制芯片100及所述数据驱动芯片400的面积及成本的目的，进而减小了承载所述时序控制芯片100及所述数据驱动芯片400的印刷电路板的面积。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (10)

  1. 一种时序控制芯片，应用于液晶显示器的驱动电路中，以连接所述驱动电路中的数据驱动芯片，其特征在于：所述时序控制芯片包括：
    脉冲信号生成模块，所述脉冲信号生成模块用于生成第一脉冲信号及第二脉冲信号；
    数据信号发送模块，所述数据信号发送模块具有数据信号，所述数据信号发送模块包括数据输出引脚，所述数据信号包括有效数据段及无效数据段；
    合成模块，所述合成模块连接至所述脉冲信号生成模块及所述数据信号发送模块之间，用于将第一及第二脉冲信号合成至所述数据信号的无效数据段中，以形成合成数据信号，并将所述合成数据信号传输至所述数据信号发送模块；其中，所述第一及第二脉冲信号与所述有效数据段至少具有预设第一时间间隔，且所述第一及第二脉冲信号之间具有预设第二时间间隔；其中，所述数据信号发送模块的数据输出引脚用于连接至所述数据驱动芯片，以将所述合成数据信号发送至所述数据驱动芯片，使得所述数据驱动芯片从所述合成数据信号中分解出第一及第二脉冲信号，以在所述第一脉冲信号的处于第一沿时抓取所述第二脉冲信号的状态，从而根据抓取到的所述第二脉冲信号的状态控制输出的驱动电压的极性。
  2. 如权利要求1所述的时序控制芯片，其特征在于，所述合成模块包括第一合成单元及第二合成单元，所述第一及第二合成单元均连接至所述脉冲信号生成模块及所述数据信号发送模块之间，所述第一合成单元用于将第一脉冲信号合成至所述数据信号中，所述第二合成单元用于将第二脉冲信号合成至所述数据信号中，从而形成所述合成数据信号。
  3. 如权利要求1所述的时序控制芯片，其特征在于，所述第一及第二脉冲信号的占空比不同。
  4. 如权利要求1所述的时序控制芯片，其特征在于，所述第一脉冲信号为TP信号，所述第二脉冲信号为POL信号。
  5. 如权利要求1所述的驱动电路，其特征在于，所述数据信号还包括复位段，所述复位段位于所述无效数据段与有效数据段之间。
  6. 如权利要求5所述的显示面板的驱动电路，其特征在于，与所述复位段相连的第一或第二脉冲数据与所述复位数据段之间具有预设第三时间间隔。
  7. 一种数据驱动芯片，应用于液晶显示器的驱动电路中，以连接时序控制芯片，其特征在于：所述数据驱动芯片包括：
    数据接收模块，所述数据接收模块包括数据接收引脚，所述数据接收引脚用于连接至所述时序控制芯片的数据输出引脚，以接收时序控制芯片输出的合成数据信号；其中，所述合成数据信号的无效数据段中具有第一脉冲信号及第二脉冲信号，所述第一及第二脉冲信号与所述有效数据段至少具有预设第一时间间隔，且所述第一及第二脉冲信号之间具有第二预设时间间隔；
    分解模块，所述分解模块连接所述数据接收模块，以对所述合成数据信号进行分解，以分别得到所述第一及第二脉冲信号；
    电压输出控制模块，所述电压数据控制模块连接至所述分解模块，以接收所述第一及第二脉冲信号，以在所述第一脉冲信号的处于第一沿时抓取所述第二脉冲信号的状态，从而根据抓取到的所述第二脉冲信号的状态控制输出的驱动电压的极性。
  8. 如权利要求7所述的驱动电路，其特征在于，所述分解模块包括第一分解单元及第二分解单元，所述第一及第二分解单元均连接至所述数据接收模块，所述第一分解单元用于对所述合成数据信号进行分解，以得到所述第一脉冲信号，所述第二分解单元用于对所述合成数据信号进行分解，以得到所述第二脉冲信号。
  9. 如权利要求7所述的驱动电路，其特征在于，所述第一及第二脉冲信号的占空比不同。
  10. 如权利要求4所述的驱动电路，其特征在于，所述第一脉冲信号为TP信号，所述第二脉冲信号为POL信号。
PCT/CN2015/087798 2015-08-10 2015-08-21 一种驱动电路 WO2017024610A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/785,852 US9886929B2 (en) 2015-08-10 2015-08-21 Driving circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510485609.7 2015-08-10
CN201510485609.7A CN105096868B (zh) 2015-08-10 2015-08-10 一种驱动电路

Publications (1)

Publication Number Publication Date
WO2017024610A1 true WO2017024610A1 (zh) 2017-02-16

Family

ID=54577160

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/087798 WO2017024610A1 (zh) 2015-08-10 2015-08-21 一种驱动电路

Country Status (3)

Country Link
US (1) US9886929B2 (zh)
CN (1) CN105096868B (zh)
WO (1) WO2017024610A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113452357A (zh) * 2021-06-18 2021-09-28 杭州士兰微电子股份有限公司 Igbt的驱动电路和驱动方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105390106B (zh) * 2015-12-07 2018-12-21 深圳市华星光电技术有限公司 薄膜晶体管液晶显示面板的电平转换电路及电平转换方法
CN105810169A (zh) 2016-05-25 2016-07-27 深圳市华星光电技术有限公司 液晶显示器的驱动系统及驱动方法
CN106938052B (zh) * 2017-04-26 2023-07-25 中国工程物理研究院流体物理研究所 一种双极性纳秒脉冲电场加载、电场灭菌装置及方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1725286A (zh) * 2004-07-23 2006-01-25 Lg.菲利浦Lcd株式会社 液晶显示器件的驱动电路及其驱动方法
US20080315933A1 (en) * 2007-06-20 2008-12-25 Shiro Sakiyama Pulse synthesis circuit
CN103345897A (zh) * 2013-06-20 2013-10-09 深圳市华星光电技术有限公司 主动矩阵显示装置、扫描驱动电路及其扫描驱动方法
CN104125315A (zh) * 2013-04-23 2014-10-29 深圳富泰宏精密工业有限公司 时序控制系统及方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003241720A (ja) * 2002-02-20 2003-08-29 Casio Comput Co Ltd 液晶駆動装置
US6925505B2 (en) * 2003-02-26 2005-08-02 Epo Science & Technology Inc. Method and device for data transmission control between IDE apparatuses
US7705841B2 (en) * 2006-01-20 2010-04-27 Novatek Microelectronics Corp. Display system and method for embeddedly transmitting data signals, control signals, clock signals and setting signals
KR100986041B1 (ko) * 2008-10-20 2010-10-07 주식회사 실리콘웍스 클럭 신호가 임베딩된 단일 레벨 신호 전송을 이용한 디스플레이 구동 시스템
CN103544128B (zh) * 2013-10-28 2016-08-24 无锡中感微电子股份有限公司 芯片之间的单信号线通信方法、装置及系统
KR102161702B1 (ko) * 2013-12-03 2020-10-07 삼성디스플레이 주식회사 표시 패널 구동 방법, 이를 수행하기 위한 표시 패널 구동 장치 및 이 표시패널 구동 장치를 포함하는 표시 장치
KR102350904B1 (ko) * 2014-01-17 2022-01-14 삼성디스플레이 주식회사 표시 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1725286A (zh) * 2004-07-23 2006-01-25 Lg.菲利浦Lcd株式会社 液晶显示器件的驱动电路及其驱动方法
US20080315933A1 (en) * 2007-06-20 2008-12-25 Shiro Sakiyama Pulse synthesis circuit
CN104125315A (zh) * 2013-04-23 2014-10-29 深圳富泰宏精密工业有限公司 时序控制系统及方法
CN103345897A (zh) * 2013-06-20 2013-10-09 深圳市华星光电技术有限公司 主动矩阵显示装置、扫描驱动电路及其扫描驱动方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113452357A (zh) * 2021-06-18 2021-09-28 杭州士兰微电子股份有限公司 Igbt的驱动电路和驱动方法
CN113452357B (zh) * 2021-06-18 2023-12-26 杭州士兰微电子股份有限公司 Igbt的驱动电路和驱动方法

Also Published As

Publication number Publication date
US20170162163A1 (en) 2017-06-08
CN105096868A (zh) 2015-11-25
CN105096868B (zh) 2018-12-21
US9886929B2 (en) 2018-02-06

Similar Documents

Publication Publication Date Title
WO2019104835A1 (zh) 异形切割的oled显示面板及oled显示器
US10229646B2 (en) Liquid crystal display driving system and method
CN105047146B (zh) 显示设备
WO2017024610A1 (zh) 一种驱动电路
TWI292569B (en) Chip-on-glass liquid crystal display and transmission method thereof
JP2006251772A (ja) 液晶ディスプレイの駆動回路
US20190164489A1 (en) Notch cutting oled display panel and oled display
US9224347B2 (en) TFT-LCD driving circuit
TW200406613A (en) Display device
WO2017202053A1 (zh) 触摸屏、显示装置以及触摸屏的驱动方法
WO2018076459A1 (zh) 液晶面板驱动电路及液晶显示装置
JP2004233580A (ja) 表示装置
US10192515B2 (en) Display device and data driver
US10636376B2 (en) GOA circuit for scan enhancing
CN105976778B (zh) 液晶显示面板的数据驱动系统
WO2019061880A1 (zh) 显示面板及其显示装置
TWI421823B (zh) 用於平面顯示器的顯示控制裝置及平面顯示裝置
CN101334978A (zh) 显示设备、其驱动方法和合并了显示设备的电子装置
KR100864921B1 (ko) 데이터 전송 장치 및 방법
TW200529122A (en) Source driver for display
WO2019196140A1 (zh) 像素驱动电路及液晶显示电路
US11210974B2 (en) Driving circuit of display apparatus
US8253715B2 (en) Source driver and liquid crystal display device having the same
KR101739137B1 (ko) 액정표시장치
US10825411B2 (en) Shutdown signal generation circuit and display apparatus

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14785852

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15900807

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15900807

Country of ref document: EP

Kind code of ref document: A1