WO2019196140A1 - 像素驱动电路及液晶显示电路 - Google Patents

像素驱动电路及液晶显示电路 Download PDF

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Publication number
WO2019196140A1
WO2019196140A1 PCT/CN2018/084846 CN2018084846W WO2019196140A1 WO 2019196140 A1 WO2019196140 A1 WO 2019196140A1 CN 2018084846 W CN2018084846 W CN 2018084846W WO 2019196140 A1 WO2019196140 A1 WO 2019196140A1
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Prior art keywords
thin film
film transistor
pixel unit
output end
pixel
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PCT/CN2018/084846
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English (en)
French (fr)
Inventor
左清成
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武汉华星光电技术有限公司
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Priority to US16/074,453 priority Critical patent/US10748495B2/en
Publication of WO2019196140A1 publication Critical patent/WO2019196140A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a pixel driving circuit and a liquid crystal display circuit.
  • FIG. 1 This is a 1:3 signal driver architecture commonly used in small and medium size LCD displays.
  • Figure 2 shows an RGB-RGB Demux drive timing corresponding to this driver architecture.
  • the disadvantage is that the frequency at which the MUX is turned on is higher, resulting in a larger power consumption of the MUX circuit.
  • the power consumption conference is one of its fatal bottlenecks. Therefore, the industry developers have proposed the RGB-BGR Demux driving sequence shown in Figure 3, as shown in Figure 3.
  • the drive timing reduces the turn-on frequency of the MUXR and MUXB by half, which greatly reduces the power consumption of the LCD display.
  • An object of the embodiments of the present invention is to provide a pixel driving circuit and a liquid crystal display circuit, which have the beneficial effects of reducing color shift and improving display quality.
  • Embodiments of the present invention provide a pixel driving circuit for driving a pixel structure, the pixel structure including a plurality of pixel units, each pixel unit including three sub-pixel units: a red sub-pixel unit, a green sub-pixel unit, and a blue Asia a pixel unit, wherein the pixel driving circuit comprises:
  • each strobe unit having a data input end, a first output end, a second output end, and a third output end, wherein the data input end is respectively connected to an output end of a data line, and the first output end Connected to the red sub-pixel unit of the corresponding pixel unit, the second output end is connected to the green sub-pixel unit of the corresponding pixel unit, and the third output end is connected to the blue sub-pixel unit of the corresponding pixel unit;
  • each scan line being respectively connected to each sub-pixel unit of at least one pixel unit;
  • each of the transformer units is connected to the scan signal, and the output end is connected to a scan line; each of the transformer units has a voltage regulation state and a through state;
  • the voltage transformation unit switches the voltage regulation state and maintains the first preset The duration, in the voltage regulation state, the voltage conversion unit switches the scan signal outputted to the sub-pixel unit from a high level to a low level, and the voltage transformation unit switches back to the through state after being in the voltage regulation state for a first preset time period;
  • the transformer unit is a gate circuit having two input terminals, one input end of the gate circuit is connected to the scan signal, and the other input end of the gate circuit is connected to the square wave signal, and the output end of the gate circuit is Scan line connection;
  • the gate unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor; an input end of the first thin film transistor, an input end of the second thin film transistor, and an input end of the third thin film transistor Connected to and connected to a data line, an output end of the first thin film transistor is connected to a red sub-pixel unit of a corresponding pixel unit, and an output end of the second thin film transistor is connected to a green sub-pixel unit of the corresponding pixel unit.
  • the output end of the third thin film transistor is connected to the blue sub-pixel unit of the corresponding pixel unit.
  • the gate circuit is an AND gate, and the square wave signal is in a low state in a voltage regulation state and a high state in a through state.
  • a gate controller is further included, and the gate controller is respectively connected to the gates of the first thin film transistor, the second thin film transistor, and the third thin film transistor.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor are all NMOS transistors.
  • An embodiment of the present invention further provides a pixel driving circuit for driving a pixel structure, the pixel structure including a plurality of pixel units, each pixel unit including three sub-pixel units: a red sub-pixel unit, a green sub-pixel unit, and a blue a sub-pixel unit, the pixel driving circuit comprising:
  • each strobe unit having a data input end, a first output end, a second output end, and a third output end, wherein the data input end is respectively connected to an output end of a data line, and the first output end Connected to the red sub-pixel unit of the corresponding pixel unit, the second output end is connected to the green sub-pixel unit of the corresponding pixel unit, and the third output end is connected to the blue sub-pixel unit of the corresponding pixel unit;
  • each scan line being respectively connected to each sub-pixel unit of at least one pixel unit;
  • each of the transformer units is connected to the scan signal, and the output end is connected to a scan line; each of the transformer units has a voltage regulation state and a through state;
  • the voltage transformation unit switches the voltage regulation state and maintains the first preset The duration, in the voltage regulation state, the voltage conversion unit switches the scan signal outputted to the sub-pixel unit from a high level to a low level, and the voltage transformation unit switches back to the through state after being in the voltage regulation state for a first preset time period.
  • the voltage transforming unit is a gate circuit having two input terminals, one input end of the gate circuit is connected to the scan signal, and the other input end of the gate circuit is connected to one side.
  • a wave signal, the output of the gate is connected to the scan line.
  • the gate circuit is an AND gate, and the square wave signal is in a low state in a voltage regulation state and a high state in a through state.
  • the gate unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor; an input end of the first thin film transistor and an input of the second thin film transistor And an input end of the third thin film transistor is connected to and connected to a data line, an output end of the first thin film transistor is connected to a red sub-pixel unit of a corresponding pixel unit, and an output end of the second thin film transistor Connected to the green sub-pixel unit of the corresponding pixel unit, the output end of the third thin film transistor is connected to the blue sub-pixel unit of the corresponding pixel unit.
  • a gate controller is further included, and the gate controller is respectively connected to the gates of the first thin film transistor, the second thin film transistor, and the third thin film transistor.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor are all NMOS transistors.
  • a liquid crystal display circuit comprising a pixel driving circuit and a pixel structure, the pixel structure comprising a plurality of pixel units, each pixel unit comprising three sub-pixel units: a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit,
  • the pixel driving circuit includes:
  • each strobe unit having a data input end, a first output end, a second output end, and a third output end, wherein the data input end is respectively connected to an output end of a data line, and the first output end Connected to the red sub-pixel unit of the corresponding pixel unit, the second output end is connected to the green sub-pixel unit of the corresponding pixel unit, and the third output end is connected to the blue sub-pixel unit of the corresponding pixel unit;
  • each scan line being respectively connected to each sub-pixel unit of at least one pixel unit;
  • each of the transformer units is connected to the scan signal, and the output end is connected to a scan line; each of the transformer units has a voltage regulation state and a through state;
  • the voltage transformation unit switches the voltage regulation state and maintains the first preset The duration, in the voltage regulation state, the voltage conversion unit switches the scan signal outputted to the sub-pixel unit from a high level to a low level, and the voltage transformation unit switches back to the through state after being in the voltage regulation state for a first preset time period.
  • the voltage transformation unit is a gate circuit having two input terminals, one input end of the gate circuit is connected to the scan signal, and the other input end of the gate circuit is connected to one side.
  • a wave signal, the output of the gate is connected to the scan line.
  • the gate circuit is an AND gate, and the square wave signal is in a low state in a voltage regulation state and a high state in a through state.
  • the gate unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor; an input end of the first thin film transistor and an input of the second thin film transistor And an input end of the third thin film transistor is connected to and connected to a data line, an output end of the first thin film transistor is connected to a red sub-pixel unit of a corresponding pixel unit, and an output end of the second thin film transistor Connected to the green sub-pixel unit of the corresponding pixel unit, the output end of the third thin film transistor is connected to the blue sub-pixel unit of the corresponding pixel unit.
  • a gate controller is further included, and the gate controller is respectively connected to the gates of the first thin film transistor, the second thin film transistor, and the third thin film transistor.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor are all NMOS transistors.
  • the pixel driving circuit provided by the invention enables the red/green/blue sub-pixel units (R/G/B sub-pixel units) to have the same voltage drop when charging, so as to ensure that the gray scales of all sub-pixel displays are consistent, thereby avoiding occurrence.
  • the color shift of the display due to the voltage is not.
  • FIG. 1 is a structural diagram of a pixel driving circuit in the prior art.
  • FIG. 2 is a driving timing diagram of a pixel driving circuit in the prior art.
  • FIG. 3 is another driving timing diagram of a pixel driving circuit in the prior art.
  • FIG. 4 is another driving timing and pixel cell voltage drop diagram of the pixel driving circuit in the prior art.
  • FIG. 5 is a structural diagram of a pixel driving circuit in some embodiments of the present invention.
  • FIG. 6 is a diagram showing driving timings and pixel cell voltage drops of a pixel driving circuit according to some embodiments of the present invention.
  • FIG. 7 is a structural diagram of a liquid crystal display circuit in some embodiments of the present invention.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include one or more of the described features either explicitly or implicitly.
  • the meaning of "a plurality” is two or more unless specifically and specifically defined otherwise.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; may be mechanically connected, may be electrically connected or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediate medium, may be internal communication of two elements or interaction of two elements relationship.
  • Connected, or integrally connected may be mechanically connected, may be electrically connected or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediate medium, may be internal communication of two elements or interaction of two elements relationship.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the first feature "on” or “under” the second feature may include direct contact of the first and second features, and may also include first and second features, unless otherwise specifically defined and defined. It is not in direct contact but through additional features between them.
  • the first feature "above”, “above” and “above” the second feature includes the first feature directly above and above the second feature, or merely indicating that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature includes the first feature directly below and below the second feature, or merely the first feature level being less than the second feature.
  • FIG. 1 is a structural diagram of a pixel driving circuit in some embodiments of the present invention.
  • the pixel driving circuit is for driving a pixel structure. among them.
  • the pixel structure includes a plurality of pixel units arranged in a matrix, each pixel unit including three sub-pixel units: a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit.
  • the pixel driving circuit includes a plurality of transforming units 10, a plurality of data lines S, a plurality of gate units 20, and a plurality of scanning lines GATE(m).
  • each data line S is connected to the data signal.
  • Each of the gating units 20 has a data input end, a first output end, a second output end, and a third output end.
  • the data input end is respectively connected to an output end of a data line S, and the first output end is connected to The red sub-pixel unit of the corresponding pixel unit is connected, the second output end is connected to the green sub-pixel unit of the corresponding pixel unit, and the third output end is connected to the blue sub-pixel unit of the corresponding pixel unit.
  • Each of the scan lines GATE(m) is connected to each sub-pixel unit of at least one pixel unit.
  • each transformer unit 10 The input end of each transformer unit 10 is connected to a scan signal, and the output end is connected to a scan line.
  • Each of the transforming units 10 is for processing the scan signal, and then transmitting the processed scan signal to the scan line GATE(m).
  • Each of the voltage transformation units 10 has a voltage regulation state and a through state, wherein when the signal outputted by the first output terminal of the gate unit 20 is switched from a high level to a low level or the second output end of the gate unit 20 When the signal is switched from the high level to the low level, the voltage transformation unit 10 switches the voltage regulation state and maintains the voltage regulation state for the first preset time length.
  • the voltage transformation unit 10 When the voltage transformation unit 10 is in the voltage regulation state, the scan signal input from the input terminal is switched from the high level to the low level, and then the switched scan signal is transmitted to the scan line GATE(m).
  • the transformer unit 10 switches back to the through state after the voltage regulation state continues for the first predetermined duration.
  • the transformer unit 10 does not process the scan signal input by the input terminal, and directly transmits it to the scan line, that is, when the input terminal inputs a high level, the high level is input to the scan line, and the input is high.
  • the input is low and the low is passed to the scan line.
  • the transformer unit 10 can be implemented with a gate circuit, for example, the transformer unit 10 is an AND gate having two inputs.
  • An input of the AND gate, the access clock signal CKm, that is, the scan signal that is not processed by the transforming unit 10, is provided by the scan driver.
  • the other input of the AND gate is connected to a square wave signal, and the output of the AND gate is connected to the scan line GATE(m).
  • the square wave signal is at a low level when the voltage transformation unit is in a voltage regulation state, and is at a high level when the pressure transformation unit is in a through state.
  • transformer unit 10 can also be implemented by using other gate circuits as long as the waveform of the signal input by the other input terminal is controlled.
  • the gating unit 20 includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3.
  • the input end of the first thin film transistor T1, the input end of the second thin film transistor T2, and the input end of the third thin film transistor T3 are connected and connected to a data line S.
  • the output end of the first thin film transistor T1 is The red sub-pixel unit of the corresponding pixel unit is connected.
  • the output end of the second thin film transistor T2 is connected to the green sub-pixel unit of the corresponding pixel unit.
  • the output end of the third thin film transistor T3 is connected to the blue sub-pixel unit of the corresponding pixel unit.
  • the pixel driving circuit further includes a gate controller connected to the gates of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3, respectively. It is used to control the on-off condition of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3, wherein when one of the thin film transistors is turned on, the other two thin film transistors are in an off state.
  • FIG. 6 is a driving timing diagram of the pixel driving circuit provided by the present invention, wherein each timing of the AND operation is controlled by TCON in the driving chip to ensure the falling edge of the MUXR and the MUXG. That is, when the signal outputted by the first output terminal is switched from the high level to the low level or the signal of the second output end of the gate unit 20 is switched from the high level to the low level, the scanning of the output line of the scan line Gate(m) The signal is also in a low state.
  • the red/green/blue sub-pixel unit (R/G/B sub-pixel unit) of the present invention can have the same voltage drop when charging, so as to ensure that the gray scales of all sub-pixel displays are consistent, thereby avoiding the occurrence of voltage failure. The resulting color cast of the display.
  • FIG. 7 is a structural diagram of a liquid crystal display circuit in some embodiments of the present invention.
  • the liquid crystal display circuit includes a pixel structure and a pixel driving circuit for driving the pixel structure. among them.
  • the pixel structure includes a plurality of pixel units 30 arranged in a matrix, each pixel unit 30 including three sub-pixel units: a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit.
  • the pixel driving circuit includes a plurality of transforming units 10, a plurality of data lines S, a plurality of gate units 20, and a plurality of scanning lines GATE(m).
  • each data line S is connected to the data signal.
  • Each of the gating units 20 has a data input end, a first output end, a second output end, and a third output end.
  • the data input end is respectively connected to an output end of a data line S, and the first output end is connected to The red sub-pixel unit of the corresponding pixel unit is connected, the second output end is connected to the green sub-pixel unit of the corresponding pixel unit, and the third output end is connected to the blue sub-pixel unit of the corresponding pixel unit.
  • Each of the scan lines GATE(m) is connected to each sub-pixel unit of at least one pixel unit.
  • each transformer unit 10 The input end of each transformer unit 10 is connected to a scan signal, and the output end is connected to a scan line.
  • Each of the transforming units 10 is for processing the scan signal, and then transmitting the processed scan signal to the scan line GATE(m).
  • Each of the voltage transformation units 10 has a voltage regulation state and a through state, wherein when the signal outputted by the first output terminal of the gate unit 20 is switched from a high level to a low level or the second output end of the gate unit 20 When the signal is switched from the high level to the low level, the voltage transformation unit 10 switches the voltage regulation state and maintains the voltage regulation state for the first preset time length.
  • the voltage transformation unit 10 When the voltage transformation unit 10 is in the voltage regulation state, the scan signal input from the input terminal is switched from the high level to the low level, and then the switched scan signal is transmitted to the scan line GATE(m).
  • the transformer unit 10 switches back to the through state after the voltage regulation state continues for the first predetermined duration.
  • the transformer unit 10 does not process the scan signal input by the input terminal, and directly transmits it to the scan line, that is, when the input terminal inputs a high level, the high level is input to the scan line, and the input is high.
  • the input is low and the low is passed to the scan line.
  • the transformer unit 10 can be implemented with a gate circuit, for example, the transformer unit 10 is an AND gate having two inputs.
  • An input of the AND gate, the access clock signal CKm, that is, the scan signal that is not processed by the transforming unit 10, is provided by the scan driver.
  • the other input of the AND gate is connected to a square wave signal, and the output of the AND gate is connected to the scan line GATE(m).
  • the square wave signal is at a low level when the voltage transformation unit is in a voltage regulation state, and is at a high level when the pressure transformation unit is in a through state.
  • transformer unit 10 can also be implemented by using other gate circuits as long as the waveform of the signal input by the other input terminal is controlled.
  • the gating unit 20 includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3.
  • the input end of the first thin film transistor T1, the input end of the second thin film transistor T2, and the input end of the third thin film transistor T3 are connected and connected to a data line S.
  • the output end of the first thin film transistor T1 is The red sub-pixel unit of the corresponding pixel unit is connected.
  • the output end of the second thin film transistor T2 is connected to the green sub-pixel unit of the corresponding pixel unit.
  • the output end of the third thin film transistor T3 is connected to the blue sub-pixel unit of the corresponding pixel unit.
  • the pixel driving circuit further includes a gate controller connected to the gates of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3, respectively. It is used to control the on-off condition of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3, wherein when one of the thin film transistors is turned on, the other two thin film transistors are in an off state.
  • the pixel driving circuit provided by the embodiment of the present invention is described in detail above.
  • the principles and embodiments of the present invention are described in the following. The description of the above embodiments is only for helping to understand the present invention. In the meantime, the present invention is not limited by the scope of the present invention.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明提供了一种像素驱动电路，包括：数据线；选通单元，其数据输入端与数据线的输出端连接，其第一输出端与红亚像素单元连接，其第二输出端与绿亚像素单元连接，其第三输出端与蓝亚像素单元连接；扫描线；变压单元，每一变压单元的输入端接入扫描信号，输出端与一扫描线连接；每一变压单元具有调压状态和直通状态。

Description

像素驱动电路及液晶显示电路 技术领域
本发明涉及液晶显示领域，具体涉及一种像素驱动电路及液晶显示电路。
 背景技术
随着中小尺寸电子显示行业日新月异的发展，人们对中小尺寸LCD液晶显示屏的分辨率等品质要求也越来高。显示品质的提高与显示数据的传输速率和信号的完整性都有着密不可分的联系。如图1所示：这是目前中小尺寸LCD显示屏较常用的一种1:3的信号驱动架构，图2是此驱动架构对应的一种RGB-RGB的Demux驱动时序，这种驱动时序的缺点是：MUX开启的频率较高从而导致MUX电路的功耗较大。而对于像手机这种小尺寸的显示屏，功耗大会是其致命的瓶颈之一，因此业内研发人员又提出了图3所示的RGB-BGR的Demux驱动时序，如图3所示，这种驱动时序会将MUXR和MUXB的开启频率降低一半，从而大大降低了LCD显示屏的功耗。
但这种驱动时序又引出了另一个问题：如图4所示，对于R的数据，由于电容的耦合作用，它的电位会有两次Drop ，第一次是在MUXR关闭时被拉低△V1，第二次是在Gate关闭时再次被拉低△V2，G此时也一样；但对于B的数据，在第一行里却只有一次Drop，即只有当Gate关闭时才会被拉低△V2。综上，R\G与B在显示的过程中数据电压产生的压降不同，以致于最后施加在R\G亚像素和B亚像素上的压差不一样，显示的效果就是同一灰阶时，R\G亚像素和B亚像素具有不同的显示亮度，最终后果就是人眼看起来画面会有色偏。
因此，现有技术存在缺陷，急需改进
 技术问题
本发明实施例的目的是提供一种像素驱动电路及液晶显示电路，具有降低色偏、提高显示质量的有益效果。
 技术解决方案
本发明实施例提供了一种像素驱动电路，用于驱动像素结构，该像素结构包括多个像素单元，每一像素单元包括三个亚像素单元：红亚像素单元、绿亚像素单元以及蓝亚像素单元，其中，该像素驱动电路包括：
多条数据线，其输入端接入数据信号；
多个选通单元，每一选通单元具有一数据输入端、第一输出端、第二输出端以及第三输出端，该数据输入端分别与一条数据线的输出端连接，第一输出端与对应像素单元的红亚像素单元连接，第二输出端与对应像素单元的绿亚像素单元连接，第三输出端与对应像素单元的蓝亚像素单元连接；
多条扫描线，每一条扫描线分别与至少一个像素单元的每一亚像素单元连接；
多个变压单元，每一变压单元的输入端接入扫描信号，输出端与一扫描线连接；每一变压单元具有调压状态和直通状态；
当所述第一输出端输出的信号由高电平切换为低电平时或者第二输出端的信号由高电平切换为低电平时，所述变压单元切换调压状态并保持第一预设时长，在调压状态下变压单元将输出给亚像素单元的扫描信号由高电平切换为低电平，所述变压单元在处于调压状态第一预设时长后切换回直通状态；
所述变压单元为一个具有两个输入端的门电路，该门电路的一个输入端接入扫描信号，所述门电路的另一个输入端接入一方波信号，所述门电路的输出端与扫描线连接；
所述选通单元包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；所述第一薄膜晶体管的输入端、所述第二薄膜晶体管的输入端以及所述第三薄膜晶体管的输入端连接并与一所述数据线连接，所述第一薄膜晶体管的输出端与对应像素单元的红亚像素单元连接，所述第二薄膜晶体管的输出端与对应像素单元的绿亚像素单元连接，所述第三薄膜晶体管的输出端与对应像素单元的蓝亚像素单元连接。
在本发明所述的像素驱动电路中，所述门电路为与门，所述方波信号在调压状态下处于低电平状态，在直通状态下处于高电平状态。
在本发明所述的像素驱动电路中，还包括一选通控制器，所述选通控制器分别与所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管的栅极连接。
在本发明所述的像素驱动电路中，所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为NMOS管。
本发明实施例还提供了一种像素驱动电路，用于驱动像素结构，该像素结构包括多个像素单元，每一像素单元包括三个亚像素单元：红亚像素单元、绿亚像素单元以及蓝亚像素单元，该像素驱动电路包括：
多条数据线，其输入端接入数据信号；
多个选通单元，每一选通单元具有一数据输入端、第一输出端、第二输出端以及第三输出端，该数据输入端分别与一条数据线的输出端连接，第一输出端与对应像素单元的红亚像素单元连接，第二输出端与对应像素单元的绿亚像素单元连接，第三输出端与对应像素单元的蓝亚像素单元连接；
多条扫描线，每一条扫描线分别与至少一个像素单元的每一亚像素单元连接；
多个变压单元，每一变压单元的输入端接入扫描信号，输出端与一扫描线连接；每一变压单元具有调压状态和直通状态；
当所述第一输出端输出的信号由高电平切换为低电平时或者第二输出端的信号由高电平切换为低电平时，所述变压单元切换调压状态并保持第一预设时长，在调压状态下变压单元将输出给亚像素单元的扫描信号由高电平切换为低电平，所述变压单元在处于调压状态第一预设时长后切换回直通状态。
在本发明所述的像素驱动电路中，所述变压单元为一个具有两个输入端的门电路，该门电路的一个输入端接入扫描信号，所述门电路的另一个输入端接入一方波信号，所述门电路的输出端与扫描线连接。
在本发明所述的像素驱动电路中，所述门电路为与门，所述方波信号在调压状态下处于低电平状态，在直通状态下处于高电平状态。
在本发明所述的像素驱动电路中，所述选通单元包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；所述第一薄膜晶体管的输入端、所述第二薄膜晶体管的输入端以及所述第三薄膜晶体管的输入端连接并与一所述数据线连接，所述第一薄膜晶体管的输出端与对应像素单元的红亚像素单元连接，所述第二薄膜晶体管的输出端与对应像素单元的绿亚像素单元连接，所述第三薄膜晶体管的输出端与对应像素单元的蓝亚像素单元连接。
在本发明所述的像素驱动电路中，还包括一选通控制器，所述选通控制器分别与所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管的栅极连接。
在本发明所述的像素驱动电路中，所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为NMOS管。
一种液晶显示电路，包括像素驱动电路以及像素结构，该像素结构包括多个像素单元，每一像素单元包括三个亚像素单元：红亚像素单元、绿亚像素单元以及蓝亚像素单元，该像素驱动电路包括：
多条数据线，其输入端接入数据信号；
多个选通单元，每一选通单元具有一数据输入端、第一输出端、第二输出端以及第三输出端，该数据输入端分别与一条数据线的输出端连接，第一输出端与对应像素单元的红亚像素单元连接，第二输出端与对应像素单元的绿亚像素单元连接，第三输出端与对应像素单元的蓝亚像素单元连接；
多条扫描线，每一条扫描线分别与至少一个像素单元的每一亚像素单元连接；
多个变压单元，每一变压单元的输入端接入扫描信号，输出端与一扫描线连接；每一变压单元具有调压状态和直通状态；
当所述第一输出端输出的信号由高电平切换为低电平时或者第二输出端的信号由高电平切换为低电平时，所述变压单元切换调压状态并保持第一预设时长，在调压状态下变压单元将输出给亚像素单元的扫描信号由高电平切换为低电平，所述变压单元在处于调压状态第一预设时长后切换回直通状态。
在本发明所述的液晶显示电路中，所述变压单元为一个具有两个输入端的门电路，该门电路的一个输入端接入扫描信号，所述门电路的另一个输入端接入一方波信号，所述门电路的输出端与扫描线连接。
在本发明所述的液晶显示电路中，所述门电路为与门，所述方波信号在调压状态下处于低电平状态，在直通状态下处于高电平状态。
在本发明所述的液晶显示电路中，所述选通单元包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；所述第一薄膜晶体管的输入端、所述第二薄膜晶体管的输入端以及所述第三薄膜晶体管的输入端连接并与一所述数据线连接，所述第一薄膜晶体管的输出端与对应像素单元的红亚像素单元连接，所述第二薄膜晶体管的输出端与对应像素单元的绿亚像素单元连接，所述第三薄膜晶体管的输出端与对应像素单元的蓝亚像素单元连接。
在本发明所述的液晶显示电路中，还包括一选通控制器，所述选通控制器分别与所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管的栅极连接。
在本发明所述的液晶显示电路中，所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为NMOS管。
 有益效果
本发明提供的像素驱动电路使得红/绿/蓝亚像素单元(R/G/B亚像素单元)在充电时能够具有相同的压降，以保证所有亚像素显示的灰阶一致，从而避免出现因电压不致而造成的显示的色偏。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的的像素驱动电路的结构图。
图2为现有技术中的的像素驱动电路的一种驱动时序图。
图3为现有技术中的的像素驱动电路的另一种驱动时序图。
图4为现有技术中的像素驱动电路的另一种驱动时序及像素单元压降图。
图5为本发明一些实施例中的像素驱动电路的结构图。
图6为本发明一些实施例中的像素驱动电路的驱动时序及像素单元压降图。
图7为本发明一些实施例中的液晶显示电路的结构图。
 本发明的最佳实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参阅图1，图1是本发明一些实施例中的像素驱动电路的结构图。该像素驱动电路用于驱动像素结构。其中。该像素结构包括多个呈矩阵排布像素单元，每一像素单元包括三个亚像素单元：红亚像素单元、绿亚像素单元以及蓝亚像素单元。
其中，该像素驱动电路包括多个变压单元10、多条数据线S、多个选通单元20、多条扫描线GATE（m）。
其中，该每一数据线S的输入端均接入数据信号。
其中，该每一选通单元20具有一数据输入端、第一输出端、第二输出端以及第三输出端，该数据输入端分别与一条数据线S的输出端连接，第一输出端与对应像素单元的红亚像素单元连接，第二输出端与对应像素单元的绿亚像素单元连接，第三输出端与对应像素单元的蓝亚像素单元连接。
其中，该每一条扫描线GATE（m）分别与至少一个像素单元的每一亚像素单元连接。
其中，该每一变压单元10的输入端接入扫描信号，输出端与一扫描线连接。该每一变压单元10用于对扫描信号进行处理，而后将处理后的扫描信号传递给扫描线GATE（m）。
该每一变压单元10具有调压状态和直通状态，其中，当该选通单元20的第一输出端输出的信号由高电平切换为低电平时或者选通单元20的第二输出端的信号由高电平切换为低电平时，该变压单元10切换调压状态并保持调压状态第一预设时长。该变压单元10在调压状态下时，将由输入端接入的扫描信号由高电平切换为低电平，然后将切换后的扫描信号传递给扫描线GATE（m）。该变压单元10在在调压状态持续第一预设时长后切换回直通状态。直通状态下，该变压单元10不对由输入端接入的扫描信号进行处理，直接传输给扫描线，也即是，输入端输入高电平，则传递给扫描线的就是高电平，输入端输入的是低电平，传递给扫描线的就是低电平。
在一些实施例中，该变压单元10可以采用门电路来实现，例如，该变压单元10为一个具有两个输入端的与门。该与门的一个输入端接入时钟信号CKm也即是未经该变压单元10处理的扫描信号，由扫描驱动器提供。该与门的另一个输入端接入一方波信号，该与门的输出端与扫描线GATE（m）连接。其中，该方波信号在该变压单元处于调压状态下时处于低电平，在该变压单元处于直通状态下时处于高电平。
当然，可以理解地，变压单元10还可以采用其他门电路来实现，只要控制好其另一输入端输入的信号的波形即可。
在一些实施例中，选通单元20包括第一薄膜晶体管T1、第二薄膜晶体管T2以及第三薄膜晶体管T3。
其中，该第一薄膜晶体管T1的输入端、该第二薄膜晶体管T2的输入端以及该第三薄膜晶体管T3的输入端连接并与一数据线S连接，该第一薄膜晶体管T1的输出端与对应像素单元的红亚像素单元连接。该第二薄膜晶体管T2的输出端与对应像素单元的绿亚像素单元连接。该第三薄膜晶体管T3的输出端与对应像素单元的蓝亚像素单元连接。
在一些实施例中，该像素驱动电路还包括一选通控制器，该选通控制器分别与所述第一薄膜晶体管T1、第二薄膜晶体管T2以及第三薄膜晶体管T3的栅极连接。其用于控制该第一薄膜晶体管T1、第二薄膜晶体管T2以及第三薄膜晶体管T3的导通截止情况，其中，当其中一个薄膜晶体管导通时，另外两个薄膜晶体管处于截止状态。
其中，请参照图6，图6是本发明提供的像素驱动电路的驱动时序图，其中，每次作与运算的时机由驱动芯片内的TCON去控制，以保证在MUXR和MUXG的下降沿时，也即是第一输出端输出的信号由高电平切换为低电平时或者选通单元20的第二输出端的信号由高电平切换为低电平时，扫描线Gate(m)输出的扫描信号同时也处于低电平的状态。这样由于选通单元的对应输出端和扫描信号同为低电平，就不会因电容耦合的作用而产生数据电平的压降△V1，从面保证红/绿/蓝亚像素单元的数据电平都具有相同的压降△V2。因此，本发明红/绿/蓝亚像素单元(R/G/B亚像素单元)在充电时能够具有相同的压降，以保证所有亚像素显示的灰阶一致，从而避免出现因电压不致而造成的显示的色偏。
请参照图7，图7是本发明一些实施例中的液晶显示电路的结构图。该液晶显示电路包括像素结构以及用于用于驱动像素结构的像素驱动电路。其中。该像素结构包括多个呈矩阵排布像素单元30，每一像素单元30包括三个亚像素单元：红亚像素单元、绿亚像素单元以及蓝亚像素单元。
其中，该像素驱动电路包括多个变压单元10、多条数据线S、多个选通单元20、多条扫描线GATE（m）。
其中，该每一数据线S的输入端均接入数据信号。
其中，该每一选通单元20具有一数据输入端、第一输出端、第二输出端以及第三输出端，该数据输入端分别与一条数据线S的输出端连接，第一输出端与对应像素单元的红亚像素单元连接，第二输出端与对应像素单元的绿亚像素单元连接，第三输出端与对应像素单元的蓝亚像素单元连接。
其中，该每一条扫描线GATE（m）分别与至少一个像素单元的每一亚像素单元连接。
其中，该每一变压单元10的输入端接入扫描信号，输出端与一扫描线连接。该每一变压单元10用于对扫描信号进行处理，而后将处理后的扫描信号传递给扫描线GATE（m）。
该每一变压单元10具有调压状态和直通状态，其中，当该选通单元20的第一输出端输出的信号由高电平切换为低电平时或者选通单元20的第二输出端的信号由高电平切换为低电平时，该变压单元10切换调压状态并保持调压状态第一预设时长。该变压单元10在调压状态下时，将由输入端接入的扫描信号由高电平切换为低电平，然后将切换后的扫描信号传递给扫描线GATE（m）。该变压单元10在在调压状态持续第一预设时长后切换回直通状态。直通状态下，该变压单元10不对由输入端接入的扫描信号进行处理，直接传输给扫描线，也即是，输入端输入高电平，则传递给扫描线的就是高电平，输入端输入的是低电平，传递给扫描线的就是低电平。
在一些实施例中，该变压单元10可以采用门电路来实现，例如，该变压单元10为一个具有两个输入端的与门。该与门的一个输入端接入时钟信号CKm也即是未经该变压单元10处理的扫描信号，由扫描驱动器提供。该与门的另一个输入端接入一方波信号，该与门的输出端与扫描线GATE（m）连接。其中，该方波信号在该变压单元处于调压状态下时处于低电平，在该变压单元处于直通状态下时处于高电平。
当然，可以理解地，变压单元10还可以采用其他门电路来实现，只要控制好其另一输入端输入的信号的波形即可。
在一些实施例中，选通单元20包括第一薄膜晶体管T1、第二薄膜晶体管T2以及第三薄膜晶体管T3。
其中，该第一薄膜晶体管T1的输入端、该第二薄膜晶体管T2的输入端以及该第三薄膜晶体管T3的输入端连接并与一数据线S连接，该第一薄膜晶体管T1的输出端与对应像素单元的红亚像素单元连接。该第二薄膜晶体管T2的输出端与对应像素单元的绿亚像素单元连接。该第三薄膜晶体管T3的输出端与对应像素单元的蓝亚像素单元连接。
在一些实施例中，该像素驱动电路还包括一选通控制器，该选通控制器分别与所述第一薄膜晶体管T1、第二薄膜晶体管T2以及第三薄膜晶体管T3的栅极连接。其用于控制该第一薄膜晶体管T1、第二薄膜晶体管T2以及第三薄膜晶体管T3的导通截止情况，其中，当其中一个薄膜晶体管导通时，另外两个薄膜晶体管处于截止状态。
以上对本发明实施例提供的像素驱动电路进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (16)

  1. 一种像素驱动电路，用于驱动像素结构，该像素结构包括多个像素单元，每一像素单元包括三个亚像素单元：红亚像素单元、绿亚像素单元以及蓝亚像素单元，其中，该像素驱动电路包括：
    多条数据线，其输入端接入数据信号；
    多个选通单元，每一选通单元具有一数据输入端、第一输出端、第二输出端以及第三输出端，该数据输入端分别与一条数据线的输出端连接，第一输出端与对应像素单元的红亚像素单元连接，第二输出端与对应像素单元的绿亚像素单元连接，第三输出端与对应像素单元的蓝亚像素单元连接；
    多条扫描线，每一条扫描线分别与至少一个像素单元的每一亚像素单元连接；
    多个变压单元，每一变压单元的输入端接入扫描信号，输出端与一扫描线连接；每一变压单元具有调压状态和直通状态；
    当所述第一输出端输出的信号由高电平切换为低电平时或者第二输出端的信号由高电平切换为低电平时，所述变压单元切换调压状态并保持第一预设时长，在调压状态下变压单元将输出给亚像素单元的扫描信号由高电平切换为低电平，所述变压单元在处于调压状态第一预设时长后切换回直通状态；
    所述变压单元为一个具有两个输入端的门电路，该门电路的一个输入端接入扫描信号，所述门电路的另一个输入端接入一方波信号，所述门电路的输出端与扫描线连接；
    所述选通单元包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；所述第一薄膜晶体管的输入端、所述第二薄膜晶体管的输入端以及所述第三薄膜晶体管的输入端连接并与一所述数据线连接，所述第一薄膜晶体管的输出端与对应像素单元的红亚像素单元连接，所述第二薄膜晶体管的输出端与对应像素单元的绿亚像素单元连接，所述第三薄膜晶体管的输出端与对应像素单元的蓝亚像素单元连接。
  2. 根据权利要求1所述的像素驱动电路，其中，所述门电路为与门，所述方波信号在调压状态下处于低电平状态，在直通状态下处于高电平状态。
  3. 根据权利要求1所述的像素驱动电路，其中，还包括一选通控制器，所述选通控制器分别与所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管的栅极连接。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为NMOS管。
  5. 一种像素驱动电路，用于驱动像素结构，该像素结构包括多个像素单元，每一像素单元包括三个亚像素单元：红亚像素单元、绿亚像素单元以及蓝亚像素单元，其中，该像素驱动电路包括：
    多条数据线，其输入端接入数据信号；
    多个选通单元，每一选通单元具有一数据输入端、第一输出端、第二输出端以及第三输出端，该数据输入端分别与一条数据线的输出端连接，第一输出端与对应像素单元的红亚像素单元连接，第二输出端与对应像素单元的绿亚像素单元连接，第三输出端与对应像素单元的蓝亚像素单元连接；
    多条扫描线，每一条扫描线分别与至少一个像素单元的每一亚像素单元连接；
    多个变压单元，每一变压单元的输入端接入扫描信号，输出端与一扫描线连接；每一变压单元具有调压状态和直通状态；
    当所述第一输出端输出的信号由高电平切换为低电平时或者第二输出端的信号由高电平切换为低电平时，所述变压单元切换调压状态并保持第一预设时长，在调压状态下变压单元将输出给亚像素单元的扫描信号由高电平切换为低电平，所述变压单元在处于调压状态第一预设时长后切换回直通状态。
  6. 根据权利要求5所述的像素驱动电路，其中，所述变压单元为一个具有两个输入端的门电路，该门电路的一个输入端接入扫描信号，所述门电路的另一个输入端接入一方波信号，所述门电路的输出端与扫描线连接。
  7. 根据权利要求6所述的像素驱动电路，其中，所述门电路为与门，所述方波信号在调压状态下处于低电平状态，在直通状态下处于高电平状态。
  8. 根据权利要求5所述的像素驱动电路，其中，所述选通单元包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；所述第一薄膜晶体管的输入端、所述第二薄膜晶体管的输入端以及所述第三薄膜晶体管的输入端连接并与一所述数据线连接，所述第一薄膜晶体管的输出端与对应像素单元的红亚像素单元连接，所述第二薄膜晶体管的输出端与对应像素单元的绿亚像素单元连接，所述第三薄膜晶体管的输出端与对应像素单元的蓝亚像素单元连接。
  9. 根据权利要求8所述的像素驱动电路，其中，还包括一选通控制器，所述选通控制器分别与所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管的栅极连接。
  10. 根据权利要求9所述的像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为NMOS管。
  11. 一种液晶显示电路，其包括像素驱动电路以及像素结构，该像素结构包括多个像素单元，每一像素单元包括三个亚像素单元：红亚像素单元、绿亚像素单元以及蓝亚像素单元，该像素驱动电路包括：
    多条数据线，其输入端接入数据信号；
    多个选通单元，每一选通单元具有一数据输入端、第一输出端、第二输出端以及第三输出端，该数据输入端分别与一条数据线的输出端连接，第一输出端与对应像素单元的红亚像素单元连接，第二输出端与对应像素单元的绿亚像素单元连接，第三输出端与对应像素单元的蓝亚像素单元连接；
    多条扫描线，每一条扫描线分别与至少一个像素单元的每一亚像素单元连接；
    多个变压单元，每一变压单元的输入端接入扫描信号，输出端与一扫描线连接；每一变压单元具有调压状态和直通状态；
    当所述第一输出端输出的信号由高电平切换为低电平时或者第二输出端的信号由高电平切换为低电平时，所述变压单元切换调压状态并保持第一预设时长，在调压状态下变压单元将输出给亚像素单元的扫描信号由高电平切换为低电平，所述变压单元在处于调压状态第一预设时长后切换回直通状态。
  12. 根据权利要求11所述的液晶显示电路，其中，所述变压单元为一个具有两个输入端的门电路，该门电路的一个输入端接入扫描信号，所述门电路的另一个输入端接入一方波信号，所述门电路的输出端与扫描线连接。
  13. 根据权利要求12所述的液晶显示电路，其中，所述门电路为与门，所述方波信号在调压状态下处于低电平状态，在直通状态下处于高电平状态。
  14. 根据权利要求11所述的液晶显示电路，其中，所述选通单元包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；所述第一薄膜晶体管的输入端、所述第二薄膜晶体管的输入端以及所述第三薄膜晶体管的输入端连接并与一所述数据线连接，所述第一薄膜晶体管的输出端与对应像素单元的红亚像素单元连接，所述第二薄膜晶体管的输出端与对应像素单元的绿亚像素单元连接，所述第三薄膜晶体管的输出端与对应像素单元的蓝亚像素单元连接。
  15. 根据权利要求14所述的液晶显示电路，其中，还包括一选通控制器，所述选通控制器分别与所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管的栅极连接。
  16. 根据权利要求15所述的液晶显示电路，其中，所述第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均为NMOS管。
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CN106297723A (zh) * 2016-11-09 2017-01-04 厦门天马微电子有限公司 一种像素驱动电路、显示面板以及像素驱动方法

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