WO2017020338A1 - 薄膜晶体管阵列基板及其制备方法、液晶面板 - Google Patents

薄膜晶体管阵列基板及其制备方法、液晶面板 Download PDF

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WO2017020338A1
WO2017020338A1 PCT/CN2015/086815 CN2015086815W WO2017020338A1 WO 2017020338 A1 WO2017020338 A1 WO 2017020338A1 CN 2015086815 W CN2015086815 W CN 2015086815W WO 2017020338 A1 WO2017020338 A1 WO 2017020338A1
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thin film
film transistor
gate insulating
insulating layer
array substrate
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PCT/CN2015/086815
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English (en)
French (fr)
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武岳
雍玮娜
李珊
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深圳市华星光电技术有限公司
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Priority to US14/773,410 priority Critical patent/US20170139247A1/en
Publication of WO2017020338A1 publication Critical patent/WO2017020338A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a thin film transistor array substrate and a method for fabricating the same, and to a liquid crystal panel including the thin film transistor array substrate.
  • LCD Liquid Crystal Display
  • TFT Thin Film Transistor
  • a commonly used liquid crystal panel includes at least an oppositely disposed thin film transistor array substrate and a color filter substrate, and a liquid crystal layer between the thin film transistor array substrate and the filter substrate.
  • the thin film transistor array substrate includes a glass substrate and a thin film transistor arrayed on the glass substrate.
  • the cross-sectional structure of the thin film transistor is as shown in FIG. 1 , and includes a gate electrode 2 formed on the glass substrate 1 and covered on the gate electrode. a gate insulating layer 3 on 2, an active layer 4 formed on the gate insulating layer 3, and a source electrode 5 and a drain electrode 6 formed on the active layer 4.
  • the source electrode 5 and the drain electrode 6 are spaced apart from each other, and a region of the active layer 4 corresponding to the source electrode 5 and the drain electrode 6 being spaced apart from each other is a channel region 4a.
  • 2 is a schematic plan view showing a planar structure of a thin film transistor, in which only the gate electrode 2 of the thin film transistor, the active layer 4, and the source electrode 5 and the drain electrode 6 are shown.
  • the channel region 4a has a length L and a width W.
  • the thin film transistor In the design process of the thin film transistor array substrate, the thin film transistor is required to have a large on-state current and a small off-state current.
  • one of the methods for increasing the on-state current is to increase the aspect ratio (W/L) of the channel region.
  • the way to increase the aspect ratio is either to increase the width W or to decrease the length L.
  • the area of the pixel area needs to be as small as possible, and the aperture ratio needs to be as large as possible. Therefore, the driving thin film transistor and the peripheral circuit cannot exceed a certain area, which determines the channel region width of the thin film transistor. W can't be made too wide.
  • the length-to-length ratio of the channel region of the thin film transistor it is only necessary to reduce the length-to-length ratio of the channel region of the thin film transistor by reducing the length L, but the length L of the channel region of the thin film transistor is reduced to a certain extent.
  • the degree of leakage current and channel breakdown can cause the thin film transistor to fail.
  • the present invention provides a thin film transistor array substrate and a method for fabricating the same, which are used to increase the aspect ratio (W/L) of a thin film transistor channel region to improve an on-state current of a thin film transistor. Improve the driving ability of thin film transistors.
  • a thin film transistor array substrate comprising a plurality of thin film transistors arranged on a glass substrate, each thin film transistor comprising: a gate electrode formed on the glass substrate, and a gate insulating layer disposed on the gate electrode a layer, an active layer formed on the gate insulating layer, and source and drain electrodes formed on the active layer, wherein the source and drain electrodes are spaced apart from each other in a first direction, a region of the active layer corresponding to the source electrode and the drain electrode being spaced apart from each other is a channel region; wherein, the gate insulating layer faces one side of the active layer, and at least a portion corresponding to the channel region has a plurality of And a raised structure forming a pleated surface having a plurality of trenches; a side of the active layer facing the gate insulating layer is completely coupled to a surface of the gate insulating layer.
  • each convex structure extends along the first direction; the plurality of convex structures are sequentially arranged in a second direction perpendicular to the first direction.
  • the protrusion structure extends in a straight line or a curved shape along the first direction.
  • the cross section of the convex structure in the second direction is semicircular or approximately semicircular.
  • the plurality of convex structures are arranged at equal intervals along the second direction, and the cross-sectional surface of the pleated surface having the plurality of grooves has a wavy structure in the second direction.
  • the convex structure has a triangular cross section in the second direction.
  • the plurality of convex structures are arranged at equal intervals in the second direction, and the cross-sectional surface of the pleated surface having the plurality of grooves has a zigzag structure in the second direction.
  • the array substrate further includes scan lines and data lines formed on the glass substrate and pixel regions defined by intersections of scan lines and data lines; the thin film transistor is located in the pixel area, and the pixel area is further set There is a pixel electrode electrically connected to a source electrode or a drain electrode of the thin film transistor.
  • a method for preparing a thin film transistor array substrate comprising the steps of: S101, Providing a glass substrate and preparing a gate electrode on the glass substrate; S102, preparing a gate insulating layer on the gate electrode; wherein the gate insulating layer covers at least the gate electrode; S103, at the gate The upper surface of the insulating layer obtains a pleated surface having a plurality of trenches by a plurality of convex structures by an imprint process or an etching process; S104, preparing an active layer on the gate insulating layer, the active layer One side facing the gate insulating layer is completely meshed with the surface of the gate insulating layer; S105, a source electrode and a drain electrode are formed on the active layer.
  • the present invention also provides a liquid crystal panel comprising an array substrate and a filter substrate disposed opposite to each other and a liquid crystal layer between the array substrate and the filter substrate, wherein the array substrate is a thin film transistor array substrate as described above .
  • the surface of the active layer and the gate insulating layer are mutually coupled at a portion corresponding to the channel region.
  • a raised structure forming a pleated surface having a plurality of grooves, thereby increasing the width of the channel region (the surface of the channel region is expanded to a planar width), and increasing the aspect ratio of the channel region of the thin film transistor (W/L) ), the on-state current of the thin film transistor is improved, and the driving ability of the thin film transistor is improved.
  • the thin film transistor structure does not change the length of the channel region and the vertical width of the channel region (the vertical distance from one end to the other in the width direction) while increasing the aspect ratio of the channel region, Does not cause a decrease in aperture ratio.
  • FIG. 1 is a schematic cross-sectional view of a conventional thin film transistor.
  • FIG. 2 is a schematic plan view showing the structure of the thin film transistor of FIG. 1.
  • FIG. 3 is a schematic structural diagram of a liquid crystal panel according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a thin film transistor array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a filter substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing the planar structure of a thin film transistor according to an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of the thin film transistor of FIG. 6 taken along line AA.
  • FIG. 8 is a schematic cross-sectional view of the thin film transistor of FIG. 6 taken along line BB.
  • Figure 9 is a plan view of a gate insulating layer in an embodiment of the present invention.
  • Figure 10 is a plan view of a gate insulating layer in another embodiment of the present invention.
  • Figure 11 is a side cross-sectional view showing a gate insulating layer in an embodiment of the present invention.
  • Figure 12 is a side cross-sectional view showing a gate insulating layer in another embodiment of the present invention.
  • FIG. 13 is a process flow diagram of a method of fabricating a thin film transistor array substrate in an embodiment of the present invention.
  • the liquid crystal panel provided in this embodiment includes a thin film crystal array substrate 100 and a filter substrate 200 disposed opposite to each other, and a liquid crystal layer 300 between the array substrate 100 and the filter substrate 200 .
  • the thin film crystal array substrate 100 includes a glass substrate 101, scan lines 102 and data lines 103 on the glass substrate 101, and a pixel region 104 defined by the intersection of the scan lines 102 and the data lines 103.
  • a thin film transistor 105 and a pixel electrode 106 electrically connected to the thin film transistor 50 are disposed in the pixel region 104, and the thin film transistor 105 is electrically connected to the scan line 102 and the data line 103.
  • FIG. 1 the thin film crystal array substrate 100 includes a glass substrate 101, scan lines 102 and data lines 103 on the glass substrate 101, and a pixel region 104 defined by the intersection of the scan lines 102 and the data lines 103.
  • a thin film transistor 105 and a pixel electrode 106 electrically connected to the thin film transistor 50 are disposed in the
  • the filter substrate 200 includes at least a glass substrate 201 and a black matrix 202 and a color resist unit 203 formed on the glass substrate 201.
  • the color resist unit 203 includes a red color resist, a green color resist, and a blue color resist.
  • Each color resist 203 in the filter substrate 200 and its surrounding black matrix 202 correspond to one pixel region 104 in the thin film crystal array substrate 100.
  • FIG. 6 is a schematic plan view of a thin film transistor according to the embodiment
  • FIG. 7 is a cross-sectional structural view of the thin film transistor of FIG. 6 along line AA
  • FIG. 8 is a schematic diagram of FIG. Schematic diagram of the cross-sectional structure of the thin film transistor along the BB line.
  • the thin film transistor 105 of the present embodiment includes a gate electrode 10 formed on the glass substrate 101, a gate insulating layer 20 overlying the gate electrode 10, and a gate insulating layer 20 formed on the gate insulating layer 20.
  • the source layer 30 and the source electrode 40 and the drain electrode 50 formed on the active layer 30.
  • the source electrode 40 and the drain electrode 50 are spaced apart from each other in a first direction (such as the X direction in FIG. 6), and the active layer 30 corresponds to a region where the source electrode 40 and the drain electrode 50 are spaced apart from each other.
  • Channel region 60 wherein, in conjunction with FIG. 4, the gate electrode 10 of the thin film transistor 105 is electrically One of the source electrode 40 and the drain electrode 50 is electrically connected to the data line 103, and the other is electrically connected to the pixel electrode 106.
  • the channel region 60 has a length L in the first direction and a vertical width W in the second direction (in the Y direction in FIG. 6).
  • the vertical width W refers to the vertical distance of the channel region 60 from one end to the other end in the second direction.
  • the gate insulating layer 20 faces a side of the active layer 30, and at least a portion corresponding to the channel region 60 has a plurality of convex structures 21 A pleated surface having a plurality of trenches 22 is formed; one side of the active layer 30 facing the gate insulating layer 20 is completely toothed to the surface of the gate insulating layer 20.
  • the active layer 30 and the gate insulating layer 20 are coupled to each other.
  • the side of the active layer 30 facing the gate insulating layer 20 also has a corresponding pleated surface corresponding to the gate insulating layer.
  • the position of the raised structure 21 of 20, the surface of the active layer 30 should have a groove; and at the position corresponding to the groove 22 of the gate insulating layer 20, the surface of the active layer 30 should have a convex structure.
  • each of the plurality of protruding structures 21 on the gate insulating layer 20 extends in the first direction (X direction);
  • the plurality of convex structures 21 are sequentially arranged in the second direction (Y direction).
  • the protruding structure 21 extends linearly in the first direction.
  • the protruding structure 21 in the gate insulating layer 20 may also extend in the first direction to form a curved shape.
  • the cross section of the protruding structure 21 in the second direction is semicircular or approximately semicircular.
  • the plurality of convex structures 21 are equally spaced along the second direction, and the pleated surface having the plurality of grooves 22 has a wavy structure in a cross section in the second direction.
  • the plurality of raised structures 21 may also be arranged at unequal intervals along the second direction.
  • the gate insulating layer 20, the raised structure 21 may also be designed in other shapes, for example, as shown in FIG. 12, the cross section of the raised structure 21 in the second direction.
  • the plurality of convex structures 21 are arranged at equal intervals in the second direction, and the cross-sectional surface of the pleated surface having the plurality of grooves 22 in the second direction has a zigzag structure.
  • the surface of the active layer 30 and the gate insulating layer 20 which are coupled to each other has a plurality of convex structures, forming a pleated surface having a plurality of grooves, thereby increasing the effective width of the channel region 60 (the surface of the channel region 60 is expanded to a planar width which is greater than the vertical width W of the channel region 60), increasing the channel of the thin film transistor
  • the aspect ratio of the region 60 increases the on-state current of the thin film transistor 105 and improves the thinness The driving ability of the film transistor 105.
  • This thin film transistor structure does not change the length of the channel region and the vertical width of the channel region while increasing the aspect ratio of the channel region, and thus does not cause a decrease in aperture ratio.
  • the aspect ratio of the thin film transistor is to be kept constant, in the thin film transistor of such a structure, the vertical width of the channel region can be reduced, thereby increasing the aperture ratio.
  • a method of preparing the thin film transistor array substrate as described above will be described below. As shown in FIG. 13, the method specifically includes the steps of:
  • a glass substrate is provided and a gate electrode is prepared on the glass substrate.
  • a plurality of convex structures are formed on the upper surface of the gate insulating layer by an imprint process or an etching process to obtain a wrinkle surface having a plurality of trenches.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Ceramic Engineering (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管阵列基板(100)，包括阵列设置于一玻璃基板(101)上的多个薄膜晶体管(105)，每一薄膜晶体管(105)包括：形成于玻璃基板(101)上的栅电极(10)、覆设于栅电极(10)上的栅极绝缘层(20)、形成于栅极绝缘层(20)上的有源层(30)以及形成于有源层(30)上的源电极(40)和漏电极(50)，其中，所述源电极(40)和漏电极(50)在第一方向上相互间隔，所述有源层(30)对应于所述源电极(40)和漏电极(50)相互间隔的区域为沟道区(60)；其中，所述栅极绝缘层(20)朝向所述有源层(30)的一面，至少对应于所述沟道区(60)的部分具有多个凸起结构(21)，形成具有多个沟槽(22)的褶皱表面；所述有源层(30)朝向所述栅极绝缘层(20)的一面与所述栅极绝缘层(20)的表面完全齿合。

Description

薄膜晶体管阵列基板及其制备方法、液晶面板 技术领域
本发明涉及液晶显示技术领域,尤其涉及一种薄膜晶体管阵列基板及其制备方法，还涉及包含该薄膜晶体管阵列基板的液晶面板。
背景技术
液晶显示器(Liquid Crystal Display，LCD)，为平面超薄的显示设备，它由一定数量的彩色或黑白像素组成，放置于光源或者反射面前方。液晶显示器功耗很低，并且具有高画质、体积小、重量轻的特点，因此倍受大家青睐，成为显示器的主流。目前液晶显示器是以薄膜晶体管(Thin Film Transistor，TFT)液晶显示器为主，液晶面板是液晶显示器的主要组件。
常用的液晶面板至少包括相对设置的薄膜晶体管阵列基板(array substrate)和滤光基板(color filter substrate)以及位于薄膜晶体管阵列基板和滤光基板之间的液晶层。其中，薄膜晶体管阵列基板包括玻璃基板以及阵列设置于玻璃基板上的薄膜晶体管，薄膜晶体管剖面结构如图1所示，其包括形成于玻璃基板1上的栅电极2、覆设于所述栅电极2上的栅极绝缘层3、形成于所述栅极绝缘层3上的有源层4以及形成于所述有源层4上的源电极5和漏电极6。其中，所述源电极5和漏电极6相互间隔，所述有源层4对应于所述源电极5和漏电极6相互间隔的区域为沟道区4a。图2是薄膜晶体管的平面结构示意图，图中仅示出了薄膜晶体管的栅电极2、有源层4以及源电极5和漏电极6。其中，沟道区4a的长度为L，宽度为W。
在薄膜晶体管阵列基板的设计工艺中，要求薄膜晶体管具有较大的开态电流和较小的关态电流的特性。其中，提高开态电流的方法之一是增加沟道区的宽长比(W/L)。提高宽长比的方式要么是增加宽度W，要么是减小长度L。为了保证显示屏的分辨率，像素区的面积需要尽可能的小，开口率需要尽可能的大，因此驱动薄膜晶体管以及外围电路不能超过一定的面积，这就决定了薄膜晶体管的沟道区宽度W不能做的太宽，在这种情况下需要增大薄膜晶体管沟道区的宽长比就只能通过减小长度L来解决，但是薄膜晶体管沟道区长度L降低到一定 程度会引起漏电流和沟道击穿等现象，造成薄膜晶体管无法工作。
发明内容
鉴于现有技术存在的不足，本发明提供了一种薄膜晶体管阵列基板及其制备方法，用以实现增加薄膜晶体管沟道区的宽长比(W/L)，以提高薄膜晶体管的开态电流，提升薄膜晶体管的驱动能力。
为了实现上述目的，本发明采用了如下的技术方案：
一种薄膜晶体管阵列基板，包括阵列设置于一玻璃基板上的多个薄膜晶体管，每一薄膜晶体管包括：形成于所述玻璃基板上的栅电极、覆设于所述栅电极上的栅极绝缘层、形成于所述栅极绝缘层上的有源层以及形成于所述有源层上的源电极和漏电极，其中，所述源电极和漏电极在第一方向上相互间隔，所述有源层对应于所述源电极和漏电极相互间隔的区域为沟道区；其中，所述栅极绝缘层朝向所述有源层的一面，至少对应于所述沟道区的部分具有多个凸起结构，形成具有多个沟槽的褶皱表面；所述有源层朝向所述栅极绝缘层的一面与所述栅极绝缘层的表面完全齿合。
其中，所述多个凸起结构中，每一凸起结构沿所述第一方向延伸；所述多个凸起结构沿与第一方向垂直的第二方向依次排列。
其中，所述凸起结构沿所述第一方向延伸呈直线状或曲线状。
其中，所述凸起结构在第二方向上的截面呈半圆形或近似于半圆形。
其中，所述多个凸起结构沿所述第二方向等间距排列，所述具有多个沟槽的褶皱表面在第二方向上的截面呈波浪状结构。
其中，所述凸起结构在第二方向上的截面呈三角形。
其中，所述多个凸起结构沿所述第二方向等间距排列，所述具有多个沟槽的褶皱表面在第二方向上的截面呈锯齿状结构。
其中，该阵列基板还包括形成于所述玻璃基板上的扫描线和数据线以及由扫描线和数据线交叉限定的像素区域；所述薄膜晶体管位于所述像素区域中，所述像素区域还设置有像素电极，所述像素电极与所述薄膜晶体管的源电极或漏电极电性连接。
如上所述的薄膜晶体管阵列基板的制备方法，该方法包括步骤：S101、提 供一玻璃基板并在该玻璃基板上制备栅电极；S102、在所述栅电极上制备栅极绝缘层；其中，所述栅极绝缘层至少覆盖所述栅电极；S103、在所述栅极绝缘层的上表面通过压印工艺或刻蚀工艺多个凸起结构，获得具有多个沟槽的褶皱表面；S104、在所述栅极绝缘层的上制备有源层，所述有源层朝向所述栅极绝缘层的一面与所述栅极绝缘层的表面完全齿合；S105、在所述有源层上制备源电极和漏电极。
本发明还提供了一种液晶面板，其包括相对设置的阵列基板和滤光基板以及位于阵列基板和滤光基板之间的液晶层，其中，所述阵列基板为如上所述的薄膜晶体管阵列基板。
相比于现有技术，本发明实施例中提供的薄膜晶体管阵列基板，其中的薄膜晶体管中，在对应于沟道区的部分，有源层与栅极绝缘层相互齿合的表面具有具有多个凸起结构，形成具有多个沟槽的褶皱表面，从而增加了沟道区的宽度(沟道区表面展开为平面的宽度)，增加了薄膜晶体管沟道区的宽长比(W/L)，提高了薄膜晶体管的开态电流，提升了薄膜晶体管的驱动能力。这种薄膜晶体管结构在增加了沟道区的宽长比的同时，其并不改变沟道区的长度以及沟道区的垂直宽度(在宽度方向上从一端到另一端的垂直距离)，因此不会导致开口率降低。
附图说明
图1是现有的一种薄膜晶体管的剖面结构示意图。
图2是如图1的薄膜晶体管的平面结构示意图。
图3是本发明实施例提供的液晶面板的结构示意图。
图4是本发明实施例提供的薄膜晶体管阵列基板的结构示意图。
图5是本发明实施例提供的滤光基板的结构示意图。
图6是本发明实施例提供的薄膜晶体管的平面结构示意图。
图7是如图6的薄膜晶体管沿AA线的剖面结构示意图。
图8是如图6的薄膜晶体管沿BB线的剖面结构示意图。
图9是本发明一实施例中的栅极绝缘层的俯视图。
图10是本发明另一实施例中的栅极绝缘层的俯视图。
图11是本发明一实施例中的栅极绝缘层的侧视剖面图。
图12是本发明另一实施例中的栅极绝缘层的侧视剖面图。
图13是本发明实施例中薄膜晶体管阵列基板的制备方法的工艺流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
如图3所示，本实施例提供的液晶面板包括相对设置的薄膜晶体阵列基板100和滤光基板200以及位于阵列基板100和滤光基板200之间的液晶层300。其中，如图4所示，薄膜晶体阵列基板100包括玻璃基板101、位于所述玻璃基板101上的扫描线102和数据线103以及由扫描线102和数据线103交叉限定的像素区域104。所述像素区域104中设置有薄膜晶体管105以及和薄膜晶体管50电性连接的像素电极106，并且，所述薄膜晶体管105与所述扫描线102和数据线103电性连接。如图5所示，滤光基板200至少包括玻璃基板201以及形成玻璃基板201上的黑色矩阵202和色阻单元203，所述色阻单元203包括红色色阻、绿色色阻和蓝色色阻。滤光基板200中的每一色阻203及其四周的黑色矩阵202对应于薄膜晶体阵列基板100中的一个像素区域104。
具体地，参阅图6-图8，其中，图6是本实施例提供的薄膜晶体管的平面结构示意图，图7是如图6的薄膜晶体管沿AA线的剖面结构示意图，图8是如图6的薄膜晶体管沿BB线的剖面结构示意图。本实施例中的薄膜晶体管105包括形成于所述玻璃基板101上的栅电极10、覆设于所述栅电极10上的栅极绝缘层20、形成于所述栅极绝缘层20上的有源层30以及形成于所述有源层30上的源电极40和漏电极50。其中，所述源电极40和漏电极50在第一方向(如图6中的X方向)上相互间隔，所述有源层30对应于所述源电极40和漏电极50相互间隔的区域为沟道区60。其中，结合图4，薄膜晶体管105的栅电极10电 性连接于所述扫描线102；源电极40和漏电极50的其中之一电性连接于所述数据线103，另一个电性连接于像素电极106。其中，沟道区60在第一方向上具有长度L，在第二方向(如图6中的Y方向)上具有垂直宽度W。在此，垂直宽度W是指在第二方向上沟道区60从一端到另一端的垂直距离。
进一步地，本实施例中，如图8所示的，所述栅极绝缘层20朝向所述有源层30的一面，至少对应于所述沟道区60的部分具有多个凸起结构21，形成具有多个沟槽22的褶皱表面；所述有源层30朝向所述栅极绝缘层20的一面与所述栅极绝缘层20的表面完全齿合。在此，有源层30与栅极绝缘层20相互齿合，应当理解为所述有源层30朝向所述栅极绝缘层20的一面也具有相应的褶皱表面，在对应于栅极绝缘层20的凸起结构21的位置，有源层30的表面应当具有沟槽；而在对应于栅极绝缘层20的沟槽22的位置，有源层30的表面应当具有凸起结构。
其中，在本实施例中，如图9所示的，所述栅极绝缘层20上的多个凸起结构21中，每一凸起结构21沿所述第一方向(X方向)延伸；所述多个凸起结构21沿第二方向(Y方向)依次排列。进一步地，所述凸起结构21沿第一方向延伸呈直线状。当然，在另外的一些实施例中，如图10所示的，所述栅极绝缘层20中凸起结构21沿第一方向延伸也可以是形成弯曲的形状。
其中，在本实施例中的栅极绝缘层20，如图11所示的，所述凸起结构21在第二方向上的截面呈半圆形或近似于半圆形。并且，进一步地，所述多个凸起结构21沿所述第二方向等间距排列，所述具有多个沟槽22的褶皱表面在第二方向上的截面呈波浪状结构。当然，在另外的一些实施例中，多个凸起结构21沿所述第二方向也可以是形成不等间距排列。
进一步地，在另外的一些实施例中栅极绝缘层20，凸起结构21也可以设计为其它的形状，例如，如图12所示的，所述凸起结构21在第二方向上的截面呈三角形，将所述多个凸起结构21沿所述第二方向等间距排列，所述具有多个沟槽22的褶皱表面在第二方向上的截面呈锯齿状结构。
如上提供的薄膜晶体管阵列基板100，其中的薄膜晶体管105中，在对应于沟道区60的部分，有源层30与栅极绝缘层20相互齿合的表面具有具有多个凸起结构，形成具有多个沟槽的褶皱表面，从而增加了沟道区60的有效宽度(沟道区60表面展开为平面的宽度，该宽度大于沟道区60的垂直宽度W)，增加了薄膜晶体管沟道区60的宽长比，提高了薄膜晶体管105的开态电流，提升了薄 膜晶体管105的驱动能力。这种薄膜晶体管结构在增加了沟道区的宽长比的同时，其并不改变沟道区的长度以及沟道区的垂直宽度，因此不会导致开口率降低。或者可以换一个角度来说，当要保持薄膜晶体管的宽长比不变时，这种结构的薄膜晶体管中，可以减小沟道区的垂直宽度，从而提升开口率。
下面介绍如上所述的薄膜晶体管阵列基板的制备方法。如图13所示，该方法具体包括步骤：
S101、提供一玻璃基板并在该玻璃基板上制备栅电极。
S102、在所述栅电极上制备栅极绝缘层；其中，所述栅极绝缘层至少覆盖所述栅电极。
S103、在所述栅极绝缘层的上表面通过压印工艺或刻蚀工艺多个凸起结构，获得具有多个沟槽的褶皱表面。
S104、在所述栅极绝缘层的上制备有源层，所述有源层朝向所述栅极绝缘层的一面与所述栅极绝缘层的表面完全齿合。
S105、在所述有源层上制备源电极和漏电极。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种薄膜晶体管阵列基板，包括阵列设置于一玻璃基板上的多个薄膜晶体管，每一薄膜晶体管包括：形成于所述玻璃基板上的栅电极、覆设于所述栅电极上的栅极绝缘层、形成于所述栅极绝缘层上的有源层以及形成于所述有源层上的源电极和漏电极，其中，所述源电极和漏电极在第一方向上相互间隔，所述有源层对应于所述源电极和漏电极相互间隔的区域为沟道区；其中，所述栅极绝缘层朝向所述有源层的一面，至少对应于所述沟道区的部分具有多个凸起结构，形成具有多个沟槽的褶皱表面；所述有源层朝向所述栅极绝缘层的一面与所述栅极绝缘层的表面完全齿合。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述多个凸起结构中，每一凸起结构沿所述第一方向延伸；所述多个凸起结构沿与第一方向垂直的第二方向依次排列。
  3. 根据权利要求2所述的薄膜晶体管阵列基板，其中，所述凸起结构沿所述第一方向延伸呈直线状或曲线状。
  4. 根据权利要求3所述的薄膜晶体管阵列基板，其中，所述凸起结构在第二方向上的截面呈半圆形或近似于半圆形。
  5. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述多个凸起结构沿所述第二方向等间距排列，所述具有多个沟槽的褶皱表面在第二方向上的截面呈波浪状结构。
  6. 根据权利要求3所述的薄膜晶体管阵列基板，其中，所述凸起结构在第二方向上的截面呈三角形。
  7. 根据权利要求6所述的薄膜晶体管阵列基板，其中，所述多个凸起结构沿所述第二方向等间距排列，所述具有多个沟槽的褶皱表面在第二方向上的截面呈锯齿状结构。
  8. 根据权利要求1所述的薄膜晶体管阵列基板，其中，该阵列基板还包括形成于所述玻璃基板上的扫描线和数据线以及由扫描线和数据线交叉限定的像素区域；所述薄膜晶体管位于所述像素区域中，所述像素区域还设置有像素电极，所述像素电极与所述薄膜晶体管的源电极或漏电极电性连接。
  9. 一种薄膜晶体管阵列基板的制备方法，其中，包括步骤：
    S101、提供一玻璃基板并在该玻璃基板上制备栅电极；
    S102、在所述栅电极上制备栅极绝缘层；其中，所述栅极绝缘层至少覆盖所述栅电极；
    S103、在所述栅极绝缘层的上表面通过压印工艺或刻蚀工艺多个凸起结构，获得具有多个沟槽的褶皱表面；
    S104、在所述栅极绝缘层的上制备有源层，所述有源层朝向所述栅极绝缘层的一面与所述栅极绝缘层的表面完全齿合；
    S105、在所述有源层上制备源电极和漏电极。
  10. 根据权利要求9所述的薄膜晶体管阵列基板的制备方法，其中，所述多个凸起结构中，每一凸起结构沿所述第一方向延伸；所述多个凸起结构沿与第一方向垂直的第二方向依次排列。
  11. 根据权利要求10所述的薄膜晶体管阵列基板的制备方法，其中，所述凸起结构沿所述第一方向延伸呈直线状或曲线状。
  12. 根据权利要求11所述的薄膜晶体管阵列基板的制备方法，其中，所述凸起结构在第二方向上的截面呈半圆形或近似于半圆形；所述多个凸起结构沿所述第二方向等间距排列，所述具有多个沟槽的褶皱表面在第二方向上的截面呈波浪状结构。
  13. 根据权利要求11所述的薄膜晶体管阵列基板的制备方法，其中，所述凸起结构在第二方向上的截面呈三角形；所述多个凸起结构沿所述第二方向等间距排列，所述具有多个沟槽的褶皱表面在第二方向上的截面呈锯齿状结构。
  14. 一种液晶面板，包括相对设置的阵列基板和滤光基板以及位于阵列基板和滤光基板之间的液晶层，所述阵列基板包括阵列设置于一玻璃基板上的多个薄膜晶体管，每一薄膜晶体管包括：形成于所述玻璃基板上的栅电极、覆设于所述栅电极上的栅极绝缘层、形成于所述栅极绝缘层上的有源层以及形成于所述有源层上的源电极和漏电极，其中，所述源电极和漏电极在第一方向上相互间隔，所述有源层对应于所述源电极和漏电极相互间隔的区域为沟道区；其中，所述栅极绝缘层朝向所述有源层的一面，至少对应于所述沟道区的部分具有多个凸起结构，形成具有多个沟槽的褶皱表面；所述有源层朝向所述栅极绝 缘层的一面与所述栅极绝缘层的表面完全齿合。
  15. 根据权利要求14所述的液晶面板，其中，所述多个凸起结构中，每一凸起结构沿所述第一方向延伸；所述多个凸起结构沿与第一方向垂直的第二方向依次排列。
  16. 根据权利要求15所述的液晶面板，其中，所述凸起结构沿所述第一方向延伸呈直线状或曲线状。
  17. 根据权利要求16所述的液晶面板，其中，所述凸起结构在第二方向上的截面呈半圆形或近似于半圆形。
  18. 根据权利要求17所述的液晶面板，其中，所述多个凸起结构沿所述第二方向等间距排列，所述具有多个沟槽的褶皱表面在第二方向上的截面呈波浪状结构。
  19. 根据权利要求16所述的液晶面板，其中，所述凸起结构在第二方向上的截面呈三角形。
  20. 根据权利要求19所述的液晶面板，其中，所述多个凸起结构沿所述第二方向等间距排列，所述具有多个沟槽的褶皱表面在第二方向上的截面呈锯齿状结构。
PCT/CN2015/086815 2015-08-06 2015-08-13 薄膜晶体管阵列基板及其制备方法、液晶面板 WO2017020338A1 (zh)

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