WO2017008346A1 - 显示面板及薄膜晶体管阵列基板 - Google Patents

显示面板及薄膜晶体管阵列基板 Download PDF

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Publication number
WO2017008346A1
WO2017008346A1 PCT/CN2015/085753 CN2015085753W WO2017008346A1 WO 2017008346 A1 WO2017008346 A1 WO 2017008346A1 CN 2015085753 W CN2015085753 W CN 2015085753W WO 2017008346 A1 WO2017008346 A1 WO 2017008346A1
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WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
signal line
disposed
connecting member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/085753
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English (en)
French (fr)
Inventor
赵莽
田勇
易士娟
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Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
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Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US14/777,984 priority Critical patent/US20170017129A1/en
Publication of WO2017008346A1 publication Critical patent/WO2017008346A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a thin film transistor array substrate.
  • the signal line layers of the thin film transistor array substrate are generally a single metal layer.
  • ESD Electro Static Discharge, electrostatic discharge
  • a display panel comprising: a color filter substrate; a liquid crystal layer; and a thin film transistor array substrate, the thin film transistor array substrate comprising: a substrate; a light shielding metal layer, the light shielding metal layer Provided on the substrate; a first insulating layer; a semiconductor layer, the semiconductor layer is disposed on the first insulating layer; a second insulating layer, the second insulating layer is disposed on the first insulating layer And a layer of the first signal line, the first signal line layer is disposed on the second insulating layer; a third insulating layer, the third insulating layer is disposed on the second On the insulating layer and the first signal line layer; a second signal line layer, the second signal line layer is disposed on the third insulating layer, and the second signal line layer passes through the first through hole
  • the semiconductor layer is connected; a fourth insulating layer, the fourth insulating layer is disposed on the third insulating layer and the second signal line layer; a common line layer, the common line layer
  • connection member is disposed in the through hole; the through hole passes through the first insulating layer, the second insulating layer, and the third insulating layer.
  • the second signal line in the second signal line layer includes: at least one first segment; and at least one second segment;
  • the light shielding line in the light shielding metal layer comprises: at least one a third segment; and at least a fourth segment;
  • the connecting member comprising: at least one first sub-connecting member; and at least a second sub-connecting member; wherein the first segment and the third segment Connected by the first sub-connecting member, the second segment and the fourth segment are connected by the second sub-connecting member.
  • the end of the connecting member has a bent portion that is in contact with the light shielding metal layer and/or the second signal line layer.
  • a display panel comprising: a color filter substrate; a liquid crystal layer; and a thin film transistor array substrate, the thin film transistor array substrate comprising: a substrate; a light shielding metal layer, the light shielding metal layer Provided on the substrate; a first insulating layer; a semiconductor layer, the semiconductor layer is disposed on the first insulating layer; a second insulating layer, the second insulating layer is disposed on the first insulating layer And a layer of the first signal line, the first signal line layer is disposed on the second insulating layer; a third insulating layer, the third insulating layer is disposed on the second On the insulating layer and the first signal line layer; a second signal line layer, the second signal line layer is disposed on the third insulating layer, and the second signal line layer passes through the first through hole
  • the semiconductor layer is connected; a fourth insulating layer, the fourth insulating layer is disposed on the third insulating layer and the second signal line layer; a common line layer, the common line layer
  • the light shielding metal layer and the second signal line layer are connected by a connection member.
  • connection member is disposed in the through hole; the through hole passes through the first insulating layer, the second insulating layer, and the third insulating layer.
  • the through hole is formed by performing a mask process on the first insulating layer, the second insulating layer, and the third insulating layer.
  • the second signal line in the second signal line layer includes: at least one first segment; and at least one second segment;
  • the light shielding line in the light shielding metal layer comprises: at least one a third segment; and at least a fourth segment;
  • the connecting member comprising: at least one first sub-connecting member; and at least a second sub-connecting member; wherein the first segment and the third segment Connected by the first sub-connecting member, the second segment and the fourth segment are connected by the second sub-connecting member.
  • the second signal line in the second signal line layer is connected in parallel with the light shielding line in the light shielding metal layer, and the second signal line and the light shielding line are every There is a connection point at the predetermined distance.
  • the end of the connecting member has a bent portion that is in contact with the light shielding metal layer and/or the second signal line layer.
  • the connecting member includes a first end and a second end; the first end is in contact with the light shielding metal layer, the first end has a first bent portion, and the first bending a portion extending away from the connecting member; the second end is in contact with the second signal line layer, the second end has a second bent portion, and the second bent portion is away from the connection The direction of the member extends.
  • a thin film transistor array substrate comprising: a substrate; a light shielding metal layer, the light shielding metal layer is disposed on the substrate; a first insulating layer; a semiconductor layer, the semiconductor layer is disposed On the first insulating layer; a second insulating layer, the second insulating layer is disposed on the first insulating layer and the semiconductor layer; a first signal line layer, the first signal line layer Provided on the second insulating layer; a third insulating layer, the third insulating layer is disposed on the second insulating layer and the first signal line layer; a second signal line layer, the first a second signal line layer is disposed on the third insulating layer, and the second signal line layer is connected to the semiconductor layer through a first via hole; a fourth insulating layer, the fourth insulating layer is disposed on the a third insulating layer and the second signal line layer; a common line layer, the common line layer is disposed on the fourth insulating layer; a third signal line layer
  • the light shielding metal layer and the second signal line layer are connected by a connection member.
  • connection member is disposed in the through hole; the through hole passes through the first insulating layer, the second insulating layer, and the third insulating layer.
  • the through hole is formed by performing a mask process on the first insulating layer, the second insulating layer, and the third insulating layer.
  • the second signal line of the second signal line layer includes: at least one first segment; and at least one second segment;
  • the light shielding line in the light shielding metal layer includes: at least a third segment; and at least a fourth segment;
  • the connecting member comprising: at least one first sub-connecting member; and at least a second sub-connecting member; wherein the first segment and the third portion The segments are connected by the first sub-connecting member, and the second segment and the fourth segment are connected by the second sub-connecting member.
  • the second signal line in the second signal line layer is connected in parallel with the light shielding line in the light shielding metal layer, and the second signal line and the light shielding line There is one connection point every predetermined distance.
  • the end of the connecting member has a bent portion that is in contact with the light shielding metal layer and/or the second signal line layer.
  • connection member includes a first end and a second end; the first end is in contact with the light shielding metal layer, and the first end has a first bent portion, the first The bent portion extends away from the connecting member; the second end is in contact with the second signal line layer, the second end has a second bent portion, and the second bent portion faces away from The direction of the connecting member extends.
  • the present invention is advantageous in preventing display defects caused by disconnection of signal lines, and can effectively improve the yield of products.
  • FIG. 1 is a schematic diagram showing the partitioning of a thin film transistor array substrate of the present invention
  • FIG. 2 is a schematic view of a thin film transistor array substrate of the present invention
  • FIG. 3 is a schematic view showing a line of a peripheral region in a thin film transistor array substrate of the present invention.
  • Figure 4 is a schematic view of the A-A' section of Figure 3;
  • Fig. 5 is a schematic view showing a section B-B' in Fig. 3.
  • the display panel of the present invention may be a TFT-LCD (Thin Film Transistor Liquid) Crystal Display, thin film transistor liquid crystal display panel, etc.
  • TFT-LCD Thin Film Transistor Liquid
  • LCD Thin Film Transistor Liquid
  • FIG. 1 is a schematic diagram of a partition of a thin film transistor array substrate according to the present invention
  • FIG. 2 is a schematic diagram of a thin film transistor array substrate of the present invention
  • FIG. 3 is a periphery of the thin film transistor array substrate of the present invention. Schematic diagram of the area's lines.
  • the display panel of the present invention includes a color filter substrate, a liquid crystal layer, and a thin film transistor array substrate.
  • the color filter substrate and the thin film transistor array substrate are superimposed and combined into a liquid crystal cell, and the liquid crystal layer is disposed in the liquid crystal cell.
  • the thin film transistor array substrate includes a pixel area (AA, Active) An area 101 and a peripheral area, the peripheral area being disposed on at least one side of the pixel area.
  • AA pixel area
  • Active Active
  • the peripheral area includes GOA (Gate-driver On Array, row scan driver integrated on the array substrate) area 102, Fanout area 103, IC (Integrated At least one of a circuit 104 and an FPC (Flexible Printed Circuit) area 105.
  • GOA Gate-driver On Array, row scan driver integrated on the array substrate
  • Fanout area 103 Fanout area 103
  • IC Integrated At least one of a circuit 104
  • FPC Flexible Printed Circuit
  • the GOA area 102 is used to generate TFTs in the display panel (Thin Film) a gate drive signal of a Transistor, a thin film transistor, the Fanout region 103 is used for a trace connection of the IC region 104 with a Dataline of the pixel region 101; and the IC region 104 is used for Bonding of an IC (Joining), the circuit in the display panel and the TFT are driven by the IC, the FPC area 105 is used for Bonding of the FPC, and the main board of the display panel is connected through the FPC.
  • the thin film transistor array substrate further includes a substrate 210 and a light shielding (LS, Light) Shield) metal layer 201, protective layer (buffer layer) 211, first insulating layer 212, semiconductor (polysilicon) layer 202, second insulating layer 213, first signal line layer 203, third insulating layer 214, second signal line
  • the light shielding metal layer 201 is disposed on the substrate 210, and the light shielding metal layer 201 is used to block the NMOS (Negative Channel Metal Oxide a back channel of the transistor, the N-channel metal oxide semiconductor) reduces the leakage current of the NMOS device;
  • the buffer layer 211 is disposed on the substrate and the light-shielding metal layer 201;
  • the first insulating layer 212 is disposed at On the substrate 210 and the buffer layer 211;
  • the semiconductor layer 202 is disposed on the first insulating layer 212;
  • the second insulating layer 213 is disposed on the first insulating layer 212 and the semiconductor layer 202
  • the first signal line layer 203 is disposed on the second insulating layer 213, wherein the first signal line in the first signal line layer 203 may be a scan line;
  • the third insulating layer 214 is disposed on The second insulating layer 213 and the first signal line layer 203;
  • the second signal line layer 209
  • the material of the light shielding metal layer 201 and the material of the second signal line layer 209 are both electrically conductive materials.
  • the light shielding metal layer 201 and the second signal line layer 209 are the same metal.
  • the GOA region 102 in the thin film transistor array substrate includes a ground line (GND) 302, a level signal line (STV) 303, a first scan direction control signal line (U2D) 304, and a second scan direction control signal line ( D2U) 305, clock signal line (CK) (306, 307), first power line (VGH) 308, second power line (VGL) 309, and the like.
  • the second signal line in the second signal line layer 209 may be the ground line 302, the level signal line 303, and the first scan direction control signal line 304.
  • the second signal line may be a data line.
  • the ground line is used for electrostatic protection, and the level signal line is used to provide a start signal to the GOA circuit of the thin film transistor; the first scan direction control signal line and the second scan direction control signal A line is used to control a scanning direction of the GOA circuit, the clock signal line is for generating and controlling a gate shift signal, and the first power line and the second power line are used to supply power to the GOA circuit.
  • FIG. 4 is a schematic view of the A-A' cross section of FIG. 3
  • FIG. 5 is a schematic view of the B-B' cross section of FIG.
  • the light shielding metal layer 201 and the second signal line layer 209 are connected by a connecting member 301.
  • the connecting member 301 is disposed in the through hole, and the through hole passes through the first insulating layer 212, the second insulating layer 213, and the third insulating layer 214.
  • the through hole is formed by performing a mask process on the first insulating layer 212, the second insulating layer 213, and the third insulating layer 214.
  • the second signal line layer 209 and the light shielding metal layer 201 are connected by the connection member 301, the second signal line in the second signal line layer 209 is broken.
  • the second signal line is broken into at least two parts, the two broken portions of the second signal line can still be connected through the light shielding metal layer 201, so that the signal line can be greatly reduced.
  • the probability of disconnection of the two signal lines prevents the display defect caused by the disconnection of the signal line, and can effectively improve the yield of the product.
  • the above technical solution is also advantageous for reducing the impedance of the entire signal line (second signal line) and improving the anti-ESD capability of the signal line.
  • the second signal line in the second signal line layer 209 includes at least a first segment 501 and at least a second segment 502.
  • the light shielding line in the light shielding metal layer 201 includes at least a third segment 503 and at least a fourth segment 504.
  • the connecting member 301 includes at least one first sub-connecting member 3011 and at least one second sub-connecting member 3012.
  • first segment 501 and the third segment 503 are connected by the first sub-connecting member 3011, and the second segment 502 and the fourth segment 504 are connected by the second sub-segment Member 3012 is connected.
  • the second signal line in the second signal line layer 209 is connected in parallel with the light shielding line in the light shielding metal layer 201, and the second signal line is The shading line has a connection point every predetermined distance.
  • the end of the connecting member 301 has a bent portion that is in contact with the light shielding metal layer 201 and/or the second signal line layer 209.
  • the connecting member 301 includes a first end and a second end, the first end being in contact with the light shielding metal layer 201, and the second end being in contact with the second signal line layer 209.
  • the first end has a first bent portion that extends in a direction away from the connecting member 301.
  • the second end has a second bent portion that extends in a direction away from the connecting member 301.
  • the above technical solution is advantageous for expanding the contact area of the connecting member 301 with the light shielding metal layer 201 and/or the second signal line layer 209, thereby facilitating the avoidance of the connecting member 301 and the light shielding metal layer 201 and / or the second signal line layer 209 is in poor contact.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Geometry (AREA)

Abstract

一种薄膜晶体管阵列基板，包括像素区（101）和外围区；薄膜晶体管阵列基板还包括基板（210），遮光金属层（201），第一绝缘层（212），半导体层（202），第二绝缘层（213），第一、第二、第三信号线层（203、209、206），第三绝缘层（214），第四绝缘层（204），公共线层（205），第五绝缘层（207），像素电极层（208）。还提供了一种显示面板。能防止因信号线断线而造成的显示不良问题。

Description

显示面板及薄膜晶体管阵列基板 技术领域
本发明涉及显示技术领域，特别涉及一种显示面板及薄膜晶体管阵列基板。
 背景技术
在传统的显示面板中，薄膜晶体管阵列基板的信号线层一般都是单一的金属层。
单一的金属层的抗ESD（Electro Static Discharge，静电放电）能力较差，并且，所述薄膜晶体管阵列基板中出现较大的静电时，单一的金属层很容易熔断，这会导致所述薄膜晶体管阵列基板中部分区域显示失效。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种显示面板及薄膜晶体管阵列基板，其能防止因信号线断线而造成的显示不良问题。
 技术解决方案
一种显示面板，所述显示面板包括：一彩色滤光片基板；一液晶层；以及一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一基板；一遮光金属层，所述遮光金属层设置在所述基板上；一第一绝缘层；一半导体层，所述半导体层设置在所述第一绝缘层上；一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述半导体层上；一第一信号线层，所述第一信号线层设置在所述第二绝缘层上；一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述第一信号线层上；一第二信号线层，所述第二信号线层设置在所述第三绝缘层上，并且所述第二信号线层通过第一通孔与所述半导体层连接；一第四绝缘层，所述第四绝缘层设置在所述第三绝缘层和所述第二信号线层上；一公共线层，所述公共线层设置在所述第四绝缘层上；一第三信号线层；一第五绝缘层，所述第五绝缘层设置在所述第三信号线层上；以及一像素电极层，所述像素电极层设置在所述第五绝缘层上；所述遮光金属层与所述第二信号线层通过连接构件连接；所述遮光金属层用于遮挡N沟道金属氧化物半导体晶体管的背沟道，降低N沟道金属氧化物半导体器件的漏电流；所述遮光金属层与所述第二信号线层为同一种金属。
在上述显示面板中，所述连接构件设置于通孔内；所述通孔穿过所述第一绝缘层、所述第二绝缘层和所述第三绝缘层。
在上述显示面板中，所述第二信号线层中的第二信号线包括：至少一第一分段；以及至少一第二分段；所述遮光金属层中的遮光线包括：至少一第三分段；以及至少一第四分段；所述连接构件包括：至少一第一子连接构件；以及至少一第二子连接构件；其中，所述第一分段和所述第三分段通过所述第一子连接构件连接，所述第二分段和所述第四分段通过所述第二子连接构件连接。
在上述显示面板中，所述连接构件的末端具有弯折部，所述弯折部与所述遮光金属层和/或所述第二信号线层接触。
一种显示面板，所述显示面板包括：一彩色滤光片基板；一液晶层；以及一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一基板；一遮光金属层，所述遮光金属层设置在所述基板上；一第一绝缘层；一半导体层，所述半导体层设置在所述第一绝缘层上；一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述半导体层上；一第一信号线层，所述第一信号线层设置在所述第二绝缘层上；一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述第一信号线层上；一第二信号线层，所述第二信号线层设置在所述第三绝缘层上，并且所述第二信号线层通过第一通孔与所述半导体层连接；一第四绝缘层，所述第四绝缘层设置在所述第三绝缘层和所述第二信号线层上；一公共线层，所述公共线层设置在所述第四绝缘层上；一第三信号线层；一第五绝缘层，所述第五绝缘层设置在所述第三信号线层上；以及一像素电极层，所述像素电极层设置在所述第五绝缘层上。
在上述显示面板中，所述遮光金属层与所述第二信号线层通过连接构件连接。
在上述显示面板中，所述连接构件设置于通孔内；所述通孔穿过所述第一绝缘层、所述第二绝缘层和所述第三绝缘层。
在上述显示面板中，所述通孔是通过对所述第一绝缘层、所述第二绝缘层、所述第三绝缘层进行光罩制程来形成的。
在上述显示面板中，所述第二信号线层中的第二信号线包括：至少一第一分段；以及至少一第二分段；所述遮光金属层中的遮光线包括：至少一第三分段；以及至少一第四分段；所述连接构件包括：至少一第一子连接构件；以及至少一第二子连接构件；其中，所述第一分段和所述第三分段通过所述第一子连接构件连接，所述第二分段和所述第四分段通过所述第二子连接构件连接。
在上述显示面板中，所述第二信号线层中的所述第二信号线与所述遮光金属层中的所述遮光线并联，并且，所述第二信号线与所述遮光线每隔预定距离存在一个连接点。
在上述显示面板中，所述连接构件的末端具有弯折部，所述弯折部与所述遮光金属层和/或所述第二信号线层接触。
在上述显示面板中，所述连接构件包括第一末端和第二末端；所述第一末端与所述遮光金属层接触，所述第一末端具有第一弯折部，所述第一弯折部朝远离所述连接构件的方向延伸；所述第二末端与所述第二信号线层接触，所述第二末端具有第二弯折部，所述第二弯折部朝远离所述连接构件的方向延伸。
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一基板；一遮光金属层，所述遮光金属层设置在所述基板上；一第一绝缘层；一半导体层，所述半导体层设置在所述第一绝缘层上；一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述半导体层上；一第一信号线层，所述第一信号线层设置在所述第二绝缘层上；一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述第一信号线层上；一第二信号线层，所述第二信号线层设置在所述第三绝缘层上，并且所述第二信号线层通过第一通孔与所述半导体层连接；一第四绝缘层，所述第四绝缘层设置在所述第三绝缘层和所述第二信号线层上；一公共线层，所述公共线层设置在所述第四绝缘层上；一第三信号线层；一第五绝缘层，所述第五绝缘层设置在所述第三信号线层上；以及一像素电极层，所述像素电极层设置在所述第五绝缘层上。
在上述薄膜晶体管阵列基板中，所述遮光金属层与所述第二信号线层通过连接构件连接。
在上述薄膜晶体管阵列基板中，所述连接构件设置于通孔内；所述通孔穿过所述第一绝缘层、所述第二绝缘层和所述第三绝缘层。
在上述薄膜晶体管阵列基板中，所述通孔是通过对所述第一绝缘层、所述第二绝缘层、所述第三绝缘层进行光罩制程来形成的。
在上述薄膜晶体管阵列基板中，所述第二信号线层中的第二信号线包括：至少一第一分段；以及至少一第二分段；所述遮光金属层中的遮光线包括：至少一第三分段；以及至少一第四分段；所述连接构件包括：至少一第一子连接构件；以及至少一第二子连接构件；其中，所述第一分段和所述第三分段通过所述第一子连接构件连接，所述第二分段和所述第四分段通过所述第二子连接构件连接。
在上述薄膜晶体管阵列基板中，所述第二信号线层中的所述第二信号线与所述遮光金属层中的所述遮光线并联，并且，所述第二信号线与所述遮光线每隔预定距离存在一个连接点。
在上述薄膜晶体管阵列基板中，所述连接构件的末端具有弯折部，所述弯折部与所述遮光金属层和/或所述第二信号线层接触。
在上述薄膜晶体管阵列基板中，所述连接构件包括第一末端和第二末端；所述第一末端与所述遮光金属层接触，所述第一末端具有第一弯折部，所述第一弯折部朝远离所述连接构件的方向延伸；所述第二末端与所述第二信号线层接触，所述第二末端具有第二弯折部，所述第二弯折部朝远离所述连接构件的方向延伸。
 有益效果
相对现有技术，本发明有利于防止因信号线断线而造成的显示不良问题，能够有效地提升产品的良率。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
 附图说明
图1为本发明的薄膜晶体管阵列基板的分区示意图；
图2为本发明的薄膜晶体管阵列基板的示意图；
图3为本发明的薄膜晶体管阵列基板中的外围区域的线路的示意图；
图4为图3中A-A’截面的示意图；
图5为图3中B-B’截面的示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）等。
参考图1、图2和图3，图1为本发明的薄膜晶体管阵列基板的分区示意图，图2为本发明的薄膜晶体管阵列基板的示意图，图3为本发明的薄膜晶体管阵列基板中的外围区域的线路的示意图。
本发明的显示面板包括彩色滤光片基板、液晶层以及薄膜晶体管阵列基板。其中，所述彩色滤光片基板和所述薄膜晶体管阵列基板叠加组合成液晶盒，所述液晶层设置于所述液晶盒内。
所述薄膜晶体管阵列基板包括像素区（AA，Active Area）101和外围区，所述外围区设置于所述像素区的至少一侧。
所述外围区包括GOA（Gate-driver On Array，集成在阵列基板上的行扫描驱动器）区102、Fanout（扇出）区103、IC（Integrated Circuit，集成电路）区104和FPC（Flexible Printed Circuit，柔性电路板）区105中的至少一者。
其中，所述GOA区102用于产生所述显示面板内TFT（Thin Film Transistor，薄膜晶体管）的栅极驱动信号，所述Fanout区103用于所述IC区104与所述像素区101的Dataline（数据线）的走线连接；所述IC区104用于IC的Bonding（接合），通过所述IC来驱动所述显示面板内的电路和所述TFT，所述FPC区105用于FPC的Bonding，并通过所述FPC连接所述显示面板的主板。
所述薄膜晶体管阵列基板还包括基板210、遮光（LS，Light Shield）金属层201、保护层（缓冲层）211、第一绝缘层212、半导体（多晶硅）层202、第二绝缘层213、第一信号线层203、第三绝缘层214、第二信号线层209、第四绝缘层204、公共线层205、第三信号线层206、第五绝缘层207以及像素电极层208。
其中，所述遮光金属层201设置在所述基板210上，所述遮光金属层201用于遮挡NMOS（Negative channel Metal Oxide Semiconductor，N沟道金属氧化物半导体）晶体管的背沟道，降低NMOS器件的漏电流；缓冲层211设置在所述基板和所述遮光金属层201上；所述第一绝缘层212设置在所述基板210和所述缓冲层211上；所述半导体层202设置在所述第一绝缘层212上；所述第二绝缘层213设置在所述第一绝缘层212和所述半导体层202上；所述第一信号线层203设置在所述第二绝缘层213上，其中，所述第一信号线层203中的第一信号线可以是扫描线；所述第三绝缘层214设置在所述第二绝缘层213和所述第一信号线层203上；所述第二信号线层209设置在所述第三绝缘层214上，并且所述第二信号线层209通过第一通孔与所述半导体层202连接；所述第四绝缘层204设置在所述第三绝缘层214和所述第二信号线层209上；所述公共线层205设置在所述第四绝缘层204上；所述第五绝缘层207设置在所述第三信号线层206上，其中，所述第三信号线层206中的第三信号线可以是触控感应线；所述像素电极层208设置在所述第五绝缘层207上。
其中，所述遮光金属层201的材料与所述第二信号线层209的材料均为可导电的材料，例如，所述遮光金属层201与所述第二信号线层209为同一种金属。
所述薄膜晶体管阵列基板中的所述GOA区102包括接地线（GND）302、级传信号线（STV）303、第一扫描方向控制信号线（U2D）304、第二扫描方向控制信号线（D2U）305、时钟信号线（CK）（306，307）、第一电源线（VGH）308、第二电源线（VGL）309等。在所述GOA区102中，所述第二信号线层209中的所述第二信号线可以是所述接地线302、所述级传信号线303、所述第一扫描方向控制信号线304、所述第二扫描方向控制信号线305、所述时钟信号线（306，307）、所述第一电源线308、所述第二电源线309中的任意一者。在所述像素区中，所述第二信号线可以是数据线。
其中，所述接地线用于静电防护，所述级传信号线用于向所述薄膜晶体管的GOA电路提供起始信号；所述第一扫描方向控制信号线和所述第二扫描方向控制信号线用于控制所述GOA电路的扫描方向，所述时钟信号线用于产生和控制栅极移位信号，所述第一电源线和所述第二电源线用于向所述GOA电路供电。
参考图4和图5，图4为图3中A-A’截面的示意图，图5为图3中B-B’截面的示意图。
在本实施例中，所述遮光金属层201与所述第二信号线层209通过连接构件301连接。
在本实施例中，所述连接构件301设置于通孔内，所述通孔穿过所述第一绝缘层212、所述第二绝缘层213和所述第三绝缘层214。其中，所述通孔是通过对所述第一绝缘层212、所述第二绝缘层213、所述第三绝缘层214进行光罩制程来形成的。
在上述技术方案中，由于所述第二信号线层209与所述遮光金属层201通过连接构件301连接，因此，在所述第二信号线层209中的第二信号线出现断线部的情况下，即，所述第二信号线断开成至少两部分，所述第二信号线的断开的两部分仍可以通过所述遮光金属层201连接起来，这样可以大大降低信号线（第二信号线）断线的概率，防止因信号线断线而造成的显示不良问题，能够有效地提升产品的良率。
此外，上述技术方案还有利于降低整条信号线（第二信号线）的阻抗，并可以提高信号线的抗ESD能力。
本发明的第二实施例与上述第一实施例相似，不同之处在于：
在本实施例中，所述第二信号线层209中的第二信号线包括至少一第一分段501以及至少一第二分段502。
所述遮光金属层201中的遮光线包括至少一第三分段503以及至少一第四分段504。
所述连接构件301包括至少一第一子连接构件3011以及至少一第二子连接构件3012。
其中，所述第一分段501和所述第三分段503通过所述第一子连接构件3011连接，所述第二分段502和所述第四分段504通过所述第二子连接构件3012连接。
也就是说，在本实施例中，所述第二信号线层209中的所述第二信号线与所述遮光金属层201中的所述遮光线并联，并且，所述第二信号线与所述遮光线每隔预定距离存在一个连接点。
这样有利于降低所述第二信号线断线的概率，同时也有利于降低所述第二信号线的阻抗，从而有利于提高所述薄膜晶体管阵列基板的抗ESD能力。
本发明的第三实施例与上述第二实施例相似，不同之处在于：
在本实施例中，所述连接构件301的末端具有弯折部，所述弯折部与所述遮光金属层201和/或所述第二信号线层209接触。
具体地，所述连接构件301包括第一末端和第二末端，所述第一末端与所述遮光金属层201接触，所述第二末端与所述第二信号线层209接触。所述第一末端具有第一弯折部，所述第一弯折部朝远离所述连接构件301的方向延伸。所述第二末端具有第二弯折部，所述第二弯折部朝远离所述连接构件301的方向延伸。
上述技术方案有利于扩大所述连接构件301与所述遮光金属层201和/或所述第二信号线层209的接触面积，从而有利于避免所述连接构件301与所述遮光金属层201和/或所述第二信号线层209接触不良。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    一彩色滤光片基板；
    一液晶层；以及
    一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
    一基板；
    一遮光金属层，所述遮光金属层设置在所述基板上；
    一第一绝缘层；
    一半导体层，所述半导体层设置在所述第一绝缘层上；
    一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述半导体层上；
    一第一信号线层，所述第一信号线层设置在所述第二绝缘层上；
    一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述第一信号线层上；
    一第二信号线层，所述第二信号线层设置在所述第三绝缘层上，并且所述第二信号线层通过第一通孔与所述半导体层连接；
    一第四绝缘层，所述第四绝缘层设置在所述第三绝缘层和所述第二信号线层上；
    一公共线层，所述公共线层设置在所述第四绝缘层上；
    一第三信号线层；
    一第五绝缘层，所述第五绝缘层设置在所述第三信号线层上；以及
    一像素电极层，所述像素电极层设置在所述第五绝缘层上；
    所述遮光金属层与所述第二信号线层通过连接构件连接；
    所述遮光金属层用于遮挡N沟道金属氧化物半导体晶体管的背沟道，降低N沟道金属氧化物半导体器件的漏电流；
    所述遮光金属层与所述第二信号线层为同一种金属。
  2. 根据权利要求1所述的显示面板，其中，所述连接构件设置于通孔内；
    所述通孔穿过所述第一绝缘层、所述第二绝缘层和所述第三绝缘层。
  3. 根据权利要求1所述的显示面板，其中，所述第二信号线层中的第二信号线包括：
    至少一第一分段；以及
    至少一第二分段；
    所述遮光金属层中的遮光线包括：
    至少一第三分段；以及
    至少一第四分段；
    所述连接构件包括：
    至少一第一子连接构件；以及
    至少一第二子连接构件；
    其中，所述第一分段和所述第三分段通过所述第一子连接构件连接，所述第二分段和所述第四分段通过所述第二子连接构件连接。
  4. 根据权利要求1所述的显示面板，其中，所述连接构件的末端具有弯折部，所述弯折部与所述遮光金属层和/或所述第二信号线层接触。
  5. 一种显示面板，其中，所述显示面板包括：
    一彩色滤光片基板；
    一液晶层；以及
    一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
    一基板；
    一遮光金属层，所述遮光金属层设置在所述基板上；
    一第一绝缘层；
    一半导体层，所述半导体层设置在所述第一绝缘层上；
    一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述半导体层上；
    一第一信号线层，所述第一信号线层设置在所述第二绝缘层上；
    一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述第一信号线层上；
    一第二信号线层，所述第二信号线层设置在所述第三绝缘层上，并且所述第二信号线层通过第一通孔与所述半导体层连接；
    一第四绝缘层，所述第四绝缘层设置在所述第三绝缘层和所述第二信号线层上；
    一公共线层，所述公共线层设置在所述第四绝缘层上；
    一第三信号线层；
    一第五绝缘层，所述第五绝缘层设置在所述第三信号线层上；以及
    一像素电极层，所述像素电极层设置在所述第五绝缘层上。
  6. 根据权利要求5所述的显示面板，其中，所述遮光金属层与所述第二信号线层通过连接构件连接。
  7. 根据权利要求6所述的显示面板，其中，所述连接构件设置于通孔内；
    所述通孔穿过所述第一绝缘层、所述第二绝缘层和所述第三绝缘层。
  8. 根据权利要求7所述的显示面板，其中，所述通孔是通过对所述第一绝缘层、所述第二绝缘层、所述第三绝缘层进行光罩制程来形成的。
  9. 根据权利要求6所述的显示面板，其中，所述第二信号线层中的第二信号线包括：
    至少一第一分段；以及
    至少一第二分段；
    所述遮光金属层中的遮光线包括：
    至少一第三分段；以及
    至少一第四分段；
    所述连接构件包括：
    至少一第一子连接构件；以及
    至少一第二子连接构件；
    其中，所述第一分段和所述第三分段通过所述第一子连接构件连接，所述第二分段和所述第四分段通过所述第二子连接构件连接。
  10. 根据权利要求9所述的显示面板，其中，所述第二信号线层中的所述第二信号线与所述遮光金属层中的所述遮光线并联，并且，所述第二信号线与所述遮光线每隔预定距离存在一个连接点。
  11. 根据权利要求6所述的显示面板，其中，所述连接构件的末端具有弯折部，所述弯折部与所述遮光金属层和/或所述第二信号线层接触。
  12. 根据权利要求11所述的显示面板，其中，所述连接构件包括第一末端和第二末端；
    所述第一末端与所述遮光金属层接触，所述第一末端具有第一弯折部，所述第一弯折部朝远离所述连接构件的方向延伸；
    所述第二末端与所述第二信号线层接触，所述第二末端具有第二弯折部，所述第二弯折部朝远离所述连接构件的方向延伸。
  13. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    一基板；
    一遮光金属层，所述遮光金属层设置在所述基板上；
    一第一绝缘层；
    一半导体层，所述半导体层设置在所述第一绝缘层上；
    一第二绝缘层，所述第二绝缘层设置在所述第一绝缘层和所述半导体层上；
    一第一信号线层，所述第一信号线层设置在所述第二绝缘层上；
    一第三绝缘层，所述第三绝缘层设置在所述第二绝缘层和所述第一信号线层上；
    一第二信号线层，所述第二信号线层设置在所述第三绝缘层上，并且所述第二信号线层通过第一通孔与所述半导体层连接；
    一第四绝缘层，所述第四绝缘层设置在所述第三绝缘层和所述第二信号线层上；
    一公共线层，所述公共线层设置在所述第四绝缘层上；
    一第三信号线层；
    一第五绝缘层，所述第五绝缘层设置在所述第三信号线层上；以及
    一像素电极层，所述像素电极层设置在所述第五绝缘层上。
  14. 根据权利要求13所述的薄膜晶体管阵列基板，其中，所述遮光金属层与所述第二信号线层通过连接构件连接。
  15. 根据权利要求14所述的薄膜晶体管阵列基板，其中，所述连接构件设置于通孔内；
    所述通孔穿过所述第一绝缘层、所述第二绝缘层和所述第三绝缘层。
  16. 根据权利要求15所述的薄膜晶体管阵列基板，其中，所述通孔是通过对所述第一绝缘层、所述第二绝缘层、所述第三绝缘层进行光罩制程来形成的。
  17. 根据权利要求14所述的薄膜晶体管阵列基板，其中，所述第二信号线层中的第二信号线包括：
    至少一第一分段；以及
    至少一第二分段；
    所述遮光金属层中的遮光线包括：
    至少一第三分段；以及
    至少一第四分段；
    所述连接构件包括：
    至少一第一子连接构件；以及
    至少一第二子连接构件；
    其中，所述第一分段和所述第三分段通过所述第一子连接构件连接，所述第二分段和所述第四分段通过所述第二子连接构件连接。
  18. 根据权利要求17所述的薄膜晶体管阵列基板，其中，所述第二信号线层中的所述第二信号线与所述遮光金属层中的所述遮光线并联，并且，所述第二信号线与所述遮光线每隔预定距离存在一个连接点。
  19. 根据权利要求14所述的薄膜晶体管阵列基板，其中，所述连接构件的末端具有弯折部，所述弯折部与所述遮光金属层和/或所述第二信号线层接触。
  20. 根据权利要求19所述的薄膜晶体管阵列基板，其中，所述连接构件包括第一末端和第二末端；
    所述第一末端与所述遮光金属层接触，所述第一末端具有第一弯折部，所述第一弯折部朝远离所述连接构件的方向延伸；
    所述第二末端与所述第二信号线层接触，所述第二末端具有第二弯折部，所述第二弯折部朝远离所述连接构件的方向延伸。
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