WO2017008344A1 - 一种阵列基板的制作方法及阵列基板 - Google Patents

一种阵列基板的制作方法及阵列基板 Download PDF

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WO2017008344A1
WO2017008344A1 PCT/CN2015/085659 CN2015085659W WO2017008344A1 WO 2017008344 A1 WO2017008344 A1 WO 2017008344A1 CN 2015085659 W CN2015085659 W CN 2015085659W WO 2017008344 A1 WO2017008344 A1 WO 2017008344A1
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trench
layer
etching
array substrate
passivation layer
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French (fr)
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邓竹明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/774,051 priority Critical patent/US9647015B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate and an array substrate.
  • the general PSVA (polymer stabilized vertically) Aligned, polymer stable vertical alignment structure forms four domains in one pixel to improve color shift.
  • the passivation layer under the pixel electrode layer is mainly patterned to form two different The trenches, and the combination of the two different trench depths, can achieve an 8-domain display effect, thereby improving the color shift to a greater extent; and to achieve this structure, the vias and the trenches of the two different depths will At the same time, it appears in one pixel, that is, three different etching amounts appear.
  • three masks and three yellow light processes will be used, which is a big cost and production efficiency.
  • the burden although the GTM process can be used to save mask and yellow light times, the GTM process is more complex, many process parameters will be re-commissioned, and the process stability and reproducibility are not as good as the general mask.
  • An object of the present invention is to provide a method for fabricating an array substrate and an array substrate, which can save one mask and can reduce one yellow light process, thereby saving cost and improving efficiency.
  • a method for fabricating an array substrate wherein the method for fabricating the array substrate comprises:
  • the first metal layer including a scan line
  • the first trench and the second trench have the same depth; the etching depth of the third trench is the first etching of the first trench The sum of the etch depths is greater than or equal to the thickness of the passivation layer.
  • the step of performing the second etching on the passivation layer to obtain the third trench comprises:
  • the etching depth of the first trench and the third trench is the same for the second etching.
  • a method for fabricating an array substrate comprises:
  • the first metal layer including a scan line
  • a pixel electrode layer is formed on the passivation layer.
  • the first trench and the second trench obtained by the first etching have the same depth.
  • a sum of an etch depth of the third trench and an etch depth of the first trench etched for the first time is greater than or equal to a ratio of the passivation layer thickness.
  • the step of performing the second etching on the passivation layer to obtain the third trench comprises:
  • the etching depth of the first trench and the third trench is the same for the second etching.
  • the first metal layer is disposed on the glass substrate, and the first metal layer includes a scan line;
  • An insulating layer, the insulating layer is disposed on the first metal layer;
  • the second metal layer is disposed on the insulating layer, and the second metal layer includes a data line;
  • the passivation layer is disposed on the second metal layer, the passivation layer includes a first trench, a second trench, and a third trench;
  • a pixel electrode layer disposed on the passivation layer.
  • the depth of the first trench is greater than the depth of the second trench.
  • a sum of an etching depth of the third trench and an etching depth of the first trench etched for the first time is greater than or equal to a thickness of the passivation layer.
  • the position of the first trench corresponds to the data line.
  • the passivation layer is a silicon nitride layer.
  • the present invention performs a second etching on the passivation layer, and the first etching obtains the first trench and the second trench, and the depth is the same, and the second etching obtains the third trench and is exposed.
  • the second metal layer; that is, the first trench is equally etched by the first trench and the third trench, and finally the first trench is completely etched. The effect is to save a mask and save a yellow light process, which saves costs and improves efficiency.
  • FIG. 1 is a schematic flowchart of an implementation process of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic structural flowchart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • the first trench and the second trench are obtained by the first etching, and the depth is the same, and the second trench is obtained by the second etching, and the exposed portion is exposed.
  • the second metal layer that is, the same depth etching of the first trench is performed when both the second trench and the third trench are etched, and finally the effect of completely etching the first trench is achieved. This saves a mask and saves a yellow process, saving costs and increasing efficiency.
  • FIG. 1 and FIG. 2 are schematic diagrams showing an implementation process of a method for fabricating an array substrate according to an embodiment of the present invention; the method includes the following steps:
  • step S101 a glass substrate is provided, and a first metal layer and an insulating layer are sequentially formed on the glass substrate, and the first metal layer includes a scan line;
  • the first metal layer is deposited on the entire surface of the glass substrate by a sputter coating method, and the ultraviolet ray is coated on the first metal layer.
  • Photosensitive photoresist pre-baking the photoresist, next, placing a mask over the photoresist, and irradiating with ultraviolet light (exposure), and next, developing the photoresist, Then, the first metal layer is etched to obtain a scan line.
  • an insulating layer is formed on the entire surface of the glass substrate by chemical vapor deposition.
  • the insulating layer may be a silicon nitride layer or a silicon oxide layer.
  • step S102 a second metal layer is formed on the insulating layer, and the second metal layer includes a data line;
  • the second metal layer is deposited on the insulating layer by a sputter coating method, and a photoresist sensitive to ultraviolet rays is coated on the second metal layer, and the photoresist is applied to the photoresist.
  • step S103 forming a passivation layer on the second metal layer
  • a passivation layer is formed on the entire surface of the glass substrate by chemical vapor deposition.
  • the insulating layer can be a silicon nitride layer.
  • step S104 the passivation layer is first etched to obtain a first trench and a second trench;
  • a photoresist sensitive to ultraviolet light is coated on the passivation layer, and the photoresist is pre-baked.
  • a mask is placed over the photoresist, and the mask is used.
  • Ultraviolet irradiation (exposure) next, the photoresist is developed, and then the passivation layer is first etched to obtain a first trench and a second trench.
  • the first trench and the second trench obtained by the first etching have the same depth. That is, the passivation layer is etched with an equal depth to obtain a first trench and a second trench.
  • step S105 the passivation layer is etched a second time to obtain a third trench
  • a second etching is performed on a position of the passivation layer corresponding to the third trench and a position corresponding to the first trench to obtain the third trench. And exposing the second metal layer.
  • the etching depth of the first trench and the third trench is the same for the second etching.
  • the sum of the etching depth of the third trench and the etching depth of the first trench etched for the first time is greater than or equal to the thickness of the passivation layer. That is, as long as the etching depth of the first trench is first etched and the etching depth of the first trench is etched to be greater than or equal to the thickness of the passivation layer, Via the via and expose the second metal layer.
  • the thickness of the passivation layer is 5700A
  • the depth of the first etching is 4000A
  • the depth of the first trench obtained by the first etching is 4000A
  • the depth of the second trench is 4000A.
  • the depth of the second etching is 2000A.
  • the second etching etches only the first trench and the third trench. Therefore, the depth of the third trench is 2000A, the first The depth of the trench is 5700A.
  • step S106 a pixel electrode layer is formed on the passivation layer.
  • a pixel electrode layer is formed on the passivation layer by a sputter coating method, and the pixel electrode layer includes a pixel electrode.
  • the first trench and the second trench are obtained by the first etching in the passivation layer, and the second trench is obtained by the second etching, and the third trench is obtained by the second etching.
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the array substrate includes a glass substrate 10, a first metal layer 20, an insulating layer 30, a second metal layer 40, a passivation layer 50, and a pixel electrode layer 60.
  • the first metal layer 20 is disposed on the glass substrate 10, the first metal layer 20 includes a scan line; the insulating layer 30 is disposed on the first metal layer 20; and the second metal layer 40 is Provided on the insulating layer 30, the second metal layer 40 includes a data line; the passivation layer 50 is disposed on the second metal layer 40, and the passivation layer 50 includes a first trench, Two trenches and a third trench; the pixel electrode layer 60 is disposed on the passivation layer 50, and the pixel electrode layer 60 includes a pixel electrode.
  • the depth of the first trench is greater than the depth of the second trench. Moreover, a sum of an etch depth of the third trench and an etch depth of the first trench etched for the first time is greater than or equal to a thickness of the passivation layer. The position of the first trench corresponds to the data line.
  • the passivation layer can be a silicon nitride layer.
  • the insulating layer may be a silicon nitride layer or a silicon oxide layer.
  • the present invention obtains the first trench and the second trench by the first etching in the passivation layer, and the second trench is obtained by the first etching, and the third trench is obtained by the second etching. Exposing the second metal layer; that is, the first trench is equally etched by the first trench and the third trench, and finally the first trench is completely etched. This saves a mask and saves a yellow process, saving costs and increasing efficiency.

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Abstract

PSVA(polymer stabilized vertically aligned，聚合物稳定垂直取向)阵列基板的制作方法及相应的阵列基板：在玻璃基板(10)上依次形成第一金属层(20)、绝缘层(30)和第二金属层(40)；在第二金属层(40)上形成一钝化层(50)；对钝化层(50)进行第一次刻蚀，得到第一沟槽和第二沟槽；对钝化层(50)进行第二次刻蚀，得到第三沟槽；在钝化层上形成像素电极层(60)。该方法能节省一张掩模，且能少一道黄光工艺，从而节省成本，提高效率。

Description

一种阵列基板的制作方法及阵列基板 技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板的制作方法及阵列基板。
 背景技术
目前，一般的PSVA（polymer stabilized vertically aligned，聚合物稳定垂直取向）结构在一个像素内形成4个畴以改善色偏，而在现有技术中主要是将像素电极层下方的钝化层进行图形化处理，从而形成两种不同的沟槽，而且两种不同沟槽深度进行内外组合，可以达到8畴的显示效果，进而更大程度地改善色偏；而为实现这种结构，过孔和这两种不同深度的沟槽将同时出现在一个像素内，即出现三个不同的刻蚀量，在现有的制程中，将会用到三张掩膜和三次黄光工艺，这在成本和生产效率都是一个很大的负担，尽管可以采用GTM工艺节省掩膜和黄光次数，但GTM工艺较复杂，许多制程参数将要重新调试，且工艺的稳定性和再现性也不如一般的掩模。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种阵列基板的制作方法及阵列基板，其能节省一张掩模，且能少一道黄光工艺，从而节省了成本，且能提高效率。
 技术解决方案
一种阵列基板的制作方法，其中所述阵列基板的制作方法包括：
提供一玻璃基板，在所述玻璃基板上依次形成第一金属层和绝缘层，所述第一金属层包括扫描线；
在所述绝缘层上形成第二金属层，所述第二金属层包括数据线；
在所述第二金属层上形成一钝化层；
对所述钝化层进行第一次刻蚀，得到第一沟槽和第二沟槽；
对所述钝化层进行第二次刻蚀，得到第三沟槽；
在所述钝化层上形成像素电极层；
其中，第一次刻蚀得到的所述第一沟槽和所述第二沟槽的深度相同；所述第三沟槽的刻蚀深度与第一次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度。
优选的，在所述的阵列基板的制作方法中，其中对所述钝化层进行第二次刻蚀，得到第三沟槽的步骤，包括：
对所述钝化层的对应所述第三沟槽的位置处以及对应所述第一沟槽的位置处进行第二次刻蚀，得到所述第三沟槽，并露出所述第二金属层。
优选的，在所述的阵列基板的制作方法中，其中第二次刻蚀所述第一沟槽和所述第三沟槽的刻蚀深度相同。
一种阵列基板的制作方法，所述阵列基板的制作方法包括：
提供一玻璃基板，在所述玻璃基板上依次形成第一金属层和绝缘层，所述第一金属层包括扫描线；
在所述绝缘层上形成第二金属层，所述第二金属层包括数据线；
在所述第二金属层上形成一钝化层；
对所述钝化层进行第一次刻蚀，得到第一沟槽和第二沟槽；
对所述钝化层进行第二次刻蚀，得到第三沟槽；
在所述钝化层上形成像素电极层。
优选的，在所述的阵列基板的制作方法中，第一次刻蚀得到的所述第一沟槽和所述第二沟槽的深度相同。
优选的，在所述的阵列基板的制作方法中，所述第三沟槽的刻蚀深度与第一次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度。
优选的，在所述的阵列基板的制作方法中，对所述钝化层进行第二次刻蚀，得到第三沟槽的步骤，包括：
对所述钝化层的对应所述第三沟槽的位置处以及对应所述第一沟槽的位置处进行第二次刻蚀，得到所述第三沟槽，并露出所述第二金属层。
优选的，在所述的阵列基板的制作方法中，第二次刻蚀所述第一沟槽和所述第三沟槽的刻蚀深度相同。
一种阵列基板，所述阵列基板包括：
一玻璃基板；
一第一金属层，所述第一金属层设置于所述玻璃基板上，所述第一金属层包括扫描线；
一绝缘层，所述绝缘层设置于所述第一金属层上；
一第二金属层，所述第二金属层设置于所述绝缘层上，所述第二金属层包括数据线；
一钝化层，所述钝化层设置于所述第二金属层上，所述钝化层包括第一沟槽、第二沟槽以及第三沟槽；
一像素电极层，所述像素电极层设置于所述钝化层上。
优选的，在所述的阵列基板中，所述第一沟槽的深度大于所述第二沟槽的深度。
优选的，在所述的阵列基板中，所述第三沟槽的刻蚀深度与第一次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度。
优选的，在所述的阵列基板中，所述第一沟槽的位置对应所述数据线。
优选的，在所述的阵列基板中，所述钝化层为氮化硅层。
 有益效果
相对现有技术，本发明在钝化层进行二次刻蚀，第一次刻蚀得到第一沟槽和第二沟槽，且深度相同，第二次刻蚀得到第三沟槽，并露出所述第二金属层；即本发明通过在刻蚀第二沟槽和第三沟槽时均对所述第一沟槽进行同等深度刻蚀，最后实现所述第一沟槽完全刻透的效果，如此可节省一张掩模，且能少一道黄光工艺，从而节省了成本，且能提高效率。
 附图说明
图1为本发明实施例提供的阵列基板的制作方法的实现流程示意图；
图2为本发明实施例提供的阵列基板的制作方法的结构流程示意图；
图3为本发明实施例提供的阵列基板的结构示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指用作实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为意指“一个或多个”，除非另外指定或从上下文清楚导向单数形式。
在本发明中，通过在钝化层进行二次刻蚀，第一次刻蚀得到第一沟槽和第二沟槽，且深度相同，第二次刻蚀得到第三沟槽，并露出所述第二金属层；即本发明通过在刻蚀第二沟槽和第三沟槽时均对所述第一沟槽进行同等深度刻蚀，最后实现所述第一沟槽完全刻透的效果，如此可节省一张掩模，且能少一道黄光工艺，从而节省了成本，且能提高效率。
为了说明本发明所述的技术方案，下面通过具体实施例来进行说明。
请一并参阅图1及图2，为本发明实施例提供的阵列基板的制作方法的实现流程示意图；其主要包括以下步骤：
在步骤S101中，提供一玻璃基板，在所述玻璃基板上依次形成第一金属层和绝缘层，所述第一金属层包括扫描线；
在本发明实施例中，首先，对所述玻璃基板洗净之后，利用溅射镀膜法在所述玻璃基板全表面沉积所述第一金属层，在所述第一金属层上涂布对紫外线感光的光刻胶，对所述光刻胶进行预烘烤，下一步，在所述光刻胶上方放置掩模，并用紫外线照射（曝光），下一步，对所述光刻胶进行显影，然后，对所述第一金属层进行刻蚀，得到扫描线。接着，利用化学气相沉积法在所述玻璃基板全表面形成绝缘层。然而，可以理解的是，所述绝缘层可以为氮化硅层或者是氧化硅层。
在步骤S102中，在所述绝缘层上形成第二金属层，所述第二金属层包括数据线；
在本发明实施例中，利用溅射镀膜法在所述绝缘层上沉积所述第二金属层，在所述第二金属层上涂布对紫外线感光的光刻胶，对所述光刻胶进行预烘烤，下一步，在所述光刻胶上方放置掩模，并用紫外线照射（曝光），下一步，对所述光刻胶进行显影，然后，对所述第二金属层进行刻蚀，得到数据线。
在步骤S103中，在所述第二金属层上形成一钝化层；
在本发明实施例中，利用化学气相沉积法在所述玻璃基板全表面形成钝化层。然而，可以理解的是，所述绝缘层可以为氮化硅层。
在步骤S104中，对所述钝化层进行第一次刻蚀，得到第一沟槽和第二沟槽；
在本发明实施例中，在所述钝化层上涂布对紫外线感光的光刻胶，对所述光刻胶进行预烘烤，下一步，在所述光刻胶上方放置掩模，并用紫外线照射（曝光），下一步，对所述光刻胶进行显影，然后，对所述钝化层进行第一次刻蚀，得到第一沟槽和第二沟槽。其中，第一次刻蚀得到的所述第一沟槽和所述第二沟槽的深度相同。即，采用同等深度刻蚀所述钝化层，从而得到第一沟槽和第二沟槽。
在步骤S105中，对所述钝化层进行第二次刻蚀，得到第三沟槽；
在本发明实施例中，对所述钝化层的对应所述第三沟槽的位置处以及对应所述第一沟槽的位置处进行第二次刻蚀，得到所述第三沟槽，并露出所述第二金属层。第二次刻蚀所述第一沟槽和所述第三沟槽的刻蚀深度相同。
然而，可以理解的是，所述第三沟槽的刻蚀深度与第一次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度。即只要第一次刻蚀所述第一沟槽的刻蚀深度加上第二次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度，这样便能得到过孔，并露出所述第二金属层。
例如，所述钝化层的厚度是5700A，第一次刻蚀的深度是4000A，第一次刻蚀得到的所述第一沟槽的深度是4000A，所述第二沟槽的深度是4000A，第二次刻蚀的深度是2000A，第二次刻蚀只刻蚀所述第一沟槽和所述第三沟槽，因此，所述第三沟槽的深度是2000A，所述第一沟槽的深度是5700A。
在步骤S106中，在所述钝化层上形成像素电极层。
在本发明实施例中，利用溅射镀膜法在所述钝化层上形成像素电极层，所述像素电极层包括像素电极。
由上可知，本实施例通过在钝化层进行二次刻蚀，第一次刻蚀得到第一沟槽和第二沟槽，且深度相同，第二次刻蚀得到第三沟槽，并露出所述第二金属层；即本发明通过在刻蚀第二沟槽和第三沟槽时均对所述第一沟槽进行同等深度刻蚀，最后实现所述第一沟槽完全刻透的效果，如此可节省一张掩模，且能少一道黄光工艺，从而节省了成本，且能提高效率。
请参阅图3，为本发明实施例提供的阵列基板的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。
所述阵列基板包括：一玻璃基板10、一第一金属层20、一绝缘层30、一第二金属层40、一钝化层50、以及一像素电极层60。所述第一金属层20设置于所述玻璃基板10上，所述第一金属层20包括扫描线；所述绝缘层30设置于所述第一金属层20上；所述第二金属层40设置于所述绝缘层30上，所述第二金属层40包括数据线；所述钝化层50设置于所述第二金属层40上，所述钝化层50包括第一沟槽、第二沟槽以及第三沟槽；所述像素电极层60设置于所述钝化层50上，所述像素电极层60包括像素电极。
在本发明实施例中，所述第一沟槽的深度大于所述第二沟槽的深度。而且，所述第三沟槽的刻蚀深度与第一次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度。所述第一沟槽的位置对应所述数据线。
然而，可以理解的是，所述钝化层可以为氮化硅层。所述绝缘层可以为氮化硅层或者是氧化硅层。
综上所述，本发明通过在钝化层进行二次刻蚀，第一次刻蚀得到第一沟槽和第二沟槽，且深度相同，第二次刻蚀得到第三沟槽，并露出所述第二金属层；即本发明通过在刻蚀第二沟槽和第三沟槽时均对所述第一沟槽进行同等深度刻蚀，最后实现所述第一沟槽完全刻透的效果，如此可节省一张掩模，且能少一道黄光工艺，从而节省了成本，且能提高效率。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种阵列基板的制作方法，其中所述阵列基板的制作方法包括：
    提供一玻璃基板，在所述玻璃基板上依次形成第一金属层和绝缘层，所述第一金属层包括扫描线；
    在所述绝缘层上形成第二金属层，所述第二金属层包括数据线；
    在所述第二金属层上形成一钝化层；
    对所述钝化层进行第一次刻蚀，得到第一沟槽和第二沟槽；
    对所述钝化层进行第二次刻蚀，得到第三沟槽；
    在所述钝化层上形成像素电极层；
    其中，第一次刻蚀得到的所述第一沟槽和所述第二沟槽的深度相同；所述第三沟槽的刻蚀深度与第一次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度。
  2. 根据权利要求1所述的阵列基板的制作方法，其中对所述钝化层进行第二次刻蚀，得到第三沟槽的步骤，包括：
    对所述钝化层的对应所述第三沟槽的位置处以及对应所述第一沟槽的位置处进行第二次刻蚀，得到所述第三沟槽，并露出所述第二金属层。
  3. 根据权利要求2所述的阵列基板的制作方法，其中第二次刻蚀所述第一沟槽和所述第三沟槽的刻蚀深度相同。
  4. 一种阵列基板的制作方法，其中所述阵列基板的制作方法包括：
    提供一玻璃基板，在所述玻璃基板上依次形成第一金属层和绝缘层，所述第一金属层包括扫描线；
    在所述绝缘层上形成第二金属层，所述第二金属层包括数据线；
    在所述第二金属层上形成一钝化层；
    对所述钝化层进行第一次刻蚀，得到第一沟槽和第二沟槽；
    对所述钝化层进行第二次刻蚀，得到第三沟槽；
    在所述钝化层上形成像素电极层。
  5. 根据权利要求4所述的阵列基板的制作方法，其中第一次刻蚀得到的所述第一沟槽和所述第二沟槽的深度相同。
  6. 根据权利要求4所述的阵列基板的制作方法，其中所述第三沟槽的刻蚀深度与第一次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度。
  7. 根据权利要求4所述的阵列基板的制作方法，其中对所述钝化层进行第二次刻蚀，得到第三沟槽的步骤，包括：
    对所述钝化层的对应所述第三沟槽的位置处以及对应所述第一沟槽的位置处进行第二次刻蚀，得到所述第三沟槽，并露出所述第二金属层。
  8. 根据权利要求7所述的阵列基板的制作方法，其中第二次刻蚀所述第一沟槽和所述第三沟槽的刻蚀深度相同。
  9. 一种阵列基板，其中所述阵列基板包括：
    一玻璃基板；
    一第一金属层，所述第一金属层设置于所述玻璃基板上，所述第一金属层包括扫描线；
    一绝缘层，所述绝缘层设置于所述第一金属层上；
    一第二金属层，所述第二金属层设置于所述绝缘层上，所述第二金属层包括数据线；
    一钝化层，所述钝化层设置于所述第二金属层上，所述钝化层包括第一沟槽、第二沟槽以及第三沟槽；
    一像素电极层，所述像素电极层设置于所述钝化层上。
  10. 根据权利要求9所述的阵列基板，其中所述第一沟槽的深度大于所述第二沟槽的深度。
  11. 根据权利要求9所述的阵列基板，其中所述第三沟槽的刻蚀深度与第一次刻蚀所述第一沟槽的刻蚀深度之和大于等于所述钝化层的厚度。
  12. 根据权利要求9所述的阵列基板，其中所述第一沟槽的位置对应所述数据线。
  13. 根据权利要求9所述的阵列基板，其中所述钝化层为氮化硅层。
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