Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
  • H03M1/188—Multi-path, i.e. having a separate analogue/digital converter for each possible range
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
  • H03F3/45183—Long tailed pairs
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
  • H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
  • H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45696—Indexing scheme relating to differential amplifiers the LC comprising more than two resistors

Definitions

• the invention relates to a voltage amplifier for a programmable voltage range and associated method for
• Input signal limited.
• the input signal can only be amplified to the extent that it can still be amplified linearly.
• ADC pipeline analog-to-digital converters
• the signal is then evaluated by one or more comparators and this value subtracted from the input signal of the comparators, to then only amplify the difference, the so-called residual error.
• Pipeline ADC need to be calibrated consuming
• Pipeline ADCs can thus not be switched on and off at short notice, since this can lead to a shift in the operating points.
• the voltage amplifier for a programmable voltage range provided.
• the voltage amplifier has at least a first and a second operating point with respect to an input voltage signal.
• the voltage amplifier is set up, a first area of the
• the voltage amplifier is further configured to supply a second range of the input voltage signal by means of the second operating point linearly to a second output signal
• the operating points of the voltage amplifier are always to be seen in this context in relation to the input voltage signal. For example, different ranges of the input voltage signal are shifted so that an amplifier that can linearly amplify input voltages between -5V and + 5V also covers such portions of the
• Voltage amplifier could for this purpose, for example, a
• Input voltage signal can be adjusted.
• Input voltage signal could, for example, by means of adjustable
• Resistances or reference potentials are moved continuously or discretely. Different ranges of periodic signals could thus be successively linearly amplified.
• the voltage amplifier could be configured in an alternative embodiment to provide the first operating point and the second operating point at the same time. It would thus be possible in particular for non-periodic signals a strongly fluctuating signal, the
• Example between -10 V and +10 V fluctuates, with for example two
• Amplifiers amplify linearly, the amplifier only at one
• a first range of this input voltage signal which is between -10V and V is thereby shifted in the range of the one amplifier in which this linearly amplified.
• a second range of this input voltage signal which is between OV and 10V and is thereby shifted in the range of the other amplifier in which this linearly amplified.
• Operating point are preferably adjusted so that the first range of the input voltage signal and the second range of the
• Input voltage signal have at least one common value. It is preferred that the first and second regions are at least partially different. However, the first and second areas may overlap. The first range of the input voltage signal and the second range of the input voltage signal are adjacent in an alternative
• Embodiment to each other would have the advantage that an input voltage signal can be linearly amplified with as few components as possible.
• An overlapping of the areas could alternatively have the advantage that due to the redundancy an error detection and
• the voltage amplifier is preferably arranged to amplify the first output signal by a predetermined first gain factor from the first range of the input voltage signal and amplify the second output signal by a predetermined second gain factor from the second range of the input voltage signal.
• the first and second gains may be different or equal.
• the voltage amplifier preferably has a control stage, at least one input reference resistor arrangement and a
• the voltage amplifier may have two, three or more control stages. The one or more control levels are preferred
• Input reference resistor arrangement is preferably set up, to provide at least a first image of the first range of the input voltage signal and a second image of the second range of the input voltage signal by means of the input current signal (s), such that the first image represents the first operating point with respect to the input signal
• Input voltage signal includes, and the second image of the second
• Amplifier circuit is preferably further configured to transform the first image to the first output signal and the second image to the second output signal.
• the amplifier circuit is in this case preferably further configured to output the first output signal as a voltage drop of the first output current across a first output reference resistor, and to output the second output signal as a voltage drop of the second output current via a second output reference resistor.
• the output reference resistor and the second output reference resistor may be identical or different. The or the
• Output reference resistors may also be adjustable, which could increase the flexibility of the circuitry.
• the amplifier circuit is preferably configured to amplify the first output current by a defined first current amplification factor with respect to the input current signal, and the second
• the embodiment could include one or more current mirrors with defined mirror ratios.
• the first current gain factor could be equal to or different than the second current gain factor.
• the amplifier circuit could comprise at least a first amplifier and a second amplifier in an alternative embodiment. The first amplifier is preferably set up, the first image by means of a first negative feedback to the first output signal
• the second amplifier is preferably set up to transform the second image with a second negative feedback to the second output signal.
• the amplifier circuit could also have 3, 4, 5 or more amplifiers with associated negative feedback.
• the negative feedback of the individual amplifiers can be selected the same or different.
• the amplifiers may be, for example, operational amplifiers.
• the first negative feedback is equal to the second negative feedback (and also the same size as any further negative feedback in the case of more than two amplifiers).
• the voltage amplifier is preferably arranged to amplify the first output signal by means of the first amplifier by the first gain factor, and the second output signal by means of the second amplifier to the second
• the first gain may be equal to or different than the second gain.
• the voltage amplifier has 3, 4, 5 or more amplifiers which are designed as operational amplifiers and have the same amplification factor by means of corresponding resistor circuits.
• the analog-to-digital converter circuitry includes at least one
• the analog-to-digital converter is set up to convert at least the first output signal into a first digital signal and convert at least the second output signal into a second digital signal.
• the conversion can be carried out successively with periodic output signals, so that only one analog-to-digital converter is required.
• Circuitry 2, 3, 4 or more analog-to-digital converters so that different portions of the input voltage signal can be converted simultaneously into a digital signal.
• Such an arrangement could be continuous, especially for non-periodic signals
• the first digital signal preferably represents a first linear transformed portion of the input voltage signal when the first digital signal has a first value, the first value being greater than a first minimum digital value and less than a first maximum digital value.
• the second digital signal preferably represents a second linearly transformed portion of the input voltage signal when the second digital signal has a second value, the second value being greater than a second minimum digital value and less than a second maximum digital value.
• only one of the analog-to-digital converters generally has a value which lies between the minimum and maximum digital output values of the analog-to-digital converters.
• Such analog-to-digital converters that convert an output signal that has too high or too low a voltage output either the minimum or the maximum digital output value.
• the method comprises the steps:
• the method includes the additional steps in addition to the steps mentioned above:
• Fig. 1 shows a first voltage amplifier
• Fig. 2 shows a second voltage amplifier
• Fig. 3 shows a waveform for the second voltage amplifier
• Fig. 4 shows a third voltage amplifier
• Fig. 5 shows a waveform for the third voltage amplifier
• FIG. 6 shows a schematic diagram of a fourth voltage amplifier
• Fig. 7 shows an analog-to-digital converter with the third
• Fig. 8 shows a schematic of a method for
• Fig. 1 shows a first voltage amplifier 100.
• Voltage amplifier 100 comprises a control stage 110 having a current source and a differential amplifier constructed of field-effect transistors.
• the input and thus the input voltage signal 10 is conducted to a gate of a normally-off first field effect transistor of the differential amplifier, wherein the source of this field effect transistor is connected to the current source.
• the output of the differential amplifier is connected to a gate of a self-conducting field effect transistor, which in turn is connected to a further gate of a second self-locking field effect transistor of the differential amplifier, which is connected to the first self-locking field effect transistor at the input. Because of this circuit is at the gate of the second normally-off field-effect transistor
• the first voltage amplifier 100 also has an amplifier circuit 130, which in this case is designed as a current mirror.
• the first voltage amplifier 100 includes a
• Input reference resistor assembly 120 with a
• Input reference resistor 121 and an input reference voltage 133.
• the input reference voltage 133 is connected to the input reference resistor 121, which in turn is connected to the gate of the second normally-off field-effect transistor.
• the input voltage is thus also applied to the output of the input reference resistor.
• the input voltage is thus:
• Input reference voltage 133 denotes.
• the current i si Gnai designates the current flowing through the input reference resistor 121 current.
• Biass voltage 131 is applied between the inputs of the two normally-off field-effect transistor of the current mirror of the amplifier circuit 130 and the associated gates, the current mirror having a mirror ratio M / N.
• a current i B i as flows via the self-locking
• Input reference resistor 121 and the gate of the second normally-off field effect transistor of the differential amplifier is connected.
• a current i ⁇ ias + isignai flows through the normally-applied field-effect transistor of the amplifier circuit 130 whose gate is used to feed back the input voltage signal 10.
• current flows through the output side of the current mirror 137 and an output reference voltage 135 a current (M / N) * i B ias and below the contact point a current (M / N) * i B ias + isignai- About the
• Output reference resistor 137 thus flows a current (M / N) * i si gnai-
• a first output signal 191 thus results in the case of the first voltage amplifier 100 to:
• V ou tput Routput * (M / N) * Isignal
• Output reference voltage 135 denotes.
• the operating point of the first voltage amplifier 100 can thus be determined using the
• Various input voltage signals 10 can thus be adapted so that they can be amplified linearly by means of the amplifier circuit 130.
• the reference resistors and also the reference voltages can be made adjustable.
• the concrete values for the reference resistors as well as the reference voltages depend on the application, the technology and the overall concept.
• Fig. 2 shows a second voltage amplifier 100.
• Voltage amplifier 100 again comprises a control stage 1 10 with a current source and a differential amplifier, wherein the output signal is fed back in an analogous manner to the differential amplifier, as in
• a bias current is analogous to how in FIG. 1 by means of a bias voltage 131, this bias current flowing via the input reference resistors 122, 123, 124 and 125 of the input reference resistor arrangement 120.
• Input reference resistors 122, 123, 124 and 125 are now selected so that defined potentials can be set in each case between the input reference resistors 122, 123, 124 and 125 so that different potentials can be set
• Input voltage signal 10 can be adjusted.
• Amplifier circuit 130 in this case has a first amplifier 140 whose positive input is connected to reference resistor arrangement 120, wherein at the positive input of the first amplifier 140, the potential between the first input reference resistor 122 and the second
• Input reference resistor 123 is applied.
• the output of the first amplifier 140 is fed back to a first negative feedback resistor 142.
• the negative output of the first amplifier 140 is also connected to a first amplifier ground voltage 146 via a first amplifier resistor 144.
• the gain of the first amplifier 140 is adjusted by means of the first negative feedback resistor 142 and the first amplifier resistor 144 and may also include the value 1.
• a normally-off field-effect transistor in the input of the differential resistance which is connected to the normally-off field-effect transistor, which receives the input voltage signal 10 as a control signal, is between the second input reference resistor 123 and the third
• Input reference resistor 124 connected. At this point, as discussed in connection with FIG. 1, the input voltage is present. A positive input of a second amplifier 150, also from the
• Amplifier circuit 130 is included between the third and the third
• Input reference resistor 124 and the fourth input reference resistor 125 connected.
• the output of the second amplifier 150 is coupled to a second negative feedback resistor 152.
• Output of the second amplifier 150 is also via a second Amplifier resistor 154 is connected to a second amplifier Biordschreib 156.
• the gain of the second amplifier 150 is amplified by means of the second negative feedback resistor 152 and the second
• Amplifier resistor 154 is set.
• the individual components have the following values: first input reference resistor 122 the value R2, second
• Input reference resistor 123 is R2 / 2, third
• Input reference resistor 124 is R2 / 2, fourth
• Amplifier resistor 144, 154 are respectively R1
• the first and second negative feedback resistors 142, 152 are respectively 2 * R1
• Fig. 3 shows a waveform for the second voltage amplifier 100.
• the signal amplitude 20 of the input voltage signal 10 is plotted here over the time 30.
• the input voltage signal is divided into a first region 12 and a second region 14 by vertical dashed lines.
• the input voltage signal 10 is in this case sinusoidal and the second region corresponds to the positive half-wave and the first region of the negative half-wave.
• the second output signal 192 has a linear part 434 in the second region 14 of the input voltage signal 10.
• the second amplifier 150 has in this second area of the
• Input voltage signal 10 a linear gain. This linear gain is due to the fact that the voltage at the positive input of the second amplifier 150 is reduced by the value R2 / 2 * i B i as in relation to the input voltage.
• R2 / 2 * i B i the value at which the voltage at the positive input of the second amplifier 150 is reduced by the value R2 / 2 * i B i as in relation to the input voltage.
• Input voltage signal 10 overrides the second amplifier 150 and outputs a nonlinear signal 432.
• the first output signal 191 has a linear part 424 in the first region 12 of the input voltage signal 10.
• the first amplifier 140 has in this first area of the
• Input voltage signal 10 a linear gain. This linear gain is due to the fact that the voltage at the positive input of the first amplifier 140 is increased by the value R2 / 2 * i B i as in relation to the input voltage.
• R2 / 2 * i B i the value at which the voltage at the positive input of the first amplifier 140 is increased by the value R2 / 2 * i B i as in relation to the input voltage.
• Input voltage signal 10 overrides the first amplifier 140 and outputs a non-linear signal 422.
• FIG. 4 shows a third voltage amplifier 100 with 4 outputs.
• the basic circuit of the voltage amplifier 100 is very similar to that in FIG. 2. Unlike in FIG. 2, however, a control stage 110 is provided at the input per output.
• the determination of the operating points of the 4 parallel amplifiers in relation to the input voltage signal 10 takes place again by means of the input reference resistor arrangement, which has 4 input reference resistors 126, 127, 128 and 129.
• the potential applied at the positive inputs of the amplifiers (V1, V2, V3, V4) becomes thereby by the position of the contact points relative to the
• Input reference resistors 126, 127, 128 and 129 in the current path of the respective bias currents (chosen equal) and the size of the
• Input reference resistors 126, 127, 128 and 129 are determined.
• the individual components have the following values: fifth input reference resistor 126 the value 1, 5 * R2, sixth input reference resistor 127 the value R2 / 2, seventh
• Input reference resistor 128 is R2 / 2, fourth
• Input reference resistor 129 the value 1, 5 * R2
• the amplifier resistors 144 each have the value R1
• the negative feedback resistors 142 each
• the first amplifier Biordbond 146 is the same for all amplifiers and has a different value than the bias voltage 131th
• FIG. 5 shows a waveform for the third voltage amplifier 100 as described in FIG. 4.
• the input voltage signal 10 the voltage V3 at the positive input of the third amplifier, the voltage V4 at the positive input of the fourth amplifier, the third output signal 193 and the fourth output signal 194 are shown.
• the voltages V3 and V4 are offset by the input reference resistors 128 and 129, respectively
• Input voltage signal 10 shifted.
• different operating points of the amplifiers relative to the input voltage signal 10 are determined by means of the input reference resistors 128 and 129.
• Consequence of the shift can be seen in the third and fourth output signals 193 and 194, where it can be seen that the input voltage signal 10 from the respective amplifier is linearly amplified only in certain areas. It is thus possible an input voltage signal 10 in various combinations
• FIG. 6 shows a schematic diagram of a fourth voltage amplifier 300, as becomes clear from the discussion of FIGS. 1 to 3
• Representation of the fourth voltage amplifier includes a bias 310, an input buffer 320, an input reference resistor array 330, a control of the input 340, an output 350, a
• Voltage amplifier 300 can be both integrated
• FIG. 7 shows an analog-to-digital converter circuit arrangement with the third voltage amplifier 100.
• Each of the 4 amplification branches with the different input reference voltages 1 1 1, 1 12, 1 13 and 1 14 has one of the amplifiers shown in FIG Output signals 191, 192, 193 and 194 output.
• Each of these output signals 191, 192, 193 and 194 is sent to a unique analog-to-digital converter 510
• Each of these analog-to-digital converters 510 is connected to ground 525 and, in this case, uniform reference voltage 515.
• the analog-to-digital converters 510 now output digital signals 531.
• Output signals 191, 192, 193 and 194 and the reference voltage 515 are now selected so that only one of the four analog-to-digital converters 510 outputs a digital value that is between a minimum and maximum digital value.
• the three other analog-to-digital converters 510 receive
• These 3 analog-to-digital converters 510 thus output either the minimum digital value (for example 0000) or the maximum digital value (for example 1 1 1 1).
• the linearly reinforced Range of the input voltage signal 10 can thus be determined in a simple manner by comparing the digital signals 531 at the outputs of the analog-to-digital converter 510.
• the digital signals 531 are output in time-discrete steps, which are determined by a clock 40. In the case where the output signals are exactly on the boundary between two regions of the input voltage signal 10, the analog-to-digital converter (s) 510 outputs the correct value at which the maximum digital value changes to the minimum digital value or vice versa.
• Fig. 8 shows a schematic of a method for
• step 710 an input voltage signal 10 is transformed so that a first region 12 of the input voltage signal 10 is in a first defined relation to a first operating point of a
• Amplifier circuit is set.
• step 720 a
• Input voltage signal 10 is transformed so that a second region 14 of the input voltage signal 10 is set in a second defined reference to a second operating point of the amplifier circuit.
• the first region 12 is transformed linearly to a first output signal 191.
• the second region 14 becomes linear to a second one
• Output signals may then be converted to digital signals, for example, by a plurality of analog-to-digital converters 510. It is thus possible to obtain a high-resolution digital signal 531 by means of relatively simple analog-to-digital converters 510. An elaborate calibration, how to Example in case of pipeline ADCs needs to be done is not required.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Power Engineering (AREA)
• Analogue/Digital Conversion (AREA)
• Amplifiers (AREA)

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• 2015
  • 2015-07-09 DE DE102015212842.3A patent/DE102015212842A1/de not_active Withdrawn
• 2016
  • 2016-07-05 EP EP16742190.8A patent/EP3320619B1/de active Active
  • 2016-07-05 US US15/742,983 patent/US10340937B2/en active Active
  • 2016-07-05 CN CN201680040673.7A patent/CN107852167B/zh not_active Expired - Fee Related
  • 2016-07-05 WO PCT/EP2016/065845 patent/WO2017005743A1/de not_active Ceased
  • 2016-07-05 JP JP2018500547A patent/JP7120918B2/ja active Active

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