WO2017000681A1 - 具有沟槽栅极结构的半导体器件及其制造方法 - Google Patents

具有沟槽栅极结构的半导体器件及其制造方法 Download PDF

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Publication number
WO2017000681A1
WO2017000681A1 PCT/CN2016/081927 CN2016081927W WO2017000681A1 WO 2017000681 A1 WO2017000681 A1 WO 2017000681A1 CN 2016081927 W CN2016081927 W CN 2016081927W WO 2017000681 A1 WO2017000681 A1 WO 2017000681A1
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Prior art keywords
trench
semiconductor device
layer
gate structure
doped region
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French (fr)
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芮强
邓小社
孙永生
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the present invention relates to a semiconductor process, and more particularly to a semiconductor device having a trench gate structure, and to a method of fabricating a semiconductor device having a trench gate structure.
  • insulated gate bipolar transistors IGBTs
  • N-type heavily doped regions NSD
  • the density of the trench cannot be increased without limitation.
  • a semiconductor device having a trench gate structure comprising a drift region, a metal electrode on the drift region, a trench penetrating from below the metal electrode to the drift region, a gate oxide layer on the inner surface of the trench, and polysilicon in the trench
  • the gate further includes a dielectric layer disposed in the trench and above the polysilicon gate, and a doped region on both sides of the top of the trench.
  • a method of fabricating a semiconductor device having a trench gate structure comprising the steps of: forming a trench by photolithography and etching on a surface of a substrate material; forming a gate oxide layer on an inner surface of the trench; depositing polysilicon and performing photolithography And etching, leaving a space between the top of the polysilicon in the trench and the top of the trench; injecting impurities and annealing, forming doped regions on both sides of the top of the trench; depositing the dielectric and etching back, at the top of the trench A dielectric layer is formed in the space; a metal electrode is formed on the surface of the doped region and the dielectric layer.
  • the dielectric layer can be avoided by using the orifice plate; and at the same time, the dielectric layer is formed
  • doping region does not need to consider the alignment with the trench, therefore, the spacing of the trench can be reduced without affecting the fabrication of the dielectric layer and the doped region, thereby effectively increasing the unit density of the trench, thereby improving the product.
  • the effect of current density because the orifice plate is not used, the production cost of the product can be reduced and the competitiveness of the product can be enhanced.
  • FIG. 1 is a schematic structural view of a dielectric layer and a doped region in a trench in an embodiment
  • Figure 2a is a cross-sectional view taken along line A - A' of Figure 1;
  • Figure 2b is a cross-sectional view taken along line B-B' of Figure 1;
  • FIG. 3 to FIG. 6 are cross-sectional views showing a semiconductor device having a trench gate structure in a manufacturing process in an embodiment
  • FIG. 7 is a cross-sectional view of a device fabricated by a method of fabricating a semiconductor device having a trench gate structure
  • FIG. 8 is a flow chart of a method of fabricating a semiconductor device having a trench gate structure in an embodiment.
  • FIG. 1 is a schematic view showing the structure of a dielectric layer and a doped region in a trench in an embodiment.
  • the device is a field-off insulated gate bipolar transistor (FS-IGBT), and the doped region is used as an emission.
  • FS-IGBT field-off insulated gate bipolar transistor
  • a very large N-type heavily doped region 14 As shown, the direction in which the trench extends in the plane of FIG. 1 is perpendicular to the direction in which the N-type heavily doped region 14 extends in the plane of FIG. 1, that is, the direction in which the trench extends in the cross-section of the device is perpendicular to the N-type. The direction in which the heavily doped region 14 extends in the cross section of the device.
  • the FS-IGBT includes a metal electrode 11, a dielectric layer 12, a polysilicon gate 13, an N-type heavily doped region 14, a body region 15, a gate oxide layer 16, a drift region 17, a field stop layer 18, a P+ layer 19, and a back metal structure. 20.
  • FIG. 8 is a flow chart of a method of fabricating the above-described semiconductor device having a trench gate structure. Taking a manufacturing field-off insulated gate bipolar transistor (FS-IGBT) as an example, the following steps are included:
  • Photolithography and etching form trenches 22.
  • P-type impurity implantation is performed on the front side of the N-type substrate material (generally the flawless region melting method FZ material as the drift region 17) to push the well to form a body region.
  • FZ material the flawless region melting method
  • 15 steps Since the FS-IGBT is fabricated, a step of implanting a back surface N-type impurity and pushing a well to form a field stop layer 18 is also included before forming the body region 15.
  • the cross section of the device after completion of step S110 is as shown in FIG.
  • the step of preparing the field stop layer 18 can also be carried out in a later step, as will be described in more detail below. Of course, the step of preparing the field stop layer 18 will be omitted for a device other than the FS type.
  • the gate oxide layer 16 is thermally oxidized on the inner surface (i.e., the bottom surface and the side surface) of the trench 22.
  • step S130 The cross section of the device after completion of step S130 is as shown in FIG.
  • N-type impurity implantation is performed on the front side of the device and annealed to form a heavily doped region 14.
  • the heavily doped region 14 has a depth of about 0.4 to 1 micron.
  • the cross section of the device after completion of step S140 is as shown in FIG. It can be understood that due to the existence of each trench 22 (filled with the gate oxide layer 16 and the polysilicon gate 13 in the trench 22), the heavily doped region 14 is also separated by the trench 22 without using a mask.
  • the arranged structure is, for example, a structure in FIG. 5 which is divided into three by the groove 22 in the lateral direction.
  • a photolithographic mask of the corresponding pattern can be used.
  • the deposition medium may be borophosphosilicate glass (BPSG), phosphosilicate glass (PSG) or silica formed by using tetraethyl orthosilicate (TEOS) as a gas source, and the medium is filled into the space which is hollowed out in step S130. And the surface of the entire wafer, and then the medium on the surface of the wafer is removed by etching back, and the dielectric layer 12 can be formed in the space (i.e., in the trench 22) which is hollowed out in step S130 without using a mask.
  • the cross section of the device after completion of step S150 is as shown in FIG. 6.
  • the front metal electrode is formed, and may be aluminum or an aluminum alloy such as AlSi or AlSiCu.
  • the device can be back-thinned, and after the thinning, the field stop layer 18 can be prepared on the back side (corresponding to the embodiment in which the field stop layer 18 is not formed in the previous step).
  • the preparation of the P+ layer 19 is performed, specifically, P-type impurity implantation and annealing are performed on the back surface.
  • the implanted ions may be boron, and the implantation dose is 1*10 12 ⁇ 1*10 16 /cm 2 .
  • the annealing temperature is between 300 and 500 degrees Celsius, and the annealing time is between 10 and 200 minutes.
  • the preparation of the back metal structure is carried out, generally an Al-Ti-Ni-Ag metal structure.
  • the cross section of the device after completion is shown in Figure 7.
  • a conventional insulated gate bipolar transistor having a trench gate structure requires a via hole formed between the two trenches to achieve contact between the front metal electrode and the underlying silicon. Since the through hole also has a minimum strip width limitation, it cannot be made very small; at the same time, in order to ensure the quality of the device parameters, a certain space guarantee is required between the through hole and the groove, and the front emitter injection also needs a certain size to form, which The 3 aspects lead to the trench spacing of the conventional technology cannot be made small.
  • the etching is performed before the hole, thereby avoiding the use of the orifice plate to form the dielectric layer; at the same time, the dielectric layer and the doping region are formed It is not necessary to consider the alignment with the trenches. Therefore, the pitch of the trenches can be reduced without affecting the fabrication of the dielectric layer and the doped regions, thereby effectively increasing the unit density of the trenches and improving the current density of the product. .
  • the orifice plate is not used, the production cost of the product can be reduced and the competitiveness of the product can be enhanced.

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  • Electrodes Of Semiconductors (AREA)

Abstract

一种具有沟槽栅极结构的半导体器件，包括漂移区(17)、漂移区（17）上的金属电极（11）、从金属电极（11）下方贯穿至漂移区（17）的沟槽、沟槽内表面的栅氧化层（16）、以及沟槽内的多晶硅栅极（13），还包括设于所述沟槽内且在所述多晶硅栅极（13）上方的介质层（12），以及所述沟槽顶部两侧的掺杂区。

Description

具有沟槽栅极结构的半导体器件及其制造方法
【技术领域】
本发明涉及半导体工艺，特别是涉及一种具有沟槽栅极结构的半导体器件，还涉及一种具有沟槽栅极结构的半导体器件的制造方法。
【背景技术】
传统具有沟槽栅极结构的绝缘栅双极型晶体管（IGBT）一直通过压缩孔、N型重掺杂区（NSD）的光刻和套刻尺寸，以便提升单位面积的沟槽（Trench）密度，来提升产品电流密度。但受限于工艺能力影响，无法无限制的提升沟槽的密度。
【发明内容】
基于此，有必要提供一种能够提升沟槽密度的具有沟槽栅极结构的半导体器件及其制造方法。
一种具有沟槽栅极结构的半导体器件，包括漂移区、漂移区上的金属电极、从金属电极下方贯穿至漂移区的沟槽、沟槽内表面的栅氧化层、以及沟槽内的多晶硅栅极，还包括设于所述沟槽内且在所述多晶硅栅极上方的介质层，以及所述沟槽顶部两侧的掺杂区。
一种具有沟槽栅极结构的半导体器件的制造方法，包括步骤：在衬底材料表面光刻和刻蚀形成沟槽；在沟槽的内表面形成栅氧化层；淀积多晶硅并进行光刻和刻蚀，在沟槽内的多晶硅顶部与沟槽顶部之间空出空间；注入杂质并退火，在沟槽顶部的两侧形成掺杂区；淀积介质并回刻，在沟槽顶部所述空间内形成介质层；在掺杂区和介质层表面形成金属电极。
上述具有沟槽栅极结构的半导体器件的制造方法，通过更改掺杂区和沟槽的设计，孔前淀积介质层并回刻，可以避免使用孔板制作介质层；同时，由于制作介质层和掺杂区时不需要考虑与沟槽的对位，因此，可减小沟槽的间距而不会影响介质层和掺杂区的制作，从而有效提升沟槽的单位密度，达到提高产品的电流密度的效果。同时由于不使用孔板，可以降低产品的生产成本，增强产品的竞争力。
【附图说明】
通过附图中所示的本发明的优选实施例的更具体说明，本发明的上述及其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本发明的主旨。
图1是一实施例中沟槽内的介质层与掺杂区的结构示意图；
图2a是沿图1中A—A’线的剖视图；
图2b是沿图1中B—B’线的剖视图；
图3至图6是一实施例中具有沟槽栅极结构的半导体器件在制造过程中的剖面图；
图7是采用具有沟槽栅极结构的半导体器件的制造方法制造出的器件的剖面图；
图8是一实施例中具有沟槽栅极结构的半导体器件的制造方法的流程图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1是一实施例中沟槽内的介质层与掺杂区的结构示意图，在该实施例中，器件为场截止型绝缘栅双极型晶体管（FS-IGBT），掺杂区是作为发射极的N型重掺杂区14。如图所示，沟槽在图1所在平面上的延伸方向垂直于N型重掺杂区14在图1所在平面上的延伸方向，即沟槽在器件横截面上的延伸方向垂直于N型重掺杂区14在器件横截面上的延伸方向。图2a、图2b分别是沿图1的A——A’线和B——B’线的剖视图。FS-IGBT包括金属电极11、介质层12、多晶硅栅极13、N型重掺杂区14、体区15、栅氧化层16、漂移区17、场截止层18、P+层19以及背面金属结构20。
图8是上述具有沟槽栅极结构的半导体器件的制造方法的流程图。以制造场截止型绝缘栅双极型晶体管（FS-IGBT）为例，包括下列步骤：
S110，在衬底材料表面光刻和刻蚀形成沟槽。
光刻和刻蚀形成沟槽22。在本实施例中，在步骤S110之前包括在N-型衬底材料（一般为无坩埚区域熔化法FZ材料，作为漂移区17）正面进行P型杂质注入并推阱，形成体区（body）15的步骤。由于是制造FS-IGBT，在形成体区15之前还包括对衬底材料进行背面N型杂质注入并推阱，形成场截止层18的步骤。步骤S110完成后器件的剖面如图3所示。制备场截止层18的步骤也可以放在后面的步骤进行，下文会具体介绍。当然，对于非FS型的器件则会省略制备场截止层18的步骤。
S120，在沟槽内表面形成栅氧化层。
在本实施例中，是在沟槽22的内表面（即底面及侧面）热氧化生长栅氧化层16。
S130，淀积多晶硅并进行光刻和刻蚀，在沟槽内的多晶硅顶部与沟槽顶部之间空出空间。
刻蚀后仅保留沟槽内的多晶硅栅极13。注意淀积的多晶硅栅极13不应将沟槽填满，而是空出供后续步骤填入介质层的空间。在本实施例中，多晶硅栅极13顶部应比硅表面（沟槽顶部）低H=0.2微米~0.8微米。步骤S130完成后器件的剖面如图4所示。
S140，注入杂质并退火，在沟槽顶部的两侧形成掺杂区。
在器件正面进行N型杂质注入并退火，形成重掺杂区14。在本实施例中，重掺杂区14的深度在0.4~1微米左右。步骤S140完成后器件的剖面如图5所示。可以理解的，由于各条沟槽22（沟槽22内填充了栅氧化层16和多晶硅栅极13）的存在，无需使用掩膜版，重掺杂区14也会被沟槽22分隔为间隔排列的结构，例如图5中在横向上被沟槽22分隔为3个的结构。在其中一个实施例中，如果需要重掺杂区14形成特殊的图案，例如图1所示的4条横条，则可以使用相应图案的光刻掩膜版实现。
S150，淀积介质并回刻，在沟槽顶部形成介质层。
淀积介质，可以为硼磷硅玻璃（BPSG），磷硅玻璃（PSG）或以正硅酸乙酯（TEOS）为气体源形成的二氧化硅等，介质会填入步骤S130中空出来的空间以及整个晶圆（wafer）的表面，然后通过回刻去除晶圆表面的该介质，无需使用掩膜版就可在步骤S130中空出来的空间（也即沟槽22内）形成介质层12。步骤S150完成后器件的剖面如图6所示。
S160，在掺杂区和介质层表面形成金属电极。
形成正面金属电极，可以为铝，或者AlSi，AlSiCu等铝合金。
步骤S160完成后可以对器件进行背面减薄，减薄后可以在背面制备场截止层18（对应在前面的步骤中未形成场截止层18的实施例）。之后进行P+层19的制备，具体可以是在背面进行P型杂质注入并退火。注入离子可以为硼，注入剂量在1*1012~1*1016/cm2。退火温度在300~500摄氏度，退火时间为10~200分钟。最后进行背面金属结构的制备，一般为Al-Ti-Ni-Ag金属结构。完成后器件的剖面如图7所示。
传统的具有沟槽栅极结构的绝缘栅双极型晶体管，需要在两个沟槽之间形成通孔，以实现正面的金属电极与下方的硅的接触。由于通孔也有最小条宽限制，无法做到非常小；同时为了保证器件参数质量，通孔和沟槽之间也需要一定的空间保证，同时正面发射极注入也需要一定的尺寸来形成，这3方面导致了传统技术的沟槽间距无法做小。
上述具有沟槽栅极结构的半导体器件的制造方法，通过更改掺杂区和沟槽的设计，孔前采用回刻，可以避免使用孔板制作介质层；同时，由于制作介质层和掺杂区时不需要考虑与沟槽的对位，因此，可减小沟槽的间距而不会影响介质层和掺杂区的制作，从而有效提升沟槽的单位密度，达到提高产品的电流密度的效果。同时由于不使用孔板，可以降低产品的生产成本，增强产品的竞争力。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种具有沟槽栅极结构的半导体器件，包括：
    漂移区；
    金属电极，位于漂移区上；
    沟槽，从所述金属电极下方贯穿至所述漂移区；
    栅氧化层，位于所述沟槽的内表面；
    多晶硅栅极，位于所述沟槽内；
    介质层，设于所述沟槽内且在所述多晶硅栅极上方；以及
    掺杂区，位于所述沟槽顶部两侧。
  2. 根据权利要求1所述的具有沟槽栅极结构的半导体器件，其特征在于，所述多晶硅栅极的顶部距所述沟槽顶部的距离为0.2微米~0.8微米，所述掺杂区的深度为0.4微米~1微米。
  3. 根据权利要求1所述的具有沟槽栅极结构的半导体器件，其特征在于，所述介质层的材质为硼磷硅玻璃、磷硅玻璃或者以正硅酸乙酯为气体源制备的二氧化硅。
  4. 根据权利要求1所述的具有沟槽栅极结构的半导体器件，其特征在于，所述半导体器件为绝缘栅双极型晶体管，包括漂移区上方的P型体区，所述沟槽从P型体区向下贯穿至所述漂移区，所述掺杂区为N型重掺杂区。
  5. 根据权利要求4所述的具有沟槽栅极结构的半导体器件，其特征在于，所述器件是场截止型绝缘栅双极型晶体管，包括背面的场截止层、所述场截止层表面的P+层、以及所述P+层表面的背面金属结构。
  6. 根据权利要求1所述的具有沟槽栅极结构的半导体器件，其特征在于，所述半导体器件为垂直双扩散金属氧化物半导体场效应晶体管，所述掺杂区为源极。
  7. 根据权利要求1所述的具有沟槽栅极结构的半导体器件，其特征在于，所述沟槽的在器件横截面上的延伸方向垂直于所述掺杂区在器件横截面上的延伸方向。
  8. 一种具有沟槽栅极结构的半导体器件的制造方法，包括：
    在衬底材料表面光刻和刻蚀形成沟槽；
    在沟槽的内表面形成栅氧化层；
    淀积多晶硅并进行光刻和刻蚀，在沟槽内的多晶硅顶部与沟槽顶部之间空出空间；
    注入杂质并退火，在沟槽顶部的两侧形成掺杂区；
    淀积介质并回刻，在沟槽顶部所述空间内形成介质层；及
    在掺杂区和介质层表面形成金属电极。
  9. 根据权利要求8所述的方法，其特征在于，所述淀积多晶硅并进行光刻和刻蚀，在沟槽内的多晶硅顶部与沟槽顶部之间空出空间的步骤，形成的多晶硅顶部距所述沟槽顶部的距离为0.2微米~0.8微米。
  10. 根据权利要求9所述的方法，其特征在于，所述注入杂质并退火，在沟槽顶部的两侧形成掺杂区的步骤，形成的掺杂区深度为0.4微米~1微米。
  11. 根据权利要求8所述的方法，其特征在于，所述淀积介质并回刻，在沟槽顶部所述空间内形成介质层的步骤，是淀积磷硅玻璃、硼磷硅玻璃或以正硅酸乙酯为气体源形成的二氧化硅。
  12. 根据权利要求8所述的方法，其特征在于，所述半导体器件为绝缘栅双极型晶体管，所述衬底材料为N-型材料，所述在衬底材料表面光刻和刻蚀形成沟槽的步骤之前，还包括注入P型杂质并推阱，形成P型体区的步骤；所述在掺杂区和介质层表面形成金属电极的步骤之后，还包括形成场截止层的步骤，形成场截止层表面的P+层的步骤，以及形成所述P+层表面的背面金属结构的步骤。
PCT/CN2016/081927 2015-07-02 2016-05-12 具有沟槽栅极结构的半导体器件及其制造方法 Ceased WO2017000681A1 (zh)

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