WO2017000442A1 - 一种直流转换器、实现方法及计算机存储介质 - Google Patents

一种直流转换器、实现方法及计算机存储介质 Download PDF

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Publication number
WO2017000442A1
WO2017000442A1 PCT/CN2015/092801 CN2015092801W WO2017000442A1 WO 2017000442 A1 WO2017000442 A1 WO 2017000442A1 CN 2015092801 W CN2015092801 W CN 2015092801W WO 2017000442 A1 WO2017000442 A1 WO 2017000442A1
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type
signal
ramp signal
ramp
converter
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PCT/CN2015/092801
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English (en)
French (fr)
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方磊
韦东
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深圳市中兴微电子技术有限公司
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Publication of WO2017000442A1 publication Critical patent/WO2017000442A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present invention relates to the field of electronic circuit technologies, and in particular, to a DC converter, an implementation method thereof, and a computer storage medium.
  • the topology capable of simultaneously implementing the step-up buck function mainly includes a buck-boost topology, SEPIC (Single Ended Primary Inductor Converter), ZETA topology, and Cuk. Topology and four-switch control structure.
  • the Buck/Boost topology and the Cuk topology can implement the buck-boost function, but the input and output voltages of these two topologies have opposite polarities, which makes them inconvenient to be used in portable electronic products.
  • the four-switch control structure is based on a single-inductor topology that controls the boost or buck modulation of the system by controlling the turn-on and turn-off of the four switches. It simply separates the buck and boost.
  • the clever combination of architectures and the relatively simple implementation of internal synchronous rectification technology are easier for designers who often use stand-alone Buck and Boost architectures.
  • the conventional four-switch control mode buck-boost converter has at least the following problem: as the input voltage changes or the output voltage changes, the continuity of the system when the buck mode or the boost mode is mutually converted is poor.
  • the embodiments of the present invention are expected to provide a DC converter, an implementation method, and a computer storage medium, which can implement continuous switching between the Buck mode and the Boost mode, and simplify the complexity of the circuit design.
  • An embodiment of the present invention provides a DC converter, where the DC converter includes:
  • a signal generation module configured to generate a first type of ramp signal and a second type of ramp signal based on a reference voltage; wherein the first type of ramp signal is to place the DC converter in a buck mode of operation, the second type a ramp signal for causing the DC converter to be in a boost mode of operation;
  • a signal control module configured to adjust the first type of ramp signal and the second type of ramp signal according to a preset algorithm to make a gap between the first type of ramp signal and the second type of ramp signal Meet the preset conditions.
  • the signal control module is further configured to:
  • a digital control signal is generated according to the acquired offset voltage value to control the signal generating module to generate a first type of ramp signal and a second type of ramp signal that satisfy a preset condition.
  • the signal control module is further configured to:
  • a digital control signal is generated according to the acquired offset voltage value to control the signal generating module to generate a first type of ramp signal and a second type of ramp signal that satisfy a preset condition.
  • the signal control module includes:
  • N N sets of resistors, wherein each set of resistors has a switch matching the resistance, and the N sets of resistors are connected in parallel; wherein N is a positive integer greater than or equal to 1;
  • a digital control signal is generated by controlling the opening or closing of a switch that matches the electrical N resistance to add an offset voltage to the signal generating module.
  • the signal generating module includes:
  • a cache module configured to buffer the reference voltage and the offset voltage value.
  • the signal generating module is further configured to:
  • a first type of ramp signal and a second type of ramp signal are generated based on a reference voltage buffered by the cache module and an offset voltage value.
  • the embodiment of the invention further provides a method for implementing a DC converter, the method comprising:
  • first type of ramp signal is for placing the DC converter in a buck mode of operation and the second type of ramp signal is for The DC converter is placed in a boost mode of operation.
  • the first type of ramp signal and the second type of ramp signal are adjusted according to a preset algorithm such that a gap between the first type of ramp signal and the second type of ramp signal generated by the signal generating module satisfies a preset condition.
  • the adjusting the first type of ramp signal and the second type of ramp signal according to a preset algorithm including:
  • a digital control signal is generated based on the acquired offset voltage value to control generation of the first type of ramp signal and the second type of ramp signal that satisfy a preset condition.
  • the adjusting the first type of ramp signal and the second type of ramp signal according to a preset algorithm including:
  • a digital control signal is generated according to the acquired offset voltage value to control the signal generating module to generate a first type of ramp signal and a second type of ramp signal that satisfy a preset condition.
  • the adjusting the first type of ramp signal and the second type of ramp signal according to a preset algorithm including:
  • N is a positive integer greater than or equal to 1;
  • a digital control signal is generated by controlling the opening or closing of a switch that matches the electrical N resistance to add an offset voltage.
  • the using the same signal generating module to generate the first type of ramp signal and the second type of ramp signal including:
  • the reference voltage and the offset voltage value are buffered.
  • the using the same signal generating module to generate the first type of ramp signal and the second type of ramp signal including:
  • a first type of ramp signal and a second type of ramp signal are generated based on the buffered reference voltage and the offset voltage value.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores a computer program, and the computer program is used to execute the DC converter implementation method described above.
  • the DC converter, the implementation method and the computer storage medium provided by the embodiments of the present invention can realize a seamless connection between the step-up ramp signal and the step-down ramp signal, and achieve the effects of continuously converting the Buck mode and the Boost mode.
  • the gap between the boost ramp signal and the buck ramp signal can be controlled as needed, which greatly simplifies the circuit design complexity.
  • the technical solution in the embodiment of the present invention adopts a four-switch control buck-boost topology, which can realize the same-direction conversion of voltage and lower system design cost than the ordinary buck-boost topology. . Thanks to the improved ramp signal, it can work in a wide voltage input range, making the process of converting Buck mode and Boost mode more smooth and complete, and making the ramp signal generation module design simpler and more convenient.
  • FIG. 1 is a schematic structural diagram of a DC converter according to an embodiment of the present invention.
  • FIG. 2 is a system block diagram of a DC switch of a four-switch control mode according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a ramp signal according to an embodiment of the present invention.
  • FIG. 4 is a schematic hardware diagram of a signal generating module according to an embodiment of the present invention.
  • FIG. 5 is another schematic diagram of a hardware of a signal generating module according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a hardware of a signal control module according to an embodiment of the present invention.
  • FIG. 7 is another schematic diagram of hardware of a signal control module according to an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart diagram of a method for implementing a DC converter according to an embodiment of the present invention.
  • the DC converter of the present invention is a buck-boost DC-DC converter, which has both a boost function and a step-down function.
  • PWM is the abbreviation of Pulse-Width Modulation
  • the Chinese name is “pulse width modulation”
  • the clock signal is represented by "CLK signal”.
  • FIG. 1 is a schematic structural diagram of a DC converter according to an embodiment of the present invention. As shown in FIG. 1 , the DC converter mainly includes:
  • a signal generating module 11 configured to generate a first type of ramp signal and a second type of ramp signal based on a reference voltage; wherein the first type of ramp signal is used to put the DC converter in a buck mode of operation, the second a ramp-like signal is used to put the DC converter in a boost mode of operation;
  • the signal control module 12 is configured to adjust the first type of ramp signal and the second type of ramp signal according to a preset algorithm to enable the first type of ramp signal and the second type of ramp signal The gap meets the preset conditions.
  • the signal control module 12 is further configured to:
  • a digital control signal is generated according to the acquired offset voltage value to control the signal generating module to generate a first type of ramp signal and a second type of ramp signal that satisfy a preset condition.
  • the signal control module 12 is further configured to:
  • a digital control signal is generated according to the acquired offset voltage value to control the signal generating module to generate a first type of ramp signal and a second type of ramp signal that satisfy a preset condition.
  • the loop may be a monitoring loop in the prior art, and details are not described herein again.
  • the signal control module 12 includes:
  • N N sets of resistors, wherein each set of resistors has a switch matching the resistance, and the N sets of resistors are connected in parallel; wherein N is a positive integer greater than or equal to 1;
  • a digital control signal is generated by controlling the opening or closing of a switch that matches the electrical N resistance to add an offset voltage to the signal generating module.
  • the signal generating module 11 includes:
  • a cache module configured to buffer the reference voltage and the offset voltage value.
  • the signal generating module 11 is further configured to:
  • a first type of ramp signal and a second type of ramp signal are generated based on a reference voltage buffered by the cache module and an offset voltage value.
  • the preset condition may be that there is no gap, or the size of the gap is less than or equal to the first threshold.
  • the first threshold may be set according to actual conditions.
  • the DC converter provided by the embodiment of the invention can realize the seamless connection between the step-up ramp signal and the step-down ramp signal, and achieve the effects of continuously converting the Buck mode and the Boost mode, and at the same time, can be controlled as needed.
  • FIG. 2 is a system block diagram of a four-switch control mode DC converter according to an embodiment of the present invention. As shown in FIG. 2, the system block diagram mainly includes several major modules:
  • First PWM comparator module corresponding to Buck mode (PWM 1 in the figure)
  • the first driving module (indicated by the driving module 1 in the figure), the second PWM comparator module corresponding to the boost mode (indicated by PWM 2 in the figure), and the second driving module (in the figure)
  • the middle is driven by the driving module 2, the power tube module, the current sampling module, the feedback sampling part of the feedback loop part, the error amplification module, the logic control module, the signal generation module and the signal control module.
  • the feedback sampling module includes resistors R1 and R2;
  • the error amplification module includes a first operational amplifier (indicated by VA in the figure) that uses a voltage loop operational amplifier for error amplification, and an error using a current loop operational amplifier.
  • An amplified second operational amplifier (represented by CA in the figure); wherein Vva is the output voltage of the first operational amplifier, Vca is the output voltage of the second operational amplifier, Vrs is the sampled value of the current sampling module, and Vref is the reference voltage .
  • the power tube module includes: a first group of power tubes corresponding to the first driving module, and a second group of power tubes corresponding to the second driving module;
  • the first group of power tubes includes a power tube a (referred to as an "upper tube”) above the first driving module, and another power tube b;
  • the second group of power tubes includes the second A power tube a (referred to as "upper tube”) above the drive module, and another power tube b.
  • the power tube a of the first group of power tubes and the power tube a of the second group of power tubes are connected by an inductor.
  • the signal control module is connected to the first end of the signal generating module; the second end of the signal generating module is connected to the first input end of the first PWM comparator module, and the signal generating module is a third end is coupled to the first input of the second PWM comparator module; a second input of the first PWM comparator module is coupled to an output of the second operational amplifier, the second PWM comparator module The second input terminal is also coupled to the output of the second operational amplifier; the non-inverting input of the second operational amplifier is coupled to the output of the current sampling module; and the inverting input of the second operational amplifier is coupled to the first An output terminal of the operational amplifier is connected; a non-inverting input terminal of the first operational amplifier is connected to a reference voltage (Vref), and the first operational amplification The inverting input of the device is connected to the feedback voltage (Vfb); the output of the first PWM comparator module and the output of the second PWM comparator module are respectively connected to the input of the logic control module; The two output ends
  • Vin is the input voltage of the entire DC converter system
  • Vout is the output voltage of the entire DC converter system
  • Vva is the output voltage of the first op amp
  • Vca is the output voltage of the second op amp
  • Vrs is The sampled value of the current sampling module
  • Vref is the reference voltage.
  • system block diagram shown in FIG. 2 adopts the control mode of the average current mode.
  • the following embodiments are also described based on the system block diagram shown in FIG. 2, but the scope of use of the present invention is not limited thereto. It can also be used for control modes such as voltage mode and peak current mode, and will not be described in detail here.
  • FIG. 3 is a schematic diagram of a ramp signal according to an embodiment of the present invention. As shown in FIG. 3, the upper half belongs to a buck type ramp signal (represented by a Ramp_buck signal), and the lower half belongs to a boost type ramp signal (a Ramp_boost signal is available). To represent).
  • a Ramp_buck signal represented by a Ramp_buck signal
  • a Ramp_boost signal is available. To represent).
  • the Ramp_buck signal and the Ramp_boost signal are simultaneously pulled back to the Vref voltage and then rise and fall at the same speed, respectively, until the next CLK trigger signal arrives.
  • the Ramp_buck signal and the Ramp_boost signal are generated by the same module circuit, that is, generated by the signal generating module, which ensures that the same Vref voltage is used, thereby ensuring that the Ramp_buck signal and the Ramp_boost signal are very well connected, thereby avoiding signal crossing.
  • the generation of a stack or a gap causes a problem in which the buck mode (buck mode) and the boost mode (boost mode) are switched to each other.
  • the signal generating module introduces a first buffer (indicated by Buf 1 in the figure) and a second buffer (in the figure).
  • Buf 1 the first buffer
  • Buf 2 the second buffer
  • it also includes a first circuit for generating a Ramp_buck signal and a second circuit for generating a Ramp_boost signal.
  • the first circuit includes two capacitors, which are respectively recorded as C1 and C2, three S1 switches, and three S2 switches.
  • One end of the first S1 switch is connected to the output end of the first buffer.
  • the other end of the first S1 switch is respectively connected to one end of the capacitor C2, one end of the second S2 switch, and one end of the third S2 switch, and the other end of the third S2 switch is connected to the bias current i_bias;
  • the other end of the S2 switch outputs a Ramp_buck signal, and the other end of the capacitor C2 is grounded.
  • one end of the first S2 switch is connected to the output end of the first buffer, and the other end of the first S2 switch is respectively connected to the capacitor C1.
  • One end, one end of the second S1 switch, one end of the third S1 switch are connected, the other end of the third S1 switch is connected to the bias current i_bias, and the other end of the second S1 switch outputs a Ramp_buck signal, the capacitor The other end of C1 is grounded.
  • the first S1 switch is represented by S1(1) in the figure
  • the second S1 switch is represented by S1(2) in the figure
  • the third S1 switch is represented by S1(3) in the figure
  • the first The S2 switch is represented by S2(1) in the figure
  • the second S2 switch is represented by S2(2) in the figure
  • the third S2 switch is represented by S2(3) in the figure.
  • the second circuit includes two capacitors, which are respectively recorded as C3 and C4, three S3 switches, and three S4 switches.
  • One end of the first S3 switch is connected to the output end of the second buffer.
  • the other end of the first S3 switch is respectively connected to one end of the capacitor C4, one end of the second S4 switch, and the One end of the three S4 switches is connected, the other end of the third S4 switch is connected to the bias current i_bias, and the other end of the bias current i_bias is grounded;
  • the other end of the second S4 switch outputs a Ramp_boost signal, and the other end of the capacitor C4 Grounding; similarly, one end of the first S4 switch is connected to the output end of the second buffer, and the other end of the first S4 switch is respectively connected to one end of the capacitor C3, one end of the second S3 switch, and the third S3 One end of the switch is connected, the other end of the third S3 switch is connected to the bias current i_bias, and the other
  • the first S3 switch is represented by S3(1) in the figure
  • the second S3 switch is represented by S3(2) in the figure
  • the third S3 switch is represented by S1(3) in the figure
  • the first The S4 switch is represented by S4(1) in the figure
  • the second S4 switch is represented by S2(2) in the figure
  • the third S4 switch is represented by S4(3) in the figure.
  • the way of alternately switching the charge and discharge capacitors is equivalent to giving the buffer and the capacitor one clock cycle to stabilize the voltage, which prevents the voltage from being stabilized and continues to be used at the moment of switching, and can avoid the Ramp_buck signal and The intermediate voltages of the Ramp_boost signals are not equal and the mode switching is discontinuous.
  • the trigger edge may be either a rising edge or a falling edge.
  • the signal generating module it is not limited to a certain circuit form, for example, a driving circuit capable of designing different common mode input voltages according to the level of the reference voltage Vref; Required to design a simple potential conversion (level The shift circuit in the form of shift or the drive circuit with higher precision; can also be designed as a complementary metal-oxide-semiconductor (CMOS) or bipolar (bipolar) according to the requirements of the process.
  • CMOS complementary metal-oxide-semiconductor
  • bipolar bipolar
  • the capacitor can be stabilized for a longer period of time after charging and discharging, and a single capacitor charging and discharging circuit can also be used, that is, each cycle is performed with the same capacitor. Charge and discharge, do not need to use two capacitors in turn, the specific implementation is shown in Figure 5.
  • FIG. 5 is another schematic diagram of a hardware of a signal generating module according to an embodiment of the present invention.
  • the signal generating module introduces a first buffer (indicated by Buf 1 in the figure) and a second buffer (at The figure is represented by Buf 2), and at the same time, a third circuit for generating a Ramp_buck signal and a fourth circuit for generating a Ramp_boost signal are also included.
  • the third circuit includes one capacitor, denoted as C1, one S1 switch, and one S2 switch; wherein one end of the S2 switch is connected to the output end of the first buffer, and the other end of the S2 switch is respectively One end of the capacitor C1, one end of the S1 switch, and the output Ramp_buck signal end are connected, the other end of the capacitor C1 is grounded; the other end of the S1 is connected to the bias current i_bias.
  • the fourth circuit includes one capacitor, denoted as C3, one S3 switch, and one S4 switch; wherein one end of the S4 switch is connected to the output end of the second buffer, and the other end of the S4 switch is respectively One end of the capacitor C3, one end of the S3 switch, and the output Ramp_boost signal end are connected, the other end of the S3 switch is connected to the bias current i_bias, the other end of the bias current i_bias is grounded, and the other end of the capacitor C3 is grounded.
  • the bias current i_bias and the reference voltage Vref can be generated by a dedicated bias current module and a reference module of the DC converter system.
  • the analysis is based on the ideal design principle, but there will be an offset voltage in the actual circuit design.
  • the offset voltage between Buf 1 and Buf 2, PWM1 and PWM2 are compared. Offset voltages between the devices, as well as inconsistencies in logic transfer delays, can affect the offset of the final system mode switching point. These unavoidable offset voltages can be improved by trimming.
  • an adjustable offset voltage can be added to Buf 1 to compensate for the offset of the entire system by adjusting the offset voltage to make the final system.
  • the mode switch point is truly continuous.
  • this offset voltage can be adjusted after the final test of the chip through the final system-level test, or it can be dynamically adjusted by logic to determine the state of the system's operating mode.
  • FIG. 6 is a schematic diagram of a hardware of a signal control module according to an embodiment of the present invention.
  • a dotted-line frame is a single-stage differential amplifying circuit structure, and a signal control module is input through the input of the single-stage differential amplifier.
  • the source stages of the tubes M1 and M2 increase or decrease the resistance to adjust the magnitude of the offset voltage, which is controlled by a digital control signal.
  • the digital control signal can be obtained by testing the slope signal or by loop feedback through a digital algorithm.
  • the MOS transistor connected to Vref and the MOS transistor corresponding to the right side are referred to as input pair transistors, which are denoted as M1 and M2, respectively.
  • the digital control signal tests the ramp signal and performs calculation according to the test result, thereby giving a set of control signals of the overlap or gap size of the Ramp_buck and Ramp_boost signals that need to be adjusted.
  • 6 is a buffer circuit of a P-type input-to-tube operational mode, and if it is a simple level shift-type driving circuit, the hardware schematic of the signal control module can be as shown in FIG.
  • FIG. 7 is another schematic diagram of a hardware of a signal control module according to an embodiment of the present invention.
  • FIG. 7 is a simple level conversion circuit for implementing a buffer circuit function, and a basic level conversion circuit is shown in a dashed box.
  • the basic level shifting circuit is composed of a PMOS transistor M1 and an NMOS transistor M2.
  • the output voltage is equal to the reference voltage Vref plus the Vgs of M1 minus the Vgs of M2, also by adjusting the resistors r1, r2, rN.
  • the digital control signal is to test the ramp signal, and calculate according to the test result, so that the Ramp_buck and Ramp_boost signals that need to be adjusted overlap or A set of control signals for the gap size.
  • circuit design of the signal control module is not limited to the several implementation modes listed above, and will not be enumerated here.
  • FIG. 8 is a schematic flowchart of a method for implementing a DC converter according to an embodiment of the present invention. As shown in FIG. 8 , the method includes the following steps:
  • Step 801 Generate a first type of ramp signal and a second type of ramp signal by using the same signal generating module; wherein the first type of ramp signal is used to put the DC converter in a buck mode, the second type of ramp a signal for causing the DC converter to be in a boost mode of operation;
  • Step 802 Adjust the first type of ramp signal and the second type of ramp signal according to a preset algorithm, so that a gap between the first type of ramp signal and the second type of ramp signal generated by the signal generating module meets a preset condition. .
  • the preset condition may be that there is no gap, or the size of the gap is less than or equal to the first threshold.
  • the first threshold may be set according to actual conditions.
  • the adjusting the first type of the ramp signal and the second type of the ramp signal according to the preset algorithm may include:
  • the adjusting the first type of the ramp signal and the second type of the ramp signal according to the preset algorithm may include:
  • a digital control signal is generated according to the acquired offset voltage value to control the signal generating module to generate a first type of ramp signal and a second type of ramp signal that satisfy a preset condition.
  • the loop may be a monitoring loop in the prior art, and details are not described herein again.
  • the adjusting the first type of the ramp signal and the second type of the ramp signal according to the preset algorithm may include:
  • N is a positive integer greater than or equal to 1;
  • a digital control signal is generated by controlling the opening or closing of a switch that matches the electrical N resistance to add an offset voltage.
  • the generating the first type of ramp signal and the second type of ramp signal by using the same signal generating module may include:
  • the reference voltage and the offset voltage value are buffered.
  • the generating the first type of ramp signal and the second type of ramp signal by using the same signal generating module may include:
  • a first type of ramp signal and a second type of ramp signal are generated based on the buffered reference voltage and the offset voltage value.
  • the embodiment of the invention further describes a computer storage medium, wherein the computer storage medium stores a computer program, and the computer program is used to execute the DC converter implementation method shown in FIG. 8 in the embodiment of the invention.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative, examples
  • the division of the unit is only a logical function division, and the actual implementation may have another division manner, for example, multiple units or components may be combined, or may be integrated into another system, or some features may be ignored. Or not.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing storage device includes the following steps:
  • the foregoing storage medium includes: a removable storage device, a read-only memory (ROM), a magnetic disk, or an optical disk, and the like, which can store program codes.
  • the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a mobile storage device, a ROM, a magnetic disk, or an optical disk.
  • the first type of ramp signal and the second type of ramp signal are generated by using the same signal generating module, wherein the first type of ramp signal is used to put the DC converter in a step-down working mode, a second type of ramp signal for causing the DC converter to be in a boost mode of operation; adjusting the first type of ramp signal and the second type of ramp signal according to a preset algorithm to cause the first type of ramp generated by the signal generating module
  • the gap between the signal and the second type of ramp signal satisfies a preset condition; thus, a seamless connection between the boost type ramp signal and the step-down ramp signal can be realized, and the effect of continuously converting the Buck mode and the Boost mode is achieved.
  • the gap between the boost ramp signal and the buck ramp signal can be controlled as needed, which greatly simplifies the complexity of the circuit design.

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Abstract

一种直流转换器、直流转换器实现方法及计算机存储介质。其中直流转换器包括：信号产生模块（11），配置为基于基准电压产生第一类斜坡信号和第二类斜坡信号；其中，第一类斜坡信号用于使直流转换器处于降压工作模式，第二类斜坡信号用于使直流转换器处于升压工作模式；信号控制模块（12），配置为根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，以使第一类斜坡信号和第二类斜坡信号之间的空隙满足预设条件。

Description

一种直流转换器、实现方法及计算机存储介质 技术领域
本发明涉及电子电路技术领域，具体涉及一种直流转换器及其实现方法、计算机存储介质。
背景技术
随着电子技术的发展，电子产品越来越普及。如何提高电池的利用率，延长电子产品的使用时间，也越来越受到人们的关注。
目前，能够同时实现升压降压功能的拓扑结构主要有升降压(Buck/Boost)拓扑结构、单端初级电感变换(SEPIC，Single Ended Primary Inductor Converter)、ZETA拓扑结构、库克(Cuk)拓扑结构以及四开关控制结构。其中，Buck/Boost拓扑结构以及Cuk拓扑结构虽然能够实现升降压功能，但是这两种拓扑结构的输入输出电压极性相反，因而不便于应用于便携式电子产品中。SEPIC拓扑结构以及ZETA拓扑结构虽然在实现升降压变换的基础上同时又实现了输入输出电压的同向变化，但是考虑这两种拓扑结构要用到多个大的电感、电容，因而整体电路的体积和成本没有优势，在现在的消费电子市场中也是不太适用的。四开关控制结构是基于单电感的拓扑结构，通过控制四个开关管的开启关断来实现系统的升压或者降压调制，它简单地将独立的降压(Buck)和升压(Boost)架构巧妙的结合起来，同时比较简单的实现了内部同步整流技术设计，对于经常使用独立的Buck和Boost架构的设计人员来说更加容易理解。但是，现有的四开关控制模式的升降压转换器至少存在如下问题：随着输入电压变化或输出电压变化，系统在buck模式或boost模式相互转换时的连续性较差。
发明内容
有鉴于此，本发明实施例期望提供一种直流转换器、实现方法及计算机存储介质，能很好地实现Buck模式和Boost模式之间的连续切换，简化电路设计的复杂程度。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种直流转换器，所述直流转换器包括：
信号产生模块，配置为基于基准电压产生第一类斜坡信号和第二类斜坡信号；其中，所述第一类斜坡信号用于使所述直流转换器处于降压工作模式，所述第二类斜坡信号用于使所述直流转换器处于升压工作模式；
信号控制模块，配置为根据预设算法对所述第一类斜坡信号和所述第二类斜坡信号进行调节，以使所述第一类斜坡信号和所述第二类斜坡信号之间的空隙满足预设条件。
上述方案中，所述信号控制模块，还配置为：
通过系统测试结果获取失调电压值；
根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
上述方案中，所述信号控制模块，还配置为：
利用环路实时监测系统的工作状态，以获取失调电压值；
根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
上述方案中，所述信号控制模块，包括：
N组电阻，其中，每一组电阻均有与所述电阻相匹配的开关，所述N组电阻并行连接；其中，N为大于等于1的正整数；
通过控制与所述电N阻相匹配的开关的打开或关闭产生数字控制信号，以向所述信号产生模块加入失调电压。
上述方案中，所述信号产生模块包括：
缓存模块，配置为对基准电压以及失调电压值进行缓存。
上述方案中，所述信号产生模块，还配置为：
基于所述缓存模块缓存的基准电压以及失调电压值产生第一类斜坡信号和第二类斜坡信号。
本发明实施例还提供一种直流转换器实现方法，所述方法包括：
利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号；其中，所述第一类斜坡信号用于使所述直流转换器处于降压工作模式，所述第二类斜坡信号用于使所述直流转换器处于升压工作模式。
根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，以使所述信号产生模块产生的第一类斜坡信号和第二类斜坡信号之间的空隙满足预设条件。
上述方案中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，包括：
通过系统测试结果获取失调电压值；
根据所获取的失调电压值产生数字控制信号，以控制产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
上述方案中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，包括：
利用环路实时监测系统的工作状态，以获取失调电压值；
根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
上述方案中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，包括：
设置N组电阻，其中，每一组电阻均有与所述电阻相匹配的开关，所 述N组电阻并行连接；其中，N为大于等于1的正整数；
通过控制与所述电N阻相匹配的开关的打开或关闭产生数字控制信号，以加入失调电压。
上述方案中，所述利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号，包括：
对基准电压以及失调电压值进行缓存。
上述方案中，所述利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号，包括：
基于所缓存的基准电压以及失调电压值产生第一类斜坡信号和第二类斜坡信号。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机程序，所述计算机程序用于执行以上所述的直流转换器实现方法。
本发明实施例提供的直流转换器、实现方法及计算机存储介质，能够实现升压型斜坡信号和降压型斜坡信号之间的无缝连接，达到了连续的转换Buck模式和Boost模式的效果，同时，又可以根据需要控制升压型斜坡信号和降压型斜坡信号之间的空隙，大大简化了电路设计的复杂程度。
具体地，本发明实施例所述技术方案，采用四开关控制的升降压拓扑结构，与普通的升降压拓扑结构相比，它能够实现电压的同向转换，且系统设计成本也更低。由于采用了改进型斜坡信号，可以工作在宽电压输入范围下，使Buck模式和Boost模式相互转换的过程更加流畅、完整，并且，使斜坡信号产生模块设计更加简单、方便。
附图说明
图1为本发明实施例提供的直流转换器的组成结构示意图；
图2为本发明实施例提供的四开关控制模式的直流转换器的系统框图；
图3为本发明实施例提供的斜坡信号的示意图；
图4为本发明实施例提供的信号产生模块的一种硬件示意图；
图5为本发明实施例提供的信号产生模块的另一种硬件示意图；
图6为本发明实施例提供的信号控制模块的一种硬件示意图；
图7为本发明实施例提供的信号控制模块的另一种硬件示意图；
图8为本发明实施例提供的直流转换器实现方法的流程示意图。
具体实施方式
下面结合附图和具体实施例对本发明的技术方案进一步详细阐述。
本发明所述直流转换器为升降压型DC-DC转换器，既具有升压功能，也具有降压功能。在本发明所述的以下各实施例中，PWM是Pulse-Width Modulation的英文缩写，其中文名称是“脉宽调制”；时钟信号用“CLK信号”表示。
实施例一
图1为本发明实施例提供的直流转换器的组成结构示意图，如图1所示，所述直流转换器主要包括：
信号产生模块11，配置为基于基准电压产生第一类斜坡信号和第二类斜坡信号；其中，所述第一类斜坡信号用于使所述直流转换器处于降压工作模式，所述第二类斜坡信号用于使所述直流转换器处于升压工作模式；
信号控制模块12，配置为根据预设算法对所述第一类斜坡信号和所述第二类斜坡信号进行调节，以使所述第一类斜坡信号和所述第二类斜坡信号之间的空隙满足预设条件。
在一具体子实施例中，所述信号控制模块12，还配置为：
通过系统测试结果获取失调电压值；
根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
在一具体子实施例中，所述信号控制模块12，还配置为：
利用环路实时监测系统的工作状态，以获取失调电压值；
根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
这里，所述环路可以是现有技术中的监测环路，在此不再赘述。
在一具体子实施例中，所述信号控制模块12，包括：
N组电阻，其中，每一组电阻均有与所述电阻相匹配的开关，所述N组电阻并行连接；其中，N为大于等于1的正整数；
通过控制与所述电N阻相匹配的开关的打开或关闭产生数字控制信号，以向所述信号产生模块加入失调电压。
在一具体子实施例中，所述信号产生模块11，包括：
缓存模块，配置为对基准电压以及失调电压值进行缓存。
在一具体子实施例中，所述信号产生模块11，还配置为：
基于所述缓存模块缓存的基准电压以及失调电压值产生第一类斜坡信号和第二类斜坡信号。
这里，所述预设条件可以是没有空隙、或者空隙的大小小于等于第一阈值。其中，所述第一阈值可以根据实际情况进行设定。
本发明实施例提供的直流转换器，能够实现升压型斜坡信号和降压型斜坡信号之间的无缝连接，达到了连续的转换Buck模式和Boost模式的效果，同时，又可以根据需要控制升压型斜坡信号和降压型斜坡信号之间的空隙。
实施例二
图2为本发明实施例提供的四开关控制模式的直流转换器的系统框图，如图2所示，所述系统框图主要包括几大模块：
与降压(Buck)模式对应的第一PWM比较器模块(在图中用PWM 1 表示)、第一驱动模块(在图中用驱动模块1表示)，与升压(Boost)模式对应的第二PWM比较器模块(在图中用PWM 2表示)、第二驱动模块(在图中用驱动模块2表示)，功率管模块，电流采样模块，反馈环路部分的反馈采样模块，误差放大模块，逻辑控制模块，信号产生模块和信号控制模块。
具体地，所述反馈采样模块包括电阻R1与R2；所述误差放大模块包括采用电压环运放进行误差放大的第一运算放大器(在图中用VA表示)，以及采用电流环运放进行误差放大的第二运算放大器(在图中用CA表示)；其中，Vva是第一运算放大器的输出电压，Vca是第二运算放大器的输出电压，Vrs表示电流采样模块的采样值，Vref是基准电压。
具体地，所述功率管模块包括：与第一驱动模块对应的第一组功率管、与第二驱动模块对应的第二组功率管；
其中，所述第一组功率管包括位于所述第一驱动模块上方的功率管a(简称“上管”)、以及另一个功率管b；所述第二组功率管包括位于所述第二驱动模块上方的功率管a(简称“上管”)、以及另一个功率管b。
可选地，所述第一组功率管的功率管a与所述第二组功率管的功率管a通过一电感相连接。
具体地，所述信号控制模块与信号产生模块的第一端相连接；所述信号产生模块的第二端与第一PWM比较器模块的第一输入端相连接，所述信号产生模块的第三端与第二PWM比较器模块的第一输入端相连接；所述第一PWM比较器模块的第二输入端与第二运算放大器的输出端相连接，所述第二PWM比较器模块的第二输入端也与第二运算放大器的输出端相连接；所述第二运算放大器的同相输入端与电流采样模块的输出端相连接；所述第二运算放大器的反相输入端与第一运算放大器的输出端相连接；所述第一运算放大器的同相输入端与基准电压(Vref)相连接，所述第一运算放大 器的反相输入端与反馈电压(Vfb)相连接；所述第一PWM比较器模块的输出端以及所述第二PWM比较器模块的输出端分别与逻辑控制模块的输入端相连接；所述逻辑控制模块的两个输出端分别与第一驱动模块和第二驱动模块相连接；所述逻辑控制模块与振荡器相连接。
在图2中，Vin是整个直流转换器系统的输入电压，Vout是指整个直流转换器系统的输出电压；Vva是第一运算放大器的输出电压，Vca是第二运算放大器的输出电压，Vrs表示电流采样模块的采样值，Vref是基准电压。
需要说明的是，图2所示系统框图采用的是平均电流模的控制方式，以下各实施例也都是基于图2所示的系统框图进行说明的，但本发明的使用范围不仅限于此，它也可以用于电压模、峰值电流模等控制方式，在此不再一一详细说明。
实施例三
图3为本发明实施例提供的斜坡信号的示意图，如图3所示，上半部分属于降压型斜坡信号(可用Ramp_buck信号来表示)，下半部分属于升压型斜坡信号(可用Ramp_boost信号来表示)。
当CLK信号触发时，Ramp_buck信号和Ramp_boost信号同时被拉回Vref电压，然后分别以相同的速度上升和下降，直到下一个CLK触发信号到来。
Ramp_buck信号和Ramp_boost信号由同一个模块电路产生，即均由信号产生模块产生，这样可以保证使用相同的Vref电压，进而保证Ramp_buck信号和Ramp_boost信号之间非常好地连接在一起，避免了因信号交叠或空隙的产生而引起降压模式(buck模式)和升压模式(boost模式)相互切换不连续性的问题。
从图3可以看出，当误差放大模块的输出电压等于Vref时，系统工作在降压模式的100％占空比，或者说是升压模式的0％占空比，此时，降压 拓扑结构的上管和升压拓扑结构的上管同时常开。当误差放大模块的输出电压上升时，系统进入降压模式，电压越高，降压工作占空比越小；当误差放大模块的输出电压下降时，系统进入升压模式，电压越高，升压工作占空比越大。
实施例四
图4为本发明实施例提供的信号产生模块的一种硬件示意图，如图4所示，信号产生模块引入了第一缓存器(在图中用Buf 1表示)、第二缓存器(在图中用Buf 2表示)，同时，还包括用于产生Ramp_buck信号的第一电路、用于产生Ramp_boost信号的第二电路。
具体地，所述第一电路包括2个电容，分别记为C1、C2；3个S1开关、3个S2开关；其中，第一个S1开关的一端与第一缓存器的输出端相连接，第一个S1开关的另一端分别与电容C2的一端、第二个S2开关的一端、第三个S2开关的一端相连接，第三个S2开关的另一端与偏置电流i_bias相连；第二个S2开关的另一端输出Ramp_buck信号，电容C2的另一端接地；同理，第一个S2开关的一端与第一缓存器的输出端相连接，第一个S2开关的另一端分别与电容C1的一端、第二个S1开关的一端、第三个S1开关的一端相连接，第三个S1开关的另一端与偏置电流i_bias相连接，第二个S1开关的另一端输出Ramp_buck信号，电容C1的另一端接地。
其中，第一个S1开关在图中用S1(1)表示，第二个S1开关在图中用S1(2)表示，第三个S1开关在图中用S1(3)表示；第一个S2开关在图中用S2(1)表示，第二个S2开关在图中用S2(2)表示，第三个S2开关在图中用S2(3)表示。
具体地，所述第二电路包括2个电容，分别记为C3、C4；3个S3开关、3个S4开关；其中，第一个S3开关的一端与第二缓存器的输出端相连接，第一个S3开关的另一端分别与电容C4的一端、第二个S4开关的一端、第 三个S4开关的一端相连接，第三个S4开关的另一端与偏置电流i_bias相连，偏置电流i_bias的另一端接地；第二个S4开关的另一端输出Ramp_boost信号，电容C4的另一端接地；同理，第一个S4开关的一端与第二缓存器的输出端相连接，第一个S4开关的另一端分别与电容C3的一端、第二个S3开关的一端、第三个S3开关的一端相连接，第三个S3开关的另一端与偏置电流i_bias相连接，偏置电流i_bias的另一端接地；第二个S3开关的另一端输出Ramp_buck信号；电容C3的另一端接地。
其中，第一个S3开关在图中用S3(1)表示，第二个S3开关在图中用S3(2)表示，第三个S3开关在图中用S1(3)表示；第一个S4开关在图中用S4(1)表示，第二个S4开关在图中用S2(2)表示，第三个S4开关在图中用S4(3)表示。
当CLK的触发沿到来时，S1和S3同时打开，S2和S4同时关断，Buf 1和Buf 2驱动电容C1和电容C3，使其电压都等于Vref。当下一个CLK触发沿到来时，S2和S4同时打开，S1和S3同时关断，Buf 1和Buf 2驱动电容C2和电容C4，使其电压等于Vref，此时，电容C1和电容C3已经分别开始被偏置电流(可用i_bias表示)充电和放电，由于电流相等，电容相等，所以电容C1和电容C3上的电压变化速度也相等。如此反复，这样交替切换充放电电容的方式，相当于给了缓存器和电容一个时钟周期的时间用来稳定电压，可以防止在切换瞬间电压还没有稳定就开始继续使用，能避免因Ramp_buck信号与Ramp_boost信号的中间电压不相等而导致模式切换不连续。
这里，所述触发沿既可以是上升沿、也可以是下降沿。
需要说明的是，在信号产生模块的设计实现中，不仅仅限于某一种电路形式，比如，可以根据基准电压Vref的高低，设计成不同共模输入电压的驱动电路；也可以根据面积成本的要求，设计成简单的电位转换(level  shift)形式的驱动电路或是精度要求更高的驱动电路；也可以根据工艺的要求，设计成互补金属氧化物半导体(CMOS，Complementary Metal-Oxide-Semiconductor Transistor)或是双极性(Bipolar)的驱动电路，在此不再一一详细说明。
实施例五
在开关控制电容充放电的电路实现中，在低频率应用条件下，允许电容充放电后稳定的时间更长，也可以使用单个电容充放电电路，即每个周期都是用同一个电容来进行充放电，不用进行两个电容的轮流使用，具体实现如图5所示。
图5为本发明实施例提供的信号产生模块的另一种硬件示意图，如图5所示，信号产生模块引入了第一缓存器(在图中用Buf 1表示)、第二缓存器(在图中用Buf 2表示)，同时，还包括用于产生Ramp_buck信号的第三电路、用于产生Ramp_boost信号的第四电路。
具体地，所述第三电路包括1个电容，记为C1，1个S1开关、1个S2开关；其中，S2开关的一端与第一缓存器的输出端相连接，S2开关的另一端分别与电容C1的一端、S1开关的一端、输出Ramp_buck信号端相连接，电容C1的另一端接地；S1的另一端与偏置电流i_bias相连。
具体地，所述第四电路包括1个电容，记为C3，1个S3开关、1个S4开关；其中，S4开关的一端与第二缓存器的输出端相连接，S4开关的另一端分别与电容C3的一端、S3开关的一端、输出Ramp_boost信号端相连接，S3开关的另一端与偏置电流i_bias相连，偏置电流i_bias的另一端接地；电容C3的另一端接地。
这里，偏置电流i_bias和基准电压Vref可以由直流转换器系统专门的偏置电流模块和基准模块产生。
实施例六
在以上的设计考虑中，都是以理想的设计原理分析的，但在实际电路设计中肯定会有失调电压的产生，例如，Buf 1和Buf 2之间的失调电压、PWM1和PWM2两个比较器之间的失调电压、还有逻辑传输延迟的不一致等都会影响到最终系统模式切换点的失调。这些不可避免的失调电压都可以通过修调来改善，在信号产生模块中，可以在Buf 1处加入一个可以调节的失调电压，通过这个失调电压的调整来补偿整个系统的失调，使最终的系统模式切换点真正实现连续。当然，这个失调电压可以通过最终系统级的测试在芯片最终测试后修调，也可以通过逻辑判断系统工作模式的状态来动态的调整。
图6为本发明实施例提供的信号控制模块的一种硬件示意图，如图6所示，虚线框中是一个单级差分放大电路结构，信号控制模块是通过在这个单级差分放大器的输入对管M1和M2的源级加大或减小电阻的方式来调节失调电压的大小，电阻的增加或减小是通过数字控制(Digital Control)信号来控制的。而数字控制信号可以通过对斜坡信号的测试结果得到，也可以通过数字算法的方式通过环路反馈得到。
具体地，在图6中，与Vref连接的MOS管和右边与之对应的MOS管，被称为输入对管，分别记为M1和M2。
具体地，该数字控制信号是对斜坡信号进行测试，根据测试结果进行计算，从而给出需要进行调整的Ramp_buck和Ramp_boost信号交叠或间隙大小的一组控制信号。
实施例七
在信号控制模块的电路实现时，需要根据信号产生模块电路实现方式的不同，给予相应的实现电路设计。图6是P型输入对管的运放形式的缓存电路，而如果是简单的level shift形式的驱动电路，信号控制模块的硬件示意图可如图7所示。
图7为本发明实施例提供的信号控制模块的另一种硬件示意图，如图7所示，图7是利用简单的电平转换电路来实现缓存电路功能，虚线框中为基本电平转换电路，所述基本电平转换电路是由一个PMOS管M1和一个NMOS管M2组合，输出电压等于基准电压Vref加上M1的Vgs再减去M2的Vgs，同样是通过调节电阻r1、r2、rN的组合大小来调节失调电压，而数字控制信号与图6中一样，即：该数字控制信号是对斜坡信号进行测试，根据测试结果进行计算，从而给出需要进行调整的Ramp_buck和Ramp_boost信号交叠或间隙大小的一组控制信号。
需要说明的是，所以信号控制模块的电路设计也不仅限于以上列举的几种实现方式，在此不再一一列举。
实施例八
图8为本发明实施例提供的直流转换器实现方法的流程示意图，如图8所示，该方法包括以下步骤：
步骤801：利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号；其中，所述第一类斜坡信号用于使所述直流转换器处于降压工作模式，所述第二类斜坡信号用于使所述直流转换器处于升压工作模式；
步骤802：根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，以使所述信号产生模块产生的第一类斜坡信号和第二类斜坡信号之间的空隙满足预设条件。
其中，所述预设条件可以是没有空隙、或者空隙的大小小于等于第一阈值。其中，所述第一阈值可以根据实际情况进行设定。
上述方案中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，可以包括：
通过系统测试结果获取失调电压值；
根据所获取的失调电压值产生数字控制信号，以控制产生满足预设条 件的第一类斜坡信号和第二类斜坡信号。
上述方案中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，可以包括：
利用环路实时监测系统的工作状态，以获取失调电压值；
根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
这里，所述环路可以是现有技术中的监测环路，在此不再赘述。
上述方案中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，可以包括：
设置N组电阻，其中，每一组电阻均有与所述电阻相匹配的开关，所述N组电阻并行连接；其中，N为大于等于1的正整数；
通过控制与所述电N阻相匹配的开关的打开或关闭产生数字控制信号，以加入失调电压。
上述方案中，所述利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号，可以包括：
对基准电压以及失调电压值进行缓存。
上述方案中，所述利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号，可以包括：
基于所缓存的基准电压以及失调电压值产生第一类斜坡信号和第二类斜坡信号。
本发明实施例还记载一种计算机存储介质，所述计算机存储介质中存储有计算机程序，所述计算机程序用于执行本发明实施例中图8所示的直流转换器实现方法。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例 如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本发明上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：移动存储设备、ROM、磁碟或者光盘等各 种可以存储程序代码的介质。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明实施例中，利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号；其中，所述第一类斜坡信号用于使所述直流转换器处于降压工作模式，所述第二类斜坡信号用于使所述直流转换器处于升压工作模式；根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，以使所述信号产生模块产生的第一类斜坡信号和第二类斜坡信号之间的空隙满足预设条件；如此，能够实现升压型斜坡信号和降压型斜坡信号之间的无缝连接，达到了连续的转换Buck模式和Boost模式的效果，同时，又可以根据需要控制升压型斜坡信号和降压型斜坡信号之间的空隙，大大简化了电路设计的复杂程度。

Claims (13)

  1. 一种直流转换器，所述直流转换器包括：
    信号产生模块，配置为基于基准电压产生第一类斜坡信号和第二类斜坡信号；其中，所述第一类斜坡信号用于使所述直流转换器处于降压工作模式，所述第二类斜坡信号用于使所述直流转换器处于升压工作模式；
    信号控制模块，配置为根据预设算法对所述第一类斜坡信号和所述第二类斜坡信号进行调节，以使所述第一类斜坡信号和所述第二类斜坡信号之间的空隙满足预设条件。
  2. 根据权利要求1所述的直流转换器，其中，所述信号控制模块，还配置为：
    通过系统测试结果获取失调电压值；
    根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
  3. 根据权利要求1所述的直流转换器，其中，所述信号控制模块，还配置为：
    利用环路实时监测系统的工作状态，以获取失调电压值；
    根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
  4. 根据权利要求1所述的直流转换器，其中，所述信号控制模块，包括：
    N组电阻，其中，每一组电阻均有与所述电阻相匹配的开关，所述N组电阻并行连接；其中，N为大于等于1的正整数；
    通过控制与所述电N阻相匹配的开关的打开或关闭产生数字控制信号，以向所述信号产生模块加入失调电压。
  5. 根据权利要求1所述的直流转换器，其中，所述信号产生模块包括：
    缓存模块，配置为对基准电压以及失调电压值进行缓存。
  6. 根据权利要求5所述的直流转换器，其中，所述信号产生模块，还配置为：
    基于所述缓存模块缓存的基准电压以及失调电压值产生第一类斜坡信号和第二类斜坡信号。
  7. 一种直流转换器实现方法，所述方法包括：
    利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号；其中，所述第一类斜坡信号用于使所述直流转换器处于降压工作模式，所述第二类斜坡信号用于使所述直流转换器处于升压工作模式；
    根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，以使所述信号产生模块产生的第一类斜坡信号和第二类斜坡信号之间的空隙满足预设条件。
  8. 根据权利要求7所述的方法，其中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，包括：
    通过系统测试结果获取失调电压值；
    根据所获取的失调电压值产生数字控制信号，以控制产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
  9. 根据权利要求7所述的方法，其中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，包括：
    利用环路实时监测系统的工作状态，以获取失调电压值；
    根据所获取的失调电压值产生数字控制信号，以控制所述信号产生模块产生满足预设条件的第一类斜坡信号和第二类斜坡信号。
  10. 根据权利要求7所述的方法，其中，所述根据预设算法对第一类斜坡信号和第二类斜坡信号进行调节，包括：
    设置N组电阻，其中，每一组电阻均有与所述电阻相匹配的开关，所 述N组电阻并行连接；其中，N为大于等于1的正整数；
    通过控制与所述电N阻相匹配的开关的打开或关闭产生数字控制信号，以加入失调电压。
  11. 根据权利要求8所述的方法，其中，所述利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号，包括：
    对基准电压以及失调电压值进行缓存。
  12. 根据权利要求11所述的方法，其中，所述利用同一信号产生模块产生第一类斜坡信号和第二类斜坡信号，包括：
    基于所缓存的基准电压以及失调电压值产生第一类斜坡信号和第二类斜坡信号。
  13. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求7至12任一项所述的方法。
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Publication number Priority date Publication date Assignee Title
CN112689947A (zh) * 2018-09-13 2021-04-20 微芯片技术股份有限公司 四开关、单电感器、非反相的降压-升压转换器的控制
CN114221543A (zh) * 2021-11-25 2022-03-22 西安领充创享新能源科技有限公司 H桥四开关电路的控制方法及双向充放电装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11183935B2 (en) * 2019-03-14 2021-11-23 Microchip Technology Incorporated Current control for buck-boost converters using conditional offsets

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1578083A (zh) * 2003-07-08 2005-02-09 罗姆股份有限公司 升压/降压直流－直流转换器及使用其的便携设备
CN102694469A (zh) * 2012-05-21 2012-09-26 成都芯源系统有限公司 直流-直流电压转换器
WO2014089116A1 (en) * 2012-12-03 2014-06-12 Mindspeed Technologies, Inc. Automatic buck/boost mode selection system for dc-dc converter
US20150054478A1 (en) * 2012-06-04 2015-02-26 Texas Instruments Deutschland Gmbh Electronic device for average current mode dc-dc conversion

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103178711A (zh) * 2011-12-23 2013-06-26 联芯科技有限公司 升降压直流变换电路
CN102810984B (zh) * 2012-07-13 2015-01-07 电子科技大学 一种开关电源电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1578083A (zh) * 2003-07-08 2005-02-09 罗姆股份有限公司 升压/降压直流－直流转换器及使用其的便携设备
CN102694469A (zh) * 2012-05-21 2012-09-26 成都芯源系统有限公司 直流-直流电压转换器
US20150054478A1 (en) * 2012-06-04 2015-02-26 Texas Instruments Deutschland Gmbh Electronic device for average current mode dc-dc conversion
WO2014089116A1 (en) * 2012-12-03 2014-06-12 Mindspeed Technologies, Inc. Automatic buck/boost mode selection system for dc-dc converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112689947A (zh) * 2018-09-13 2021-04-20 微芯片技术股份有限公司 四开关、单电感器、非反相的降压-升压转换器的控制
CN112689947B (zh) * 2018-09-13 2024-04-19 微芯片技术股份有限公司 四开关、单电感器、非反相的降压-升压转换器的控制
CN114221543A (zh) * 2021-11-25 2022-03-22 西安领充创享新能源科技有限公司 H桥四开关电路的控制方法及双向充放电装置
CN114221543B (zh) * 2021-11-25 2024-05-24 西安领充创享新能源科技有限公司 H桥四开关电路的控制方法及双向充放电装置

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