WO2017000400A1 - 唤醒主mcu的电路、方法及装置 - Google Patents

唤醒主mcu的电路、方法及装置 Download PDF

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Publication number
WO2017000400A1
WO2017000400A1 PCT/CN2015/090602 CN2015090602W WO2017000400A1 WO 2017000400 A1 WO2017000400 A1 WO 2017000400A1 CN 2015090602 W CN2015090602 W CN 2015090602W WO 2017000400 A1 WO2017000400 A1 WO 2017000400A1
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Prior art keywords
peripheral interface
peripheral
chip
mcu
unit
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PCT/CN2015/090602
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English (en)
French (fr)
Inventor
孟德国
丁一
侯恩星
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小米科技有限责任公司
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Priority to KR1020167007390A priority Critical patent/KR20170012182A/ko
Priority to RU2016111925A priority patent/RU2643474C2/ru
Priority to JP2017525668A priority patent/JP6446548B2/ja
Priority to MX2016001783A priority patent/MX358065B/es
Publication of WO2017000400A1 publication Critical patent/WO2017000400A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4418—Suspend and resume; Hibernate and awake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21097—DMA
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/23—Pc programming
    • G05B2219/23319—Microprocessor control or manual control
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25279—Switch on power, awake device from standby if detects action on device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • the present disclosure relates to the field of devices, and more particularly to circuits, methods and apparatus for waking up a main MCU micro control unit.
  • the developer In the process of embedded system software development, in order to reduce the power consumption of the device and save energy, the developer will let the system enter the low power mode when idle, and the Microcontroller Unit (MCU) chip will enter. Sleep or deep sleep state. In the deep sleep state, the general MCU peripherals (such as serial peripheral interface SPI, universal asynchronous transmit and receive UART, analog-to-digital AD conversion unit) will not work properly, only external interrupts and timer interrupts can wake up the MCU. When other chips pass the serial port, they cannot communicate with the device MCU normally.
  • SPI serial peripheral interface
  • UART universal asynchronous transmit and receive UART
  • analog-to-digital AD conversion unit analog-to-digital AD conversion unit
  • the smart device system in order to reduce the power consumption of the smart device as much as possible and utilize energy efficiently, the smart device system enters a low power mode when idle. You can choose to let the MCU enter a light sleep or deep sleep (standby standby / hibrnate hibernation). When the MCU enters deep sleep mode, the main clock will stop working. Some internal peripherals (such as UART unit, SPI unit, ICC bus unit I2C unit, A/D unit, pulse width modulation PWM unit, etc.) depend on The main MCU clock will also not work. In this way, the main MCU will not be able to receive data sent by other chips to it through the UART unit, SPI unit, I2C unit, etc. in time.
  • the embodiments of the present disclosure provide a circuit, a method, and a device for waking up a main MCU, so that the main MCU of the device can wake up and send and receive data in time after entering deep sleep.
  • a circuit for waking up a main MCU comprising:
  • a main micro control unit MCU a peripheral interface chip, and a peripheral processing chip
  • the peripheral processing chip is connected to the main MCU through the peripheral interface chip;
  • the clock line of the main MCU is connected to the main clock signal; the clock line of the peripheral processing chip and the clock line of the peripheral interface chip are respectively connected to the slave clock signal, so that when the main MCU enters a deep sleep state, , said The peripheral processing chip and the peripheral interface chip maintain a normal working state;
  • the peripheral interface chip is configured to monitor data amount of data sent by the peripheral processing chip to the peripheral interface chip, and when the data amount exceeds a threshold, the peripheral interface chip is sent to the main MCU Send a wake-up signal.
  • the peripheral interface chip sends a wake-up signal to the primary MCU, including:
  • the peripheral interface chip transmits a wake-up signal in a manner of transmitting an interrupt signal to the main MCU.
  • the peripheral processing chip and the peripheral interface chip maintain a normal working state, including:
  • the peripheral processing chip and the peripheral interface chip perform data transmission by directly accessing the DMA through the memory.
  • the peripheral interface chip is a universal asynchronous transceiver transmission UART unit, a serial peripheral interface SPI unit, an internal integrated circuit bus I2C unit, or a Bluetooth unit;
  • the peripheral processing chip is an analog/digital A/D unit, a pulse width modulation PWM unit, a video processing unit, or an audio processing unit.
  • the present disclosure also provides a method for waking up a main MCU, which is applied to a device including a main MCU, a peripheral interface chip, and a peripheral processing chip, wherein the method includes:
  • a wake-up signal is sent to the primary MCU.
  • the sending the wake-up signal to the primary MCU includes:
  • the wake-up signal is transmitted in such a manner as to send an interrupt signal to the main MCU.
  • the main MCU is configured to be in a deep sleep state
  • the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state, including:
  • the clock line of the main MCU is connected to the main clock signal
  • the main MCU is configured to be in a deep sleep state by controlling the main clock signal and the slave clock signal, and the peripheral processing chip and the peripheral interface chip are configured to operate normally.
  • the configuring the peripheral processing chip and the peripheral interface chip to be in a normal working state including:
  • the peripheral processing chip and the peripheral interface chip are configured to perform data transmission by directly accessing the DMA through the memory.
  • the peripheral interface chip is a universal asynchronous transceiver transceiver UART unit and a serial peripheral device.
  • the peripheral processing chip is an analog/digital A/D unit, a PWM pulse width modulation unit, a video processing unit, or an audio processing unit.
  • the present disclosure also provides an apparatus for waking up a main MCU, which is applied to a device including a main MCU, a peripheral interface chip, and a peripheral processing chip, the apparatus comprising:
  • a configuration module configured to configure the main micro control unit MCU to be in a deep sleep state, and configure the peripheral processing chip and the peripheral interface chip to be in a normal working state;
  • a monitoring module configured to monitor a data amount of data sent by the peripheral processing chip to the peripheral interface chip
  • a sending module configured to send a wake-up signal to the primary MCU when the amount of data exceeds a threshold.
  • the sending module is configured to: send a wake-up signal in a manner to send an interrupt signal to the main MCU.
  • the configuration module includes:
  • a first connection submodule configured to connect a clock line of the main MCU to a main clock signal
  • a second connection submodule configured to respectively connect a clock line of the peripheral processing chip and a clock line of the peripheral interface chip to a slave clock signal
  • control submodule configured to configure the main MCU and the peripheral interface chip to be in a normal working state by controlling the main clock signal and the slave clock signal to configure the main MCU to be in a deep sleep state.
  • the configuration module is configured to perform data transmission between the peripheral processing chip and the peripheral interface chip configured to directly access the DMA through the memory.
  • the peripheral interface chip is a universal asynchronous transceiver transmission UART unit, a serial peripheral interface SPI unit, an internal integrated circuit bus I2C unit, or a Bluetooth unit;
  • the peripheral processing chip is an analog/digital A/D unit, a PWM pulse width modulation unit, a video processing unit, or an audio processing unit.
  • the present disclosure also provides an apparatus for waking up a primary MCU, including:
  • a memory for storing processor executable instructions
  • processor is configured to:
  • a wake-up signal is sent to the primary MCU.
  • the clock line of the main MCU is connected to the main clock signal; the clock line of the peripheral processing chip and the clock line of the peripheral interface chip are respectively connected to the slave clock signal, the main MCU, the peripheral processing chip, and The clock line of the peripheral interface chip is connected to different clock signals. Therefore, when the main MCU enters a deep sleep state, the peripheral processing chip and the peripheral interface chip can maintain a normal working state; thus, when the peripheral processing chip to the peripheral interface chip After the data amount of the sent data exceeds the threshold, the peripheral interface chip sends a wake-up signal to the main MCU, so that the main MCU is woken up, and then the data is transmitted and received and processed. In this way, the main MCU of the device can wake up to send and receive data in time after entering deep sleep.
  • FIG. 1 is a schematic diagram of a circuit for waking up a main MCU, according to an exemplary embodiment.
  • FIG. 2 is a flow chart showing a method of waking up a primary MCU, according to an exemplary embodiment.
  • FIG. 3 is a flowchart of step S201 in a method for waking up a primary MCU, according to an exemplary embodiment.
  • FIG. 4 is a block diagram of an apparatus for waking up a primary MCU, according to an exemplary embodiment.
  • FIG. 5 is a block diagram of a configuration module in an apparatus for waking up a primary MCU, according to an exemplary embodiment.
  • FIG. 6 is a block diagram of an apparatus suitable for waking up a primary MCU, according to an exemplary embodiment.
  • a circuit for waking up a main MCU including: a main micro control unit MCU 11, a peripheral interface chip 12, and a peripheral processing chip 13 according to an exemplary embodiment;
  • the peripheral processing chip 13 is connected to the main MCU 11 through the peripheral interface chip 12;
  • the clock line of the main MCU 11 is connected to the main clock signal; the clock line of the peripheral processing chip 13 and the clock line of the peripheral interface chip 12 are respectively connected to the slave clock signal, so that when the main MCU 11 enters deep sleep In the state, the peripheral processing chip 13 and the peripheral interface chip 12 maintain a normal working state; the peripheral interface chip 12 is configured to monitor the amount of data sent by the peripheral processing chip 13 to the peripheral interface chip 12, when the amount of data exceeds Threshold Thereafter, the peripheral interface chip 12 sends a wake-up signal to the main MCU 11.
  • the clock line of the main MCU 11 is connected to the main clock signal; the clock line of the peripheral processing chip 13 and the clock line of the peripheral interface chip 12 are respectively connected to the slave clock signal, and the main MCU and the peripheral processing chip 13 are The clock line of the peripheral interface chip is connected to different clock signals. Therefore, when the main MCU 11 enters the deep sleep state, the peripheral processing chip 13 and the peripheral interface chip 12 can maintain a normal working state; thus, when the peripheral processing chip 13 gives After the data amount of the data sent by the peripheral interface chip 12 exceeds the threshold, the peripheral interface chip 12 sends a wake-up signal to the main MCU 11, so that after the main MCU is woken up, data is transmitted and received and processed. In this way, in this way, the main MCU of the device can wake up and send and receive data in time after entering deep sleep.
  • the peripheral interface chip is provided with a buffer, and the data that the peripheral processing chip prepares to send to the main MCU through the peripheral interface chip is first sent to the peripheral interface chip and stored in the buffer of the peripheral interface chip.
  • the peripheral interface chip sends a wake-up signal to the master MCU.
  • the peripheral interface chip sends a wake-up signal in a manner that sends an interrupt signal to the main MCU, so that the main MCU of the device can wake up and send and receive data in time after entering deep sleep.
  • the step may be: monitoring the amount of data sent by the peripheral processing chip to the peripheral interface chip. When the amount of data exceeds the threshold, the peripheral interface chip generates an interrupt signal and sends the interrupt signal to the main MCU to wake up the main MCU.
  • the peripheral processing chip and the peripheral interface chip can perform data transmission by means of direct memory access (DMA).
  • DMA mode is a high-speed data transfer operation that allows direct reading and writing of data between external devices and memory. It does not require CPU or CPU intervention. The entire data transfer operation is controlled by the "DMA controller", thus making the master The MCU can still perform data transmission between the peripheral processing chip and the peripheral interface chip in the deep sleep state.
  • the peripheral interface chip can be a universal asynchronous transceiver transmission UART unit, a serial peripheral interface SPI unit, an internal integrated circuit bus I2C unit, or a Bluetooth unit; the peripheral processing chip can be an analog/digital A/D unit, a pulse width A modulation PWM unit, a video processing unit, or an audio processing unit.
  • peripheral interface chip as a universal asynchronous transceiver transmission and transmission UART unit and a peripheral processing chip as an analog/digital A/D unit as an example.
  • a low-power circuit applied to a smart device can wake up to send and receive data when the device MCU enters deep sleep.
  • the circuit is an internal peripheral design structure independent of the main clock.
  • the internal peripheral UART unit and the analog/digital A/D unit have their own working clock independent of the main MCU, so that when the main MCU enters deep sleep mode, Configure the working status of a peripheral separately.
  • the UART module is configured to continue to maintain a normal working state after the main MCU enters deep sleep, and performs data transmission with the analog/digital A/D unit through the DMA method.
  • the UART controller wakes up the main MCU by sending an interrupt signal, so that the main MCU performs data transmission and reception and processing. In this way To ensure that the device can still receive data in the ultra low power mode.
  • FIG. 2 is a flowchart of a method for waking up a main MCU according to an exemplary embodiment. As shown in FIG. 2, the method for waking up a main MCU is used to include a main MCU, a peripheral interface chip, and a peripheral processing chip. Apparatus, the method comprising the following steps S201-S203:
  • step S201 the main micro control unit MCU is configured to be in a deep sleep state, and the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state;
  • step S202 monitoring the amount of data of the data sent by the peripheral processing chip to the peripheral interface chip
  • step S203 when the amount of data exceeds the threshold, a wake-up signal is sent to the main MCU.
  • This step may be: sending a wake-up signal to the primary MCU in an interrupted manner.
  • the main micro control unit MCU is configured to be in a deep sleep state, and the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state; when the peripheral processing chip sends data to the peripheral interface chip, the data amount exceeds After the threshold, a wake-up signal is sent to the primary MCU. In this way, the main MCU of the device can wake up to send and receive data after entering deep sleep.
  • the peripheral interface chip can be a universal asynchronous transceiver transmission UART unit, a serial peripheral interface SPI unit, an internal integrated circuit bus I2C unit, or a Bluetooth unit; the peripheral processing chip can be an analog/digital A/D unit, a PWM pulse. A wide modulation unit, a video processing unit, or an audio processing unit.
  • step S21 the method includes: configuring the peripheral processing chip and the peripheral interface chip to perform data transmission by directly accessing the DMA through the memory.
  • DMA mode is a high-speed data transfer operation that allows direct reading and writing of data between external devices and memory. It does not require CPU or CPU intervention. The entire data transfer operation is controlled by the "DMA controller", thus making the master The MCU can still perform data transmission between the peripheral processing chip and the peripheral interface chip in the deep sleep state.
  • step S201 includes:
  • step S2011 the clock line of the main MCU is connected to the main clock signal
  • step S0212 the clock line of the peripheral processing chip and the clock line of the peripheral interface chip are respectively connected to the slave clock signal
  • step S2013 the main MCU is configured to be in a deep sleep state by controlling the main clock signal and the slave clock signal, and the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state.
  • the clock line of the main MCU is connected to the main clock signal; the peripheral processing chip and the peripheral interface chip respectively access the slave clock signal, the clock line of the main MCU and the clock line and peripheral interface chip of the peripheral processing chip;
  • the clock line is connected to different clock signals, so when the main MCU enters a deep sleep state, the peripheral processing chip and the peripheral interface chip can be configured to remain in a normal working state.
  • FIG. 4 is a block diagram of an apparatus for waking up a primary MCU, as shown in FIG. 4, according to an exemplary embodiment.
  • the device for waking up the main MCU is applied to a device including a main MCU, a peripheral interface chip, and a peripheral processing chip, the device comprising:
  • the configuration module 41 is configured to configure the main micro control unit MCU to be in a deep sleep state, and configure the peripheral processing chip and the peripheral interface chip to be in a normal working state;
  • the monitoring module 42 is configured to monitor the amount of data of the data sent by the peripheral processing chip to the peripheral interface chip;
  • the sending module 43 is configured to send a wake-up signal to the main MCU after the amount of data exceeds the threshold. Wherein, the wake-up signal can be sent to the main MCU in an interrupted manner.
  • the main micro control unit MCU is configured to be in a deep sleep state, and the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state; when the peripheral processing chip sends data to the peripheral interface chip, the data amount exceeds After the threshold, a wake-up signal is sent to the primary MCU. In this way, the main MCU of the device can wake up to send and receive data after entering deep sleep.
  • the configuration module 41 is configured to perform data transmission between the peripheral processing chip and the peripheral interface chip configured to directly access the DMA through the memory.
  • DMA mode is a high-speed data transfer operation that allows direct reading and writing of data between external devices and memory. It does not require CPU or CPU intervention. The entire data transfer operation is controlled by the "DMA controller", thus making the master The MCU can still perform data transmission between the peripheral processing chip and the peripheral interface chip in the deep sleep state.
  • the configuration module 41 includes:
  • the first connection submodule 411 is configured to connect the clock line of the main MCU to the main clock signal
  • the second connection sub-module 412 is configured to respectively connect the clock line of the peripheral processing chip and the clock line of the peripheral interface chip to the slave clock signal;
  • the control sub-module 413 is configured to configure the main MCU to be in a deep sleep state by controlling the main clock signal and the slave clock signal, and configure the peripheral processing chip and the peripheral interface chip to operate normally.
  • the clock line of the main MCU is connected to the main clock signal; the clock line of the peripheral processing chip and the clock line of the peripheral interface chip are respectively connected to the slave clock signal, the clock line of the main MCU and the clock of the peripheral processing chip
  • the clock lines of the line and peripheral interface chips are connected to different clock signals. Therefore, when the main MCU enters a deep sleep state, the peripheral processing chip and the peripheral interface chip can maintain a normal working state.
  • the peripheral interface chip can be a universal asynchronous transceiver transmission UART unit, a serial peripheral interface SPI unit, an internal integrated circuit bus I2C unit, or a Bluetooth unit.
  • the peripheral processing chip can be an analog/digital A/D unit, a PWM pulse width modulation unit, a video processing unit, or an audio processing unit.
  • FIG. 6 is a block diagram of an apparatus 1200 for waking up a primary MCU, the apparatus being applicable to a terminal device, according to an exemplary embodiment.
  • device 1200 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a gaming console, a tablet device, a medical device, a fitness device, a personal digital assistant, and the like.
  • apparatus 1200 can include one or more of the following components: processing component 1202, memory 1204, power component 1206, multimedia component 1208, audio component 1210, input/output (I/O) interface 1212, sensor component 1214, And a communication component 1216.
  • Processing component 1202 typically controls the overall operation of device 1200, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations.
  • Processing component 1202 can include one or more processors 1220 to execute instructions to perform all or part of the steps of the above described methods.
  • processing component 1202 can include one or more modules to facilitate interaction between component 1202 and other components.
  • processing component 1202 can include a multimedia module to facilitate interaction between multimedia component 1208 and processing component 1202.
  • Memory 1204 is configured to store various types of data to support operation at device 1200. Examples of such data include instructions for any application or method operating on device 1200, contact data, phone book data, messages, pictures, videos, and the like.
  • the memory 1204 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Disk or Optical Disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read only memory
  • EPROM erasable Programmable Read Only Memory
  • PROM Programmable Read Only Memory
  • ROM Read Only Memory
  • Magnetic Memory Flash Memory
  • Disk Disk or Optical Disk.
  • Power component 1206 provides power to various components of device 1200.
  • Power component 1206 can include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for device 1200.
  • Multimedia component 1208 includes a screen between the device 1200 and a user that provides an output interface.
  • the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user.
  • the touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor may sense not only the boundary of the touch or sliding action, but also the duration and pressure associated with the touch or slide operation.
  • the multimedia component 1208 includes a front camera and/or a rear camera. When the device 1200 is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the rear camera can receive external multimedia data. Each front and rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.
  • the audio component 1210 is configured to output and/or input an audio signal.
  • audio component 1210 includes a microphone (MIC) that is configured to receive an external audio signal when device 1200 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode.
  • the received audio signal may be further stored in memory 1204 or transmitted via communication component 1216.
  • the audio component 1210 also includes a speakerphone For outputting audio signals.
  • the I/O interface 1212 provides an interface between the processing component 1202 and the peripheral interface module, which may be a keyboard, a click wheel, a button, or the like. These buttons may include, but are not limited to, a home button, a volume button, a start button, and a lock button.
  • Sensor assembly 1214 includes one or more sensors for providing status assessment of various aspects to device 1200.
  • sensor assembly 1214 can detect an open/closed state of device 1200, a relative positioning of components, such as the display and keypad of device 1200, and sensor component 1214 can also detect a change in position of one component of device 1200 or device 1200. The presence or absence of contact by the user with the device 1200, the orientation or acceleration/deceleration of the device 1200 and the temperature change of the device 1200.
  • Sensor assembly 1214 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact.
  • Sensor assembly 1214 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications.
  • the sensor assembly 1214 can also include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
  • Communication component 1216 is configured to facilitate wired or wireless communication between device 1200 and other devices.
  • the device 1200 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof.
  • the communication component 1216 receives broadcast signals or broadcast associated information from an external broadcast management system via a broadcast channel.
  • the communication component 1216 also includes a near field communication (NFC) module to facilitate short range communication.
  • NFC near field communication
  • the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
  • RFID radio frequency identification
  • IrDA infrared data association
  • UWB ultra-wideband
  • Bluetooth Bluetooth
  • device 1200 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable A gate array (FPGA), controller, microcontroller, microprocessor, or other electronic component implementation for performing the above methods.
  • ASICs application specific integrated circuits
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLDs programmable logic devices
  • FPGA field programmable A gate array
  • controller microcontroller, microprocessor, or other electronic component implementation for performing the above methods.
  • non-transitory computer readable storage medium comprising instructions, such as a memory 1204 comprising instructions executable by processor 820 of apparatus 1200 to perform the above method.
  • the non-transitory computer readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device.
  • a device for waking up a main MCU comprising:
  • a memory for storing processor executable instructions
  • processor is configured to:
  • the main micro control unit MCU is configured to be in a deep sleep state, and the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state;
  • a wake-up signal is sent to the primary MCU.
  • the processor is further configured to:
  • Sending a wake-up signal to the primary MCU including:
  • the wake-up signal is transmitted in such a manner as to send an interrupt signal to the main MCU.
  • the processor is further configured to:
  • the main MCU is configured to be in a deep sleep state, and the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state, including:
  • the clock line of the main MCU is connected to the main clock signal
  • the main MCU is configured to be in a deep sleep state by controlling the main clock signal and the slave clock signal, and the peripheral processing chip and the peripheral interface chip are configured to operate normally.
  • the processor is further configured to:
  • the configuring the peripheral processing chip and the peripheral interface chip to be in a normal working state including:
  • the peripheral processing chip and the peripheral interface chip are configured to perform data transmission by directly accessing the DMA through the memory.
  • the processor is further configured to:
  • the peripheral interface chip is a universal asynchronous transceiver transmission UART unit, a serial peripheral interface SPI unit, an internal integrated circuit bus I2C unit, or a Bluetooth unit;
  • the peripheral processing chip is an analog/digital A/D unit, a PWM pulse width modulation unit, a video processing unit, or an audio processing unit.
  • a non-transitory computer readable storage medium when instructions in the storage medium are executed by a processor of a mobile terminal, to enable a mobile terminal to perform a method of waking up a primary MCU, the method comprising:
  • the main micro control unit MCU is configured to be in a deep sleep state, and the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state;
  • a wake-up signal is sent to the primary MCU.
  • the sending the wake-up signal to the primary MCU includes:
  • the wake-up signal is transmitted in such a manner as to send an interrupt signal to the main MCU.
  • the main MCU is configured to be in a deep sleep state
  • the peripheral processing chip and the peripheral interface chip are configured to be in a normal working state, including:
  • the clock line of the main MCU is connected to the main clock signal
  • the main MCU is configured to be in a deep sleep state by controlling the main clock signal and the slave clock signal, and the peripheral processing chip and the peripheral interface chip are configured to operate normally.
  • the configuring the peripheral processing chip and the peripheral interface chip to be in a normal working state including:
  • the peripheral processing chip and the peripheral interface chip are configured to perform data transmission by directly accessing the DMA through the memory.
  • the peripheral interface chip is a universal asynchronous transceiver transmission UART unit, a serial peripheral interface SPI unit, an internal integrated circuit bus I2C unit, or a Bluetooth unit;
  • the peripheral processing chip is an analog/digital A/D unit, a PWM pulse width modulation unit, a video processing unit, or an audio processing unit.

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Abstract

公开了一种关于唤醒主MCU微控制单元的电路、方法及装置，使得设备的主MCU进入深度睡眠后能够及时醒来收发数据。该方法包括：将主微控制单元MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态（S201）；监测外设处理芯片给外设接口芯片发送的数据的数据量（S202）；当数据量超过阈值后，给主MCU发送唤醒信号（S203）。该方法能够使设备的主MCU进入深度睡眠后能够及时醒来收发数据。

Description

唤醒主MCU的电路、方法及装置
本申请基于申请号为201510370154.4、申请日为2015/6/29的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及设备领域，尤其涉及唤醒主MCU微控制单元的电路、方法及装置。
背景技术
在嵌入式系统软件开发的过程中，开发者为了尽可能的降低设备功耗、节约能源，会让系统在空闲时进入低功耗模式，这时微控制单元(Microcontroller Unit，MCU)芯片将进入睡眠或者深度睡眠状态。在深度睡眠状态下，一般MCU的外设(如串行外设接口SPI、通用异步收发传输UART、模/数AD转换单元)将无法正常工作，只有外部中断和定时器中断可以唤醒MCU，此时其它芯片通过串口等方式无法和设备MCU进行正常通信。
在另一场景中，为了尽可能的降低智能设备的功耗，有效利用能源，智能设备系统在空闲时会进入低功耗模式。可以选择让MCU进入浅睡眠(sleep)或者深度睡眠(standby备用/hibrnate冬眠)。当MCU进入到深度睡眠模式时，主时钟将停止工作，一些内部外设(例如包括UART单元、SPI单元、内部集成电路总线I2C单元、A/D单元、脉宽调制PWM单元等)如果依赖于主MCU时钟的话，也将无法工作。这样，主MCU将无法及时接收其它芯片通过UART单元、SPI单元、I2C单元等发送给它的数据。
发明内容
为克服相关技术中存在的问题，本公开实施例提供唤醒主MCU的电路、方法和装置，使得设备的主MCU进入深度睡眠后能够及时醒来收发数据。
根据本公开实施例的第一方面，提供一种唤醒主MCU的电路，所述电路包括：
主微控制单元MCU、外设接口芯片、以及外设处理芯片；
所述外设处理芯片通过所述外设接口芯片与所述主MCU连接；
所述主MCU的时钟线接入主时钟信号；所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入从时钟信号，使得当所述主MCU进入深度睡眠状态时，所述 外设处理芯片与所述外设接口芯片保持正常工作状态；
所述外设接口芯片，用于监测所述外设处理芯片给所述外设接口芯片发送的数据的数据量，当所述数据量超过阈值后，所述外设接口芯片给所述主MCU发送唤醒信号。
在一实施例中，所述外设接口芯片给所述主MCU发送唤醒信号，包括：
所述外设接口芯片以给所述主MCU发送中断信号的方式发送唤醒信号。
所述外设处理芯片与所述外设接口芯片保持正常工作状态，包括：
所述外设处理芯片与所述外设接口芯片之间通过存储器直接访问DMA的方式进行数据传输。
所述外设接口芯片为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；
所述外设处理芯片为模/数A/D单元、脉宽调制PWM单元、视频处理单元、或音频处理单元。
本公开还提供一种唤醒主MCU的方法，应用于包括主MCU、外设接口芯片、以及外设处理芯片的设备，其特征在于，所述方法包括：
将主微控制单元MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态；
监测所述外设处理芯片给所述外设接口芯片发送的数据的数据量；
当所述数据量超过阈值后，给所述主MCU发送唤醒信号。
在一实施例中，所述给所述主MCU发送唤醒信号，包括：
以给所述主MCU发送中断信号的方式发送唤醒信号。
在一实施例中，所述将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态，包括：
将所述主MCU的时钟线接入主时钟信号；
将所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入从时钟信号；
通过控制所述主时钟信号和所述从时钟信号，将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态。
在一实施例中，所述将所述外设处理芯片与所述外设接口芯片配置为正常工作状态，包括：
将所述外设处理芯片与所述外设接口芯片之间配置为通过存储器直接访问DMA的方式进行数据传输。
在一实施例中，所述外设接口芯片为通用异步收发传输UART单元、串行外设接 口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；
所述外设处理芯片为模/数A/D单元、PWM脉宽调制单元、视频处理单元、或音频处理单元。
本公开还提供一种唤醒主MCU的装置，应用于包括主MCU、外设接口芯片、以及外设处理芯片的设备，所述装置包括：
配置模块，用于将主微控制单元MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态；
监测模块，用于监测所述外设处理芯片给所述外设接口芯片发送的数据的数据量；
发送模块，用于当所述数据量超过阈值后，给所述主MCU发送唤醒信号。
在一实施例中，所述发送模块用于：以给所述主MCU发送中断信号的方式发送唤醒信号。
在一实施例中，所述配置模块，包括：
第一连接子模块，用于将所述主MCU的时钟线接入主时钟信号；
第二连接子模块，用于将所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入从时钟信号；
控制子模块，用于通过控制所述主时钟信号和所述从时钟信号，将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态。
在一实施例中，所述配置模块用于，将所述外设处理芯片与所述外设接口芯片之间配置为通过存储器直接访问DMA的方式进行数据传输。
在一实施例中，所述外设接口芯片为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；
所述外设处理芯片为模/数A/D单元、PWM脉宽调制单元、视频处理单元、或音频处理单元。
本公开还提供一种唤醒主MCU的装置，包括：
处理器；
用于存储处理器可执行指令的存储器；
其中，所述处理器被配置为：
将主微控制单元MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态；
监测所述外设处理芯片给所述外设接口芯片发送的数据的数据量；
当所述数据量超过阈值后，给所述主MCU发送唤醒信号。
本公开的实施例提供的技术方案可以包括以下有益效果：
上述实施例中，主MCU的时钟线接入主时钟信号；所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入从时钟信号，主MCU、外设处理芯片和外设接口芯片的时钟线接入不同时钟信号，因此，当主MCU进入深度睡眠状态时，外设处理芯片与外设接口芯片可以保持正常工作状态；这样，当外设处理芯片给外设接口芯片发送的数据的数据量超过阈值后，外设接口芯片给主MCU发送唤醒信号，使得主MCU被唤醒后，进行数据的收发和处理。采用这种方式，可以使得设备的主MCU进入深度睡眠后能够及时醒来对数据进行收发和处理。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。
图1是根据一示例性实施例示出的唤醒主MCU的电路的示意图。
图2是根据一示例性实施例一示出的唤醒主MCU的方法的流程图。
图3是根据一示例性实施例一示出的唤醒主MCU的方法中步骤S201的流程图。
图4是根据一示例性实施例示出的一种唤醒主MCU的装置的框图。
图5是根据一示例性实施例示出的一种唤醒主MCU的装置中配置模块的框图。
图6是根据一示例性实施例示出的一种适用于唤醒主MCU的装置的框图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本发明的一些方面相一致的装置和方法的例子。
图1是根据一示例性实施例示出的一种唤醒主MCU的电路，该电路包括：主微控制单元MCU 11、外设接口芯片12、以及外设处理芯片13；
外设处理芯片13通过外设接口芯片12与主MCU 11连接；
所述主MCU 11的时钟线接入主时钟信号；将所述外设处理芯片13的时钟线与所述外设接口芯片12的时钟线分别接入从时钟信号，使得当主MCU 11进入深度睡眠状态时，外设处理芯片13与外设接口芯片12保持正常工作状态；外设接口芯片12，用于监测外设处理芯片13给外设接口芯片12发送的数据的数据量，当数据量超过阈值 后，外设接口芯片12给主MCU 11发送唤醒信号。
上述实施例中，主MCU 11的时钟线接入主时钟信号；外设处理芯片13的时钟线与外设接口芯片12的时钟线分别接入从时钟信号，主MCU与外设处理芯片13与外设接口芯片的时钟线接入不同时钟信号，因此，当主MCU 11进入深度睡眠状态时，外设处理芯片13与外设接口芯片12可以保持正常工作状态；这样，当外设处理芯片13给外设接口芯片12发送的数据的数据量超过阈值后，外设接口芯片12给主MCU 11发送唤醒信号，使得主MCU被唤醒后，进行数据的收发和处理。采用这种方式，采用这种方式，可以使得设备的主MCU进入深度睡眠后能够及时醒来收发数据。
上述实施例中，外设接口芯片中设置有缓冲器，外设处理芯片准备通过外设接口芯片给主MCU发送的数据，首先发送给外设接口芯片，并存储在外设接口芯片的缓冲器中；当数据量超过阈值后，则外设接口芯片给主MCU发送唤醒信号。
其中，所述外设接口芯片以给所述主MCU发送中断信号的方式发送唤醒信号，使得设备的主MCU进入深度睡眠后能够及时醒来收发数据。该步骤可以为：监测外设处理芯片给外设接口芯片发送的数据的数据量，当数据量超过阈值后，外设接口芯片产生中断信号，发送给主MCU，以对主MCU进行唤醒。
其中，外设处理芯片与外设接口芯片之间可以通过存储器直接访问(Direct Memory Access，DMA)的方式进行数据传输。DMA方式是一种高速数据传输操作，允许外部设备和存储器之间直接读写数据，既不通过CPU，也不需要CPU干预，整个数据传输操作由“DMA控制器”进行控制，因此，使得主MCU在深度睡眠状态下外设处理芯片与外设接口芯片之间仍然能够进行数据传输。
其中，外设接口芯片可以为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；外设处理芯片可以为模/数A/D单元、脉宽调制PWM单元、视频处理单元、或音频处理单元。
以外设接口芯片为通用异步收发传输UART单元，外设处理芯片为模/数A/D单元为例，描述本公开的应用场景。
一种应用于智能设备中的低功耗电路，当设备MCU进入深度睡眠后能够及时醒来收发数据。该电路为一种独立于主时钟的内部外设设计结构，内部外设UART单元和模/数A/D单元有自己独立于主MCU的工作时钟，这样，当主MCU进入深度睡眠模式时，可以单独配置某个外设的工作状态。例如UART模块在主MCU进入深度睡眠后被配置为继续保持正常工作状态，通过DMA方式与模/数A/D单元进行数据传输。当模/数A/D单元通过UART发送的数据量超过一定的阈值后，UART控制器会以发送中断信号的方式唤醒主MCU，使得主MCU进行数据的收发和处理。采用这种方式可 以保证设备在超低功耗模式下仍能够保持数据的正常接收。
图2是根据一示例性实施例示出的一种唤醒主MCU的方法的流程图，如图2所示，该唤醒主MCU的方法用于包括主MCU、外设接口芯片、以及外设处理芯片的设备，所述方法包括以下步骤S201-S203：
在步骤S201中，将主微控制单元MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态；
在步骤S202中，监测外设处理芯片给外设接口芯片发送的数据的数据量；
在步骤S203中，当数据量超过阈值后，给主MCU发送唤醒信号。该步骤可以为：以中断的方式给主MCU发送唤醒信号。
上述实施例中，将主微控制单元MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态；当外设处理芯片给外设接口芯片发送的数据的数据量超过阈值后，给主MCU发送唤醒信号。采用这种方式，可以使得设备的主MCU进入深度睡眠后及时醒来收发数据。
其中，外设接口芯片可以为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；外设处理芯片可以为模/数A/D单元、PWM脉宽调制单元、视频处理单元、或音频处理单元。
在步骤S21中，包括：将外设处理芯片与外设接口芯片之间配置为通过存储器直接访问DMA的方式进行数据传输。DMA方式是一种高速数据传输操作，允许外部设备和存储器之间直接读写数据，既不通过CPU，也不需要CPU干预，整个数据传输操作由“DMA控制器”进行控制，因此，使得主MCU在深度睡眠状态下外设处理芯片与外设接口芯片之间仍然能够进行数据传输。
如图3所示，步骤S201包括：
在步骤S2011中，将主MCU的时钟线接入主时钟信号；
在步骤S0212中，将外设处理芯片的时钟线与外设接口芯片的时钟线分别接入从时钟信号；
在步骤S2013中，通过控制主时钟信号和从时钟信号，将主MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态。
上述实施例中，主MCU的时钟线接入主时钟信号；外设处理芯片与外设接口芯片分别接入从时钟信号，主MCU的时钟线与外设处理芯片的时钟线与外设接口芯片的时钟线接入不同时钟信号，因此，当主MCU进入深度睡眠状态时，外设处理芯片与外设接口芯片可以配置为保持正常工作状态。
图4是根据一示例性实施例示出的一种唤醒主MCU的装置的框图，如图4所示， 唤醒主MCU的装置，应用于包括主MCU、外设接口芯片、以及外设处理芯片的设备，所述装置包括：
配置模块41，被配置为将主微控制单元MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态；
监测模块42，被配置为监测外设处理芯片给外设接口芯片发送的数据的数据量；
发送模块43，被配置为当数据量超过阈值后，给主MCU发送唤醒信号。其中，可以以中断的方式给主MCU发送唤醒信号。
上述实施例中，将主微控制单元MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态；当外设处理芯片给外设接口芯片发送的数据的数据量超过阈值后，给主MCU发送唤醒信号。采用这种方式，可以使得设备的主MCU进入深度睡眠后及时醒来收发数据。
其中，配置模块41被配置为，将外设处理芯片与外设接口芯片之间配置为通过存储器直接访问DMA的方式进行数据传输。DMA方式是一种高速数据传输操作，允许外部设备和存储器之间直接读写数据，既不通过CPU，也不需要CPU干预，整个数据传输操作由“DMA控制器”进行控制，因此，使得主MCU在深度睡眠状态下外设处理芯片与外设接口芯片之间仍然能够进行数据传输。
如图5所示，配置模块41，包括：
第一连接子模块411，被配置为将主MCU的时钟线接入主时钟信号；
第二连接子模块412，被配置为将外设处理芯片的时钟线与外设接口芯片的时钟线分别接入从时钟信号；
控制子模块413，被配置为通过控制主时钟信号和从时钟信号，将主MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态。
上述实施例中，主MCU的时钟线接入主时钟信号；外设处理芯片的时钟线与外设接口芯片的时钟线分别接入从时钟信号，主MCU的时钟线与外设处理芯片的时钟线与外设接口芯片的时钟线接入不同时钟信号，因此，当主MCU进入深度睡眠状态时，外设处理芯片与外设接口芯片可以保持正常工作状态。
外设接口芯片可以为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元。
外设处理芯片可以为模/数A/D单元、PWM脉宽调制单元、视频处理单元、或音频处理单元。
关于上述实施例中的装置，其中各个模块执行操作的具体方式已经在有关该方法的实施例中进行了详细描述，此处将不做详细阐述说明。
图6是根据一示例性实施例示出的一种用于唤醒主MCU的装置1200的框图，该装置适用于终端设备。例如，装置1200可以是移动电话，计算机，数字广播终端，消息收发设备，游戏控制台，平板设备，医疗设备，健身设备，个人数字助理等。
参照图6，装置1200可以包括以下一个或多个组件：处理组件1202，存储器1204，电源组件1206，多媒体组件1208，音频组件1210，输入/输出(I/O)的接口1212，传感器组件1214，以及通信组件1216。
处理组件1202通常控制装置1200的整体操作，诸如与显示，电话呼叫，数据通信，相机操作和记录操作相关联的操作。处理元件1202可以包括一个或多个处理器1220来执行指令，以完成上述的方法的全部或部分步骤。此外，处理组件1202可以包括一个或多个模块，便于处理组件1202和其他组件之间的交互。例如，处理部件1202可以包括多媒体模块，以方便多媒体组件1208和处理组件1202之间的交互。
存储器1204被配置为存储各种类型的数据以支持在设备1200的操作。这些数据的示例包括用于在装置1200上操作的任何应用程序或方法的指令，联系人数据，电话簿数据，消息，图片，视频等。存储器1204可以由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(SRAM)，电可擦除可编程只读存储器(EEPROM)，可擦除可编程只读存储器(EPROM)，可编程只读存储器(PROM)，只读存储器(ROM)，磁存储器，快闪存储器，磁盘或光盘。
电力组件1206为装置1200的各种组件提供电力。电力组件1206可以包括电源管理系统，一个或多个电源，及其他与为装置1200生成、管理和分配电力相关联的组件。
多媒体组件1208包括在所述装置1200和用户之间的提供一个输出接口的屏幕。在一些实施例中，屏幕可以包括液晶显示器(LCD)和触摸面板(TP)。如果屏幕包括触摸面板，屏幕可以被实现为触摸屏，以接收来自用户的输入信号。触摸面板包括一个或多个触摸传感器以感测触摸、滑动和触摸面板上的手势。所述触摸传感器可以不仅感测触摸或滑动动作的边界，而且还检测与所述触摸或滑动操作相关的持续时间和压力。在一些实施例中，多媒体组件1208包括一个前置摄像头和/或后置摄像头。当设备1200处于操作模式，如拍摄模式或视频模式时，前置摄像头和/或后置摄像头可以接收外部的多媒体数据。每个前置摄像头和后置摄像头可以是一个固定的光学透镜系统或具有焦距和光学变焦能力。
音频组件1210被配置为输出和/或输入音频信号。例如，音频组件1210包括一个麦克风(MIC)，当装置1200处于操作模式，如呼叫模式、记录模式和语音识别模式时，麦克风被配置为接收外部音频信号。所接收的音频信号可以被进一步存储在存储器1204或经由通信组件1216发送。在一些实施例中，音频组件1210还包括一个扬声 器，用于输出音频信号。
I/O接口1212为处理组件1202和外围接口模块之间提供接口，上述外围接口模块可以是键盘，点击轮，按钮等。这些按钮可包括但不限于：主页按钮、音量按钮、启动按钮和锁定按钮。
传感器组件1214包括一个或多个传感器，用于为装置1200提供各个方面的状态评估。例如，传感器组件1214可以检测到设备1200的打开/关闭状态，组件的相对定位，例如所述组件为装置1200的显示器和小键盘，传感器组件1214还可以检测装置1200或装置1200一个组件的位置改变，用户与装置1200接触的存在或不存在，装置1200方位或加速/减速和装置1200的温度变化。传感器组件1214可以包括接近传感器，被配置用来在没有任何的物理接触时检测附近物体的存在。传感器组件1214还可以包括光传感器，如CMOS或CCD图像传感器，用于在成像应用中使用。在一些实施例中，该传感器组件1214还可以包括加速度传感器，陀螺仪传感器，磁传感器，压力传感器或温度传感器。
通信组件1216被配置为便于装置1200和其他设备之间有线或无线方式的通信。装置1200可以接入基于通信标准的无线网络，如WiFi，2G或3G，或它们的组合。在一个示例性实施例中，通信部件1216经由广播信道接收来自外部广播管理系统的广播信号或广播相关信息。在一个示例性实施例中，所述通信部件1216还包括近场通信(NFC)模块，以促进短程通信。例如，在NFC模块可基于射频识别(RFID)技术，红外数据协会(IrDA)技术，超宽带(UWB)技术，蓝牙(BT)技术和其他技术来实现。
在示例性实施例中，装置1200可以被一个或多个应用专用集成电路(ASIC)、数字信号处理器(DSP)、数字信号处理设备(DSPD)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、控制器、微控制器、微处理器或其他电子元件实现，用于执行上述方法。
在示例性实施例中，还提供了一种包括指令的非临时性计算机可读存储介质，例如包括指令的存储器1204，上述指令可由装置1200的处理器820执行以完成上述方法。例如，所述非临时性计算机可读存储介质可以是ROM、随机存取存储器(RAM)、CD-ROM、磁带、软盘和光数据存储设备等。
一种唤醒主MCU的装置，包括：
处理器；
用于存储处理器可执行指令的存储器；
其中，处理器被配置为：
将主微控制单元MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态；
监测外设处理芯片给外设接口芯片发送的数据的数据量；
当数据量超过阈值后，给主MCU发送唤醒信号。
在一实施例中，处理器还被配置为：
所述给所述主MCU发送唤醒信号，包括：
以给所述主MCU发送中断信号的方式发送唤醒信号。
在一实施例中，处理器还被配置为：
所述将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态，包括：
将所述主MCU的时钟线接入主时钟信号；
将所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入到从时钟信号；
通过控制所述主时钟信号和所述从时钟信号，将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态。
在一实施例中，处理器还被配置为：
所述将所述外设处理芯片与所述外设接口芯片配置为正常工作状态，包括：
将所述外设处理芯片与所述外设接口芯片之间配置为通过存储器直接访问DMA的方式进行数据传输。
在一实施例中，处理器还被配置为：
所述外设接口芯片为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；
所述外设处理芯片为模/数A/D单元、PWM脉宽调制单元、视频处理单元、或音频处理单元。
一种非临时性计算机可读存储介质，当所述存储介质中的指令由移动终端的处理器执行时，使得移动终端能够执行一种唤醒主MCU的方法，所述方法包括：
将主微控制单元MCU配置为深度睡眠状态，将外设处理芯片与外设接口芯片配置为正常工作状态；
监测外设处理芯片给外设接口芯片发送的数据的数据量；
当数据量超过阈值后，给主MCU发送唤醒信号。
在一实施例中，所述给所述主MCU发送唤醒信号，包括：
以给所述主MCU发送中断信号的方式发送唤醒信号。
在一实施例中，所述将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态，包括：
将所述主MCU的时钟线接入主时钟信号；
将所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入到从时钟信号；
通过控制所述主时钟信号和所述从时钟信号，将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态。
在一实施例中，所述将所述外设处理芯片与所述外设接口芯片配置为正常工作状态，包括：
将所述外设处理芯片与所述外设接口芯片之间配置为通过存储器直接访问DMA的方式进行数据传输。
在一实施例中，所述外设接口芯片为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；
所述外设处理芯片为模/数A/D单元、PWM脉宽调制单元、视频处理单元、或音频处理单元。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (15)

  1. 一种唤醒主MCU微控制单元的电路，其特征在于，所述电路包括：
    主微控制单元MCU、外设接口芯片、以及外设处理芯片；
    所述外设处理芯片通过所述外设接口芯片与所述主MCU连接；
    所述主MCU的时钟线接入主时钟信号；所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入从时钟信号，使得当所述主MCU进入深度睡眠状态时，所述外设处理芯片与所述外设接口芯片保持正常工作状态；
    所述外设接口芯片，用于监测所述外设处理芯片给所述外设接口芯片发送的数据的数据量，当所述数据量超过阈值后，所述外设接口芯片给所述主MCU发送唤醒信号。
  2. 根据权利要求1所述的电路，其特征在于，所述外设接口芯片给所述主MCU发送唤醒信号，包括：
    所述外设接口芯片以给所述主MCU发送中断信号的方式发送唤醒信号。
  3. 根据权利要求1所述的电路，其特征在于，所述外设处理芯片与所述外设接口芯片保持正常工作状态，包括：
    所述外设处理芯片与所述外设接口芯片之间通过存储器直接访问DMA的方式进行数据传输。
  4. 根据权利要求1所述的电路，其特征在于，
    所述外设接口芯片为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；
    所述外设处理芯片为模/数A/D单元、脉宽调制PWM单元、视频处理单元、或音频处理单元。
  5. 一种唤醒主MCU的方法，应用于包括主MCU、外设接口芯片、以及外设处理芯片的设备，其特征在于，所述方法包括：
    将主微控制单元MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态；
    监测所述外设处理芯片给所述外设接口芯片发送的数据的数据量；
    当所述数据量超过阈值后，给所述主MCU发送唤醒信号。
  6. 根据权利要求5所述的方法，其特征在于，所述给所述主MCU发送唤醒信号，包括：
    以给所述主MCU发送中断信号的方式发送唤醒信号。
  7. 根据权利要求5所述的方法，其特征在于，所述将主MCU配置为深度睡眠状 态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态，包括：
    将所述主MCU的时钟线接入主时钟信号；
    将所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入从时钟信号；
    通过控制所述主时钟信号和所述从时钟信号，将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态。
  8. 根据权利要求5所述的方法，其特征在于，所述将所述外设处理芯片与所述外设接口芯片配置为正常工作状态，包括：
    将所述外设处理芯片与所述外设接口芯片之间配置为通过存储器直接访问DMA的方式进行数据传输。
  9. 根据权利要求5所述的方法，其特征在于，
    所述外设接口芯片为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；
    所述外设处理芯片为模/数A/D单元、PWM脉宽调制单元、视频处理单元、或音频处理单元。
  10. 一种唤醒主MCU的装置，应用于包括主MCU、外设接口芯片、以及外设处理芯片的设备，其特征在于，所述装置包括：
    配置模块，用于将主微控制单元MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态；
    监测模块，用于监测所述外设处理芯片给所述外设接口芯片发送的数据的数据量；
    发送模块，用于当所述数据量超过阈值后，给所述主MCU发送唤醒信号。
  11. 根据权利要求10所述的装置，其特征在于，所述发送模块用于：以给所述主MCU发送中断信号的方式发送唤醒信号。
  12. 根据权利要求10所述的装置，其特征在于，所述配置模块，包括：
    第一连接子模块，用于将所述主MCU的时钟线接入主时钟信号；
    第二连接子模块，用于将所述外设处理芯片的时钟线与所述外设接口芯片的时钟线分别接入从时钟信号；
    控制子模块，用于通过控制所述主时钟信号和所述从时钟信号，将主MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态。
  13. 根据权利要求10所述的装置，其特征在于，所述配置模块用于，将所述外设处理芯片与所述外设接口芯片之间配置为通过存储器直接访问DMA的方式进行数据传输。
  14. 根据权利要求10所述的装置，其特征在于，
    所述外设接口芯片为通用异步收发传输UART单元、串行外设接口SPI单元、内部集成电路总线I2C单元、或蓝牙单元；
    所述外设处理芯片为模/数A/D单元、PWM脉宽调制单元、视频处理单元、或音频处理单元。
  15. 一种唤醒主MCU的装置，其特征在于，包括：
    处理器；
    用于存储处理器可执行指令的存储器；
    其中，所述处理器被配置为：
    将主微控制单元MCU配置为深度睡眠状态，将所述外设处理芯片与所述外设接口芯片配置为正常工作状态；
    监测所述外设处理芯片给所述外设接口芯片发送的数据的数据量；
    当所述数据量超过阈值后，给所述主MCU发送唤醒信号。
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