WO2016206263A1 - 一种防止spi flash开关机时数据破坏的系统及方法 - Google Patents

一种防止spi flash开关机时数据破坏的系统及方法 Download PDF

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WO2016206263A1
WO2016206263A1 PCT/CN2015/093013 CN2015093013W WO2016206263A1 WO 2016206263 A1 WO2016206263 A1 WO 2016206263A1 CN 2015093013 W CN2015093013 W CN 2015093013W WO 2016206263 A1 WO2016206263 A1 WO 2016206263A1
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power
voltage
spi flash
sampling
reference voltage
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PCT/CN2015/093013
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French (fr)
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文君
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上海斐讯数据通信技术有限公司
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Publication of WO2016206263A1 publication Critical patent/WO2016206263A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory

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  • the present invention relates to the technical field of data protection of SPI FLASH, and in particular to a system and method for preventing data corruption when SPI FLASH is turned on and off.
  • SPI Serial Peripheral Interface
  • SPI FLASH is a serial memory that reads and writes via the SPI port.
  • the application number is 201210226126.1
  • the Chinese invention patent entitled "Power-down protection circuit for flash memory and power-down protection sequence circuit” discloses a power-down protection circuit for a flash memory, including a power monitoring module and an electronic switch unit.
  • the power monitoring module is connected to an electronic switch unit, and the electronic switch unit is configured to connect a write protection pin of the flash memory;
  • the power monitoring module is configured to obtain an external power supply, and the voltage of the external power supply is less than a power failure threshold Controlling the electronic switch unit to output a low level to the write protection pin;
  • the electronic switch unit includes a first voltage dividing resistor, a second voltage dividing resistor, a pull-down resistor, and a first switching tube, the first switch The tube includes an input end, an output end, and a control end, wherein an output end of the first switch tube is used to connect the write protection pin, and an output end of the first switch tube is grounded through the pull-down resistor;
  • An input end of a switch tube is used to connect
  • the write-protect pin of the flash memory can be pulled low, and the flash memory is placed in write-protected state until the end of power-down. Therefore, the data stored in the flash memory will not be erased during the power down process.
  • the FLASH-specific area is usually protected by an encryption algorithm.
  • the scheme is only applicable to the underlying FLASH driver or some special data areas, and cannot cover all the data areas of the FLASH. At the same time, it also occupies the resources of the processor, complicates the system, and introduces system instability factors.
  • the object of the present invention is to provide a system and method for preventing data corruption when the SPI FLASH is turned on and off, and to solve the data destruction risk caused by the noise of the switch by the hysteresis comparator circuit.
  • the system power-on and system power-off trigger protection time can be flexibly set to better protect the data in the FLASH and improve the stability of the system.
  • the present invention provides a system for preventing data corruption when the SPI FLASH is turned on and off, and is disposed between the system power supply and the SPI FLASH, including a power sampling module, a power-on voltage processing module, and a power-down voltage processing.
  • the power sampling module is configured to sample a system power supply to obtain a power-on sampling voltage or a power-down sampling voltage
  • the power-on voltage processing module is connected to the power sampling module, and includes a connected a hysteresis comparator and a first programmable delay circuit
  • the first hysteresis comparator is configured to compare the power-on sampling voltage and the power-on reference voltage, and input the comparison result to the first programmable delay circuit
  • a programmable delay circuit is configured to delay the comparison result of the first hysteresis comparator for a first time
  • the power down voltage processing module is connected to the power sampling module, and includes a connected second hysteresis comparator and a second programmable delay circuit
  • the second hysteresis comparator is configured to compare the power down sampling voltage and the power down reference voltage, and input the comparison result
  • the second programmable delay circuit is configured to delay the comparison result of the second hysteresis comparator for
  • the first hysteresis comparator outputs a high level when the power-on sampling voltage is higher than the power-on reference voltage, and the power-on sampling voltage is lower than the power-on reference.
  • the second hysteresis comparator outputs a high level when the power-down sampling voltage is higher than the power-down reference voltage, and outputs a low level when the power-down sampling voltage is lower than the power-down reference voltage.
  • the combination logic module when the first delay When the comparator output is low, the combination logic module outputs a low level, and the SPI FLASH is in a write protection state; when the first hysteresis comparator outputs a high level, the combination logic module outputs a high level, SPI FLASH Not in the write protection state; when the second hysteresis comparator outputs a low level, the combination logic module outputs a low level, and the SPI FLASH is in a write protection state; when the second hysteresis comparator outputs a high level, The combination logic module outputs a high level, and SPIFLASH is not in a write protection state.
  • the power-on sampling voltage is triggered by a rising edge
  • the power-down sampling voltage is triggered by a falling edge
  • the power-on voltage processing module includes only a first hysteresis comparator, the first hysteresis comparator inputs a comparison result to the combinational logic module;
  • the power down voltage processing module includes only a second hysteresis comparator that inputs the comparison result to the combinational logic module.
  • the present invention also provides a method for preventing data corruption when the SPI FLASH is turned on and off, including the following steps:
  • Step S1 sampling the system power supply to obtain a sampling voltage
  • Step S2 If the voltage is the power-on sampling voltage, compare the sampling voltage with the power-on reference voltage; if the sampling voltage is the power-down sampling voltage, compare the sampling voltage with the power-down reference voltage;
  • Step S3 delaying the comparison result
  • Step S4 according to the comparison result after the delay, when the power-on voltage of the system power is lower than the power-on reference voltage or the power-off voltage is lower than the power-down reference voltage, the output disable signal is sent to the write protection pin of the SPI FLASH, so that SPI FLASH is write protected and the data area will not be overwritten.
  • the comparison result is output as high power.
  • the comparison result is output low.
  • step S4 when the comparison result is output to a high level, the SPI FLASH is not in the write protection state; when the comparison result is outputted to the low level, SPIFLASH is write protected.
  • step S3 the delay in step S3 is not performed, and directly, according to the comparison result, when the power-on voltage of the system power supply is lower than the power-on reference voltage or the power-down voltage is lower than When the voltage is referenced, the output disable signal is sent to the write protection pin of SPI FLASH, which makes the SPI FLASH write-protected.
  • the system and method for preventing data corruption in the SPI FLASH switching machine of the present invention have the following beneficial effects:
  • the hysteresis comparator circuit can be used to solve the data destruction risk caused by the noise of the switch;
  • FIG. 1 is a schematic structural view showing a preferred embodiment of a system for preventing data corruption when the SPI FLASH switch is in accordance with the present invention
  • FIG. 2 is a block diagram showing another preferred embodiment of a system for preventing data corruption when the SPI FLASH switch is in accordance with the present invention
  • FIG. 3 is a flow chart showing a preferred embodiment of a method of preventing data corruption when the SPI FLASH switch is in accordance with the present invention.
  • a system for preventing data corruption in a SPI FLASH switch is provided between a system power supply and a SPI FLASH, and includes a power sampling module 1 and a power-on voltage processing module 2.
  • the voltage processing module 3 and the combination logic module 4 are powered off.
  • the power sampling module 1 is respectively connected to the system power supply, the power-on voltage processing module 2 and the power-down voltage processing module 3; the power-on voltage processing module 2 and the power-down voltage processing module 3 are all connected to the combination logic module 4; the combination logic module 4 is connected to SPI FLASH.
  • the power sampling module 1 is used to sample the system power supply to obtain the power-on sampling voltage or the power-down sampling voltage.
  • the system power supply can be 3v3 or other external power source.
  • the power-on sampling voltage is triggered by the rising edge; the power-down sampling voltage is triggered by the falling edge. Therefore, according to the rising edge or the falling edge of the trigger, it can be determined whether the obtained power-up sampling voltage or the power-down sampling voltage is obtained.
  • the power-on voltage processing module 2 includes a connected first hysteresis comparator 21 and a first programmable delay circuit 22.
  • the first hysteresis comparator 21 is for comparing the power-up sampling voltage with the power-on reference voltage V refh and inputting the comparison result to the first programmable delay circuit 22. Specifically, the first hysteresis comparator 21 outputs a high level when the power-on sampling voltage is higher than the power-on reference voltage V refh , and outputs a low level when the power-on sampling voltage is lower than the power-on reference voltage.
  • the first programmable delay circuit 22 is configured to delay the comparison result of the first hysteresis comparator 21 by the first time T1. Through different T1 selections, the time for system power-on trigger protection can be flexibly set according to different systems.
  • the power-down voltage processing module includes a connected second hysteresis comparator 31 and a second programmable delay circuit 32.
  • the second hysteresis comparator 31 is for comparing the down-sampling voltage and the power-down reference voltage V refl and inputting the comparison result to the second programmable delay circuit 32. Specifically, the second hysteresis comparator 31 outputs a high level when the power-down sampling voltage is higher than the power-down reference voltage V refl , and outputs a low level when the power-down sampling voltage is lower than the power-down reference voltage.
  • the second programmable delay circuit 32 is configured to delay the comparison result of the second hysteresis comparator 31 by the second time T2. Through different T2 selections, the time for system power-off trigger protection can be flexibly set according to different systems.
  • the combination logic module 4 is configured to output an ban according to the output of the power-on voltage processing module 2 or the power-down voltage processing module 4 when the power-on voltage of the system power source is lower than the power-on reference voltage or the power-down voltage is lower than the power-down reference voltage.
  • the signal can be written to the SPIFLASH write-protect pin, so that the SPI FLASH is write-protected and the data area is not overwritten.
  • the combination logic module when the first hysteresis comparator outputs a high level, the combination logic module outputs a high level; when the first hysteresis comparator outputs a low level, the combination logic module outputs a low level; when the second hysteresis comparator outputs a high level; In normal times, the combinational logic module outputs a high level; when the second hysteresis comparator outputs a low level, the combinational logic module outputs a low level.
  • the SPI FLASH is in the write protection state, and the data area will not be overwritten.
  • the first hysteresis comparator If the power supply voltage is higher than the power-on reference voltage V refh , the first hysteresis comparator outputs a high level, after the delay time T1 of the first programmable delay circuit, the combination logic module outputs a high level, and the write protection of the SPI FLASH The input of the foot WP# is high level, the SPI FLASH is released from the write protection state, and the system can erase, read and write the SPI FLASH.
  • the combination logic module When the system is powered off, if the power supply voltage is higher than the power-down reference voltage V refl , the second hysteresis comparator outputs a high level, and after the delay time T2 of the second programmable delay circuit, the combination logic module outputs a high level.
  • the input of SPI FLASH write protection pin WP# is high level, and the system can erase, read and write the SPI FLASH.
  • the second hysteresis comparator If the power supply voltage is lower than the power-down reference voltage V refl , the second hysteresis comparator outputs a low level, after the delay time T2 of the second programmable delay circuit, the combination logic module outputs a low level, and the write protection of the SPI FLASH
  • the input of the foot WP# is low level, the SPI FLASH is in the write protection state, and the system cannot erase or write the SPI FLASH. That is to say, after the T2 time after the SPI FLASH block is powered off, the SPI FLASH is in the write protection state, and the data area will not be overwritten.
  • T1 and T2 are both greater than or equal to 0, and the two may be the same or different. It depends on factors such as the load of the system power supply, the switching waveform, and the system wiring. Therefore, T1 and T2 can be flexibly and independently set according to the specific system.
  • the design of the hysteresis voltage in the present invention has a good suppression capability for "switching noise” or "power supply noise” in system operation, and effectively prevents damage to the SPIFLASH block.
  • the system for preventing data corruption during the SPI FLASH switching machine of the present invention is disposed between the system power supply and the SPI FLASH, including the power sampling module 1, and the power-on voltage processing.
  • Module 2 power down voltage processing module 3 and combination logic module 4.
  • the power sampling module 1 is respectively connected to the system power supply, the power-on voltage processing module 2, and the power-down voltage processing module 3; the power-on voltage processing module 2 and the power-down voltage processing module 3 are both associated with the group.
  • the logic module 4 is connected; the combination logic module 4 is connected to the SPI FLASH.
  • the power sampling module 1 is used to sample the system power.
  • the system power supply can be 3v3 or other external power source.
  • the power-on sampling voltage is triggered by the rising edge; the power-down sampling voltage is triggered by the falling edge. Therefore, according to the rising edge or the falling edge of the trigger, it can be determined whether the obtained power-up sampling voltage or the power-down sampling voltage is obtained.
  • the power-on voltage processing module 2 includes a first hysteresis comparator 21.
  • the first hysteresis comparator 21 is for comparing the power-up sampling voltage and the power-on reference voltage V refh and inputting the comparison result to the combinational logic module 4. Specifically, the first hysteresis comparator 21 outputs a high level when the power-on sampling voltage is higher than the power-on reference voltage V refh , and outputs a low level when the power-on sampling voltage is lower than the power-on reference voltage.
  • the power-down voltage processing module 3 includes a second hysteresis comparator 31.
  • the second hysteresis comparator 31 is for comparing the down-sampling voltage and the power-down reference voltage V refl and inputting the comparison result to the combinational logic module 4. Specifically, the second hysteresis comparator 31 outputs a high level when the power-down sampling voltage is higher than the power-down reference voltage V refl , and outputs a low level when the power-down sampling voltage is lower than the power-down reference voltage.
  • the combination logic module 4 is configured to output an ban according to the output of the power-on voltage processing module 2 or the power-down voltage processing module 3 when the power-on voltage of the system power source is lower than the power-on reference voltage or the power-down voltage is lower than the power-down reference voltage.
  • the signal can be written to the SPIFLASH write-protect pin, so that the SPI FLASH is write-protected and the data area is not overwritten.
  • the combination logic module when the first hysteresis comparator outputs a high level, the combination logic module outputs a high level; when the first hysteresis comparator outputs a low level, the combination logic module outputs a low level; when the second hysteresis comparator outputs a high level; In normal times, the combinational logic module outputs a high level; when the second hysteresis comparator outputs a low level, the combinational logic module outputs a low level.
  • the first hysteresis comparator If the power supply voltage is higher than the power-on reference voltage V refh , the first hysteresis comparator outputs a high level, the combination logic module outputs a high level, the input of the write protection pin WP# of the SPI FLASH is a high level, and the SPI FLASH is written off. Protection status, the system can erase, read and write operations on SPI FLASH.
  • the system When the system is powered off, if the power supply voltage is higher than the power-down reference voltage V refl , the second hysteresis comparator outputs a high level, the combination logic module outputs a high level, and the input of the SPI FLASH write protection pin WP# is high. Level, the system can erase, read and write SPI FLASH.
  • the second hysteresis comparator If the power supply voltage is lower than the power-down reference voltage V refl , the second hysteresis comparator outputs a low level, the combination logic module outputs a low level, the input of the SPI FLASH write protection pin WP# is a low level, and the SPI FLASH enters the write Protected state, the system cannot erase or write to SPI FLASH. That is to say, as long as the power supply voltage is lower than the power-down reference voltage V refl , the SPI FLASH is in the write protection state, and the data area is not overwritten.
  • system for preventing data corruption during the SPI FLASH switch can be set as a separate circuit between the system power supply and the SPI FLASH, or integrated in the SPI FLASH chip or the FLASH controller of the main chip. To increase the function of ISIC.
  • the method for preventing data corruption when the SPI FLASH switch is turned on includes the following steps:
  • Step S1 sampling the system power supply to obtain the sampling voltage.
  • the system power supply can be 3v3 or other external power source.
  • the system power is sampled by the power sampling module.
  • Step S2 If the voltage is the power-on sampling voltage, the sampling voltage is compared with the power-on reference voltage V refh ; if the sampling voltage is the power-down sampling voltage, the sampling voltage is compared with the power-down reference voltage V refl .
  • the power-on sampling voltage is triggered by the rising edge; the power-down sampling voltage is triggered by the falling edge. Therefore, according to the rising edge or the falling edge of the trigger, it can be determined whether the obtained power-up sampling voltage or the power-down sampling voltage is obtained.
  • the power-on sampling voltage and the power-on reference voltage V refh are compared by a first hysteresis comparator. Specifically, the first hysteresis comparator outputs a high level when the power-on sampling voltage is higher than the power-on reference voltage V refh , and outputs a low level when the power-on sampling voltage is lower than the power-on reference voltage.
  • the power down sampling voltage and the power down reference voltage V refl are compared by a second hysteresis comparator. Specifically, the second hysteresis comparator outputs a high level when the power-down sampling voltage is higher than the power-down reference voltage V refl , and outputs a low level when the power-down sampling voltage is lower than the power-down reference voltage.
  • step S3 the comparison result is delayed.
  • the comparison result of the first hysteresis comparator is delayed by the first programmable delay circuit for a first time T1.
  • the comparison result of the second hysteresis comparator is delayed by the second programmable delay circuit for a second time T2.
  • Step S4 according to the comparison result after the delay, when the power-on voltage of the system power is lower than the power-on reference voltage or the power-off voltage is lower than the power-down reference voltage, the output disable signal is sent to the write protection pin of the SPI FLASH, so that SPI FLASH is write protected and the data area will not be overwritten.
  • the combination logic module compares the power-on voltage of the system power supply to the power-on reference power according to the comparison result after the delay.
  • the output disable signal is sent to the write protection pin of SPI FLASH, so that SPIFLASH is in write-protected state and the data area is not overwritten.
  • the combination logic module when the first hysteresis comparator outputs a high level, the combination logic module outputs a high level; when the first hysteresis comparator outputs a low level, the combination logic module outputs a low level; when the second hysteresis comparator outputs a high level; In normal times, the combinational logic module outputs a high level; when the second hysteresis comparator outputs a low level, the combinational logic module outputs a low level.
  • the SPI FLASH is in the write protection state, and the data area will not be overwritten.
  • the first hysteresis comparator If the power supply voltage is higher than the power-on reference voltage V refh, the first hysteresis comparator outputs a high level, after the delay time T1 of the first programmable delay circuit, the combination logic module outputs a high level, and the write protection of the SPI FLASH The input of the foot WP# is high level, the SPI FLASH is released from the write protection state, and the system can erase, read and write the SPI FLASH.
  • the combination logic module When the system is powered off, if the power supply voltage is higher than the power-down reference voltage V refl , the second hysteresis comparator outputs a high level, and after the delay time T2 of the second programmable delay circuit, the combination logic module outputs a high level.
  • the input of SPI FLASH write protection pin WP# is high level, and the system can erase, read and write the SPI FLASH.
  • the second hysteresis comparator If the power supply voltage is lower than the power-down reference voltage V refl , the second hysteresis comparator outputs a low level, after the delay time T2 of the second programmable delay circuit, the combination logic module outputs a low level, and the write protection of the SPI FLASH
  • the input of the foot WP# is low level, the SPI FLASH is in the write protection state, and the system cannot erase or write the SPI FLASH. That is to say, after the T2 time after the SPI FLASH block is powered off, the SPI FLASH is in the write protection state, and the data area will not be overwritten.
  • T1 and T2 are both greater than or equal to 0, and the two may be the same or different.
  • step S3 may be removed to directly determine whether to make the SPI FLASH in a write-protected state according to the comparison result.
  • the system and method for preventing data corruption in the SPI FLASH switching machine of the present invention can also be used in an automatic control system for solving the instability of the switch.
  • the similar technical solutions that utilize the principles and structures of the present invention are all within the scope of the present invention and will not be further described herein.
  • the system and method for preventing data corruption in the SPI FLASH switching machine of the present invention can solve the data destruction risk caused by the noise of the switch machine through the hysteresis comparator circuit; the system can be flexibly set according to different systems. And the time when the system is powered off to trigger protection; the chip-level solution is used to better protect the data in the FLASH and improve the stability of the system. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

一种防止SPI FLASH开关机时数据破坏的系统及方法，系统设置在系统电源与SPI FLASH之间，包括电源采样模块(1)、上电电压处理模块(2)、下电电压处理模块(3)和组合逻辑模块(4)；电源采样模块(1)分别与系统电源、上电电压处理模块(2)和下电电压处理模块(3)相连；上电电压处理模块(2)和下电电压处理模块(3)均与组合逻辑模块(4)相连；组合逻辑模块(4)再与SPI FLASH相连，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，SPI FLASH处于写保护状态。所述防止SPI FLASH开关机时数据破坏的系统及方法解决了开关机噪声带来的数据破坏风险；根据不同的系统灵活地设定系统上电和下电触发保护的时间，提升了系统的稳定性。

Description

一种防止SPI FLASH开关机时数据破坏的系统及方法 技术领域
本发明涉及SPI FLASH的数据保护的技术领域，特别是涉及一种防止SPI FLASH开关机时数据破坏的系统及方法。
背景技术
SPI(Serial Peripheral Interface)是串行外设接口。SPI FLASH则是串行存储器，通过SPI口进行读写。
当系统开关机时，由于电源噪声、系统不稳定或者开关机过快等误动作，很容易引起FLASH数据区被擦除或者数据被改写。由于SPI FLASH的接口单一，指令和协议相对简单，在系统开关机时，SPI FLASH的存储区更容易被破坏，会导致系统不能启动。因此，需要对SPI FLASH进行开关机时的数据保护。
如申请号为201210226126.1、发明名称为《用于闪存的掉电保护电路及掉电保护时序电路》的中国发明专利公开一种用于闪存的掉电保护电路，包括电源监控模块和电子开关单元，所述电源监控模块连接电子开关单元，所述电子开关单元用于连接闪存的写保护引脚；所述电源监控模块用于获取外部供电电源，并在所述外部供电电源的电压小于掉电阈值时控制所述电子开关单元输出低电平给所述写保护引脚；所述电子开关单元包括第一分压电阻、第二分压电阻、下拉电阻及第一开关管，所述第一开关管包括输入端、输出端及控制端，所述第一开关管的输出端用于连接所述写保护引脚，且所述第一开关管的输出端通过所述下拉电阻接地；所述第一开关管的输入端用于连接所述闪存的电源，且所述第一开关管的输入端通过所述第二分压电阻连接所述第一开关管的控制端；所述第一开关管的控制端通过所述第一分压电阻连接所述电源监控模块。当外部供电电源的电压跌落至掉电阈值以下时，能够将闪存的写保护引脚拉至低电平，闪存被置于写保护状态，直至掉电结束。因此在掉电过程中，闪存存储的数据不会被擦除。
然而，对于SPI FLASH而言，上述解决方案存在以下缺陷：
(1)无法消除开关机过程中的“开关噪声”所引起的数据破坏；
(2)无法消除上电过程中系统不稳定所导致的数据破坏；
(3)系统掉电后触发保护的时间不精准，导致存在数据破坏的风险。
(4)采用分立器件的参数不稳定，也会带来系统误动作，从而导致数据破坏。
另外，为了防止FLASH数据被破坏，通常对FLASH特定的区域通过加密算法进行保护。但该方案仅适用于FLASH底层驱动或者一些特殊数据区，无法涵盖到FLASH的全部数据区，同时也会占用处理器的资源，使系统复杂化，引入了系统不稳定因素。
现有技术中，为了保护FLASH数据区，另一种常见的方案为采用数据双备份。但这会增加FLASH的容量，增加系统开销，且缺乏对开关机的采样，判定和输出控制，无法从根本上避免SPI FLASH开关机时出现的数据破坏。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种防止SPI FLASH开关机时数据破坏的系统及方法，通过迟滞比较器电路来解决开关机噪声带来的数据破坏风险，也能根据不同的系统灵活地设定系统上电和系统下电触发保护的时间，从而更好的保护FLASH中的数据，提升系统的稳定性。
为实现上述目的及其他相关目的，本发明提供一种防止SPI FLASH开关机时数据破坏的系统，设置在系统电源与SPI FLASH之间，包括电源采样模块、上电电压处理模块、下电电压处理模块和组合逻辑模块；所述电源采样模块用于对系统电源进行采样，以获取上电采样电压或下电采样电压；所述上电电压处理模块与所述电源采样模块相连，包括相连的第一迟滞比较器和第一可编程延时电路；所述第一迟滞比较器用于比较上电采样电压和上电参考电压，并将比较结果输入所述第一可编程延时电路；所述第一可编程延时电路用于对所述第一迟滞比较器的比较结果进行延时第一时间；所述下电电压处理模块与所述电源采样模块相连，包括相连的第二迟滞比较器和第二可编程延时电路；所述第二迟滞比较器用于比较下电采样电压和下电参考电压，并将比较结果输入所述第二可编程延时电路；所述第二可编程延时电路用于对所述第二迟滞比较器的比较结果进行延时第二时间；所述组合逻辑模块分别与所述上电电压处理模块和所述下电电压处理模块相连，用于根据所述上电电压处理模块或所述下电电压处理模块的输出，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPI FLASH的写保护引脚，使得SPI FLASH处于写保护状态。
根据上述的防止SPI FLASH开关机时数据破坏的系统，其中：所述第一迟滞比较器在上电采样电压高于上电参考电压时输出高电平，在上电采样电压低于上电参考电压时输出低电平；所述第二迟滞比较器在下电采样电压高于下电参考电压时输出高电平，在下电采样电压低于下电参考电压时输出低电平。
进一步地，根据上述的防止SPI FLASH开关机时数据破坏的系统，其中：当所述第一迟 滞比较器输出低电平时，所述组合逻辑模块输出低电平，SPI FLASH处于写保护状态；当所述第一迟滞比较器输出高电平时，所述组合逻辑模块输出高电平，SPI FLASH不处于写保护状态；当所述第二迟滞比较器输出低电平时，所述组合逻辑模块输出低电平，SPI FLASH处于写保护状态；当所述第二迟滞比较器输出高电平时，所述组合逻辑模块输出高电平，SPIFLASH不处于写保护状态。
根据上述的防止SPI FLASH开关机时数据破坏的系统，其中：所述上电采样电压由上升沿触发；所述下电采样电压由下降沿触发。
根据上述的防止SPI FLASH开关机时数据破坏的系统，其中：所述上电电压处理模块仅包括第一迟滞比较器，所述第一迟滞比较器将比较结果输入所述组合逻辑模块；所述下电电压处理模块仅包括第二迟滞比较器，所述第二迟滞比较器将比较结果输入所述组合逻辑模块。
同时，本发明还提供一种防止SPI FLASH开关机时数据破坏的方法，包括以下步骤：
步骤S1、对系统电源进行采样，以获取采样电压；
步骤S2、若采用电压为上电采样电压，将采样电压与上电参考电压相比较；若采样电压为下电采样电压，将采样电压与下电参考电压相比较；
步骤S3、将比较结果进行延时；
步骤S4、根据延时后的比较结果，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPI FLASH的写保护引脚，使得SPI FLASH处于写保护状态，数据区不会被改写。
根据上述的防止SPI FLASH开关机时数据破坏的方法，其中：所述步骤S2中，将采样电压与上电参考电压相比较时，采样电压高于上电参考电压时，比较结果输出为高电平；采样电压低于上电参考电压时，比较结果输出为低电平。
根据上述的防止SPI FLASH开关机时数据破坏的方法，其中：所述步骤S2中，将采样电压与下电参考电压相比较时，采样电压高于下电参考电压时，比较结果输出为高电平；采样电压低于下电参考电压时，比较结果输出为低电平。
进一步地，根据上述的防止SPI FLASH开关机时数据破坏的方法，其中：所述步骤S4中，当比较结果输出为高电平时，SPI FLASH不处于写保护状态；当比较结果输出低电平时，SPIFLASH处于写保护状态。
根据上述的防止SPI FLASH开关机时数据破坏的方法，其中：不进行步骤S3中的延时，直接根据比较结果，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPI FLASH的写保护引脚，使得SPI FLASH处于写保护状态。
如上所述，本发明的防止SPI FLASH开关机时数据破坏的系统及方法，具有以下有益效果：
(1)能够通过迟滞比较器电路来解决开关机噪声带来的数据破坏风险；
(2)能够根据不同的系统灵活地设定系统上电和系统下电触发保护的时间；
(3)采用芯片级解决方案，更好地保护了FLASH中的数据，提升了系统的稳定性。
附图说明
图1显示为本发明的防止SPI FLASH开关机时数据破坏的系统的一个优选实施例的结构示意图；
图2显示为本发明的防止SPI FLASH开关机时数据破坏的系统的另一个优选实施例的结构示意图；
图3显示为本发明的防止SPI FLASH开关机时数据破坏的方法的一个优选实施例的流程图。
元件标号说明
1                  电源采样模块
2                  上电电压处理模块
21                 第一迟滞比较器
22                 第一可编程延时电路
3                  下电电压处理模块
31                 第二迟滞比较器
32                 第二可编程延时电路
4                  组合逻辑模块
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式 中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
参照图1，在本发明的一个优选实施例中，本发明的防止SPI FLASH开关机时数据破坏的系统设置在系统电源与SPI FLASH之间，包括电源采样模块1、上电电压处理模块2、下电电压处理模块3和组合逻辑模块4。其中，电源采样模块1分别与系统电源、上电电压处理模块2和下电电压处理模块3相连；上电电压处理模块2和下电电压处理模块3均与组合逻辑模块4相连；组合逻辑模块4再与SPI FLASH相连。
电源采样模块1用于对系统电源进行采样，以获取上电采样电压或下电采样电压。具体地，系统电源可以采用3v3或其它外部电源。
需要说明的是，上电采样电压由上升沿触发；下电采样电压由下降沿触发。故根据触发的上升沿或者下降沿，即可判断所获取的是上电采样电压还是下电采样电压。
上电电压处理模块2包括相连的第一迟滞比较器21和第一可编程延时电路22。
第一迟滞比较器21用于比较上电采样电压和上电参考电压Vrefh，并将比较结果输入第一可编程延时电路22。具体地，第一迟滞比较器21在上电采样电压高于上电参考电压Vrefh时输出高电平，在上电采样电压低于上电参考电压时输出低电平。
第一可编程延时电路22用于对第一迟滞比较器21的比较结果进行延时第一时间T1。通过不同的T1的选择，能够根据不同的系统灵活地设定系统上电触发保护的时间。
下电电压处理模块包括相连的第二迟滞比较器31和第二可编程延时电路32。
第二迟滞比较器31用于比较下电采样电压和下电参考电压Vrefl，并将比较结果输入第二可编程延时电路32。具体地，第二迟滞比较器31在下电采样电压高于下电参考电压Vrefl时输出高电平，在下电采样电压低于下电参考电压时输出低电平。
第二可编程延时电路32用于对第二迟滞比较器31的比较结果进行延时第二时间T2。通过不同的T2的选择，能够根据不同的系统灵活地设定系统下电触发保护的时间。
组合逻辑模块4用于根据上电电压处理模块2或下电电压处理模块4的输出，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPIFLASH的写保护引脚，使得SPI FLASH处于写保护状态，数据区不会被改写。
具体地，当第一迟滞比较器输出高电平时，组合逻辑模块输出高电平；当第一迟滞比较器输出低电平时，组合逻辑模块输出低电平；当第二迟滞比较器输出高电平时，组合逻辑模块输出高电平；当第二迟滞比较器输出低电平时，组合逻辑模块输出低电平。
设定SPI FLASH的写保护引脚WP#的使能信号为高电平，禁能信号为低电平。在本发明 的防止SPI FLASH开关机时数据破坏的系统中，当系统上电时，若电源电压低于上电参考电压Vrefh，第一迟滞比较器输出低电平，经过第一可编程延时电路延时时间T1后，组合逻辑模块输出低电平，则SPI FLASH的写保护引脚WP#的输入为低电平，SPI FLASH处于写保护状态，系统不能对SPI FLASH进行写操作，SPI FLASH区块被保护。也就是说，SPI FLASH区块上电后T1时间后，SPI FLASH即处于写保护状态，数据区不会被改写。优选地，当T1＝0时，只要电源电压低于上电参考电压Vrefh，SPI FLASH即处于写保护状态，数据区不会被改写。
若电源电压高于上电参考电压Vrefh，第一迟滞比较器输出高电平，经过第一可编程延时电路延时时间T1后，组合逻辑模块输出高电平，SPI FLASH的写保护引脚WP#的输入为高电平，SPI FLASH解除写保护状态，系统能够对SPI FLASH进行擦除、读写等操作。
当系统下电时，若当电源电压高于下电参考电压Vrefl，第二迟滞比较器输出高电平，经过第二可编程延时电路延时时间T2后，组合逻辑模块输出高电平，SPI FLASH的写保护引脚WP#的输入为高电平，系统能对SPI FLASH进行擦除、读写等操作。
若电源电压低于下电参考电压Vrefl，第二迟滞比较器输出低电平，经过第二可编程延时电路延时时间T2后，组合逻辑模块输出低电平，SPI FLASH的写保护引脚WP#的输入为低电平，SPI FLASH处于写保护状态，系统不能对SPI FLASH进行擦除或者写操作。也就是说，SPI FLASH区块下电后T2时间后，SPI FLASH即处于写保护状态，数据区不会被改写。优选地，当T2＝0时，只要电源电压低于下电参考电压Vrefl，SPI FLASH即处于写保护状态，数据区不会被改写。
其中，T1和T2的取值均大于等于0，二者可以相同，也可以不同。具体取决于系统电源的负载、开关波形及系统布线等因素。故T1和T2可以依据具体系统灵活且独立的设置。
因此，在本发明的防止SPI FLASH开关机时数据破坏的系统中，设定回差电压＝上电参考电压Vrefh-下电参考电压Vrefl。根据第一迟滞比较器和第二迟滞比较器的参数配置来设定不同的回差电压，即使系统电源的产生一定的“电源噪声”或者“电源抖动”，系统仍然维持原正常状态，SPI FLASH处于写保护状态，数据区不会被改写。因此，本发明中的回差电压的设计对“开关噪声“或者系统工作中的”电源噪声”具有很好的抑制能力，有效防止了对SPIFLASH区块的破坏。
如图2所示，在本发明的另一个优选实施例中，本发明的防止SPI FLASH开关机时数据破坏的系统设置在系统电源与SPI FLASH之间，包括电源采样模块1、上电电压处理模块2、下电电压处理模块3和组合逻辑模块4。其中，电源采样模块1分别与系统电源、上电电压处理模块2和下电电压处理模块3相连；上电电压处理模块2和下电电压处理模块3均与组 合逻辑模块4相连；组合逻辑模块4再与SPI FLASH相连。
电源采样模块1用于对系统电源进行采样。具体地，系统电源可以采用3v3或其它外部电源。
需要说明的是，上电采样电压由上升沿触发；下电采样电压由下降沿触发。故根据触发的上升沿或者下降沿，即可判断所获取的是上电采样电压还是下电采样电压。
上电电压处理模块2包括第一迟滞比较器21。
第一迟滞比较器21用于比较上电采样电压和上电参考电压Vrefh，并将比较结果输入组合逻辑模块4。具体地，第一迟滞比较器21在上电采样电压高于上电参考电压Vrefh时输出高电平，在上电采样电压低于上电参考电压时输出低电平。
下电电压处理模块3包括第二迟滞比较器31。
第二迟滞比较器31用于比较下电采样电压和下电参考电压Vrefl，并将比较结果输入组合逻辑模块4。具体地，第二迟滞比较器31在下电采样电压高于下电参考电压Vrefl时输出高电平，在下电采样电压低于下电参考电压时输出低电平。
组合逻辑模块4用于根据上电电压处理模块2或下电电压处理模块3的输出，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPIFLASH的写保护引脚，使得SPI FLASH处于写保护状态，数据区不会被改写。
具体地，当第一迟滞比较器输出高电平时，组合逻辑模块输出高电平；当第一迟滞比较器输出低电平时，组合逻辑模块输出低电平；当第二迟滞比较器输出高电平时，组合逻辑模块输出高电平；当第二迟滞比较器输出低电平时，组合逻辑模块输出低电平。
设定SPI FLASH的写保护引脚WP#的使能信号为高电平，禁能信号为低电平。在本发明的防止SPI FLASH开关机时数据破坏的系统中，当系统上电时，若电源电压低于上电参考电压Vrefh，第一迟滞比较器输出低电平，组合逻辑模块输出低电平，则SPI FLASH的写保护引脚WP#的输入为低电平，SPI FLASH处于写保护状态，系统不能对SPI FLASH进行写操作，SPIFLASH区块被保护。也就是说，只要电源电压低于上电参考电压Vrefh，SPI FLASH即处于写保护状态，数据区不会被改写。
若电源电压高于上电参考电压Vrefh，第一迟滞比较器输出高电平，组合逻辑模块输出高电平，SPI FLASH的写保护引脚WP#的输入为高电平，SPI FLASH解除写保护状态，系统能够对SPI FLASH进行擦除、读写等操作。
当系统下电时，若当电源电压高于下电参考电压Vrefl，第二迟滞比较器输出高电平，组合逻辑模块输出高电平，SPI FLASH的写保护引脚WP#的输入为高电平，系统能对SPI FLASH 进行擦除、读写等操作。
若电源电压低于下电参考电压Vrefl，第二迟滞比较器输出低电平，组合逻辑模块输出低电平，SPI FLASH的写保护引脚WP#的输入为低电平，SPI FLASH进入写保护状态，系统不能对SPI FLASH进行擦除或者写操作。也就是说，只要电源电压低于下电参考电压Vrefl，SPI FLASH即处于写保护状态，数据区不会被改写。
需要说明的是，本发明的防止SPI FLASH开关机时数据破坏的系统可以作为单独的电路设置在系统电源与SPI FLASH之间，也可以集成在SPI FLASH芯片内部或主芯片的FLASH控制器内部，以增加ISIC的功能。
参照图3，在本发明的一个优选实施例中，本发明的防止SPI FLASH开关机时数据破坏的方法包括以下步骤：
步骤S1、对系统电源进行采样，以获取采样电压。
具体地，系统电源可以采用3v3或其它外部电源。通过电源采样模块对系统电源进行采样。
步骤S2、若采用电压为上电采样电压，将采样电压与上电参考电压Vrefh相比较；若采样电压为下电采样电压，将采样电压与下电参考电压Vrefl相比较。
需要说明的是，上电采样电压由上升沿触发；下电采样电压由下降沿触发。故根据触发的上升沿或者下降沿，即可判断所获取的是上电采样电压还是下电采样电压。
通过第一迟滞比较器比较上电采样电压和上电参考电压Vrefh。具体地，第一迟滞比较器在上电采样电压高于上电参考电压Vrefh时输出高电平，在上电采样电压低于上电参考电压时输出低电平。
通过第二迟滞比较器比较下电采样电压和下电参考电压Vrefl。具体地，第二迟滞比较器在下电采样电压高于下电参考电压Vrefl时输出高电平，在下电采样电压低于下电参考电压时输出低电平。
步骤S3、将比较结果进行延时。
通过第一可编程延时电路对第一迟滞比较器的比较结果进行延时第一时间T1。
通过第二可编程延时电路对第二迟滞比较器的比较结果进行延时第二时间T2。
步骤S4、根据延时后的比较结果，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPI FLASH的写保护引脚，使得SPI FLASH处于写保护状态，数据区不会被改写。
具体地，组合逻辑模块根据延时后的比较结果，当系统电源的上电电压低于上电参考电 压或者下电电压低于下电参考电压时，输出禁能信号至SPI FLASH的写保护引脚，使得SPIFLASH处于写保护状态，数据区不会被改写。
具体地，当第一迟滞比较器输出高电平时，组合逻辑模块输出高电平；当第一迟滞比较器输出低电平时，组合逻辑模块输出低电平；当第二迟滞比较器输出高电平时，组合逻辑模块输出高电平；当第二迟滞比较器输出低电平时，组合逻辑模块输出低电平。
设定SPI FLASH的写保护引脚WP#的使能信号为高电平，禁能信号为低电平。在本发明的防止SPI FLASH开关机时数据破坏的系统中，当系统上电时，若电源电压低于上电参考电压Vrefh，第一迟滞比较器输出低电平，经过第一可编程延时电路延时时间T1后，组合逻辑模块输出低电平，则SPI FLASH的写保护引脚WP#的输入为低电平，SPI FLASH处于写保护状态，系统不能对SPI FLASH进行写操作，SPI FLASH区块被保护。也就是说，SPI FLASH区块上电后T1时间后，SPI FLASH即处于写保护状态，数据区不会被改写。优选地，当T1＝0时，只要电源电压低于上电参考电压Vrefh，SPI FLASH即处于写保护状态，数据区不会被改写。
若电源电压高于上电参考电压Vrefh，第一迟滞比较器输出高电平，经过第一可编程延时电路延时时间T1后，组合逻辑模块输出高电平，SPI FLASH的写保护引脚WP#的输入为高电平，SPI FLASH解除写保护状态，系统能够对SPI FLASH进行擦除、读写等操作。
当系统下电时，若当电源电压高于下电参考电压Vrefl，第二迟滞比较器输出高电平，经过第二可编程延时电路延时时间T2后，组合逻辑模块输出高电平，SPI FLASH的写保护引脚WP#的输入为高电平，系统能对SPI FLASH进行擦除、读写等操作。
若电源电压低于下电参考电压Vrefl，第二迟滞比较器输出低电平，经过第二可编程延时电路延时时间T2后，组合逻辑模块输出低电平，SPI FLASH的写保护引脚WP#的输入为低电平，SPI FLASH处于写保护状态，系统不能对SPI FLASH进行擦除或者写操作。也就是说，SPI FLASH区块下电后T2时间后，SPI FLASH即处于写保护状态，数据区不会被改写。优选地，当T2＝0时，只要电源电压低于下电参考电压Vrefl，SPI FLASH即处于写保护状态，数据区不会被改写。
其中，T1和T2的取值均大于等于0，二者可以相同，也可以不同。
优选地，在本发明的另一个优选实施例中，当T1和T0均取值为0时，可以去除步骤S3，直接根据比较结果，判断是否使SPI FLASH处于写保护状态。
同时，本发明的防止SPI FLASH开关机时数据破坏的系统及方法也可以用于解决开关机不稳定的自动控制系统中。凡是利用本发明的原理和结构的相似技术方案均在本发明的保护范围之内，在此不再赘述。
综上所述，本发明的防止SPI FLASH开关机时数据破坏的系统及方法能够通过迟滞比较器电路来解决开关机噪声带来的数据破坏风险；能够根据不同的系统灵活地设定系统上电和系统下电触发保护的时间；采用芯片级解决方案，更好地保护了FLASH中的数据，提升了系统的稳定性。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种防止SPI FLASH开关机时数据破坏的系统，其特征在于：设置在系统电源与SPI FLASH之间，包括电源采样模块、上电电压处理模块、下电电压处理模块和组合逻辑模块；
    所述电源采样模块用于对系统电源进行采样，以获取上电采样电压或下电采样电压；
    所述上电电压处理模块与所述电源采样模块相连，包括相连的第一迟滞比较器和第一可编程延时电路；
    所述第一迟滞比较器用于比较上电采样电压和上电参考电压，并将比较结果输入所述第一可编程延时电路；
    所述第一可编程延时电路用于对所述第一迟滞比较器的比较结果进行延时第一时间；
    所述下电电压处理模块与所述电源采样模块相连，包括相连的第二迟滞比较器和第二可编程延时电路；
    所述第二迟滞比较器用于比较下电采样电压和下电参考电压，并将比较结果输入所述第二可编程延时电路；
    所述第二可编程延时电路用于对所述第二迟滞比较器的比较结果进行延时第二时间；
    所述组合逻辑模块分别与所述上电电压处理模块和所述下电电压处理模块相连，用于根据所述上电电压处理模块或所述下电电压处理模块的输出，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPI FLASH的写保护引脚，使得SPI FLASH处于写保护状态。
  2. 根据权利要求1所述的防止SPI FLASH开关机时数据破坏的系统，其特征在于：所述第一迟滞比较器在上电采样电压高于上电参考电压时输出高电平，在上电采样电压低于上电参考电压时输出低电平；所述第二迟滞比较器在下电采样电压高于下电参考电压时输出高电平，在下电采样电压低于下电参考电压时输出低电平。
  3. 根据权利要求2所述的防止SPI FLASH开关机时数据破坏的系统，其特征在于：当所述第一迟滞比较器输出低电平时，所述组合逻辑模块输出低电平，SPI FLASH处于写保护状态；当所述第一迟滞比较器输出高电平时，所述组合逻辑模块输出高电平，SPI FLASH不处于写保护状态；当所述第二迟滞比较器输出低电平时，所述组合逻辑模块输出低电平，SPI FLASH处于写保护状态；当所述第二迟滞比较器输出高电平时，所述组合逻辑模块输出高电平，SPI FLASH不处于写保护状态。
  4. 根据权利要求1所述的防止SPI FLASH开关机时数据破坏的系统，其特征在于：所述上电采样电压由上升沿触发；所述下电采样电压由下降沿触发。
  5. 根据权利要求1所述的防止SPI FLASH开关机时数据破坏的系统，其特征在于：所述上电电压处理模块仅包括第一迟滞比较器，所述第一迟滞比较器将比较结果输入所述组合逻辑模块；所述下电电压处理模块仅包括第二迟滞比较器，所述第二迟滞比较器将比较结果输入所述组合逻辑模块。
  6. 一种防止SPI FLASH开关机时数据破坏的方法，其特征在于：包括以下步骤：
    步骤S1、对系统电源进行采样，以获取采样电压；
    步骤S2、若采用电压为上电采样电压，将采样电压与上电参考电压相比较；若采样电压为下电采样电压，将采样电压与下电参考电压相比较；
    步骤S3、将比较结果进行延时；
    步骤S4、根据延时后的比较结果，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPI FLASH的写保护引脚，使得SPI FLASH处于写保护状态，数据区不会被改写。
  7. 根据权利要求6所述的防止SPI FLASH开关机时数据破坏的方法，其特征在于：所述步骤S2中，将采样电压与上电参考电压相比较时，采样电压高于上电参考电压时，比较结果输出为高电平；采样电压低于上电参考电压时，比较结果输出为低电平。
  8. 根据权利要求6所述的防止SPI FLASH开关机时数据破坏的方法，其特征在于：所述步骤S2中，将采样电压与下电参考电压相比较时，采样电压高于下电参考电压时，比较结果输出为高电平；采样电压低于下电参考电压时，比较结果输出为低电平。
  9. 根据权利要求7或8所述的防止SPI FLASH开关机时数据破坏的方法，其特征在于：所述步骤S4中，当比较结果输出为高电平时，SPI FLASH不处于写保护状态；当比较结果输出低电平时，SPI FLASH处于写保护状态。
  10. 根据权利要求6所述的防止SPI FLASH开关机时数据破坏的方法，其特征在于：不进行 步骤S3中的延时，直接根据比较结果，当系统电源的上电电压低于上电参考电压或者下电电压低于下电参考电压时，输出禁能信号至SPI FLASH的写保护引脚，使得SPI FLASH处于写保护状态。
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