WO2019007112A1 - NAND Flash数据保护电路 - Google Patents

NAND Flash数据保护电路 Download PDF

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Publication number
WO2019007112A1
WO2019007112A1 PCT/CN2018/081175 CN2018081175W WO2019007112A1 WO 2019007112 A1 WO2019007112 A1 WO 2019007112A1 CN 2018081175 W CN2018081175 W CN 2018081175W WO 2019007112 A1 WO2019007112 A1 WO 2019007112A1
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Prior art keywords
protection
pull
signal
resistor
unit
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PCT/CN2018/081175
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English (en)
French (fr)
Inventor
郭坚湖
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深圳市英蓓特科技有限公司
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Publication of WO2019007112A1 publication Critical patent/WO2019007112A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells

Definitions

  • the utility model relates to the field of circuits, in particular to a NAND Flash data protection circuit.
  • NAND Flash As a non-power-down volatile storage device, NAND Flash is widely used in a large number of devices, especially embedded devices, due to its large capacity and price. However, in actual use, NAND Fash often suffers from data loss or equipment failure caused by errors.
  • the write protection of the NAND Flash must be performed after the software system is in effect, and then the NAND Flash cannot be protected before the software system functions. At this time, the power supply of the entire system is unstable or data. Interference causes NAND Flash to be subject to abnormal instructions, which may lead to critical data errors or even bad blocks in the area where the system stores critical data, resulting in equipment failure.
  • the protection of NAND Flash is based on the host output.
  • the host needs to configure the write protection port of NAND Flash.
  • NAND Flash The write protection port of the circuit, that is, the WP pin writes 0, and the WP pin writes 1 at other times.
  • the technical problem to be solved by the present invention is to provide an improved NAND Flash data protection circuit.
  • the technical solution adopted by the utility model to solve the technical problem thereof is to provide a NAND Flash data protection circuit, including
  • a first protection unit accessing the data signal and outputting the first protection signal
  • a second protection unit that accesses a power-on signal and outputs a second protection signal, and the second protection unit and the first protection unit form a logical relationship;
  • a pull-up pull-down unit is respectively connected to the first protection unit and the second protection unit, and the pull-up pull-down unit writes protection to the NAND Flash circuit according to the first protection signal and the second protection signal
  • the port outputs a data protection signal.
  • the first protection unit includes a first diode and a first pull-up resistor, and the first diode is positively connected to the pull-up pull-down unit, thereby outputting the first protection signal, a diode negative electrode is connected to the data signal to access the data signal; the first pull-up resistor is connected to the power source at one end and the first diode negative terminal is connected to the other end;
  • the second protection unit includes a second diode and a second pull-up resistor, the second diode is positively connected to the pull-up pull-down unit, thereby outputting the second protection signal, and the negative connection is connected to the power supply The signal is thereby connected to the power start signal; the second pull-up resistor is connected to the power supply at one end and the second diode negative terminal is connected to the other end.
  • the pull-up pull-down unit includes a total pull-up resistor and a pull-down resistor, the total pull-up resistor is connected to the power supply at one end, and the pull-down resistor is connected to the other end; the pull-up resistor is connected to the total pull-up resistor at one end, and the other One end is grounded; a connection point of the total pull-up resistor and the pull-down resistor is connected to a positive pole of the first diode and a positive pole of the second diode, thereby accessing the first protection signal and the second a protection signal; the connection point is further coupled to the write protection port to connect the data protection signal to the write protection port.
  • the first protection unit further comprises a first reserved resistor connected in parallel on the first diode.
  • the second protection unit further includes a second reserved resistor connected in parallel to the second diode.
  • the first protection unit and the second protection unit constitute a digital AND gate.
  • the utility model has the beneficial effects that the NAND Flash data protection circuit of the utility model adds a power-on signal to the data signal and the power source through a logic "AND" on the write protection port of the NAND Flash circuit.
  • the signal When the signal is high at the same time, it outputs a high level to the write protection port of the NAND Flash circuit, thus avoiding NAND Flash data loss and error when the system does not reach a steady state.
  • FIG. 1 is a block diagram of a NAND Flash data protection circuit in some embodiments of the present invention.
  • FIG. 2 is a circuit diagram of a NAND Flash data protection circuit in some embodiments of the present invention.
  • FIG. 1 illustrates a NAND Flash data protection circuit in some embodiments of the present invention for adding a power-on signal to a power-on signal on a write-protect port 50 of a NAND Flash circuit to enable a power-on signal and
  • the data signal is high at the same time, the high level is output to the write protection port 50 of the NAND flash circuit; and when the power start signal and the data signal are at least one low level, the low level is output to the write protection port 50 of the NAND flash circuit. Therefore, when the system does not reach a steady state, the NAND Flash circuit is write-protected by hardware. Understandably, after the system software works, it is operated by the software system to determine whether the write protection works or not.
  • the utility model has the advantages that it can be implemented simply and protects the NAND Flash at the hardware layer to prevent equipment failure due to NAND Flash data errors.
  • the NAND Flash data protection circuit in this embodiment includes a first protection unit 10, a second protection unit 20, and a pull-up pull-down unit 30, wherein the first protection unit 10 accesses the data signal and outputs the first protection signal, and the second protection The unit 20 is connected to a power start signal and outputs a second protection signal, and the pull-up pull-down unit 30 outputs a data protection signal according to the first protection signal and the second protection signal.
  • the first protection unit 10 accesses the data signal and outputs the first protection signal.
  • the first protection unit 10 includes a first diode D1 and a first pull-up resistor R71.
  • the negative electrode of the first diode D1 is connected to the data signal to access the data signal, and the first diode D1 is connected to the pull-up unit 30, and the first protection signal is output.
  • the first pull-up resistor R71 is connected to the power supply at one end, and the other end is connected to the negative terminal of the first diode D1.
  • the first pull-up resistor R71 is 1 k ⁇ .
  • the first protection unit 10 further includes a first reserved resistor connected in parallel to the first diode D1, or the first reserved resistor may not be provided.
  • the second protection unit 20 is connected to a power start signal and outputs a second protection signal.
  • the power start signal is the POWER GOOD signal of the system power supply. After the system power supply climbs to the normal threshold, the power supply system transmits the signal to the controller, and the signal is led to the circuit, because of the power supply of the NAND Flash circuit. It is also powered by the power system, so before the POWER GOOD signal is pulled high, the NAND Flash circuit is powered and the controller is already working. Therefore, after the POWER GOOD signal is increased, the system can work stably without abnormal operation.
  • the second protection unit 20 includes a second diode D2 and a second pull-up resistor R72.
  • the second diode D2 is connected to the power start signal to connect the power start signal, and the positive terminal is connected to the pull-down unit 30, thereby outputting the second. Protection signal.
  • the second pull-up resistor R72 is connected to the power supply at one end and the second diode D2 is connected to the other end.
  • the second pull-up resistor R72 is 1 k ⁇ .
  • the second protection unit 20 further includes a second reserved resistor connected in parallel to the second diode D2.
  • the second protection unit 20 and the first protection unit 10 constitute a logical relationship.
  • the advantage is that when the power-on signal and the data signal are simultaneously at a high level, the high level is output to the write protection port 50 of the NAND flash circuit; and when the power start signal and the data signal are at least one low level, the NAND flash circuit is turned to the NAND flash circuit.
  • the write protection port 50 outputs a low level.
  • the forms of the first protection unit 10 and the second protection unit 20 are not limited thereto, and may be other forms.
  • the first protection unit 10 and the second protection unit 20 constitute a digital AND gate.
  • the pull-up pull-down unit 30 is respectively connected to the first protection unit 10 and the second protection unit 20, and the pull-up pull-down unit 30 outputs a data protection signal to the write protection port 50 of the NAND Flash circuit according to the first protection signal and the second protection signal.
  • the pull-up pull-down unit 30 includes a total pull-up resistor R52 and a pull-down resistor R58.
  • the total pull-up resistor R52 is connected to the power supply at one end and the pull-down resistor R58 at the other end.
  • One end of the pull-down resistor R58 is connected to the total pull-up resistor R52, and the other end is grounded.
  • the total pull-up resistor R52 is 10 k ⁇ and the pull-down resistor R58 is 10 k ⁇ .
  • a connection point of the total pull-up resistor R52 and the pull-down resistor R58 is connected to the anode of the first diode D1 and the anode of the second diode D2, thereby accessing the first protection signal and the second protection signal.
  • the connection point is also connected to the write protection port 50 to connect the data protection signal to the write protection port 50.
  • the write protection port 50 is the NAND_WP pin in FIG.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

本实用新型公开了一种NAND Flash数据保护电路，包括第一保护单元，接入数据信号并输出第一保护信号；第二保护单元，接入一电源启动信号并输出第二保护信号，且所述第二保护单元和所述第一保护单元构成逻辑与关系；上拉下拉单元，分别与所述第一保护单元和所述第二保护单元相连接，所述上拉下拉单元根据所述第一保护信号和所述第二保护信号向NAND Flash电路的写保护端口输出数据保护信号。本实用新型的NAND Flash数据保护电路中，在NAND Flash电路的写保护端口上，通过数字"与"的方式增加了一个电源启动信号，在数据信号和电源启动信号同时为高电平时，才向NAND Flash电路的写保护端口输出高电平，从而在系统没有达到稳定状态时，避免NAND Flash数据丢失和错误。

Description

NAND Flash数据保护电路 技术领域
本实用新型涉及电路领域，尤其涉及一种NAND Flash数据保护电路。
 背景技术
NAND Flash作为非掉电易失性存储设备，以其大容量及价格等优势，在大量设备尤其是嵌入式设备中广泛使用。但是实际使用过程中，NAND Fash经常发生数据丢失或者错误导致设备故障的出现。
在现有技术中，对NAND Flash的写保护必须软件系统起作用之后才能执行的，那么在软件系统起作用之前，是无法对NAND Flash进行保护的，这个时候由于整个系统的电源不稳定或者数据干扰导致NAND Flash受到异常指令，则可能导致关键数据出错甚至系统存放关键数据的区域出现坏块，从而导致设备故障。
常见系统中，对NAND Flash的的保护是基于主机输出的，即要对NAND Flash中的内容进行保护，需要主机对NAND Flash的写保护端口进行配置，在需要对数据进行保护时，对NAND Flash电路的写保护端口即WP引脚写0，其他时候WP引脚写1。
 技术问题
本实用新型要解决的技术问题在于，提供一种改进的NAND Flash数据保护电路。
 技术解决方案
本实用新型解决其技术问题所采用的技术方案是：提供一种NAND Flash数据保护电路，包括
第一保护单元，接入数据信号并输出第一保护信号；
第二保护单元，接入一电源启动信号并输出第二保护信号，且所述第二保护单元和所述第一保护单元构成逻辑与关系；
上拉下拉单元，分别与所述第一保护单元和所述第二保护单元相连接，所述上拉下拉单元根据所述第一保护信号和所述第二保护信号向NAND Flash电路的写保护端口输出数据保护信号。
优选地，所述第一保护单元包括第一二极管和第一上拉电阻，所述第一二极管正极连接所述上拉下拉单元，从而输出所述第一保护信号，所述第一二极管负极连接所述数据信号从而接入所述数据信号；所述第一上拉电阻一端连接电源，另一端连接所述第一二极管负极；
所述第二保护单元包括第二二极管和第二上拉电阻，所述第二二极管正极连接所述上拉下拉单元，从而输出所述第二保护信号，负极连接所述电源启动信号从而接入所述电源启动信号；所述第二上拉电阻一端连接电源，另一端连接所述第二二极管负极。
优选地，所述上拉下拉单元包括总上拉电阻和下拉电阻，所述总上拉电阻一端连接电源，另一端连接所述下拉电阻；所述下拉电阻一端连接所述总上拉电阻，另一端接地；所述总上拉电阻和下拉电阻的连接点连接所述第一二极管的正极和所述第二二极管的正极，从而接入所述第一保护信号和所述第二保护信号；所述连接点还连接所述写保护端口，从而将所述数据保护信号接出至所述写保护端口。
优选地，所述第一保护单元还包括并联在所述第一二极管上的第一预留电阻。
优选地，所述第二保护单元还包括并联在所述第二二极管上的第二预留电阻。
优选地，所述第一保护单元和所述第二保护单元构成数字与门。
 有益效果
实施本实用新型的有益效果是：本实用新型的NAND Flash数据保护电路中，在NAND Flash电路的写保护端口上，通过逻辑“与”的方式增加了一个电源启动信号，在数据信号和电源启动信号同时为高电平时，才向NAND Flash电路的写保护端口输出高电平，从而在系统没有达到稳定状态时，避免NAND Flash数据丢失和错误。
附图说明                                                   
下面将结合附图及实施例对本实用新型作进一步说明，附图中：
图1是本实用新型一些实施例中NAND Flash数据保护电路的模块示意图；
图2是本实用新型一些实施例中NAND Flash数据保护电路的电路图。
 本发明的最佳实施方式
为了对本实用新型的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本实用新型的具体实施方式。
如图1示出了本实用新型一些实施例中的NAND Flash数据保护电路，用于在NAND Flash电路的写保护端口50上通过逻辑“与”的方式增加一个电源启动信号，使得电源启动信号和数据信号同时为高电平时，向NAND Flash电路的写保护端口50输出高电平；而在电源启动信号和数据信号至少一个为低电平时，向NAND Flash电路的写保护端口50输出低电平，从而在系统没有达到稳定状态时，通过硬件方式对NAND Flash电路进行写保护。可以理解地，系统软件起作用之后，由软件系统操作，决定写保护起作用与否。本实用新型的好处是，简单可实施，在硬件层面对NAND Flash进行保护，防止因NAND Flash数据出错导致设备故障。
本实施例中的NAND Flash数据保护电路包括第一保护单元10、第二保护单元20和上拉下拉单元30，其中，第一保护单元10接入数据信号并输出第一保护信号，第二保护单元20接入一电源启动信号并输出第二保护信号，上拉下拉单元30根据第一保护信号和第二保护信号输出数据保护信号。
其中，第一保护单元10接入数据信号并输出第一保护信号。具体地，结合图2所示，第一保护单元10包括第一二极管D1和第一上拉电阻R71。第一二极管D1负极连接数据信号从而接入数据信号，第一二极管D1正极连接上拉下拉单元30，从而输出第一保护信号。第一上拉电阻R71一端连接电源，另一端连接第一二极管D1负极。优选地，第一上拉电阻R71为1kΩ。作为选择，第一保护单元10还包括并联在第一二极管D1上的第一预留电阻，或者，第一预留电阻也可以不设置。
第二保护单元20接入一电源启动信号并输出第二保护信号。需要说明的是，电源启动信号为系统电源的POWER GOOD信号，在系统电源都爬升到正常的阀值之后由电源系统传给控制器，同时将此信号引到本电路，由于NAND Flash电路的供电也是由电源系统供电，所以在POWER GOOD信号拉高之前，NAND Flash电路供电已经稳定，同时控制器也已经工作。所以在增加了POWER GOOD信号拉高之后，系统可以稳定工作，不会产生异常操作。
第二保护单元20包括第二二极管D2和第二上拉电阻R72，第二二极管D2负极连接电源启动信号从而接入电源启动信号，正极连接上拉下拉单元30，从而输出第二保护信号。第二上拉电阻R72一端连接电源，另一端连接第二二极管D2负极。优选地，第二上拉电阻R72为1kΩ。作为选择，第二保护单元20还包括并联在第二二极管D2上的第二预留电阻。
本实施例中，第二保护单元20和第一保护单元10构成逻辑与关系。这样的好处是，电源启动信号和数据信号同时为高电平时，向NAND Flash电路的写保护端口50输出高电平；而在电源启动信号和数据信号至少一个为低电平时，向NAND Flash电路的写保护端口50输出低电平。在实际应用过程中，第一保护单元10和第二保护单元20的形式不限于此，还可以为其他形式，例如，第一保护单元10和第二保护单元20构成数字与门。
上拉下拉单元30分别与第一保护单元10和第二保护单元20相连接，上拉下拉单元30根据第一保护信号和第二保护信号向NAND Flash电路的写保护端口50输出数据保护信号。具体地，上拉下拉单元30包括总上拉电阻R52和下拉电阻R58，总上拉电阻R52一端连接电源，另一端连接下拉电阻R58。下拉电阻R58一端连接总上拉电阻R52，另一端接地。优选地，总上拉电阻R52为10kΩ，下拉电阻R58为10kΩ。总上拉电阻R52和下拉电阻R58的连接点连接第一二极管D1的正极和第二二极管D2的正极，从而接入第一保护信号和第二保护信号。连接点还连接写保护端口50，从而将数据保护信号接出至写保护端口50，需要说明的是，写保护端口50在图2中为NAND_WP引脚。
以下结合图1和图2对本实施例中的电路原理进行说明。当数据信号和电源启动信号至少一个为低电平时，第一二极管D1和/或第二二极管D2导通，总上拉电阻R52和下拉电阻R58的连接点电位被拉低，即此时NAND_WP引脚输出的数据保护信号为低电平；当数据信号和电源启动信号均为高电平时，第一二极管D1和第二二极管D2均截止，总上拉电阻R52和下拉电阻R58的连接点被拉高，即NAND_WP引脚输出的数据保护信号为高电平。从而可实现本实用新型的在系统失效或者不稳定的情况下由硬件进行写保护、软件起作用之后由软件控制写保护的功能。
 序列表自由内容
以上所述仅是本实用新型的优选实施方式，本实用新型的保护范围并不仅局限于上述实施例，凡属于本实用新型思路下的技术方案均属于本实用新型的保护范围。应当指出，对于本技术领域的普通技术人员来说，在不脱离本实用新型原理前提下的若干个改进和润饰，这些改进和润饰也应视为本实用新型的保护范围。

Claims (6)

  1. 一种NAND Flash数据保护电路，其特征在于，包括
    第一保护单元（10），接入数据信号并输出第一保护信号；
    第二保护单元（20），接入一电源启动信号并输出第二保护信号，且所述第二保护单元（20）和所述第一保护单元（10）构成逻辑与关系；
    上拉下拉单元（30），分别与所述第一保护单元（10）和所述第二保护单元（20）相连接，所述上拉下拉单元（30）根据所述第一保护信号和所述第二保护信号向NAND Flash电路的写保护端口（50）输出数据保护信号。
  2. 根据权利要求1所述的电路，其特征在于，所述第一保护单元（10）包括第一二极管（D1）和第一上拉电阻（R71），所述第一二极管（D1）负极连接所述数据信号从而接入所述数据信号，所述第一二极管（D1）正极连接所述上拉下拉单元（30），从而输出所述第一保护信号；所述第一上拉电阻（R71）一端连接电源，另一端连接所述第一二极管（D1）负极；
    所述第二保护单元（20）包括第二二极管（D2）和第二上拉电阻（R72），所述第二二极管（D2）负极连接所述电源启动信号从而接入所述电源启动信号，正极连接所述上拉下拉单元（30），从而输出所述第二保护信号；所述第二上拉电阻（R72）一端连接电源，另一端连接所述第二二极管（D2）负极。
  3. 根据权利要求2所述的电路，其特征在于，所述上拉下拉单元（30）包括总上拉电阻（R52）和下拉电阻（R58），所述总上拉电阻（R52）一端连接电源，另一端连接所述下拉电阻（R58）；所述下拉电阻（R58）一端连接所述总上拉电阻（R52），另一端接地；所述总上拉电阻（R52）和下拉电阻（R58）的连接点连接所述第一二极管（D1）的正极和所述第二二极管（D2）的正极，从而接入所述第一保护信号和所述第二保护信号；所述连接点还连接所述写保护端口（50），从而将所述数据保护信号接出至所述写保护端口（50）。
  4. 根据权利要求2或3所述的电路，其特征在于，所述第一保护单元（10）还包括并联在所述第一二极管（D1）上的第一预留电阻。
  5. 根据权利要求2或3所述的电路，其特征在于，所述第二保护单元（20）还包括并联在所述第二二极管（D2）上的第二预留电阻。
  6. 根据权利要求1所述的电路，其特征在于，所述第一保护单元（10）和所述第二保护单元（20）构成数字与门。
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CN201607723U (zh) * 2009-12-25 2010-10-13 康佳集团股份有限公司 存储器写保护电路
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