WO2016203743A1 - Dispositif à semi-conducteurs - Google Patents

Dispositif à semi-conducteurs Download PDF

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Publication number
WO2016203743A1
WO2016203743A1 PCT/JP2016/002805 JP2016002805W WO2016203743A1 WO 2016203743 A1 WO2016203743 A1 WO 2016203743A1 JP 2016002805 W JP2016002805 W JP 2016002805W WO 2016203743 A1 WO2016203743 A1 WO 2016203743A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
region
heat sink
hole
heat
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Application number
PCT/JP2016/002805
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English (en)
Japanese (ja)
Inventor
翔一朗 大前
憲司 小野田
Original Assignee
株式会社デンソー
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Publication of WO2016203743A1 publication Critical patent/WO2016203743A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to a semiconductor device in which a first semiconductor chip and a second semiconductor chip formed using materials having different Young's moduli are arranged on the same surface of a heat dissipation member and sealed with a sealing resin body.
  • Patent Document 1 discloses a semiconductor device in which a first semiconductor chip and a second semiconductor chip formed using materials having different Young's moduli are arranged on the same surface of a heat dissipation member.
  • the first semiconductor chip made of Si and the second semiconductor chip made of SiC are arranged on the same surface of the heat dissipation member.
  • the semiconductor device as described above usually further includes a sealing resin body. Then, at least one surface of the first semiconductor chip, the second semiconductor chip, and the heat dissipation member is integrally sealed with the sealing resin body.
  • the second semiconductor chip is formed using a material having a higher Young's modulus than the first semiconductor chip, and is less likely to deform (hard) than the first semiconductor chip. For this reason, in the resin-encapsulated semiconductor device, the resin is easily peeled around the second semiconductor chip due to a change in temperature of the use environment. Since the first semiconductor chip and the second semiconductor chip are arranged on the same surface of the heat dissipation member, the resin peeling that occurs around the second semiconductor chip is caused by the interface between the sealing resin body and one surface of the heat dissipation member. There is a risk of progressing to one semiconductor chip side. That is, there is a possibility that the connection reliability of the first semiconductor chip with respect to the heat dissipation member is lowered.
  • the first semiconductor chip and the second semiconductor chip are arranged on the same surface of the heat dissipation member, and for example, heat generated by the first semiconductor chip is transmitted to the second semiconductor chip via the heat dissipation member.
  • the heat of one semiconductor chip is transferred to the other semiconductor chip, the other semiconductor chip becomes high temperature, and there is a possibility that the element characteristics are deteriorated.
  • an object of the present disclosure is to provide a semiconductor device capable of suppressing heat transfer between semiconductor chips while improving connection reliability of a first semiconductor chip having a small Young's modulus.
  • the conductor device includes a first semiconductor chip, a second semiconductor chip formed using a material having a Young's modulus larger than the first semiconductor chip, one surface, the one surface, and a thickness direction.
  • the first semiconductor chip and the second semiconductor chip are arranged side by side on the one surface, and heat generated by the first semiconductor chip and the second semiconductor chip is transferred to the heat radiation.
  • a sealing resin body that integrally seals at least one surface of the first semiconductor chip, the second semiconductor chip, and the heat dissipation member.
  • the one surface of the heat dissipation member includes a first region that is an arrangement region of the first semiconductor chip and a second region that is an arrangement region of the second semiconductor chip, and penetrates over the one surface and the back surface.
  • the sealing resin body includes a first covering portion that covers the one surface, and a filling portion that is continuous with the first covering portion and is filled in the through hole.
  • the resin peeling progresses at the interface between the filling portion and the wall surface of the through hole. For this reason, compared with the structure which does not have the conventional through-hole, the path
  • the filling part which is a part of sealing resin body is arrange
  • the filling portion is provided extending in the thickness direction from the one surface side covering portion, and functions as an anchor.
  • the sealing resin body includes a first covering portion that covers the one surface, and a filling portion that is continuous with the first covering portion and is filled in the through hole.
  • the through hole penetrates over one surface and the back surface of the heat radiating member, and there is no heat radiating member in the through hole forming portion. Therefore, the semiconductor device described above can suppress heat transfer between the first semiconductor chip and the second semiconductor chip.
  • the through hole described above can suppress the heat generated by the first semiconductor chip from being transmitted to the second semiconductor chip via the heat dissipation member. Therefore, the semiconductor device according to one embodiment of the present disclosure can suppress degradation of the characteristics of the element formed in the second semiconductor chip due to heat transfer of the second semiconductor chip. Moreover, since it can suppress that resin peeling progresses to the 1st semiconductor chip side among the 1st semiconductor chip and 2nd semiconductor chip which are driven in parallel, fail-safe property can also be improved.
  • FIG. 1 is a diagram illustrating a schematic configuration of a power conversion device to which the semiconductor device of the first embodiment is applied.
  • FIG. 2 is a plan view showing a schematic configuration of the semiconductor device
  • FIG. 3 is a plan view in which the sealing resin body is omitted in the semiconductor device
  • FIG. 4 is a plan view showing the position of the through hole in the heat sink
  • FIG. 7 is a plan view showing a first modification
  • FIG. 8 is a plan view showing a second modification
  • FIG. 1 is a diagram illustrating a schematic configuration of a power conversion device to which the semiconductor device of the first embodiment is applied.
  • FIG. 2 is a plan view showing a schematic configuration of the semiconductor device
  • FIG. 3 is a plan view in which the sealing resin body is omitted in the semiconductor device
  • FIG. 4 is a plan view showing the position of the
  • FIG. 9 is a cross-sectional view showing a third modification
  • FIG. 10 is a plan view showing positions of through holes in the heat sink in the semiconductor device according to the second embodiment.
  • FIG. 11 is a cross-sectional view showing the periphery of a through hole in a semiconductor device according to the second embodiment.
  • FIG. 12 is a cross-sectional view showing the periphery of the through hole in the semiconductor device according to the third embodiment.
  • FIG. 13 is a cross-sectional view showing a fourth modification
  • FIG. 14 is a cross-sectional view showing a fifth modification.
  • the thickness direction of a heat sink is shown as a Z direction.
  • An arrangement direction of the first semiconductor chip and the second semiconductor chip that are orthogonal to the Z direction and constitute the same arm is indicated as an X direction.
  • a direction perpendicular to both the Z direction and the X direction is referred to as a Y direction.
  • the XY plane defined by the X direction and the Y direction described above is a plane orthogonal to the Z direction, and unless otherwise specified, the shape along the XY plane is a planar shape.
  • the power converter 1 is configured to convert a DC voltage supplied from a DC power source 2 into a three-phase AC and output it to a three-phase AC system motor 3.
  • the power converter 1 shown in FIG. Such a power converter 1 is mounted on, for example, an electric vehicle (EV) or a hybrid vehicle (HV).
  • the power conversion device 1 can also convert the electric power generated by the motor 3 into direct current and charge the battery as the direct current power source 2. For this reason, the motor 3 is also referred to as a motor generator.
  • Reference numeral 4 shown in FIG. 1 is a smoothing capacitor.
  • the power converter 1 has a three-phase inverter.
  • the three-phase inverter is a three-phase circuit provided between a high potential power line 5 connected to the positive electrode (high potential side) of the DC power source 2 and a low potential power line 6 connected to the negative electrode (low potential side).
  • the upper and lower arms of each phase are each constituted by a semiconductor device 10. That is, in the present embodiment, the semiconductor device 10 constitutes the upper and lower arms for one phase.
  • the semiconductor device 10 has two IGBTs 11 and two MOSFETs 12.
  • the two IGBTs 11 are connected in series between the high potential power line 5 and the low potential power line 6.
  • a MOSFET 12 is connected to each IGBT 11 in parallel.
  • a reflux FWD (not shown) is connected to the IGBT 11 in reverse parallel and can be refluxed by the FWD.
  • the MOSFET 12 has a parasitic diode (not shown), and current is circulated by the parasitic diode.
  • an n-channel IGBT 11 and an n-channel MOSFET 12 are employed.
  • the cathode electrode of the FWD is shared with the collector electrode of the IGBT 11, and the anode electrode is shared with the emitter electrode.
  • the cathode electrode of the parasitic diode is shared with the drain electrode of the MOSFET 12, and the anode electrode is shared with the source electrode.
  • the collector electrode of the IGBT 11 on the upper arm (high side) side is electrically connected to the high potential power supply line 5, and the emitter electrode is connected to the output line 7 to the motor 3.
  • the collector electrode of the IGBT 11 on the lower arm (low side) side is connected to the output line 7, and the emitter electrode is electrically connected to the low potential power supply line 6.
  • the drain electrode of the MOSFET 12 on the upper arm side is electrically connected to the collector electrode of the IGBT 11 on the upper arm side, that is, the high-potential power line 5, and the source electrode is the emitter electrode of the IGBT 11 on the upper arm side, that is, the output line. 7 is connected.
  • the drain electrode of the MOSFET 12 on the lower arm side is electrically connected to the collector electrode and the output line 7 of the IGBT 11 on the lower arm side, and the source electrode is the emitter electrode of the IGBT 11 on the lower arm side, that is, the low-potential power line 6. And are electrically connected.
  • the power conversion device 1 is used as a boost converter that boosts a DC voltage supplied from the DC power supply 2, an IGBT 11 and a MOSFET 12 that constitute a three-phase inverter, and a switching element that constitutes a boost converter.
  • a drive circuit that outputs a drive signal and a control unit that outputs a control signal to the drive circuit may be included.
  • the configuration in which the IGBT 11 and the MOSFET 12 are connected in parallel is well known.
  • the saturation voltage at the time of ON is smaller in the MOSFET 12 in the small current region and smaller in the IGBT 11 in the large current region.
  • ON / OFF of the IGBT 11 and the MOSFET 12 is controlled so that a current flows through the MOSFET 12 in the small current region and a current flows through the IGBT 11 in the large current region.
  • on-loss can be reduced.
  • the turn-off loss is only the loss of the MOSFET 12 having excellent switching performance, the tail current is reduced and the turn-off loss can be reduced.
  • FIG. 3 is a view in which the sealing resin body is omitted from FIG. 6 strictly shows the structure of the upper arm side, but the structure of the first semiconductor chip 13 and the second semiconductor chip 14 is shown because the lower arm side has the same structure.
  • the semiconductor device 10 includes a first semiconductor chip 13, a second semiconductor chip 14, heat sinks 15 and 16, terminals 17 and 18, and a sealing resin body 19. ing.
  • the semiconductor device 10 of the present embodiment includes a high potential power terminal 20, a low potential power terminal 21, an output terminal 22, and a signal terminal 23 as terminals for external connection.
  • the high potential power supply terminal 20 is also referred to as a P terminal 20.
  • the low potential power supply terminal 21 is also referred to as an N terminal 21, and the output terminal 22 is also referred to as an O terminal 22.
  • These P terminal 20, N terminal 21, and O terminal 22 are also referred to as terminals 20, 21, and 22.
  • the heat sink 15 corresponds to a first heat sink
  • the heat sink 16 corresponds to a second heat sink.
  • the first semiconductor chip 13 is formed by forming an IGBT 11 and an FWD connected in reverse parallel to the IGBT 11 on a semiconductor substrate. That is, an RC (Reverse Conducting) -IGBT is formed on the first semiconductor chip 13.
  • the IGBT 11 and the FWD have a so-called vertical structure so that a current flows in the thickness direction of the first semiconductor chip 13, that is, the Z direction.
  • the first semiconductor chip 13 includes the first semiconductor chip 131 in which the upper-arm IGBT 11 and FWD are formed, and the first semiconductor chip 132 in which the lower-arm IGBT 11 and FWD are formed. is doing.
  • a collector electrode is formed on one surface side of the first semiconductor chip 13, and an emitter electrode is formed on the surface opposite to the collector electrode formation surface.
  • the collector electrode is formed on almost the entire surface facing the heat sink 15.
  • a plurality of pads including a pad electrically connected to the gate electrode is provided in a peripheral region different from the active region where the emitter electrode is formed on the emitter electrode forming surface.
  • the first semiconductor chips 131 and 132 have substantially the same planar shape and have substantially the same size.
  • the first semiconductor chips 131 and 132 are both substantially rectangular in plan. Further, the first semiconductor chips 131 and 132 are positioned at substantially the same height in the Z direction as shown in FIG. 5, and are arranged side by side in the X direction as indicated by broken lines in FIGS. .
  • the first semiconductor chip 13 (131, 132) is formed using Si (silicon).
  • Si silicon
  • the first semiconductor chip 13 is formed by forming the IGBT 11 and the FWD on the semiconductor substrate made of Si.
  • the second semiconductor chip 14 includes a MOSFET 12 formed on a semiconductor substrate formed using a semiconductor material having a Young's modulus greater than that of the first semiconductor chip 13.
  • the MOSFET 12 has a so-called vertical structure so that a current flows in the thickness direction of the second semiconductor chip 14, that is, the Z direction.
  • the second semiconductor chip 14 includes a second semiconductor chip 141 in which the upper arm side MOSFET 12 is formed and a second semiconductor chip 142 in which the lower arm side MOSFET 12 is formed.
  • a drain electrode is formed on one surface side of the second semiconductor chip 14, and a source electrode is formed on the surface opposite to the drain electrode formation surface.
  • the drain electrode is formed on almost the entire surface facing the heat sink 15.
  • the drain electrode formation surface of the second semiconductor chip 14 is on the same side as the collector electrode formation surface of the first semiconductor chip 13 in the Z direction.
  • a plurality of pads including a pad electrically connected to the gate electrode is provided in a peripheral region different from the active region where the source electrode is formed on the source electrode formation surface.
  • the second semiconductor chips 141 and 142 have substantially the same planar shape and have substantially the same size.
  • the second semiconductor chips 141 and 142 are both substantially rectangular in plan, and the size thereof is smaller than that of the first semiconductor chip 13 as indicated by broken lines in FIGS.
  • the second semiconductor chips 141 and 142 are located at substantially the same height in the Z direction and are arranged side by side in the X direction.
  • the second semiconductor chip 14 is positioned at substantially the same height in the Z direction as the first semiconductor chip 13 disposed on the one surface 15 a of the same heat sink 15 and is aligned in the X direction. Is arranged in. Specifically, the second semiconductor chip 141 is located at substantially the same height as the first semiconductor chip 131 in the Z direction and is arranged side by side in the X direction. Further, the second semiconductor chip 142 is located at substantially the same height as the first semiconductor chip 132 in the Z direction, and is arranged side by side in the X direction. 2, the first semiconductor chip 131, the second semiconductor chip 141, the first semiconductor chip 132, and the second semiconductor chip 142 are arranged in this order in the X direction.
  • the second semiconductor chip 14 is formed using SiC (silicon carbide).
  • the second semiconductor chip 14 includes the MOSFET 12 formed on the semiconductor substrate made of SiC.
  • the first semiconductor chip 13 and the second semiconductor chip 14 are also referred to as semiconductor chips 13 and 14.
  • the IGBT 11 is formed on the first semiconductor chip 13
  • the MOSFET 12 is formed on the second semiconductor chip 14
  • the first semiconductor chip 13 and the second semiconductor chip 14 are driven in parallel. Further, since the current is controlled to flow through the IGBT 11 in the large current region, the amount of heat generated by the driving is larger in the first semiconductor chip 13 than in the second semiconductor chip 14.
  • heat sinks 15 are disposed on the collector electrode forming surface side of the first semiconductor chip 13 and on the drain electrode forming surface side of the second semiconductor chip 14.
  • heat sinks 16 are disposed on the emitter electrode forming surface side of the first semiconductor chip 13 and the source electrode forming surface side of the second semiconductor chip 14.
  • the heat sinks 15 and 16 are the heat sinks 151 and 161 sandwiching the first semiconductor chip 131 and the second semiconductor chip 141 on the upper arm side, and the first semiconductor chip 132 on the lower arm side.
  • heat sinks 152 and 162 sandwiching the second semiconductor chip 142 therebetween. That is, the heat sink 15 includes heat sinks 151 and 152, and the heat sink 16 includes heat sinks 161 and 162.
  • the heat sink 15 (151 and 152) corresponds to a heat radiating member.
  • the heat sinks 151 and 161 corresponding to the upper arm are respectively disposed so as to include the first semiconductor chip 131 and the second semiconductor chip 141 on the upper arm side in the projection view from the Z direction.
  • the heat sinks 152 and 162 corresponding to the lower arm are respectively disposed so as to include the first semiconductor chip 132 and the second semiconductor chip 142 on the lower arm side in a projected view from the Z direction.
  • each of the heat sinks 151, 152, 161, 162 has a substantially rectangular planar shape.
  • heat sinks 15 and 16 function to dissipate heat generated by the corresponding semiconductor chips 13 and 14 to the outside of the semiconductor device 10.
  • the function of electrical connection that is, the function of wiring is also achieved.
  • the heat sinks 15 and 16 are formed using metal materials, such as copper, in order to ensure heat conductivity and electrical conductivity.
  • the first semiconductor chip 13 and the second semiconductor chip 14 are disposed on the one surface 15 a of the heat sink 15. 4 and 5, a solder 24 is interposed between the heat sink 15 and the collector electrode of the first semiconductor chip 13, and the heat sink 15 and the collector electrode are thermally and electrically connected by the solder 24. It is connected to the. As shown in FIG. 6, solder 25 is interposed between one surface 15a of the heat sink 15 and the drain electrode of the second semiconductor chip 14, and the heat sink 15 and the drain electrode are thermally and electrically connected by the solder 25. It is connected to the.
  • the first semiconductor chip 131 and the second semiconductor chip 141 on the upper arm side are arranged on the one surface 15a of the heat sink 151.
  • the solder 24 is interposed between the heat sink 151 and the collector electrode of the first semiconductor chip 131, and the heat sink 151 and the collector electrode of the first semiconductor chip 131 are thermally and electrically connected by the solder 24.
  • solder 25 is interposed between the heat sink 151 and the drain electrode of the second semiconductor chip 141, and the heat sink 151 and the drain electrode of the second semiconductor chip 141 are thermally and electrically connected by the solder 25. Yes.
  • the first semiconductor chip 132 and the second semiconductor chip 142 on the lower arm side are arranged on the one surface 15 a of the heat sink 152.
  • the solder 24 is interposed between the heat sink 152 and the collector electrode of the first semiconductor chip 132, and the heat sink 152 and the collector electrode of the first semiconductor chip 132 are thermally and electrically connected by the solder 24.
  • solder 25 is interposed between the heat sink 152 and the drain electrode of the second semiconductor chip 142, and the heat sink 152 and the drain electrode of the second semiconductor chip 142 are thermally and electrically connected by the solder 25. Yes.
  • the back surface 15b opposite to the one surface 15a in each heat sink 15 (151, 152) is exposed from the first surface 19a of the sealing resin body 19 in the Z direction.
  • the back surface 15b and the first surface 19a are substantially flush.
  • the heat sink 152 on the lower arm side has a joint portion 152a as shown in FIGS.
  • the joint portion 152 a is provided thinner than the other portion (main body portion) of the heat sink 152.
  • the joint portion 152a is extended from the part of the side surface of the heat sink 152 on the heat sink 151 side to the heat sink 161 side with two bent portions. That is, it extends in the X direction and also in the Z direction.
  • a P terminal 20 is connected to the heat sink 151 on the upper arm side as shown in FIGS.
  • the P terminal 20 is electrically connected to the above-described high potential power supply line 5.
  • the P terminal 20 may be provided integrally with the heat sink 15 or may be provided as a separate member from the heat sink 15 and connected to the heat sink 15.
  • the P terminal 20 extends in the Y direction and protrudes from the side surface 19c of the sealing resin body 19 as shown in FIG.
  • the O terminal 22 is connected to the heat sink 152 on the lower arm side as shown in FIGS.
  • the O terminal 22 is electrically connected to the output line 7 described above.
  • the O terminal 22 may be provided integrally with the heat sink 152, provided as a separate member from the heat sink 152, and connected to the heat sink 152.
  • the O terminal 22 extends in the Y direction and protrudes from the same side surface 19 c as the P terminal 20 in the sealing resin body 19.
  • the O terminal 22 may be connected to the heat sink 161 on the upper arm side.
  • the heat sinks 152 and 161 may have two O terminals 22 connected to each other.
  • a heat sink 16 is disposed on the emitter electrode formation surface of the first semiconductor chip 13 and the source electrode formation surface side of the second semiconductor chip 14.
  • a terminal 17 is interposed between the first semiconductor chip 13 and the heat sink 16 as shown in FIGS.
  • a terminal 18 is interposed between the second semiconductor chip 14 and the heat sink 16 as shown in FIG.
  • the terminal 17 secures a height for connecting the signal terminal 23 and the pad of the first semiconductor chip 13 by the bonding wire 26.
  • the terminal 17 is formed using at least a metal material in order to ensure thermal conductivity and electrical conductivity in order to thermally and electrically relay the emitter electrode of the first semiconductor chip 13 and the heat sink 16.
  • the terminal 17 is disposed opposite to the emitter electrode on the emitter electrode forming surface of the first semiconductor chip 13 and is electrically connected to the emitter electrode via the solder 27.
  • the terminal 18 secures a height for connecting the signal terminal 23 and the pad of the second semiconductor chip 14 by the bonding wire 26.
  • the terminal 18 is formed using at least a metal material in order to ensure thermal conductivity and electrical conductivity in order to thermally and electrically relay the source electrode of the second semiconductor chip 14 and the heat sink 16.
  • the terminal 18 is disposed opposite the source electrode formation surface of the second semiconductor chip 14 and is electrically connected to the source electrode via the solder 28.
  • the heat sink 16 is provided so that most of the heat sink 16 overlaps the corresponding heat sink 15 in the projection view from the Z direction. Specifically, the heat sink 161 on the upper arm side is provided so as to overlap the heat sink 151, and the heat sink 162 on the lower arm side is provided so as to overlap the heat sink 152. The heat sink 16 is disposed opposite to the surfaces of the terminals 17 and 18 opposite to the semiconductor chips 13 and 14.
  • solder 29 is interposed between one surface 16 a of the heat sink 16 and the terminal 17, and the heat sink 16 and the terminal 17 are thermally and electrically connected by the solder 29.
  • solder 30 is interposed between one surface 16 a of the heat sink 16 and the terminal 18, and the heat sink 16 and the terminal 18 are thermally and electrically connected by the solder 30.
  • the terminal 17 is interposed between the one surface 16 a of the heat sink 161 and the first semiconductor chip 131 on the upper arm side, and the emitter electrode of the first semiconductor chip 131 and the terminal 17 are connected by the solder 27. Yes. Further, the terminal 17 and the heat sink 161 are connected by solder 29.
  • the terminal 18 is interposed between the one surface 16 a of the heat sink 161 and the second semiconductor chip 141 on the upper arm side, and the source electrode of the second semiconductor chip 141 and the terminal 17 are connected by solder 28. Further, the terminal 18 and the heat sink 161 are connected by the solder 30.
  • the first semiconductor chip 131 and the second semiconductor chip 141 are arranged on the one surface 16 a of the heat sink 161.
  • the terminal 17 is interposed between the one surface 16 a of the heat sink 162 and the first semiconductor chip 132 on the lower arm side, and the emitter electrode 13 b of the first semiconductor chip 132 and the terminal 17 are connected by the solder 27. Further, the terminal 17 and the heat sink 162 are connected by solder 29.
  • the terminal 18 is interposed between the one surface 16 a of the heat sink 162 and the second semiconductor chip 142 on the lower arm side, and the source electrode 14 b of the second semiconductor chip 142 and the terminal 17 are connected by the solder 28. Further, the terminal 18 and the heat sink 162 are connected by the solder 30.
  • the first semiconductor chip 132 and the second semiconductor chip 142 are arranged on the one surface 16a of the heat sink 162.
  • the back surface 16 b opposite to the one surface 16 a is exposed from the second surface 19 b of the sealing resin body 19.
  • the second surface 19b is a surface opposite to the first surface 19a.
  • the back surface 16b and the second surface 19b are substantially flush.
  • the heat sink 161 on the upper arm side of the heat sink 16 has a joint portion 161a.
  • the joint portion 161 a is provided thinner than the other portion (main body portion) of the heat sink 161. Further, the joint portion 161 a extends in the X direction from a part of the side surface of the heat sink 161 on the heat sink 162 side.
  • the distal end portion of the joint portion 161 a and the distal end portion of the joint portion 152 a face each other in the Z direction and are electrically connected via the solder 31.
  • the heat sink 162 on the lower arm side has a joint portion 162a.
  • the joint portion 162a is provided thinner than other portions (main body portions) of the heat sink 162.
  • the joint portion 162a extends in the X direction from a part of the side surface of the heat sink 162 on the heat sink 161 side.
  • the N terminal 21 is electrically connected to the joint portion 162a via solder (not shown).
  • the N terminal 21 is electrically connected to the low potential power line 6 described above.
  • the N terminal 21 is electrically connected to the joint 162 a of the heat sink 162, extends in the Y direction, and protrudes to the outside from the side surface 19 c of the sealing resin body 19.
  • the N terminal 21 protrudes from the same side surface 19 c as the P terminal 20 and the O terminal 22.
  • the protrusion part from the sealing resin body 19 in these terminals 20, 21, and 22 is arrange
  • the signal terminal 23 is electrically connected to the pads of the corresponding semiconductor chips 13 and 14 through bonding wires 26.
  • the signal terminal 23 extends in the Y direction, and protrudes to the outside from the side surface 19 d opposite to the side surface 19 c among the side surfaces of the sealing resin body 19.
  • the sealing resin body 19 integrally seals the semiconductor chips 13 and 14, a part of the heat sinks 15 and 16, the terminals 17 and 18, and a part of each of the terminals 20, 21, 22 and 23.
  • the sealing resin body 19 is made of, for example, an epoxy resin and is molded by a transfer mold method. As shown in FIG. 2, the sealing resin body 19 has a substantially rectangular plane shape, and the P terminal 20, the N terminal 21, and the O terminal 22, which are main terminals, are drawn from a side surface 19 c substantially parallel to the X direction. It is. Further, the signal terminal 23 is drawn out from the side surface 19d opposite to the side surface 19c.
  • the semiconductor device 10 configured as described above is a so-called 4-in-1 package including two first semiconductor chips 13 (131, 132) and two second semiconductor chips 14 (141, 142). Further, heat sinks 15 and 16 exist on both sides in the Z direction of the semiconductor chips 13 and 14 so that heat of the semiconductor chips 13 and 14 can be dissipated to both sides.
  • the arrangement in the Z direction is, from the first surface 19a side, the heat sink 15 (151), solders 24 and 25, the first semiconductor chip 13 (131) and the second semiconductor chip 14 ( 141), solders 27 and 28, terminals 17 and 18, solders 29 and 30, and heat sink 16 (161).
  • the arrangement in the Z direction is the heat sink 15 (152), the solders 24 and 25, the first semiconductor chip 13 (132) on the lower arm side, and the second semiconductor from the first surface 19a side.
  • Chip 14 (142), solders 27 and 28, terminals 17 and 18, solders 29 and 30, and heat sink 16 (162) are arranged in this order. That is, the arrangement in the Z direction is the same between the upper arm and the lower arm.
  • a first region 15 d that is an arrangement region of the first semiconductor chip 13 and a second region 15 e that is an arrangement region of the second semiconductor chip 14 are indicated by broken lines. Further, a facing region 15f between the first region 15d and the second region 15e is also indicated by a broken line.
  • the heat sink 15 (151 and 152) has a through hole 15c.
  • the first semiconductor chip 13 (131, 132) and the second semiconductor chip 14 (141, 142) are disposed on one surface 15a of the heat sink 15.
  • the arrangement area of each first semiconductor chip 13 is indicated as a first area 15d
  • the arrangement area of each second semiconductor chip 14 is indicated as a second area 15e.
  • the first region 15d indicates a portion where the first semiconductor chip 13 is disposed on the one surface 15a, that is, a portion where the solder 24 is joined.
  • the second region 15e indicates a portion where the second semiconductor chip 14 is disposed on the one surface 15a, that is, a portion where the solder 25 is bonded.
  • the collector electrode of the first semiconductor chip 13 is formed on almost the entire surface facing the heat sink 15.
  • the drain electrode of the second semiconductor chip 14 is formed on almost the entire surface facing the heat sink 15.
  • the first region 15d substantially coincides with the first semiconductor chip 13 in the projection view from the Z direction
  • the first region 15d has a substantially rectangular planar shape.
  • the second region 15e substantially coincides with the second semiconductor chip 14, and the second region 15e has a substantially rectangular planar shape.
  • the first region 15d and the second region 15e are provided side by side in the X direction.
  • the first region 15d and the second region 15e have two sets of opposite sides as the outer periphery having a substantially rectangular shape in plan view. Two sides forming one set are substantially parallel to the X direction, and two sides forming the other set are substantially parallel to the Y direction.
  • the through-hole 15c penetrates over the one surface 15a and the back surface 15b of the heat sink 15.
  • the through hole 15c is formed at a position between the first region 15d and the second region 15e in the X direction.
  • the X coordinate of the through hole 15c is a coordinate between the X coordinate of the first region 15d and the X coordinate of the second region 15e.
  • the X coordinate of the through hole 15c is the X coordinate of the opposite side (hereinafter referred to as the first opposite side) of the first region 15d with the second region 15e and the first region 15d of the second region 15e. This is a coordinate between the X coordinates of the opposing side (hereinafter referred to as the second opposing side).
  • the through-hole 15c is formed at a position between the shortest portions of the facing distance between the first region 15d and the second region 15e in the X direction that is the arrangement direction.
  • the through hole 15c is formed at a position near the second semiconductor chip 14 in the X direction.
  • the through hole 15c is formed at a position closer to the second region 15e than to the first region 15d.
  • the through hole 15c is formed in a facing region 15f between the first region 15d and the second region 15e.
  • the opposing region 15f is a virtual straight line connecting the first opposing side of the first region 15d, the second opposing side of the second region 15e, and the end portions of the first opposing side and the second opposing side on the P terminal 20 side. And an imaginary straight line connecting ends opposite to the P terminal 20 on the first opposing side and the second opposing side.
  • the plurality of through holes 15c are formed so as to straddle the opposing region 15f in the Y direction. Specifically, five through holes 15c are formed in the heat sinks 151 and 152, respectively. The five through holes 15c are formed at a predetermined pitch along the Y direction. Of the five through holes 15c, three are formed in the opposing region 15f, and the remaining two are formed outside the opposing region 15f.
  • the sealing resin body 19 includes a covering portion 19 e that covers one surface 15 a of the heat sink 15 that is a heat radiating member, and a filling portion 19 f that is filled in the through hole 15 c.
  • the covering portion 19e is disposed on the one surface 15a so as to close the through hole 15c, and is in close contact with the one surface 15a.
  • the covering portion 19e corresponds to a one-side covering portion (or a first covering portion).
  • the filling portion 19f is arranged from the opening end on the one surface 15a side to the opening end on the back surface 15b side with respect to the through hole 15c.
  • the filling portion 19f is in close contact with the wall surface of the through hole 15c.
  • the end on the back surface 15b side of the filling portion 19f is substantially flush with the back surface 15b.
  • the filling portion 19f is continuous with the covering portion 19e and is formed integrally with the covering portion 19e.
  • the filling portion 19f extends from the covering portion 19e on the side opposite to the heat sink 16 in the Z direction.
  • the second semiconductor chip 14 is formed using a semiconductor material having a higher Young's modulus than the first semiconductor chip 13, and is less likely to deform (hard) than the first semiconductor chip 13. For this reason, peeling is likely to occur in the periphery of the second semiconductor chip 14, for example, in the outer peripheral portion of the second semiconductor chip 14, in the sealing resin body 19 due to a temperature change in the use environment.
  • the heat sink 15 has a through hole 15c at a position between the first region 15d and the second region 15e in the X direction.
  • the sealing resin body 19 is filled in the through-hole 15c, and the filling part 19f is formed. Even if resin peeling occurs around the second semiconductor chip 14, the resin peeling progresses at the interface between the filling portion 19 f and the wall surface of the through hole 15 c, so that the second semiconductor chip is compared with the configuration having no through hole. The progress path of the resin peeling from 14 to the first semiconductor chip 13 is long.
  • the filling portion 19f which is a part of the sealing resin body 19, is disposed in the through hole 15c, and the contact area between the sealing resin body 19 and the heat sink 15 is larger than in the past. Furthermore, the filling portion 19f extends from the covering portion 19e in the Z direction, and an anchor effect can be expected.
  • the semiconductor device 10 of the present embodiment can suppress the resin peeling from progressing toward the first semiconductor chip 13 even if the resin peeling occurs around the second semiconductor chip 14. That is, the connection reliability of the first semiconductor chip 13 with respect to the heat sink 15 can be improved as compared with the conventional case.
  • the semiconductor device 10 can suppress heat transfer between the first semiconductor chip 13 and the second semiconductor chip 14.
  • the IGBT 11 formed on the first semiconductor chip 13 and the MOSFET 12 formed on the second semiconductor chip 14 are driven in parallel. Further, since the current is controlled to flow through the IGBT 11 in the large current region, the amount of heat generated by the driving is larger in the first semiconductor chip 13 than in the second semiconductor chip 14.
  • the semiconductor device 10 of this embodiment can suppress the heat of the first semiconductor chip 13 from being transmitted to the second semiconductor chip 14 via the heat sink 15. Therefore, it is possible to suppress the deterioration of the characteristics of the MOSFET 12 formed on the second semiconductor chip 14 due to the high temperature of the second semiconductor chip 14 due to heat transfer.
  • the characteristics of SiC greatly vary depending on the operating temperature range, and the conduction resistance is higher in the high temperature region than in the normal temperature region. That is, the loss increases.
  • heat transfer to the second semiconductor chip 14 made of SiC is suppressed, it is possible to suppress deterioration of characteristics.
  • the through hole 15c is formed at a position closer to the second semiconductor chip 14 than the first semiconductor chip 13 in the X direction. That is, the through hole 15 c is formed at a position away from the first semiconductor chip 13 in the X direction. Since the through hole 15 c does not exist around the first semiconductor chip 13 and the heat sink 15 exists, the semiconductor device 10 of this embodiment can also improve the heat dissipation from the first semiconductor chip 13 to the heat sink 15. .
  • the resin peeling from the second semiconductor chip 14 toward the first semiconductor chip 13 progresses in the heat sink 15 via a position between the first region 15d and the second region 15e.
  • heat conduction between the first semiconductor chip 13 and the second semiconductor chip 14 also passes through a portion between the first region 15d and the second region 15e in the X direction.
  • This heat conduction mainly passes through the opposing region 15f between the first region 15d and the second region 15e.
  • region 15f since the through-hole 15c is provided in the opposing area
  • the through hole 15c is formed so as to straddle the opposing region 15f. That is, the through-hole 15c is formed so as to block the separation progress and heat conduction in the facing region 15f. For this reason, the progress of the resin peeling toward the first semiconductor chip 13 and the heat transfer between the first semiconductor chip 13 and the second semiconductor chip 14 can be effectively suppressed.
  • FIG. 7 corresponds to FIG.
  • the arrangement of the through holes 15c is not limited to the arrangement across the above-described facing region 15f.
  • a configuration in which the through hole 15c is formed only in the facing region 15f can also be employed.
  • a configuration in which the through hole 15c is formed only at the position between the first region 15d and the second region 15e in the X direction and outside the opposing region 15f may be employed. it can.
  • a configuration in which the through hole 15c is formed at an intermediate position between the first region 15d and the second region 15e in the X direction can be adopted, or a configuration in which the through hole 15c is formed at a position close to the first region 15d. It can also be adopted.
  • FIG. 8 corresponds to FIG.
  • the first semiconductor chip 13 and the second semiconductor chip 14 are also disposed on the one surface 16a of the heat sink 16 via the corresponding terminals 17 and 18.
  • the through hole may be formed in at least one of the heat sinks 15 and 16.
  • the heat sinks 15 and 16 in which the through holes are formed correspond to heat radiating members.
  • the through hole 16 c is formed not only in the heat sink 15 but also in the heat sink 16.
  • the arrangement of the through holes 16c is the same as that of the through holes 15c. That is, the through hole 16c is formed at a position between the first region 16d and the second region 16e in the X direction.
  • the first region 16d indicates a portion where the first semiconductor chip 13 is disposed on the one surface 16a of the heat sink 16, that is, a portion where the solder 29 is bonded.
  • the second region 16e indicates a portion where the second semiconductor chip 14 is disposed on the one surface 16a, that is, a portion where the solder 30 is joined.
  • FIG. 9 corresponds to FIG.
  • the through hole 15c is formed in the heat sink 15 (151 and 152) so as to surround the second semiconductor chip 14, that is, the second region 15e. 10 corresponds to FIG. 4, and FIG. 11 corresponds to FIG.
  • a plurality of through holes 15c are formed so as to surround the second region 15e at the same pitch. That is, the through hole 15c discontinuously surrounds the second region 15e.
  • Part of the plurality of through holes 15c is formed at a position between the first region 15d and the second region 15e in the X direction.
  • a part of the plurality of through holes 15c is formed in the facing region 15f.
  • the filling part 19f is arrange
  • the resin peeling toward the first semiconductor chip 13 and the heat transfer between the first semiconductor chip 13 and the second semiconductor chip 14 can be effectively suppressed.
  • the resin peeling progresses toward the first semiconductor chip 13 by any of the through holes 15 c formed around the second semiconductor chip 14. Can be suppressed.
  • the through hole 15c surrounds the second semiconductor chip 14 discontinuously.
  • a through hole 15c formed in a C shape so as to surround the second semiconductor chip 14 may be employed.
  • the through hole 15c continuously surrounds the second semiconductor chip 14.
  • the above configuration is not limited to the through hole 15c, but can also be applied to the through hole 16c of the heat sink 16.
  • the sealing resin body 19 further includes a covering portion 19 g that is connected to the filling portion 19 f and covers the back surfaces 15 b and 16 b of the heat sinks 15 and 16.
  • This covering portion 19g corresponds to the back surface covering portion (or the second covering portion).
  • both heat sinks 15 and 16 have through holes 15c and 16c.
  • the covering portion 19 e is in close contact with the one surface 15 a of the heat sink 15 and the one surface 16 a of the heat sink 16.
  • the covering portion 19 e is a portion between the heat sinks 15 and 16.
  • the covering portion 19g is disposed on the back surface 15b of the heat sink 15 so as to close the through hole 15c, and is in close contact with the entire back surface 15b.
  • the covering portion 19g is also disposed on the back surface 16b of the heat sink 16 so as to close the through hole 16c, and is in close contact with the entire back surface 16b.
  • a covering portion 19e is connected to one end of the filling portion 19f filled in the through hole 15c, and a covering portion 19g on the back surface 15b side is connected to the other end.
  • the covering portion 19e is connected to one end of the filling portion 19f filled in the through hole 16c, and the covering portion 19g on the back surface 16b side is connected to the other end.
  • the filling part 19f connects the covering parts 19e and 19g.
  • the contact area between the sealing resin body 19 and the heat sink 15 and the contact area between the sealing resin body 19 and the heat sink 16 can be increased. Thereby, progress of resin peeling can be suppressed. Further, in the sealing resin body 19, the covering portions 19e and 19g connected by the filling portion 19f sandwich the heat sinks 15 and 16, respectively. For this reason, not only the X direction but also the progress of the resin peeling and the resin peeling due to the stress in the Z direction can be effectively suppressed.
  • the heat sinks 15 and 16 and the cooler are electrically connected by the covering portion 19g. It can also be separated. According to this, compared with the structure which uses an insulating plate in order to electrically isolate heat sinks 15 and 16 and a cooler, the number of parts can also be reduced.
  • the covering portion 19g is provided on the heat sinks 15 and 16 .
  • the covering portion 19g may be provided on the back surface 15b side.
  • what is necessary is just to provide the coating
  • the covering portion 19g is not limited to the configuration in close contact with the entire back surface 15b, 16b.
  • the covering portion 19g only needs to be connected to the filling portion 19f and be in close contact with at least the periphery of the openings of the back surfaces 15b and 16b.
  • the configuration of the semiconductor device 10 is not limited to the above example. Although an example having upper and lower arms for one phase has been shown, upper and lower arms for three phases may be provided. Further, only one set of the upper and lower arms, that is, the first semiconductor chip 13 and the second semiconductor chip 14 may be provided.
  • a configuration without the terminals 17 and 18 can be adopted as the semiconductor device 10 having a double-sided heat dissipation structure.
  • the back surfaces 15 b and 16 b of the heat sinks 15 and 16 having no through holes may be covered with the sealing resin body 19.
  • the sealing resin body 19 when the through hole 15 c is formed only in the heat sink 15, the back surface 16 b of the heat sink 16 in which no through hole is formed may be covered with the sealing resin body 19. In this case, you may cover the back surface 15b of the heat sink 15 in which the through-hole 15c was formed with the sealing resin body.
  • the heat sinks 15 and 16 are disposed on both sides of the semiconductor chips 13 and 14.
  • the present invention can also be applied to a semiconductor device in which a heat sink is disposed only on one side of the semiconductor chips 13 and 14.
  • the semiconductor device 10 includes a first semiconductor chip 13, a second semiconductor chip 14, a heat sink 15, and terminals 17 and 18.
  • the difference from the first embodiment (see FIG. 6) is that the semiconductor device 10 does not include the heat sink 16, and the O terminal 22 is connected to the terminals 17 and 18 via the bonding wires 32.
  • the N terminal 21 is used instead of the O terminal 22.
  • the through-hole 15c is formed in the heat sink 15, and the filling part 19f is arrange
  • the semiconductor device 10 includes the terminals 17 and 18, but a configuration without the terminals 17 and 18 can also be employed.
  • the back surface 15 b is exposed from the sealing resin body 19, but a configuration covered with the sealing resin body 19 can also be adopted.
  • the O terminal 22 is connected to the terminals 17 and 18 via the solders 29 and 30. That is, the first semiconductor chip 13 and the second semiconductor chip 14 are disposed on the one surface 22 a of the O terminal 22.
  • the O terminal 22 is formed with a through hole 22c penetrating over one surface 22a and a back surface 22b opposite to the one surface 22a.
  • the through holes 22c are arranged similarly to the through holes 15c.
  • the one surface 22a includes a first region 22d, which is a region where the first semiconductor chip 13 is disposed, and a second region 22e, which is a region where the second semiconductor chip 14 is disposed.
  • the through hole 22c is formed at a position between the first region 22d and the second region 22e in the X direction.
  • a filling portion 19f is disposed in the through hole 22c.
  • the sealing resin body 19 has the coating
  • the covering portion 19g is continuous with the filling portion 19f.
  • the heat sink 15 and the O terminal 22 correspond to a heat radiating member.
  • the back surface 15 b is exposed from the sealing resin body 19, but a configuration covered with the sealing resin body 19 can also be adopted.
  • the second semiconductor chip 14 may be formed using a semiconductor material having a Young's modulus larger than that of the first semiconductor chip 13.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Le dispositif à semi-conducteurs de l'invention comprend: une première puce à semi-conducteur (13); une seconde puce à semi-conducteur (14) formée avec un matériau ayant un grand module de Young; des éléments de dissipation thermique (15, 16, 22) présentant chacun une première surface (15a, 16a, 22a) et une surface revers (15b, 16b, 22b), et sur la première surface desquels la première et la seconde puce à semi-conducteur sont disposées, et auxquels la chaleur générée est transférée; et un corps de résine d'étanchéité (19) qui scelle la première et la seconde puce à semi-conducteur et au moins la première surface des éléments de dissipation thermique. Les éléments de dissipation thermique comprennent des premières régions (15d, 16d, 22d) sur lesquelles la première puce à semi-conducteur est disposée, et des secondes régions (15e, 16e, 22e) sur lesquelles la seconde puce de semi-conducteur est disposée; et comprennent également des trous traversants (15c, 16c, 22c) qui les traversent de la première surface à la surface revers et qui sont ménagés entre la première région et la seconde région. Le corps de résine d'étanchéité présente une première partie de recouvrement (19e) qui recouvre les premières surfaces, et des parties de remplissage (19f) qui remplissent les trous traversants.
PCT/JP2016/002805 2015-06-18 2016-06-10 Dispositif à semi-conducteurs WO2016203743A1 (fr)

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JP6910313B2 (ja) * 2018-02-15 2021-07-28 三菱電機株式会社 高周波デバイスおよび空中線
JP2020047725A (ja) * 2018-09-18 2020-03-26 トヨタ自動車株式会社 半導体装置
CN114026687A (zh) 2020-01-07 2022-02-08 富士电机株式会社 半导体装置

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JP2008186890A (ja) * 2007-01-29 2008-08-14 Denso Corp 半導体装置
JP2013131774A (ja) * 2013-03-15 2013-07-04 Mitsubishi Electric Corp パワー半導体モジュール、電力変換装置および鉄道車両
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CN111599796B (zh) * 2019-02-20 2023-09-08 株式会社电装 半导体模块、及使用该半导体模块的电力变换装置

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