JP2008186890A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2008186890A JP2008186890A JP2007017552A JP2007017552A JP2008186890A JP 2008186890 A JP2008186890 A JP 2008186890A JP 2007017552 A JP2007017552 A JP 2007017552A JP 2007017552 A JP2007017552 A JP 2007017552A JP 2008186890 A JP2008186890 A JP 2008186890A
- Authority
- JP
- Japan
- Prior art keywords
- heat radiating
- hole
- semiconductor device
- heat
- radiating plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】互いの内面3a、4aにて対向する第1の放熱板3と第2の放熱板4との間に、半導体素子1、2を挟み込み、これら両放熱板3、4および半導体素子1、2を包み込むようにモールド樹脂7で封止するとともに、両放熱板3、4の外面3b、4bをモールド樹脂7から露出させてなる半導体装置100において、第1の放熱板3および第2の放熱板4のそれぞれに、内面3a、4aから外面3b、4bまで貫通する貫通穴11を設けている。
【選択図】図2
Description
図1は、本発明の第1実施形態に係る半導体装置100の概略平面構成を示す図であり、図2は、図1中のA−A線に沿った概略断面図である。この半導体装置100は、たとえば自動車などの車両に搭載され、車両用電子装置を駆動するための装置として適用されるものである。
図4は、本発明の第2実施形態に係る半導体装置101の概略平面構成を示す図であり、図5は、図4中のB−B線に沿った概略断面図である。本実施形態は、上記第1実施形態に示した半導体装置において、貫通穴11の形状を変形したものであり、貫通穴11による効果は上記第1実施形態と同様に発揮される。
図6は、本発明の第3実施形態に係る半導体装置102の概略平面構成を示す図であり、図7は、図6中のC−C線に沿った概略断面図である。本実施形態も、上記第1実施形態に示した半導体装置において、貫通穴11の形状を変形したものである。
図8は、本発明の第4実施形態に係る半導体装置103の概略断面構成を示す図である。両放熱板3、4の両方に貫通穴11がある場合、上記実施形態のように互いの貫通穴11が同じ位置でなくてもよく、図8に示されるように、互いの貫通穴11が正対せずに異なる位置にあってもよい。
図9は、本発明の第5実施形態に係る半導体装置104の概略断面構成を示す図である。上記各実施形態では、貫通穴11は、両放熱板3、4の両方に設けられていたが、このように、両放熱板3、4のいずれか一方にのみ設けられていてもよい。
なお、貫通穴11の開口形状は、上記各図に示したような丸穴形状に限定されるものではなく、楕円形の穴形状、多角形の穴形状、細長のスリット形状など、空気抜き用として機能するものであれば、どのような形状であってもよい。また、片方の放熱板について貫通穴11を複数個設けてもよい。
3…第1の放熱板、3a…第1の放熱板の内面、3b…第1の放熱板の外面、
4…第2の放熱板、4a…第2の放熱板の内面、4b…第2の放熱板の外面、
7…モールド樹脂、11…貫通穴。
Claims (7)
- 互いの内面(3a、4a)にて対向する第1の放熱板(3)と第2の放熱板(4)との間に、半導体素子(1、2)を挟み込み、
これら両放熱板(3、4)および半導体素子(1、2)を包み込むようにモールド樹脂(7)で封止するとともに、前記両放熱板(3、4)における前記内面(3a、4a)とは反対側の外面(3b、4b)を前記モールド樹脂(7)から露出させてなる半導体装置において、
前記両放熱板(3、4)が対向している部位において前記両放熱板(3、4)の少なくとも一方の放熱板には、当該少なくとも一方の放熱板の前記内面(3a、4a)から前記外面(3b、4b)まで貫通する貫通穴(11)が設けられていることを特徴とする半導体装置。 - 前記貫通穴(11)は、前記両放熱板(3、4)のいずれか一方の放熱板にのみ設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記貫通穴(11)は、前記両放熱板(3、4)の両方の放熱板に設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記第1の放熱板(3)に設けられた前記貫通穴(11)と、前記第2の放熱板(4)に設けられた前記貫通穴(11)とは、同じ位置にあることを特徴とする請求項3に記載の半導体装置。
- 前記半導体素子(1、2)は前記第1の放熱板(3)と前記第2の放熱板(4)との間に複数個挟まれており、
前記貫通穴(11)は、これら複数個の半導体素子(1、2)において隣り合う半導体素子(1、2)の間に位置するように設けられていることを特徴とする請求項1ないし4のいずれか1つに記載の半導体装置。 - 前記貫通穴(11)は、当該貫通穴(11)が設けられている前記放熱板(3、4)の前記内面(3a、4a)から前記外面(3b、4b)に向かって拡がるテーパ形状をなすものであることを特徴とする請求項1ないし5のいずれか1つに記載の半導体装置。
- 前記貫通穴(11)は、当該貫通穴(11)が設けられている前記放熱板(3、4)の前記内面(3a、4a)と前記外面(3b、4b)との間に位置する中間部が絞られた鼓形状をなすものであることを特徴とする請求項1ないし5のいずれか1つに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007017552A JP4840165B2 (ja) | 2007-01-29 | 2007-01-29 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007017552A JP4840165B2 (ja) | 2007-01-29 | 2007-01-29 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008186890A true JP2008186890A (ja) | 2008-08-14 |
JP4840165B2 JP4840165B2 (ja) | 2011-12-21 |
Family
ID=39729741
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007017552A Expired - Fee Related JP4840165B2 (ja) | 2007-01-29 | 2007-01-29 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4840165B2 (ja) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010087111A (ja) * | 2008-09-30 | 2010-04-15 | Denso Corp | 半導体装置およびそれを用いたインバータ回路 |
JP2010109000A (ja) * | 2008-10-28 | 2010-05-13 | Denso Corp | 半導体パッケージ |
JP2011243872A (ja) * | 2010-05-20 | 2011-12-01 | Toyota Motor Corp | 半導体装置 |
JP2015159258A (ja) * | 2014-02-25 | 2015-09-03 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
JP2015162598A (ja) * | 2014-02-27 | 2015-09-07 | トヨタ自動車株式会社 | 半導体装置の製造方法および製造装置 |
CN105493275A (zh) * | 2013-09-06 | 2016-04-13 | 丰田自动车株式会社 | 半导体装置 |
WO2016203743A1 (ja) * | 2015-06-18 | 2016-12-22 | 株式会社デンソー | 半導体装置 |
WO2017188368A1 (ja) * | 2016-04-27 | 2017-11-02 | カルソニックカンセイ株式会社 | 半導体装置及びパワーモジュール |
JP2018074089A (ja) * | 2016-11-03 | 2018-05-10 | 株式会社デンソー | 半導体装置 |
WO2019037867A1 (en) | 2017-08-25 | 2019-02-28 | Huawei Technologies Co., Ltd. | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME |
JP2019212801A (ja) * | 2018-06-06 | 2019-12-12 | 株式会社デンソー | 半導体装置およびその製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001308263A (ja) * | 2000-04-19 | 2001-11-02 | Denso Corp | 半導体スイッチングモジュ−ル及びそれを用いた半導体装置 |
JP2003204036A (ja) * | 2002-01-10 | 2003-07-18 | Toyota Motor Corp | 複合半導体デバイス用電極板 |
JP2004253548A (ja) * | 2003-02-19 | 2004-09-09 | Denso Corp | 半導体モジュール |
JP2006066813A (ja) * | 2004-08-30 | 2006-03-09 | Renesas Technology Corp | 半導体装置 |
JP2006120970A (ja) * | 2004-10-25 | 2006-05-11 | Toyota Motor Corp | 半導体モジュールとその製造方法 |
-
2007
- 2007-01-29 JP JP2007017552A patent/JP4840165B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001308263A (ja) * | 2000-04-19 | 2001-11-02 | Denso Corp | 半導体スイッチングモジュ−ル及びそれを用いた半導体装置 |
JP2003204036A (ja) * | 2002-01-10 | 2003-07-18 | Toyota Motor Corp | 複合半導体デバイス用電極板 |
JP2004253548A (ja) * | 2003-02-19 | 2004-09-09 | Denso Corp | 半導体モジュール |
JP2006066813A (ja) * | 2004-08-30 | 2006-03-09 | Renesas Technology Corp | 半導体装置 |
JP2006120970A (ja) * | 2004-10-25 | 2006-05-11 | Toyota Motor Corp | 半導体モジュールとその製造方法 |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010087111A (ja) * | 2008-09-30 | 2010-04-15 | Denso Corp | 半導体装置およびそれを用いたインバータ回路 |
JP2010109000A (ja) * | 2008-10-28 | 2010-05-13 | Denso Corp | 半導体パッケージ |
JP2011243872A (ja) * | 2010-05-20 | 2011-12-01 | Toyota Motor Corp | 半導体装置 |
CN105493275A (zh) * | 2013-09-06 | 2016-04-13 | 丰田自动车株式会社 | 半导体装置 |
JP2015159258A (ja) * | 2014-02-25 | 2015-09-03 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
JP2015162598A (ja) * | 2014-02-27 | 2015-09-07 | トヨタ自動車株式会社 | 半導体装置の製造方法および製造装置 |
WO2016203743A1 (ja) * | 2015-06-18 | 2016-12-22 | 株式会社デンソー | 半導体装置 |
JP2017011028A (ja) * | 2015-06-18 | 2017-01-12 | 株式会社デンソー | 半導体装置 |
WO2017188368A1 (ja) * | 2016-04-27 | 2017-11-02 | カルソニックカンセイ株式会社 | 半導体装置及びパワーモジュール |
JP2017200315A (ja) * | 2016-04-27 | 2017-11-02 | カルソニックカンセイ株式会社 | 半導体装置 |
US11348855B2 (en) | 2016-04-27 | 2022-05-31 | Calsonic Kansei Corporation | Semiconductor component and power module |
JP2018074089A (ja) * | 2016-11-03 | 2018-05-10 | 株式会社デンソー | 半導体装置 |
WO2018083890A1 (ja) * | 2016-11-03 | 2018-05-11 | 株式会社デンソー | 半導体装置 |
CN109906510A (zh) * | 2016-11-03 | 2019-06-18 | 株式会社电装 | 半导体装置 |
WO2019037867A1 (en) | 2017-08-25 | 2019-02-28 | Huawei Technologies Co., Ltd. | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME |
US11251116B2 (en) | 2017-08-25 | 2022-02-15 | Huawei Technologies Co., Ltd. | Power semiconductor module for improved heat dissipation and power density, and method for manufacturing the same |
US11823996B2 (en) | 2017-08-25 | 2023-11-21 | Huawei Technologies Co., Ltd. | Power semiconductor module for improved heat dissipation and power density, and method for manufacturing the same |
JP2019212801A (ja) * | 2018-06-06 | 2019-12-12 | 株式会社デンソー | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4840165B2 (ja) | 2011-12-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4840165B2 (ja) | 半導体装置 | |
JP5339800B2 (ja) | 半導体装置の製造方法 | |
JP4702196B2 (ja) | 半導体装置 | |
JP4302607B2 (ja) | 半導体装置 | |
JP4935765B2 (ja) | 半導体装置の製造方法 | |
US20080224282A1 (en) | Semiconductor device and method of manufacturing the same | |
JP4254527B2 (ja) | 半導体装置 | |
JP4893303B2 (ja) | 半導体装置 | |
JP5649142B2 (ja) | 封止型半導体装置及びその製造方法 | |
JP2005167075A (ja) | 半導体装置 | |
JP6054345B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2014192518A (ja) | 半導体装置およびその製造方法 | |
JP5341339B2 (ja) | 回路装置 | |
JP4356494B2 (ja) | 半導体装置 | |
JP4339660B2 (ja) | 半導体装置 | |
JP5056105B2 (ja) | 半導体装置およびその製造方法 | |
JP2005116963A (ja) | 半導体装置 | |
JP2010103231A (ja) | 電子装置 | |
JP4293232B2 (ja) | 半導体装置の製造方法 | |
JP2021019065A (ja) | 半導体装置 | |
JP4258391B2 (ja) | 半導体装置 | |
JP4055700B2 (ja) | 半導体装置 | |
JP6160508B2 (ja) | モールドパッケージ | |
JP4258411B2 (ja) | 半導体装置 | |
JP3753132B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090210 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090605 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110621 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110808 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110906 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110919 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4840165 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141014 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |