WO2016201741A1 - 走线结构及阵列基板 - Google Patents

走线结构及阵列基板 Download PDF

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WO2016201741A1
WO2016201741A1 PCT/CN2015/083423 CN2015083423W WO2016201741A1 WO 2016201741 A1 WO2016201741 A1 WO 2016201741A1 CN 2015083423 W CN2015083423 W CN 2015083423W WO 2016201741 A1 WO2016201741 A1 WO 2016201741A1
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metal
metal lines
line
array substrate
lines
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French (fr)
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徐亮
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular to a trace structure and an array substrate.
  • liquid crystal displays have become the most common display devices.
  • the array substrate is an important component in the liquid crystal display.
  • a conductor structure such as a gate metal layer, an active layer, a source/drain metal layer, and a transparent electrode layer, and a plurality of insulating layers are required to be formed therebetween.
  • each conductor structure accumulates electric charge continuously, and when the electric charge accumulates to a certain extent, Electro-Static Discharge (ESD) occurs.
  • ESD Electro-Static Discharge
  • the metal traces 10 in the gate metal layer and the source/drain metal layer are particularly prone to electrostatic discharge due to a large taper angle ⁇ , which will break the gate metal layer and the source and drain electrodes.
  • the insulating layer between the metal layers causes a short circuit between the gate metal layer and the source and drain metal layers.
  • an electrostatic protection circuit is provided to prevent the occurrence of electrostatic discharge.
  • the electrostatic protection circuit is not completely formed, so that the electrostatic discharge prevention effect cannot be achieved. Electrostatic discharge generally occurs before the formation of the transparent electrode layer, so it is difficult to effectively prevent the occurrence of electrostatic discharge in the prior art.
  • the present invention provides a trace structure including a plurality of first metal lines and a plurality of second metal lines;
  • An insulating layer is disposed between the plurality of first metal lines and the plurality of second metal lines, and a projection of the plurality of first metal lines and the plurality of second metal lines intersect each other.
  • the plurality of first metal lines are parallel to each other, and the plurality of second metal lines are parallel to each other.
  • the spacing between adjacent first metal lines is within 4 to 7 microns, between adjacent second metal lines The spacing is within 4 to 7 microns.
  • the widths of the first metal line and the second metal line are all within 10 to 50 microns.
  • the length of the first metal wire and the second metal wire are both 10 mm or more.
  • the materials of the first metal wire and the second metal wire are both copper.
  • the invention also provides an array substrate, wherein the array structure is provided in the array substrate.
  • routing structure is disposed on a board edge region of the array substrate.
  • the first metal line is on the gate metal layer and the second metal line is on the source and drain metal layers.
  • the plurality of first metal lines and the plurality of second metal lines are both connected to the common electrode line.
  • the wiring structure provided by the present invention includes a plurality of first metal lines and a plurality of second metal lines crossing each other, which increases the density of the metal traces in the local area. Due to the high density of the metal traces, the first metal line and the second metal line have a larger taper angle than other regions, and thus the region is also more susceptible to electrostatic discharge. In the manufacturing process of the array substrate, the area where the trace structure is located is more likely to generate electrostatic discharge than other areas, thereby being able to protect other areas. Further, since the wiring structure provided by the present invention does not depend on the transparent electrode, the protective effect can be exhibited before the formation of the transparent electrode layer, and the occurrence of electrostatic discharge can be effectively prevented.
  • Figure 1 is a schematic view of a taper angle of a metal trace
  • FIG. 2 is a schematic diagram of a trace structure provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide a trace structure that can be applied to an array substrate of a liquid crystal display.
  • the trace structure includes a plurality of first metal lines 201 and a plurality of second metal lines 202.
  • the plurality of first metal lines 201 and the plurality of second metal lines 202 are located on different metal layers, and the insulating layer is disposed between the plurality of first metal lines 201 and the plurality of second metal lines 202, and the plurality of first metals are disposed
  • the projection of the line 201 and the plurality of second metal lines 202 cross each other.
  • the plurality of first metal lines 201 and the plurality of second metal lines 202 intersecting each other are included to increase the density of the metal traces in the local area. Since the density of the metal traces is large, the first metal lines 201 and the second metal lines 202 therein have a larger taper angle than other regions, and thus the region is also more susceptible to electrostatic discharge. In the manufacturing process of the array substrate, the area where the trace structure is located is more likely to generate electrostatic discharge than other areas, thereby being able to protect other areas. Moreover, since the trace structure provided by the embodiment of the present invention does not depend on the transparent electrode, the protective effect can be exerted before the transparent electrode layer is formed, so that the occurrence of electrostatic discharge can be effectively prevented.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • This embodiment provides an array substrate in which a wiring structure as shown in FIG. 2 is disposed.
  • a plurality of sets of trace structures 301 are disposed in the array substrate, and the trace structures 301 are disposed on the edge regions 310 of the array substrate, so that the trace structures 301 are not used.
  • the aperture ratio of the display area 320 is affected.
  • the plurality of first metal wires 201 are parallel to each other
  • the plurality of second metal wires 202 are also parallel to each other
  • the first metal wires 201 and the second metal wires 202 are perpendicular to each other.
  • the spacing d1 between adjacent first metal lines 201 is smaller than its own line width D1
  • the spacing d2 between adjacent second metal lines 202 is also smaller than its own line width D2, so that the local portion The density of the metal traces in the region is significantly increased, thereby giving the first metal line 201 and the second metal line 202 a larger cone angle.
  • the spacing d1 between adjacent first metal lines 201 and the spacing d2 between adjacent second metal lines 202 are preferably within 4 to 7 microns
  • the width D2 is preferably within 10 to 50 microns.
  • the length L1 of the first metal line 201 and the length L2 of the second metal line 202 are each preferably 10 mm or more, so that the trace structure 301 has a relatively large size to increase its ability to accumulate charges.
  • the first metal line 201 is located on the gate metal layer, that is, the first metal line 201 is in the same figure as the scan line (not shown) of the display area 320 and the common electrode line (not shown). Floor.
  • the first metal lines 201, the scan lines, and the common electrode lines may be formed in the same patterning process without separately performing a patterning process for the first metal lines 201.
  • the second metal line 202 is located on the source/drain metal layer, that is, the second metal line 202 is located in the same layer as the data line (not shown) of the display area 320.
  • the second metal lines 202 and the data lines may be formed in the same patterning process without separately performing a patterning process for the second metal lines 202.
  • the materials of the first metal line 201 and the second metal line 202 are both copper, that is, the material of the gate metal layer and the source and drain metal layers are both copper. Copper is a very low-conductivity conductor material.
  • the use of copper to make metal traces can effectively reduce the impedance of metal traces.
  • the metal trace itself has a large length, and copper can be used to make the metal trace still have a small width under the premise of satisfying low impedance, thereby increasing the aperture ratio of the liquid crystal display.
  • the metal trace formed using copper has a large taper angle, and electrostatic discharge is more likely to occur. Since the density of the metal traces in the trace structure 301 of the board edge region 310 is large, the first metal line 201 and the second metal line 202 have a larger taper angle than the metal traces of other regions, and are more likely to generate static electricity. Discharge.
  • the area where the routing structure 301 is located is more likely to generate electrostatic discharge than other areas, thereby being able to protect other areas. Further, since the wiring structure 301 does not depend on the transparent electrode, the protective effect can be exhibited before the formation of the transparent electrode layer, and the occurrence of electrostatic discharge can be effectively prevented.
  • the insulating layer between the first metal line 201 and the second metal line 202 is broken, and the first metal line 201 and the second metal line 202 are short-circuited, which is beneficial to the gate.
  • the potential of the entire metal layer and the source and drain metal layers is the same, so that electrostatic discharge between the gate metal layer and the source and drain metal layers can be more effectively prevented.
  • the first metal line 201 and the second metal line 202 are both connected to the common electrode line.
  • the common electrode line is mainly located in the gate metal layer, and a part is located in the source and drain metal layers. Therefore, the first metal line 201 may be directly connected to the common electrode line located at the gate metal layer, and the second metal line 202 may be directly connected to the common electrode line located at the source/drain metal layer.
  • the common electrode line at the gate metal layer and the common electrode line at the source/drain metal layer are inherently connected together in a subsequent manufacturing process.
  • the first metal line 201 and the second metal line 202 are also connected together, so the first metal line 201 and the second metal line 202 can be used together as a common electrode line. As part of it, there is no need to perform any processing on the trace structure 301.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • This embodiment is basically the same as the first embodiment except that in the embodiment, the first metal line in the gate metal layer is connected to the scan line, and the second metal line on the source/drain metal layer is connected to the data line. .
  • the first metal line and the second metal line can better protect the scan line and the data line.
  • the insulating layer between the first metal line 201 and the second metal line 202 is broken down, so that the first metal line 201 and The second metal line 202 is shorted to avoid electrostatic discharge between the scan line and the data line in the panel display area 320.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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Abstract

一种走线结构及阵列基板，属于显示技术领域，可用于液晶电视、液晶显示器、手机、平板电脑等显示装置，解决了现有技术难以有效防止静电放电的技术问题。走线结构包括多条第一金属线（201）和多条第二金属线（202）；多条第一金属线（201）与多条第二金属线（202）之间设置有绝缘层，且多条第一金属线（201）与多条第二金属线（202）的投影相互交叉。

Description

走线结构及阵列基板
本申请要求享有2015年6月16日提交的名称为“走线结构及阵列基板”的中国专利申请CN201510334200.5的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种走线结构及阵列基板。
背景技术
随着显示技术的发展，液晶显示器已经成为最为常见的显示装置。
阵列基板是液晶显示器中的重要部件。在阵列基板的制造过程中，通常需要依次形成栅极金属层、有源层、源漏极金属层、透明电极层等导体结构，其间还需要形成多层绝缘层。在阵列基板的制造过程中，各个导体结构会不断积累电荷，当电荷积累到一定程度时，就会发生静电放电(Electro-Static Discharge，简称ESD)。如图1所示，栅极金属层和源漏极金属层中的金属走线10由于具有较大的锥角α，尤其容易发生静电放电，这将会击穿栅极金属层和源漏极金属层之间的绝缘层，导致栅极金属层与源漏极金属层之间发生短路。
目前的阵列基板中都设置有静电保护回路，以防止静电放电的发生，但是在透明电极层形成之前，静电保护回路还没有完全形成，所以无法起到防止静电放电的效果。而静电放电一般都发生在透明电极层形成之前，因此现有技术难以有效防止静电放电的发生。
发明内容
本发明的目的在于提供一种走线结构及阵列基板，以解决现有技术难以有效防止静电放电的技术问题。
本发明提供一种走线结构，包括多条第一金属线和多条第二金属线；
所述多条第一金属线与所述多条第二金属线之间设置有绝缘层，且所述多条第一金属线与所述多条第二金属线的投影相互交叉。
进一步的是，所述多条第一金属线互相平行，所述多条第二金属线互相平行。
优选的是，相邻的第一金属线之间的间距在4至7微米以内，相邻的第二金属线之间 的间距在4至7微米以内。
优选的是，第一金属线和第二金属线的宽度均在10至50微米以内。
优选的是，第一金属线和第二金属线的长度均在10毫米以上。
优选的是，第一金属线和第二金属线的材料均为铜。
本发明还提供一种阵列基板，所述阵列基板中设置有上述的走线结构。
进一步的是，所述走线结构设置于所述阵列基板的板边区域。
优选的是，第一金属线位于栅极金属层，第二金属线位于源漏极金属层。
进一步的是，所述多条第一金属线和所述多条第二金属线均与公共电极线相连。
本发明带来了以下有益效果：本发明提供的走线结构中，包括相互交叉的多条第一金属线和多条第二金属线，增大了局部区域内金属走线的密度。由于金属走线的密度很大，会使其中的第一金属线和第二金属线具有比其他区域更大的锥角，因此该区域也更容易发生静电放电。在阵列基板的制造过程中，该走线结构所在的区域会比其他区域更容易发生静电放电，从而能够对其他区域起到保护作用。并且，本发明提供的走线结构不依赖于透明电极，因此在透明电极层形成之前就能够发挥保护作用，从而能够有效防止静电放电的发生。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是金属走线的锥角的示意图；
图2是本发明实施例提供的走线结构的示意图；
图3是本发明实施例提供的阵列基板的示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明实施例提供一种走线结构，可应用于液晶显示器的阵列基板中。如图2所示，该走线结构包括多条第一金属线201和多条第二金属线202。多条第一金属线201和多条第二金属线202位于不同的金属图层，多条第一金属线201与多条第二金属线202之间设置有绝缘层，且多条第一金属线201与多条第二金属线202的投影相互交叉。
本发明实施例提供的走线结构中，包括相互交叉的多条第一金属线201和多条第二金属线202，增大了局部区域内金属走线的密度。由于金属走线的密度很大，会使其中的第一金属线201和第二金属线202具有比其他区域更大的锥角，因此该区域也更容易发生静电放电。在阵列基板的制造过程中，该走线结构所在的区域会比其他区域更容易发生静电放电，从而能够对其他区域起到保护作用。并且，本发明实施例提供的走线结构不依赖于透明电极，因此在透明电极层形成之前就能够发挥保护作用，从而能够有效防止静电放电的发生。
实施例一：
本实施例提供一种阵列基板，其中设置有如图2所示的走线结构。如图3所示，作为一个优选方案，该阵列基板中设置有多组走线结构301，并且这些走线结构301均设置于阵列基板的板边区域310，从而不会因为这些走线结构301影响显示区域320的开口率。
如图2所示，多条第一金属线201互相平行，多条第二金属线202也互相平行，并且第一金属线201与第二金属线202互相垂直。
本实施例中，相邻的第一金属线201之间的间距d1小于其自身的线宽D1，相邻的第二金属线202之间的间距d2也小于其自身的线宽D2，使局部区域内金属走线的密度显著增大，从而使第一金属线201和第二金属线202具有更大的锥角。相邻的第一金属线201之间的间距d1及相邻的第二金属线202之间的间距d2优选在4至7微米以内，第一金属线201的宽度D1和第二金属线202的宽度D2优选在10至50微米以内。
第一金属线201的长度L1和第二金属线202的长度L2均优选在10毫米以上，使走线结构301具有相对较大的尺寸，以提高其积累电荷的能力。
本实施例中，第一金属线201位于栅极金属层，即第一金属线201与显示区域320的扫描线(图中未示出)、公共电极线(图中未示出)位于同一图层。在阵列基板的制造过程中，第一金属线201、扫描线、公共电极线可以在同一次构图工艺中形成，而不需要为第一金属线201单独进行一次构图工艺。
另一方面，第二金属线202位于源漏极金属层，即第二金属线202与显示区域320的数据线(图中未示出)位于同一图层。在阵列基板的制造过程中，第二金属线202和数据线可以在同一次构图工艺中形成，而不需要为第二金属线202单独进行一次构图工艺。
作为一个优选方案，第一金属线201和第二金属线202的材料均为铜，即栅极金属层和源漏极金属层的材料均为铜。铜是一种电阻率很低的导体材料，使用铜制作金属走线，能够有效降低金属走线的阻抗。尤其是在大尺寸液晶显示器中，金属走线本身具有很大的长度，使用铜可以在满足低阻抗的前提下，使金属走线仍然具有较小的宽度，从而提高液晶显示器的开口率。
另外，使用铜形成的金属走线具有较大的锥角，更容易发生静电放电。由于板边区域310的走线结构301中金属走线的密度较大，因此第一金属线201和第二金属线202具有比其他区域的金属走线更大的锥角，也更容易发生静电放电。
在阵列基板的制造过程中，走线结构301所在的区域会比其他区域更容易发生静电放电，从而能够对其他区域起到保护作用。并且，该走线结构301不依赖于透明电极，因此在透明电极层形成之前就能够发挥保护作用，从而能够有效防止静电放电的发生。
此外，当走线结构301发生静电放电后，第一金属线201与第二金属线202之间的绝缘层被击穿，使第一金属线201与第二金属线202短路，则有利于栅极金属层与源漏极金属层整体的电位相同，从而能够更加有效避免栅极金属层与源漏极金属层之间发生静电放电。
本实施例中，第一金属线201和第二金属线202均与公共电极线相连。公共电极线主要位于栅极金属层，也有一部分位于源漏极金属层。因此，第一金属线201可以与位于栅极金属层的公共电极线直接相连，第二金属线202可以与位于源漏极金属层的公共电极线直接相连。
位于栅极金属层的公共电极线和位于源漏极金属层的公共电极线，在后续制造过程中本来就需要连接在一起。本实施例中的走线结构301在发生静电放电之后，第一金属线201与第二金属线202也会连接在一起，所以第一金属线201和第二金属线202可以共同作为公共电极线的一部分，不需要再对走线结构301进行任何处理。
实施例二：
本实施例与实施例一基本相同，其不同点在于：本实施例中，位于栅极金属层的第一金属线与扫描线相连，位于源漏极金属层的第二金属线与数据线相连。这样在阵列基板的制造过程中，第一金属线和第二金属线能够更好的对扫描线和数据线起到保护作用。
如图2和图3所示，具体来说，当走线结构301发生静电放电后，第一金属线201与第二金属线202之间的绝缘层被击穿，使第一金属线201与第二金属线202短路，以避免面板显示区域320中的扫描线与数据线之间发生静电放电。
由于在上述过程中，第一金属线201与第二金属线202之间因绝缘层已经被击穿而短 路，在阵列基板制造完成后，对阵列基板进行测试之前，还需要利用激光对其中的走线结构301进行切割，断开各个走线结构301与其他区域的电连接，以避免扫描线与数据线之间通过走线结构301发生短路。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (11)

  1. 一种走线结构，包括多条第一金属线和多条第二金属线；
    所述多条第一金属线与所述多条第二金属线之间设置有绝缘层，且所述多条第一金属线与所述多条第二金属线的投影相互交叉。
  2. 根据权利要求1所述的走线结构，其中，所述多条第一金属线互相平行，所述多条第二金属线互相平行。
  3. 根据权利要求2所述的走线结构，其中，相邻的第一金属线之间的间距在4至7微米以内，相邻的第二金属线之间的间距在4至7微米以内。
  4. 根据权利要求2所述的走线结构，其中，相邻的第一金属线之间的间距小于第一金属线的宽度，相邻的第二金属线之间的间距小于第二金属线的宽度。
  5. 根据权利要求1所述的走线结构，其中，第一金属线和第二金属线的宽度均在10至50微米以内。
  6. 根据权利要求1所述的走线结构，其中，第一金属线和第二金属线的长度均在10毫米以上。
  7. 根据权利要求1所述的走线结构，其中，第一金属线和第二金属线的材料均为铜。
  8. 一种阵列基板，所述阵列基板中设置有一种走线结构；
    所述走线结构包括多条第一金属线和多条第二金属线；
    所述多条第一金属线与所述多条第二金属线之间设置有绝缘层，且所述多条第一金属线与所述多条第二金属线的投影相互交叉。
  9. 根据权利要求8所述的阵列基板，其中，所述走线结构设置于所述阵列基板的板边区域。
  10. 根据权利要求8所述的阵列基板，其中，第一金属线位于栅极金属层，第二金属线位于源漏极金属层。
  11. 根据权利要求8所述的阵列基板，其中，所述多条第一金属线和所述多条第二金属线均与公共电极线相连。
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