CN111323984B - 一种阵列基板、显示面板及显示装置 - Google Patents
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Abstract
本申请涉及显示技术领域,公开了一种阵列基板、显示面板及显示装置,阵列基板包括衬底基板;依次设置于衬底基板上的栅极金属层、栅极绝缘层和源漏电极金属层,其中,栅极金属层包括栅极金属和用于形成存储电容的第一电容金属层,源漏电极金属层包括源漏电极和用于形成存储电容的第二电容金属层,第一电容金属层在衬底基板上的正投影覆盖第二电容金属层在衬底基板上的正投影。本申请公开的阵列基板,通过优化存储电容结构,能够有效提升电子纸阵列基板抗静电的能力。
Description
技术领域
本申请涉及显示领域,特别涉及一种阵列基板、显示面板及显示装置。
背景技术
电子纸产品是使用电子纸模代理液晶完成显示,因其低功耗、可重复使用的特性,很受市场欢迎。目前行业内电子纸产品在阵列基板制程完成后会采用涂覆保护膜的出货方式,但在实际生产中发现,在保护膜去除过程中会产生极大的静电,静电击伤像素,产生白点不良,不良率可高达27%,且各尺寸电子纸都有发生。
上述静电现象主要是由于静电造成像素内存储电容结构的损伤导致,损伤都集中在存储电容的栅金属的边缘发生,且一个像素损伤的点只有一个,即只挑选最薄弱的一点进行击伤,在一处集中释放。目前,如何解决静电击伤像素是急需解决的问题,但由于像素区面积有限,无法直接增加大面积的静电环或其他常用的功能性防静电电路,另外,增加其他防静电电路,可能造成像素漏流增大,影响像素的正常显示。
发明内容
本申请提供了一种阵列基板,通过优化存储电容结构,能够有效提升电子纸阵列基板抗静电的能力。
为了达到上述目的,本发明提供了一种阵列基板,包括:
衬底基板;
依次设置于所述衬底基板上的栅极金属层、栅极绝缘层和源漏电极金属层,其中,所述栅极金属层包括栅极金属和用于形成存储电容的第一电容金属层,所述源漏电极金属层包括源漏电极和用于形成存储电容的第二电容金属层,所述第二电容金属层在所述衬底基板上的正投影覆盖所述第一电容金属层在所述衬底基板上的正投影。
上述阵列基板,在存储电容结构处,使得第一电容金属层在衬底基板上的正投影覆盖第二电容金属层在衬底基板上的正投影,即第一电容金属层包裹第二电容金属层,当静电从像素表面的透明薄膜导电层进入到第一电容金属层时,在存储电容的边缘不会形成尖端结构,加之在第二电容金属层边缘位置的栅极绝缘层可以平坦覆盖,致密性良好,使得存储电容结构的抗静电能力增强,大大减小了静电在存储电容处释放的概率,从而避免静电在存储电容处造成损伤。
因此,本发明提供的阵列基板,在存储电容结构中,使用第一电容金属层包裹第二电容金属层的结构,大大提高了阵列基板抗静电能力,减少了因静电造成的显示类不良,控制静电走向。除此之外,由于不需要增加其他的防静电电路,本申请中的结构可兼容现有的电子纸膜层结构,不需要增加额外的制程,且对原像素结构变动较小,不影响像素的正常显示。
优选地,所述第一电容金属层在所述衬底基板上的正投影的边缘与所述第二电容金属层在所述衬底基板上的正投影的边缘之间的距离大于等于3um。
优选地,沿列方向,每相邻两个第二电容金属层之间通过电容走线连接,其中,每一个所述第二电容金属层与所述电容走线连接的部位为梯形结构,所述梯形结构靠近所述第二电容金属层的边长大于所述梯形结构远离所述第二电容金属层的边长。
优选地,所述栅极金属层还包括冗余栅极金属层,所述冗余栅极金属层与其它金属层之间独立无连接。
优选地,所述源漏电极与所述冗余栅极金属层对应的部位具有网格结构。
优选地,还包括:依次设置于所述源漏电极金属层上的钝化层和透明薄膜导电层。
优选地,本申请还提供一种显示面板,包括上述任一项所述的阵列基板。
优选地,本申请还提供一种显示装置,包括上述显示面板。
附图说明
图1为现有技术中的存储电容的一种截面结构示意图;
图2为本申请中的阵列基板的一种截面结构示意图;
图3为本申请中的存储电容的一种截面结构示意图;
图4为本申请中的阵列基板的一种结构表面示意图。
图中:
01-栅金属;02-栅极绝缘层;03-源漏金属;1-衬底基板;2-栅极金属层;21-栅极金属;22-第一电容金属层;23-冗余栅极金属层;3-栅极绝缘层;4-源漏电极金属层;41-源漏电极;42-第二电容金属层;5-钝化层;6-透明薄膜导电层;7-电容走线。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
一般静电荷释放到某一物体时,其临近的导体表面会产生感应电荷,感应电荷均匀分布在导体表面,但当导体表面存在曲率时(不平坦,存在弯曲、尖角),电荷在曲率半径大的位置聚集,电荷密度更高,与其他物体形成的电场更大,容易发生放电现象,此现象即为尖端放电。
现有的电子纸产品产生静电一般发生在像素内存储电容结构,如图1所示,损伤一般集中在存储电容栅金属的边缘发生,发生上述现象主要原因有两个:1、常规像素的存储电容结构为源漏金属03包裹栅金属01,而栅金属01的坡度角大,在栅金属01图形边缘易形成尖端结构(如图1中A处所示),曲率变化大,电荷分布密度大,容易放电,形成损伤点;2、由于栅金属01坡度角的存在,栅极绝缘层02在坡度角位置存在缺陷,相比较于平坦位置更为疏松,容易被击穿。
基于上述原因,请参考图2-4,本发明实施例提供了一种阵列基板,用于电子纸产品,该本发明提供的阵列基板包括:衬底基板1;依次设置于衬底基板1上的栅极金属层2、栅极绝缘层3和源漏电极金属层4,其中,栅极金属层2包括栅极金属21和用于形成存储电容的第一电容金属层22,源漏电极金属层4包括源漏电极41和用于形成存储电容的第二电容金属层42,第一电容金属层22在衬底基板1上的正投影覆盖第二电容金属层42在衬底基板1上的正投影。此外,还包括依次设置于源漏电极金属层4上的钝化层5和透明薄膜导电层6。
上述阵列基板,使得第一电容金属层22在衬底基板1上的正投影覆盖第二电容金属层42在衬底基板1上的正投影,即改变了现有技术中第二电容金属层包裹第一电容金属层的结构,使得第一电容金属层22包裹第二电容金属层42,当静电从像素表面的透明薄膜导电层6进入到第一电容金属层22时,上述结构使得在存储电容的边缘不会形成尖端结构(如图3中B处所示),且在第二电容金属层42边缘位置可以平坦覆盖,致密性良好,使得该结构的抗静电能力增强,大大减小了静电在存储电容处释放的概率,从而避免静电在存储电容处造成损伤。
因此,本发明实施例提供的阵列基板,在存储电容结构中,使用第一电容金属层22包裹第二电容金属层42的结构,大大提高了阵列基板抗静电能力,减少了因静电造成的显示类不良,控制静电走向。除此之外,由于不需要增加其他的防静电电路,本申请中的结构可兼容现有的电子纸膜层结构,不需要增加额外的制程,且对原像素结构变动较小,不影响像素的正常显示。
一种可选的实施例中,第一电容金属层22在衬底基板1上的正投影的边缘距离第二电容金属层42在衬底基板1上的正投影的边缘至少3um,能够保证存储电容的边缘不会形成尖端结构,且第二电容金属层42的边缘位置可以平坦覆盖,减小静电释放的概率。
一种可选的实施例中,如图4所示,沿列方向,每相邻两个第二电容金属层42之间通过电容走线7连接,且每一个第二电容金属层42中,该第二电容金属层42与电容走线7连接的部位为梯形结构,该梯形结构靠近第二电容金属层42的边长大于该梯形结构远离第二电容金属层42的边长。通过采用梯形走线,可增大交叠位置第一电容金属层22与第二电容金属层42的正对面积,当静电进入时可以减少走线交叠位置的电荷密度,降低该处的电场强度,从而减小在走线处造成静电损伤的概率。
一种可选的实施例中,上述栅极金属层2还包括与其它金属层之间独立无连接的冗余栅极金属层23,且源漏电极41与该冗余栅极金属层23对应的部位具有网格结构,以此形成人为制造的静电释放点。当静电由表面透明薄膜导电层6进入像素后,向存储电容和薄膜晶体管方向同时传导,由于存储电容结构采用第一电容金属层22包裹第二电容金属层42和梯形走线的设计,使得静电不容易在存储电容处释放。当静电向薄膜晶体管传导时,经过冗余栅极金属层23上的源漏电极41时,由于源漏电极41采用网状结构,CD变小,导致电荷密度在源漏电极41CD减小的区域会突然增加,在该位置电场强度增加,加之栅极金属21和源漏电极41的交叠结构形成尖端,导致栅极绝缘层3的致密性变差,进而使得静电大概率在冗余栅极金属层23区域最薄弱的一点释放。由于冗余栅极金属层23没有其他的信号连接,损伤在此处也不会产生显示类不良,从而提高了产品的抗静电能力。
基于同一发明思路,本申请还提供一种显示面板,包括上述阵列基板,由于上述阵列基板抗静电能力大大提高,在采取涂覆保护膜的出货方式时,在保护膜去除过程中则不会产生极大的静电,减小了静电击伤像素的概率,降低产品的不良率。
基于同一发明思路,本申请还提供一种显示装置,包括上述显示面板,由于该显示面板的不良率降低,提高了显示装置的质量。
显然,本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (6)
1.一种阵列基板,其特征在于,包括:
衬底基板;
依次设置于所述衬底基板上的栅极金属层、栅极绝缘层和源漏电极金属层,其中,所述栅极金属层包括栅极金属和用于形成存储电容的第一电容金属层,所述源漏电极金属层包括源漏电极和用于形成存储电容的第二电容金属层,所述第一电容金属层在所述衬底基板上的正投影覆盖所述第二电容金属层在所述衬底基板上的正投影;
所述栅极金属层还包括冗余栅极金属层,所述冗余栅极金属层与其它金属层之间独立无连接;
所述源漏电极与所述冗余栅极金属层对应的部位具有网格结构。
2.根据权利要求1所述的阵列基板,其特征在于,所述第一电容金属层在所述衬底基板上的正投影的边缘与所述第二电容金属层在所述衬底基板上的正投影的边缘之间的距离大于等于3um。
3.根据权利要求1所述的阵列基板,其特征在于,沿列方向,每相邻两个第二电容金属层之间通过电容走线连接,其中,每一个所述第二电容金属层与所述电容走线连接的部位为梯形结构,所述梯形结构靠近所述第二电容金属层的边长大于所述梯形结构远离所述第二电容金属层的边长。
4.根据权利要求1所述的阵列基板,其特征在于,还包括:依次设置于所述源漏电极金属层上的钝化层和透明薄膜导电层。
5.一种显示面板,其特征在于,包括如权利要求1-4任一项所述的阵列基板。
6.一种显示装置,其特征在于,包括如权利要求5所述的显示面板。
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