WO2016201741A1

WO2016201741A1 - Wiring structure and array substrate

Info

Publication number: WO2016201741A1
Application number: PCT/CN2015/083423
Authority: WO
Inventors: 徐亮
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2015-06-16
Filing date: 2015-07-07
Publication date: 2016-12-22
Also published as: CN104865764A; CN104865764B

Abstract

A wiring structure and an array substrate, which relate to the technical field of display, can be used for display devices such as a liquid crystal display television, a liquid crystal display, a mobile phone and a tablet computer, and resolve the technical problem of difficulty in effectively preventing static electricity from discharging in the prior art. The wiring structure comprises multiple first metal wires (201) and multiple second metal wires (202). Insulation layers are disposed among the multiple first metal wires (201) and the multiple second metal wires (202), and projections of the multiple first metal wires (201) and the multiple second metal wires (202) are mutually intersected.

Description

Trace structure and array substrate

The present application claims priority to Chinese Patent Application No. CN20151033420, filed on Jun. 16, 2015, which is hereby incorporated by reference.

Technical field

The present invention relates to the field of display technologies, and in particular to a trace structure and an array substrate.

Background technique

With the development of display technology, liquid crystal displays have become the most common display devices.

The array substrate is an important component in the liquid crystal display. In the manufacturing process of the array substrate, it is generally necessary to sequentially form a conductor structure such as a gate metal layer, an active layer, a source/drain metal layer, and a transparent electrode layer, and a plurality of insulating layers are required to be formed therebetween. In the manufacturing process of the array substrate, each conductor structure accumulates electric charge continuously, and when the electric charge accumulates to a certain extent, Electro-Static Discharge (ESD) occurs. As shown in FIG. 1, the metal traces 10 in the gate metal layer and the source/drain metal layer are particularly prone to electrostatic discharge due to a large taper angle α, which will break the gate metal layer and the source and drain electrodes. The insulating layer between the metal layers causes a short circuit between the gate metal layer and the source and drain metal layers.

In the current array substrate, an electrostatic protection circuit is provided to prevent the occurrence of electrostatic discharge. However, before the formation of the transparent electrode layer, the electrostatic protection circuit is not completely formed, so that the electrostatic discharge prevention effect cannot be achieved. Electrostatic discharge generally occurs before the formation of the transparent electrode layer, so it is difficult to effectively prevent the occurrence of electrostatic discharge in the prior art.

Summary of the invention

It is an object of the present invention to provide a wiring structure and an array substrate to solve the technical problem that it is difficult to effectively prevent electrostatic discharge in the prior art.

The present invention provides a trace structure including a plurality of first metal lines and a plurality of second metal lines;

An insulating layer is disposed between the plurality of first metal lines and the plurality of second metal lines, and a projection of the plurality of first metal lines and the plurality of second metal lines intersect each other.

Further, the plurality of first metal lines are parallel to each other, and the plurality of second metal lines are parallel to each other.

Preferably, the spacing between adjacent first metal lines is within 4 to 7 microns, between adjacent second metal lines The spacing is within 4 to 7 microns.

Preferably, the widths of the first metal line and the second metal line are all within 10 to 50 microns.

Preferably, the length of the first metal wire and the second metal wire are both 10 mm or more.

Preferably, the materials of the first metal wire and the second metal wire are both copper.

The invention also provides an array substrate, wherein the array structure is provided in the array substrate.

Further, the routing structure is disposed on a board edge region of the array substrate.

Preferably, the first metal line is on the gate metal layer and the second metal line is on the source and drain metal layers.

Further, the plurality of first metal lines and the plurality of second metal lines are both connected to the common electrode line.

The invention brings about the following beneficial effects: the wiring structure provided by the present invention includes a plurality of first metal lines and a plurality of second metal lines crossing each other, which increases the density of the metal traces in the local area. Due to the high density of the metal traces, the first metal line and the second metal line have a larger taper angle than other regions, and thus the region is also more susceptible to electrostatic discharge. In the manufacturing process of the array substrate, the area where the trace structure is located is more likely to generate electrostatic discharge than other areas, thereby being able to protect other areas. Further, since the wiring structure provided by the present invention does not depend on the transparent electrode, the protective effect can be exhibited before the formation of the transparent electrode layer, and the occurrence of electrostatic discharge can be effectively prevented.

Other features and advantages of the invention will be set forth in the description which follows, The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, a brief description of the drawings required in the description of the embodiments will be briefly made below:

Figure 1 is a schematic view of a taper angle of a metal trace;

2 is a schematic diagram of a trace structure provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of an array substrate according to an embodiment of the present invention.

detailed description

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and embodiments, in which the present invention can be applied to the technical problems, and the implementation of the technical effects can be fully understood and implemented. It should be noted that the various embodiments of the present invention and the various features of the various embodiments may be combined with each other, and the technical solutions formed are all within the scope of the present invention.

Embodiments of the present invention provide a trace structure that can be applied to an array substrate of a liquid crystal display. As shown in FIG. 2, the trace structure includes a plurality of first metal lines 201 and a plurality of second metal lines 202. The plurality of first metal lines 201 and the plurality of second metal lines 202 are located on different metal layers, and the insulating layer is disposed between the plurality of first metal lines 201 and the plurality of second metal lines 202, and the plurality of first metals are disposed The projection of the line 201 and the plurality of second metal lines 202 cross each other.

In the routing structure provided by the embodiment of the present invention, the plurality of first metal lines 201 and the plurality of second metal lines 202 intersecting each other are included to increase the density of the metal traces in the local area. Since the density of the metal traces is large, the first metal lines 201 and the second metal lines 202 therein have a larger taper angle than other regions, and thus the region is also more susceptible to electrostatic discharge. In the manufacturing process of the array substrate, the area where the trace structure is located is more likely to generate electrostatic discharge than other areas, thereby being able to protect other areas. Moreover, since the trace structure provided by the embodiment of the present invention does not depend on the transparent electrode, the protective effect can be exerted before the transparent electrode layer is formed, so that the occurrence of electrostatic discharge can be effectively prevented.

Embodiment 1:

This embodiment provides an array substrate in which a wiring structure as shown in FIG. 2 is disposed. As shown in FIG. 3, as a preferred solution, a plurality of sets of trace structures 301 are disposed in the array substrate, and the trace structures 301 are disposed on the edge regions 310 of the array substrate, so that the trace structures 301 are not used. The aperture ratio of the display area 320 is affected.

As shown in FIG. 2, the plurality of first metal wires 201 are parallel to each other, the plurality of second metal wires 202 are also parallel to each other, and the first metal wires 201 and the second metal wires 202 are perpendicular to each other.

In this embodiment, the spacing d1 between adjacent first metal lines 201 is smaller than its own line width D1, and the spacing d2 between adjacent second metal lines 202 is also smaller than its own line width D2, so that the local portion The density of the metal traces in the region is significantly increased, thereby giving the first metal line 201 and the second metal line 202 a larger cone angle. The spacing d1 between adjacent first metal lines 201 and the spacing d2 between adjacent second metal lines 202 are preferably within 4 to 7 microns, the width D1 of the first metal line 201 and the second metal line 202 The width D2 is preferably within 10 to 50 microns.

The length L1 of the first metal line 201 and the length L2 of the second metal line 202 are each preferably 10 mm or more, so that the trace structure 301 has a relatively large size to increase its ability to accumulate charges.

In this embodiment, the first metal line 201 is located on the gate metal layer, that is, the first metal line 201 is in the same figure as the scan line (not shown) of the display area 320 and the common electrode line (not shown). Floor. In the manufacturing process of the array substrate, the first metal lines 201, the scan lines, and the common electrode lines may be formed in the same patterning process without separately performing a patterning process for the first metal lines 201.

On the other hand, the second metal line 202 is located on the source/drain metal layer, that is, the second metal line 202 is located in the same layer as the data line (not shown) of the display area 320. In the manufacturing process of the array substrate, the second metal lines 202 and the data lines may be formed in the same patterning process without separately performing a patterning process for the second metal lines 202.

As a preferred solution, the materials of the first metal line 201 and the second metal line 202 are both copper, that is, the material of the gate metal layer and the source and drain metal layers are both copper. Copper is a very low-conductivity conductor material. The use of copper to make metal traces can effectively reduce the impedance of metal traces. Especially in large-size liquid crystal displays, the metal trace itself has a large length, and copper can be used to make the metal trace still have a small width under the premise of satisfying low impedance, thereby increasing the aperture ratio of the liquid crystal display.

In addition, the metal trace formed using copper has a large taper angle, and electrostatic discharge is more likely to occur. Since the density of the metal traces in the trace structure 301 of the board edge region 310 is large, the first metal line 201 and the second metal line 202 have a larger taper angle than the metal traces of other regions, and are more likely to generate static electricity. Discharge.

In the manufacturing process of the array substrate, the area where the routing structure 301 is located is more likely to generate electrostatic discharge than other areas, thereby being able to protect other areas. Further, since the wiring structure 301 does not depend on the transparent electrode, the protective effect can be exhibited before the formation of the transparent electrode layer, and the occurrence of electrostatic discharge can be effectively prevented.

In addition, after the electrostatic discharge occurs in the trace structure 301, the insulating layer between the first metal line 201 and the second metal line 202 is broken, and the first metal line 201 and the second metal line 202 are short-circuited, which is beneficial to the gate. The potential of the entire metal layer and the source and drain metal layers is the same, so that electrostatic discharge between the gate metal layer and the source and drain metal layers can be more effectively prevented.

In this embodiment, the first metal line 201 and the second metal line 202 are both connected to the common electrode line. The common electrode line is mainly located in the gate metal layer, and a part is located in the source and drain metal layers. Therefore, the first metal line 201 may be directly connected to the common electrode line located at the gate metal layer, and the second metal line 202 may be directly connected to the common electrode line located at the source/drain metal layer.

The common electrode line at the gate metal layer and the common electrode line at the source/drain metal layer are inherently connected together in a subsequent manufacturing process. After the electrostatic discharge occurs in the trace structure 301 in this embodiment, the first metal line 201 and the second metal line 202 are also connected together, so the first metal line 201 and the second metal line 202 can be used together as a common electrode line. As part of it, there is no need to perform any processing on the trace structure 301.

Embodiment 2:

This embodiment is basically the same as the first embodiment except that in the embodiment, the first metal line in the gate metal layer is connected to the scan line, and the second metal line on the source/drain metal layer is connected to the data line. . Thus, in the manufacturing process of the array substrate, the first metal line and the second metal line can better protect the scan line and the data line.

As shown in FIG. 2 and FIG. 3, specifically, after the electrostatic discharge occurs in the trace structure 301, the insulating layer between the first metal line 201 and the second metal line 202 is broken down, so that the first metal line 201 and The second metal line 202 is shorted to avoid electrostatic discharge between the scan line and the data line in the panel display area 320.

Due to the short process between the first metal line 201 and the second metal line 202 due to the breakdown of the insulating layer in the above process After the array substrate is manufactured, before the array substrate is tested, it is necessary to cut the trace structure 301 by using a laser, and disconnect the electrical connection between each trace structure 301 and other regions to avoid scan lines and data. A short circuit occurs between the wires through the trace structure 301.

While the embodiments of the present invention have been described above, the described embodiments are merely illustrative of the embodiments of the invention and are not intended to limit the invention. Any modification and variation of the form and details of the embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. It is still subject to the scope defined by the appended claims.

Claims

A trace structure comprising a plurality of first metal lines and a plurality of second metal lines;

An insulating layer is disposed between the plurality of first metal lines and the plurality of second metal lines, and a projection of the plurality of first metal lines and the plurality of second metal lines intersect each other.
The wiring structure according to claim 1, wherein the plurality of first metal lines are parallel to each other, and the plurality of second metal lines are parallel to each other.
The trace structure of claim 2 wherein the spacing between adjacent first metal lines is within 4 to 7 microns and the spacing between adjacent second metal lines is within 4 to 7 microns.
The routing structure according to claim 2, wherein a spacing between adjacent first metal lines is smaller than a width of the first metal lines, and a spacing between adjacent second metal lines is smaller than a width of the second metal lines .
The trace structure of claim 1 wherein the first metal line and the second metal line each have a width within 10 to 50 microns.
The wiring structure according to claim 1, wherein the first metal wire and the second metal wire each have a length of 10 mm or more.
The wiring structure according to claim 1, wherein the material of the first metal line and the second metal line is copper.
An array substrate, wherein the array substrate is provided with a trace structure;

The trace structure includes a plurality of first metal lines and a plurality of second metal lines;

An insulating layer is disposed between the plurality of first metal lines and the plurality of second metal lines, and a projection of the plurality of first metal lines and the plurality of second metal lines intersect each other.
The array substrate according to claim 8, wherein the trace structure is disposed in a board edge region of the array substrate.
The array substrate of claim 8 wherein the first metal line is on the gate metal layer and the second metal line is on the source and drain metal layers.
The array substrate according to claim 8, wherein the plurality of first metal lines and the plurality of second metal lines are each connected to a common electrode line.