WO2016197410A1 - 多晶硅薄膜的制备方法及多晶硅tft结构 - Google Patents

多晶硅薄膜的制备方法及多晶硅tft结构 Download PDF

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WO2016197410A1
WO2016197410A1 PCT/CN2015/082265 CN2015082265W WO2016197410A1 WO 2016197410 A1 WO2016197410 A1 WO 2016197410A1 CN 2015082265 W CN2015082265 W CN 2015082265W WO 2016197410 A1 WO2016197410 A1 WO 2016197410A1
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silicon
polysilicon
polysilicon film
preparing
thin film
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French (fr)
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张良芬
连水池
罗长诚
吴元均
徐源竣
郭海成
王文
陈荣盛
周玮
张猛
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深圳市华星光电技术有限公司
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Priority to US14/892,199 priority Critical patent/US10204787B2/en
Publication of WO2016197410A1 publication Critical patent/WO2016197410A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for preparing a polysilicon film and a polysilicon TFT structure.
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • LTPS Low Temperature Poly-Silicon
  • AMLCDs active liquid crystal displays
  • AMOLEDs active organic light emitting diode displays
  • a-Si amorphous silicon
  • LTPS TFT has high carrier mobility, up to tens to hundreds of cm 2 / VS, and the device has fast response speed and good stability, which can meet high resolution.
  • LTPS TFT can also be used to build peripheral drive circuits for circuit integration.
  • Low temperature polysilicon is a branch of polysilicon (poly-Si) technology.
  • the polysilicon material has a high electron mobility derived from the polycrystalline structure of the polysilicon itself.
  • polycrystalline silicon is composed of a plurality of ordered grains.
  • the polysilicon film can be directly obtained by chemical vapor deposition (CVD); the amorphous silicon can also be crystallized by different annealing treatments, and the commonly used methods are: solid phase crystallization (Solid) Phase Crystallization (SPC), Metal-Induced Crystallization (MIC), Excimer Laser Annealing (ELA), and the like.
  • CVD chemical vapor deposition
  • amorphous silicon can also be crystallized by different annealing treatments, and the commonly used methods are: solid phase crystallization (Solid) Phase Crystallization (SPC), Metal-Induced Crystallization (MIC), Excimer Laser Annealing (ELA), and the like.
  • the main factor limiting the characteristics of polysilicon TFT devices is the grain boundary between polycrystalline silicon grains, and there are a large number of defects at the grain boundaries.
  • the polycrystalline silicon thin films obtained by the above different methods have different grain sizes and distributions, and the number of grain boundary defects is also greatly different.
  • the existing research literature proposes many methods for improving the quality of polysilicon films. Studies have shown that the use of silicon ion self-injection to amorphize the polysilicon film and then recrystallize can reduce the density of the nucleus and increase the grain size after recrystallization.
  • N. Yamauchi et al. (IEEE Electron Device Letters, Vol. 11, No. 1, 1990 and Journal of Applied Physics, vol. 75, pp. 3235-3257, 1994) produced TFTs using the polycrystalline silicon obtained by the above method. As the grain size increases, the mobility of the device increases, and the subthreshold swings steeply. However, at the same time, it is also reported that the uniformity of small-sized devices is seriously degraded due to the random distribution of large crystal grains.
  • Another object of the present invention is to provide a polysilicon TFT structure capable of reducing a grain boundary barrier in an open state, increasing carrier mobility, increasing an on-state current, reducing a threshold voltage, and improving TFT characteristics.
  • the present invention first provides a method for preparing a polysilicon film, comprising the following steps:
  • Step 1 Providing a substrate on which a polysilicon film is formed, the thickness of the polysilicon film conforming to a thickness required for manufacturing a semiconductor device;
  • Step 2 Perform self-injection of silicon ions on the polysilicon film, and the implantation dose of silicon ions is lower than a measurement limit for amorphizing polysilicon.
  • the method for preparing the polysilicon film further includes: step 3, performing post-annealing treatment on the silicon wafer self-implanted polysilicon film.
  • the substrate in the step 1 is a silicon substrate covered with a buffer layer, a glass substrate covered with a buffer layer, or a flexible substrate covered with a buffer layer.
  • the buffer layer is made of silicon oxide or silicon nitride. Or a combination of the two.
  • the step 1 forms the polysilicon film by directly vapor depositing polysilicon
  • the step 1 is to make amorphous silicon by a solid phase crystallization process or a metal induced crystallization process. Crystallizing to form the polysilicon film;
  • the amorphous silicon is subjected to liquid phase crystallization by using a laser or an LED as a heat source to form the polysilicon film.
  • the polysilicon film is subjected to silicon ion self-injection using an ion implanter or an ion sprayer.
  • the step 3 is post-annealed using a furnace tube or a rapid thermal annealing apparatus.
  • the method for preparing the polysilicon film further requires depositing a protective layer on the polysilicon film before the silicon ion self-injection, and the material of the protective layer is silicon oxide, silicon nitride, or both. combination.
  • the invention also provides a preparation method of a polysilicon film, comprising the following steps:
  • Step 1 Providing a substrate on which a polysilicon film is formed, the thickness of the polysilicon film conforming to a thickness required for manufacturing a semiconductor device;
  • Step 2 performing silicon ion self-injection on the polysilicon film, and implanting a dose of silicon ions is lower than a measurement limit for amorphizing polysilicon;
  • Step 3 performing post-annealing treatment on the silicon wafer self-implanted polysilicon film
  • the substrate in the step 1 is a silicon substrate covered with a buffer layer, a glass substrate covered with a buffer layer, or a flexible substrate covered with a buffer layer.
  • the buffer layer is made of silicon oxide or nitrogen. Silicon, or a combination of the two;
  • the polysilicon film is self-injected by using an ion implanter or an ion sprayer.
  • the present invention also provides a polysilicon TFT structure, comprising: a substrate, a buffer layer covering the substrate, an island-shaped semiconductor layer disposed on the buffer layer, a gate insulating layer covering the island-shaped semiconductor layer, a gate disposed on the gate insulating layer, a passivation layer disposed on the gate and the gate insulating layer, and a source and a drain disposed on the passivation layer;
  • the island-shaped semiconductor layer includes a channel region located in a middle portion of the island-shaped semiconductor layer, and a source contact region and a drain contact region respectively located at two sides of the channel region, the source contacting the source a contact region, the drain contacting the drain contact region;
  • the polycrystalline silicon thin film prepared by the method for preparing the polycrystalline silicon thin film is formed by photolithography and ion doping, and the source contact region and the drain contact region correspond to an ion doped region;
  • the polysilicon TFT structure belongs to a P-type TFT device or an N-type TFT device.
  • the material of the gate insulating layer and the passivation layer is silicon oxide, silicon nitride, or a combination of the two, and the material of the gate, the source, and the drain is aluminum.
  • a method for preparing a polycrystalline silicon film provided by the present invention Silicon ion self-injection is applied to the polysilicon film, and the implantation dose of silicon ions is lower than the measurement limit of amorphization of the polysilicon, so that the implanted silicon ions form interstitial silicon and move to the polycrystalline silicon grain boundary, which can reduce the grain boundary defects of the polysilicon. Density, improving the quality of polysilicon film.
  • the invention provides a polysilicon TFT structure, wherein the island-shaped semiconductor layer is made of a polysilicon film which is self-injected through low-dose silicon ions, which can reduce the grain boundary barrier in the open state, increase the carrier mobility, and increase The on-state current is reduced, the threshold voltage is reduced, and the TFT characteristics are improved.
  • FIG. 1 is a flow chart of a method for preparing a polycrystalline silicon film of the present invention
  • FIGS. 2 and 3 are schematic views showing the first step of the method for preparing a polycrystalline silicon film of the present invention
  • FIG. 4 is a schematic view showing the second step of the method for preparing a polycrystalline silicon film of the present invention.
  • step 5 is a different silicon ion implantation dose and corresponding sample label table in step 2 of the method for preparing a polycrystalline silicon film of the present invention
  • FIG. 6 is a cross-sectional view showing the structure of a polysilicon TFT of the present invention.
  • Figure 8 is a data table corresponding to Figure 7.
  • the present invention first provides a method for preparing a polysilicon film, comprising the following steps:
  • Step 1 Referring to Figures 2 and 3, a substrate 1 is provided on which a polysilicon film 3 is formed, the thickness of which is in accordance with the thickness required for fabricating a semiconductor device.
  • the substrate 1 in the step 1 is a silicon substrate covered with the buffer layer 11, a glass substrate covered with the buffer layer 11, or a flexible substrate covered with the buffer layer 11, the material of the buffer layer 11.
  • the material of the buffer layer 11 is silicon dioxide (SiO 2 ).
  • This step 1 can form the polysilicon film 3 by directly vapor-depositing polysilicon.
  • the amorphous silicon crystal may be crystallized to form the polysilicon film 3 by a solid phase crystallization process or a metal induced crystallization process.
  • the amorphous silicon is liquid-crystallized by using a laser or an LED as a heat source to form the polysilicon film 3.
  • the amorphous silicon crystal is formed into the polysilicon film 3 by a metal induced crystallization process.
  • the detailed process of the step 1 is: firstly, using low pressure chemical vapor deposition (LPCVD) deposition. a layer of amorphous silicon film 3' having a thickness of 50 nm; and depositing a thin layer (thickness ⁇ 5 nm) of metallic nickel 4' on the amorphous silicon film 3'; then annealing the amorphous silicon by nitrogen annealing, The annealing temperature was 600 ° C and the annealing time was 10 hours. After the amorphous silicon was crystallized to form the polycrystalline silicon film 3, the substrate 1 was washed with a warmed hydrogen peroxide aqueous mixture to remove the residual metallic nickel 4'.
  • LPCVD low pressure chemical vapor deposition
  • Step 2 performing silicon ion self-injection on the polysilicon film 3, and the implantation dose of the silicon ions should be lower than a measurement limit for amorphizing the polysilicon.
  • the implantation dose of the silicon ions is 4 ⁇ 10 14 /cm 2 . 8 ⁇ 10 14 /cm 2 .
  • the amorphous silicon crystal is still formed into a polycrystalline silicon thin film 3 by a metal induced crystallization process, and the polycrystalline silicon thin film 3 is subjected to silicon ion self-injection before the silicon polysilicon film 3 can be used according to actual needs.
  • a protective layer 4 is deposited thereon, and the thickness of the protective layer 4 is selected according to the large energy of the subsequent silicon ion implantation. Of course, the protective layer 4 may not be used. In the embodiment, the thickness is protected by 25 nm.
  • the material of the protective layer 4 is silicon oxide, silicon nitride, or a combination of the two.
  • the material of the protective layer 4 is SiO 2 ; then using an ion implanter or an ion sprayer
  • the polysilicon film 3 is self-injected with silicon ions, and the energy injected is 15 keV.
  • the present invention performs experiments by injecting a plurality of samples of different doses of silicon ions: as shown in FIG. 5, the silicon ion implantation dose is 2 ⁇ 10, respectively.
  • the sample number of 14 /cm 2 , 4 ⁇ 10 14 /cm 2 , 6 ⁇ 10 14 /cm 2 , 8 ⁇ 10 14 /cm 2 , 10 ⁇ 10 14 /cm 2 , 100 ⁇ 10 14 /cm 2 is 1. 2, 3, 4, 5, 6, each sample of each label selected 20 for subsequent polysilicon TFT performance test.
  • step 3 is further performed on the polysilicon film 3 which is completed by self-injection of silicon ions, and the temperature is 600 ° C and the annealing time is 4 hours.
  • the method for preparing the polysilicon film of the invention enables the implanted silicon ions to form interstitial silicon and move to the polycrystalline silicon grain boundary, which can reduce the grain boundary defect density of the polysilicon and improve the quality of the polysilicon film.
  • the present invention further provides a polysilicon TFT structure, comprising: a substrate 1, a buffer layer 11 covering the substrate 1, and a substrate disposed thereon.
  • the island-shaped semiconductor layer 30 on the buffer layer 11, the gate insulating layer 5 covering the island-shaped semiconductor layer 30, the gate electrode 7 provided on the gate insulating layer 5, and the gate electrode 7 and the gate electrode A passivation layer 8 on the insulating layer 5, and a source 91 and a drain 92 provided on the passivation layer 8.
  • the process of fabricating the polysilicon TFT structure is as follows: after the polysilicon film 3 is prepared according to the above method, the polysilicon film 3 is first photolithographically formed into an island shape; then a gate insulating layer 5 having a thickness of 50 nm is deposited by LPCVD, the gate insulating layer
  • the material of 5 is silicon oxide, silicon nitride, or a combination of the two, preferably SiO 2 ; then depositing aluminum having a thickness of 300 nm and photolithography as gate 7; and blocking the gate 7 to the island after photolithography
  • the polycrystalline silicon film is self-aligned ion implantation doping, the dose of ion implantation is 4 ⁇ 10 15 /cm 2 , and the implantation energy is 20 keV, so that the island-shaped polycrystalline silicon film becomes the island-shaped semiconductor layer 30, wherein, corresponding to ion doping
  • the region forms the source contact region 32 and the drain contact region 33, and the region which is not ion
  • Silicon or a combination of the two, preferably SiO 2 ; sputtering 700 nm thick Aluminum (containing 1% silicon) and photolithographically as source 91 and drain 92, said source 91 contacting said source contact region 32 via said first via 81, said drain 92 via said The second via 82 contacts the drain contact region 33; finally, a hydrogenation treatment is performed for 30 minutes.
  • a P-type TFT device or an N-type TFT device can be obtained according to different ion doping ions of the island-shaped polysilicon film, such as doping boron ions to obtain a P-type TFT device, doped with phosphorus Ions can produce N-type TFT devices.
  • the length L and the width W of the channel region of the polysilicon TFT are both 10 ⁇ m
  • the source-drain voltage V ds is -0.1 V
  • the dose of silicon ion implantation is 4 ⁇ 10 14 /cm 2 .
  • the carrier mobility is improved, and as the dose of silicon ion implantation increases, the carrier mobility also increases, because the implantation dose of silicon ions is lower than that of polysilicon.
  • the measurement limit of amorphization the implanted silicon ions form interstitial silicon, and move to the polycrystalline silicon grain boundary, reducing the grain boundary defect density of polysilicon.
  • the carrier mobility is significantly decreased. This is because a large amount of silicon ions are implanted into the polysilicon film, and the polysilicon is amorphized to different degrees.
  • the preparation method of the invention does not perform high-temperature annealing recrystallization treatment on the polysilicon film implanted with silicon ions, and the lattice structure of the polysilicon has been destroyed, resulting in deterioration of the performance of the polysilicon TFT.
  • the test results verified that the preparation method of the polycrystalline silicon thin film of the present invention sets the dose of silicon ion self-injection to the polycrystalline silicon thin film 3 to be lower than the measurement limit for amorphizing the polycrystalline silicon.
  • the method for preparing a polysilicon film of the present invention comprises: implanting silicon ions into a polysilicon film, and implanting a dose of silicon ions is lower than a measurement limit of amorphization of the polysilicon, so that the implanted silicon ions form interstitial silicon, And moving to the polycrystalline silicon grain boundary, can reduce the grain boundary defect density of polysilicon, and improve the quality of the polysilicon film.
  • the island-shaped semiconductor layer is made of a polysilicon film which is self-implanted by low-dose silicon ions, which can lower the grain boundary barrier in the open state, increase the carrier mobility, and increase the on-state current. The threshold voltage is reduced to improve the TFT characteristics.

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  • Recrystallisation Techniques (AREA)

Abstract

提供一种多晶硅薄膜的制备方法及多晶硅TFT结构。该多晶硅薄膜的制备方法包括：步骤1、提供一基片(1)，在所述基片(1)上形成一层多晶硅薄膜(3)，该多晶硅薄膜(3)的厚度符合制造半导体器件所要求的厚度；步骤2、对所述多晶硅薄膜(3)进行硅离子自注入，且硅离子的注入剂量低于使多晶硅非晶化的计量限度。该多晶硅薄膜的制备方法使注入的硅离子形成间隙硅，并移动到多晶硅晶界处，能够减少多晶硅的晶界缺陷密度，改善多晶硅薄膜的质量。提供的一种多晶硅TFT结构，其岛状半导体层由经过低剂量硅离子自注入的多晶硅薄膜制成，能够降低开启状态下的晶界势垒，增大载流子迁移率，增大开态电流，减小阈值电压，改善TFT特性。

Description

多晶硅薄膜的制备方法及多晶硅TFT结构 技术领域
本发明涉及显示技术领域，尤其涉及一种多晶硅薄膜的制备方法及多晶硅TFT结构。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示器已经逐步取代CRT显示器。
随着平板显示器的发展，高分辨率，低能耗的面板需求不断被提出。低温多晶硅(Low Temperature Poly-Silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)在高分辨有源液晶显示器(AMLCD)以及有源有机发光二极管显示器(AMOLED)技术中得到了业界的重视，有很大的应用价值和潜力。与非晶硅(a-Si)相比，LTPS TFT具有较高的载流子迁移率，可达几十至几百cm2/VS，器件反应速度快，稳定性好，可以满足高分辨率AMLCD及AMOLED显示器的要求。LTPS TFT除了作为像素开关，还可以用于构建周边驱动电路，实现电路集成。
低温多晶硅是多晶硅(poly-Si)技术的一个分支。多晶硅材料具有较高的电子迁移率源于多晶硅自身的多晶体结构。与高缺陷密度及高度无序的非晶硅相比，多晶硅是由多个有序晶粒构成。
现有技术中，多晶硅薄膜可以直接由化学气相沉积(Chemical Vapor Deposition，CVD)得到；也可以将非晶硅经过不同的退火处理使其晶化得到，常用的方法有：固相晶化(Solid Phase Crystallization，SPC)、金属诱导晶化(Metal-Induced Crystallization，MIC)、准分子激光退火晶化(Excimer Laser Annealing，ELA)等。
目前，限制多晶硅TFT器件特性的主要因素是多晶硅晶粒之间的晶界，晶界处存在着大量的缺陷。上述不同方法制得的多晶硅薄膜的晶粒大小和分布都有所不同，晶界缺陷的数量也有很大区别。
现有的研究文献针对如何改善多晶硅薄膜的质量提出了许多方法。有研究指出，使用硅离子自注入以令多晶硅薄膜非晶化，然后再进行重结晶，可以降低晶核密度从而增大重结晶后的晶粒尺寸。
R.Reif和J.E.Knott(Electronics Letters,Vol.17No.17,1981)证明将高剂 量的硅离子注入(如3×1015/cm2)多晶硅薄膜，可以使多晶硅薄膜大部分晶体结构非晶化，由于离子注入的隧道效应，只留下少量晶核。这些晶核在之后的SPC重结晶过程中长成了大尺寸晶粒。
N.Yamauchi等(IEEE Electron Device Letters,Vol.11,No.1,1990及Journal of Applied Physics,vol.75,pp.3235-3257,1994)用以上方法获得的多晶硅制作了TFT。由于晶粒变大，器件的迁移率增大，亚阈值摆幅陡峭，但是同时，文章中也报道了由于大晶粒的随机分布使得小尺寸器件的均匀性严重下降。
以上文献表明，高剂量硅离子自注入可以将多晶硅大部分非晶化。非晶化使得晶核密度降低，并在重结晶后得到大尺寸晶粒。晶粒增大使得晶界缺陷减少，器件特性提高。但是此方法一方面需要大剂量的硅离子注入，一方面需要再一次的结晶退火制程，另外还存在器件均匀性问题。
迄今为止，不引致非晶化的较低剂量的硅离子注入的效应还没有被研究并应用于多晶硅。
发明内容
本发明的目的在于提供一种多晶硅薄膜的制备方法，能够减少多晶硅的晶界缺陷密度，改善多晶硅薄膜的质量。
本发明的另一目的在于提供一种多晶硅TFT结构，能够降低开启状态下的晶界势垒，增大载流子迁移率，增大开态电流，减小阈值电压，改善TFT特性。
为实现上述目的，本发明首先提供一种多晶硅薄膜的制备方法，包括如下步骤：
步骤1、提供一基片，在所述基片上形成一层多晶硅薄膜，该多晶硅薄膜的厚度符合制造半导体器件所要求的厚度；
步骤2、对所述多晶硅薄膜进行硅离子自注入，且硅离子的注入剂量低于使多晶硅非晶化的计量限度。
所述多晶硅薄膜的制备方法，还包括：步骤3、对完成硅离子自注入的多晶硅薄膜进行后退火处理。
所述步骤1中的基片为覆盖有缓冲层的硅基片、覆盖有缓冲层的玻璃基片、或覆盖有缓冲层的柔性基片，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
所述步骤1通过直接气相沉积多晶硅形成所述多晶硅薄膜；
或者，所述步骤1通过固相晶化工艺、或金属诱导晶化工艺使非晶硅 结晶形成所述多晶硅薄膜；
再或者，所述步骤1采用激光或LED为热源使非晶硅产生液相结晶形成所述多晶硅薄膜。
所述步骤2使用离子注入机、或离子喷淋机对所述多晶硅薄膜进行硅离子自注入。
所述步骤3使用炉管、或快速热退火设备进行后退火处理。
所述多晶硅薄膜的制备方法对所述多晶硅薄膜进行硅离子自注入之前还需要在所述多晶硅薄膜上沉积一层保护层，所述保护层的材料为氧化硅、氮化硅、或二者的组合。
本发明还提供一种多晶硅薄膜的制备方法，包括如下步骤：
步骤1、提供一基片，在所述基片上形成一层多晶硅薄膜，该多晶硅薄膜的厚度符合制造半导体器件所要求的厚度；
步骤2、对所述多晶硅薄膜进行硅离子自注入，且硅离子的注入剂量低于使多晶硅非晶化的计量限度；
步骤3、对完成硅离子自注入的多晶硅薄膜进行后退火处理；
其中，所述步骤1中的基片为覆盖有缓冲层的硅基片、覆盖有缓冲层的玻璃基片、或覆盖有缓冲层的柔性基片，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合；
其中，所述步骤2使用离子注入机、或离子喷淋机对所述多晶硅薄膜进行硅离子自注入。
本发明还提供一种多晶硅TFT结构，包括：基片、覆盖所述基片的缓冲层、设于所述缓冲层上的岛状半导体层、覆盖所述岛状半导体层的栅极绝缘层、设于栅极绝缘层上的栅极、设于所述栅极与栅极绝缘层上的钝化层、及设于所述钝化层上的源极与漏极；
所述岛状半导体层包括位于该岛状半导体层中部的沟道区、及分别位于所述沟道区两侧的源极接触区、与漏极接触区，所述源极接触所述源极接触区，所述漏极接触所述漏极接触区；
所述岛状半导体层由上述的多晶硅薄膜的制备方法所制备的多晶硅薄膜经光刻及离子掺杂形成，所述源极接触区与漏极接触区对应于离子掺杂的区域；
所述多晶硅TFT结构属于P型TFT器件或N型TFT器件。
所述栅极绝缘层与钝化层的材料为氧化硅、氮化硅、或二者的组合，所述栅极、源极、与漏极的材料为铝。
本发明的有益效果：本发明提供的一种多晶硅薄膜的制备方法，通过 对多晶硅薄膜进行硅离子自注入，且硅离子的注入剂量低于使多晶硅非晶化的计量限度，使注入的硅离子形成间隙硅，并移动到多晶硅晶界处，能够减少多晶硅的晶界缺陷密度，改善多晶硅薄膜的质量。本发明提供的一种多晶硅TFT结构，其岛状半导体层由经过低剂量硅离子自注入的多晶硅薄膜制成，能够降低开启状态下的晶界势垒，增大载流子迁移率，增大开态电流，减小阈值电压，改善TFT特性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的多晶硅薄膜的制备方法的流程图；
图2、图3为本发明的多晶硅薄膜的制备方法的步骤1的示意图；
图4为本发明的多晶硅薄膜的制备方法的步骤2的示意图；
图5为本发明的多晶硅薄膜的制备方法的步骤2中不同的硅离子注入剂量及对应的样品标号表；
图6为本发明的多晶硅TFT结构的剖面示意图；
图7为对采用不同样品的多晶硅TFT进行载流子迁移率测试的测试结果图；
图8为对应于图7的数据表。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明首先提供一种多晶硅薄膜的制备方法，包括如下步骤：
步骤1、请参阅图2与图3，提供一基片1，在所述基片1上形成一层多晶硅薄膜3，该多晶硅薄膜3的厚度符合制造半导体器件所要求的厚度。
具体地，该步骤1中的基片1为覆盖有缓冲层11的硅基片、覆盖有缓冲层11的玻璃基片、或覆盖有缓冲层11的柔性基片，所述缓冲层11的材料为氧化硅、氮化硅、或二者的组合，优选的，所述缓冲层11的材料为二氧化硅(SiO2)。
该步骤1可以通过直接气相沉积多晶硅形成所述多晶硅薄膜3。
该步骤1也可以通过固相晶化工艺、或金属诱导晶化工艺使非晶硅结晶形成所述多晶硅薄膜3。
该步骤1还可以采用激光或LED为热源使非晶硅产生液相结晶形成所述多晶硅薄膜3。
进一步地，如图2与图3所示，以金属诱导晶化工艺使非晶硅结晶形成所述多晶硅薄膜3为例，该步骤1的详细过程为：首先使用低压化学气相沉积(LPCVD)沉积一层厚度为50nm的非晶硅薄膜3’；再在所述非晶硅薄膜3’上沉积一薄层(厚度<5nm)的金属镍4’；然后进行氮气退火将非晶硅晶化，退火温度为600℃，退火时间为10小时；非晶硅晶化完成形成多晶硅薄膜3后，使用加温的硫酸双氧水混合物清洗基片1，以将残余的金属镍4’去除。
步骤2、对所述多晶硅薄膜3进行硅离子自注入，且硅离子的注入剂量应低于使多晶硅非晶化的计量限度，优选的，硅离子的注入剂量为4×1014/cm2～8×1014/cm2。
具体地，如图4所示，仍以金属诱导晶化工艺使非晶硅结晶形成多晶硅薄膜3为例，对所述多晶硅薄膜3进行硅离子自注入之前按照实际需要可在所述多晶硅薄膜3上沉积一层保护层4，所述保护层4的厚度根据后续硅离子注入的能量大大小来进行选择，当然，也可以不用该保护层4，在本实施例中，沉积厚度为25nm的保护层4，所述保护层4的材料为氧化硅、氮化硅、或二者的组合，优选的，所述保护层4的材料为SiO2；然后使用离子注入机、或离子喷淋机对所述多晶硅薄膜3进行硅离子自注入，注入的能量为15keV。
为验证硅离子的注入剂量对多晶硅薄膜以及最终产品多晶硅TFT的性能影响，本发明以注入不同剂量硅离子的多个样品进行实验：如图5所示，分别将硅离子注入剂量为2×1014/cm2、4×1014/cm2、6×1014/cm2、8×1014/cm2、10×1014/cm2、100×1014/cm2的样品标号为1、2、3、4、5、6，每个标号的样品各选取20件进行后续的多晶硅TFT性能测试。
完成步骤2后，还需要进行步骤3、对完成硅离子自注入的多晶硅薄膜3进行氮气后退火处理，氮气后退火的温度为600℃，退火时间为4小时。
本发明的多晶硅薄膜的制备方法使得注入的硅离子形成间隙硅，并移动到多晶硅晶界处，能够减少多晶硅的晶界缺陷密度，改善多晶硅薄膜的质量。
请参阅图6，在上述多晶硅薄膜的制备方法的基础上，本发明还提供一种多晶硅TFT结构，包括：基片1、覆盖所述基片1的缓冲层11、设于所 述缓冲层11上的岛状半导体层30、覆盖所述岛状半导体层30的栅极绝缘层5、设于栅极绝缘层5上的栅极7、设于所述栅极7与栅极绝缘层5上的钝化层8、及设于所述钝化层8上的源极91与漏极92。
制作所述多晶硅TFT结构的过程为：按照上述方法制备完多晶硅薄膜3后，首先将多晶硅薄膜3光刻为岛状；然后采用LPCVD沉积厚度为50nm的栅极绝缘层5，该栅极绝缘层5的材料为氧化硅、氮化硅、或二者的组合，优选SiO2；接着沉积厚度为300nm的铝并光刻为栅极7；再以栅极7为遮挡，对光刻后的岛状多晶硅薄膜进行自对准的离子注入掺杂，离子注入的剂量为4×1015/cm2，注入能量20keV，使得岛状多晶硅薄膜成为岛状半导体层30，其中，对应于离子掺杂的区域形成源极接触区32与漏极接触区33，被栅极7遮挡未进行离子掺杂的区域成为沟道区30；接下来，采用LPCVD沉积厚度为500nm的钝化层8，并在钝化层8与栅极绝缘层5上对应源极接触区32与漏极接触区33的上方分别开第一过孔81、第二过孔82，该钝化层8的材料为氧化硅、氮化硅、或二者的组合，优选SiO2；溅射700nm厚的铝(含硅1％)并光刻为源极91与漏极92，所述源极91经由所述第一过孔81接触所述源极接触区32，所述漏极92经由所述第二过孔82接触所述漏极接触区33；最后进行30分钟的氢化处理。
上述制作多晶硅TFT结构的过程中，根据对岛状多晶硅薄膜掺杂离子的不同，可制得P型TFT器件或N型TFT器件，如掺杂硼离子可制得P型TFT器件，掺杂磷离子可制得N型TFT器件。
制成对应于不同标号样品的多个多晶硅TFT后，在室温下使用HP4156B半导体参数分析仪对多晶硅TFT性能进行测试并计算对应于同一标号样品的多个多晶硅TFT的平均载流子迁移率。
如图7、图8所示，多晶硅TFT的沟道区的长度L和宽度W都是10μm，源漏极电压Vds为-0.1V，在硅离子注入剂量为4×1014/cm2～8×1014/cm2这个范围内，载流子迁移率得到改善，随着硅离子注入剂量的增大，载流子迁移率亦增大，这是因为硅离子的注入剂量低于使多晶硅非晶化的计量限度，注入的硅离子形成间隙硅，并移动到多晶硅晶界处，减少了多晶硅的晶界缺陷密度。而当硅离子注入剂量大于或等于1×1015/cm2时，载流子迁移率明显下降，这是因为多晶硅薄膜中注入了大量的硅离子，多晶硅被不同程度的非晶化，而本发明的制备方法并未对注入硅离子的多晶硅薄膜进行高温退火重结晶处理，多晶硅的晶格结构已遭到破坏，造成多晶硅TFT的性能劣化。测试结果验证了：本发明多晶硅薄膜的制备方法将对多晶硅薄膜3进行硅离子自注入的剂量设置为低于使多晶硅非晶化的计量限度是 正确的。
综上所述，本发明的多晶硅薄膜的制备方法，通过对多晶硅薄膜进行硅离子自注入，且硅离子的注入剂量低于使多晶硅非晶化的计量限度，使注入的硅离子形成间隙硅，并移动到多晶硅晶界处，能够减少多晶硅的晶界缺陷密度，改善多晶硅薄膜的质量。本发明的多晶硅TFT结构，其岛状半导体层由经过低剂量硅离子自注入的多晶硅薄膜制成，能够降低开启状态下的晶界势垒，增大载流子迁移率，增大开态电流，减小阈值电压，改善TFT特性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (13)

  1. 一种多晶硅薄膜的制备方法，包括如下步骤：
    步骤1、提供一基片，在所述基片上形成一层多晶硅薄膜，该多晶硅薄膜的厚度符合制造半导体器件所要求的厚度；
    步骤2、对所述多晶硅薄膜进行硅离子自注入，且硅离子的注入剂量低于使多晶硅非晶化的计量限度。
  2. 如权利要求1所述的多晶硅薄膜的制备方法，还包括：
    步骤3、对完成硅离子自注入的多晶硅薄膜进行后退火处理。
  3. 如权利要求1所述的多晶硅薄膜的制备方法，其中，所述步骤1中的基片为覆盖有缓冲层的硅基片、覆盖有缓冲层的玻璃基片、或覆盖有缓冲层的柔性基片，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
  4. 如权利要求1所述的多晶硅薄膜的制备方法，其中，所述步骤1通过直接气相沉积多晶硅形成所述多晶硅薄膜；
    或者，所述步骤1通过固相晶化工艺、或金属诱导晶化工艺使非晶硅结晶形成所述多晶硅薄膜；
    再或者，所述步骤1采用激光或LED为热源使非晶硅产生液相结晶形成所述多晶硅薄膜。
  5. 如权利要求1所述的多晶硅薄膜的制备方法，其中，所述步骤2使用离子注入机、或离子喷淋机对所述多晶硅薄膜进行硅离子自注入。
  6. 如权利要求2所述的多晶硅薄膜的制备方法，其中，所述步骤3使用炉管、或快速热退火设备进行后退火处理。
  7. 如权利要求4所述的多晶硅薄膜的制备方法，其中，对所述多晶硅薄膜进行硅离子自注入之前还需要在所述多晶硅薄膜上沉积一层保护层，所述保护层的材料为氧化硅、氮化硅、或二者的组合。
  8. 一种多晶硅薄膜的制备方法，包括如下步骤：
    步骤1、提供一基片，在所述基片上形成一层多晶硅薄膜，该多晶硅薄膜的厚度符合制造半导体器件所要求的厚度；
    步骤2、对所述多晶硅薄膜进行硅离子自注入，且硅离子的注入剂量低于使多晶硅非晶化的计量限度；
    步骤3、对完成硅离子自注入的多晶硅薄膜进行后退火处理；
    其中，所述步骤1中的基片为覆盖有缓冲层的硅基片、覆盖有缓冲层的玻璃基片、或覆盖有缓冲层的柔性基片，所述缓冲层的材料为氧化硅、 氮化硅、或二者的组合；
    其中，所述步骤2使用离子注入机、或离子喷淋机对所述多晶硅薄膜进行硅离子自注入。
  9. 如权利要求8所述的多晶硅薄膜的制备方法，其中，所述步骤1通过直接气相沉积多晶硅形成所述多晶硅薄膜；
    或者，所述步骤1通过固相晶化工艺、或金属诱导晶化工艺使非晶硅结晶形成所述多晶硅薄膜；
    再或者，所述步骤1采用激光或LED为热源使非晶硅产生液相结晶形成所述多晶硅薄膜。
  10. 如权利要求8所述的多晶硅薄膜的制备方法，其中，所述步骤3使用炉管、或快速热退火设备进行后退火处理。
  11. 如权利要求9所述的多晶硅薄膜的制备方法，其中，对所述多晶硅薄膜进行硅离子自注入之前还需要在所述多晶硅薄膜上沉积一层保护层，所述保护层的材料为氧化硅、氮化硅、或二者的组合。
  12. 一种多晶硅TFT结构，包括：基片、覆盖所述基片的缓冲层、设于所述缓冲层上的岛状半导体层、覆盖所述岛状半导体层的栅极绝缘层、设于栅极绝缘层上的栅极、设于所述栅极与栅极绝缘层上的钝化层、及设于所述钝化层上的源极与漏极；
    所述岛状半导体层包括位于该岛状半导体层中部的沟道区、及分别位于所述沟道区两侧的源极接触区、与漏极接触区，所述源极接触所述源极接触区，所述漏极接触所述漏极接触区；
    所述岛状半导体层由如权利要求1至8任一项所述的多晶硅薄膜的制备方法所制备的多晶硅薄膜经光刻及离子掺杂形成，所述源极接触区与漏极接触区对应于离子掺杂的区域；
    所述多晶硅TFT结构属于P型TFT器件或N型TFT器件。
  13. 如权利要求12所述的多晶硅TFT结构，其中，所述栅极绝缘层与钝化层的材料为氧化硅、氮化硅、或二者的组合，所述栅极、源极、与漏极的材料为铝。
PCT/CN2015/082265 2015-06-09 2015-06-25 多晶硅薄膜的制备方法及多晶硅tft结构 WO2016197410A1 (zh)

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